Implementation Structure

approximately T₁/2 compared to the impulse response. If the impulse response has its maximum at t= tmax, the pulse response will thus have its maximum at t tmax+ T1/2.

Next, T₂should be chosen such that the step response and the trailing edge of the impulse response approximately add up to 1. An initial guess may be to apply the step between the end of the pulse and the maximum of the pulse response. This gives T2 0.5tmax−0.25T1. An initial guess for t^L may then be obtained either by simulating the process using the initial values for T1and T2, or by using f3(t^L,T1,T2) = 0 from Equation (5.15).

The suggested initial values has worked for all tested processes. How-ever, they must be modified if u is large negative, since the pulse-step approximation is not very good in that case. This will not be treated here, since the recommendation in the previous section was to use u= 0.

Ff. gen.

PID Σ G(s)

G(s)ˆ u_{f f}

u y

y_sp

¯ysp

Figure 5.19 Suggested implementation structure.

The other question is typically solved simply by switching to PID con-trol when the output, and possibly some of the state variables, are close enough to the desired set point. As pointed out in Malmborg (1998), this hybrid controller may cause undesired behavior such as limit cycling, if the switching strategy is not carefully formulated. To overcome this, Malmborg(1998) suggests a safe Lyapunov-based switching between dif-ferent controllers.

Here, we will suggest another controller structure as shown in Fig-ure 5.19. This structFig-ure will actually address both problems above at once.

The top left block generates the feed-forward control signal u_{f f} identical to the pulse-step control signal. The system ˆG(s) contains the process model that was used when computing u_{f f}. The output ¯ysp of this block will then be the desired output trajectory. If we have a perfect model and no disturbances, we get ¯ysp  ysp, which makes uPI D = 0 ¹. Hence, the pre-computed feed-forward signal alone will take care of the set point change, and no feedback action is used. However, when the output does not follow the desired trajectory, the PID block will try to compensate by adding a component to the control signal.

The proposed controller structure will behave as follows:

• Load disturbances and set point changes are completely separated.

This makes sense, since the PID controller typically is tuned for optimal load disturbance response. Whenever a load disturbance oc-curs, the output signal will be a superposition of an optimal set point response and an optimal load disturbance response. This is in

1In order to achieve this, the simplified controller structure in Figure 5.19 must be ex-tended with some anti-windup mechanism. Furthermore, the PID block must operate on the error ¯ysp− y only. This causes no problem in this case since ¯yspis a smooth signal, and may thus be differentiated.

the states, and consequently the switching times. Load disturbances and set point changes will thus interfere with each other.

• Modeling errors may cause a deviation between the desired and the actual output. Since these deviations are taken care of by the PID block, it may be natural to treat them as effects of a load disturbance instead. In fact, you may rewrite the effects of modeling errors as an equivalent input load disturbance v= Gvuf f, where

Gv= G− ˆG

G (1 + GGPI D) (5.21)

The two features above rely on the fact that the control signal may actually move in both directions around the constant levels used in the set point strategy. This is one good reason why not all the available control signal should be used when designing the fast step response.

Figure 5.20 shows an example with G(s) = 1/(s + 1)⁴where an input step load disturbance is applied at the same time as the set point change.

The full line shows the behavior without the load disturbance, the dashed and dotted curves have load disturbance steps of size 0.5 in positive and negative direction, respectively. u= 4 and u = −4 have been used in the fast step response design, and the PID controller has been designed to give M_s= 1.4, see page 127. Due to the load disturbance, the maximum magnitude of the control signal is 4.09 instead of 4. The actual deviation from the nominal value will of course depend on the relative size of the load disturbance, as well as the timing.

Next, we will examine what happens if G(s) and ˆG(s) differ. It is reasonable to assume that the same model is used for design of both the set point response and the PID controller. We assume that the process model used in the calculations is the same as before, namely ˆG(s) = 1/(s + 1)⁴. The following true processes are then examined:

G₁(s) = 1

(s + 1)⁴e^−sL, L= {0.5,1}

G₂(s) = 1

(4/n s + 1)ⁿ, n= {3,5} G₃(s) = K

(s + 1)⁴, K = {0.8,1.2}

The resulting responses are compared with the nominal response in Fig-ures 5.21–5.23.

0 2 4 6 8 10 12 14 16 18 20

−0.5 0 0.5 1 1.5

Output

0 2 4 6 8 10 12 14 16 18 20

−5 0 5

Control signal

Figure 5.20 Fast step response(full line) with positive (dashed) and negative (dotted) load response at time 0.

0 2 4 6 8 10 12 14 16 18 20

−0.5 0 0.5 1 1.5

Output

0 2 4 6 8 10 12 14 16 18 20

−5 0 5

Control signal

Figure 5.21 Nominal set point response(full line) with unmodeled delay of 0.5 (dashed) and 1 (dotted) time units.

0 2 4 6 8 10 12 14 16 18 20

−0.5 0 0.5

Output

0 2 4 6 8 10 12 14 16 18 20

−5 0 5

Control signal

Figure 5.22 Nominal set point response(full line) with third (dashed) and fifth (dotted) order process.

G₁(s) contains an unmodeled time delay. This implies that the nomi-nal feed-forward signomi-nal is still optimal, but the optimal response will be delayed. The responses shown in Figure 5.21 are obviously delayed, but there is also an overshoot. The deterioration mainly comes from the fact that y is delayed, whereas ¯yspis not. The PID controller then tries to com-pensate for the difference instead of just awaiting the delayed response.

The behavior is also slightly affected by the additional phase lag which is not accounted for in the PID design. This results in a higher value of M_s (1.7 and 2.1 for a delay of 0.5 and 1 time units, respectively), and consequently less well-damped behavior. The deviation from the nomi-nal response will actually be approximately the same regardless of which u and u is used for the fast set point response.

Figure 5.22 shows the response for G₂(s) where the order of the process is wrong. The time constants in G₂(s) have been changed such that the step response of the process has the correct average residence time and (approximately) the correct rise time, defined as the time when it reaches 1− e⁻¹  0.63. Compared to G1 there is an additional sources of the deviation from the nominal response. Here, the pre-computed uf f is no longer optimal. For example, the large control signal should have been applied for a longer time when n = 3. This is the main reason for the sluggish response of the dashed curve in Figure 5.22.

0 2 4 6 8 10 12 14 16 18 20

−0.5 0 0.5 1 1.5

Output

0 2 4 6 8 10 12 14 16 18 20

−5 0 5

Control signal

Figure 5.23 Nominal set point response(full line) with decreased (dashed) and increased(dotted) process gain.

Figure 5.23 shows the response when the process gain is incorrect. u_{f f} will not be correct in this case either. When K = 0.8, the magnitude of u and u should have been decreased when solving the normalized problem setup. Thus, the switching times T1and T2should have been larger. The resulting response will thus be too slow.

To summarize the robustness evaluations in this section, the proposed controller structure behaves reasonably well for the rather large distur-bances and model errors simulated here. It has nice stability properties, since the PID controller has been designed with robustness in mind, and the switching scheme is not part of the feedback loop. In all the simula-tions above, it outperforms the PID controller with set point weighting.

To achieve closer following of the nominal response, a higher order robust controller could be designed, but that is outside the scope of this thesis. Furthermore, a strategy where the switching times are allowed to change may be better at compensating for deviations, but such a strategy would inevitably be more complicated. The proposed structure is tractable in its simplicity. A nice property is that it has very low demands on real-time computing power, as opposed to for example Model Predictive Con-trol, which can used to solve similar problems.

A drawback with the proposed controller structure is when the set point change causes the control signal to saturate. There is then no room

truly optimal in all cases.