A Continuous-Time ADC and DSP for Smart Dust

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Institutionen för systemteknik

Department of Electrical Engineering

Examensarbete

A Continuous-Time ADC and DSP for Smart Dust

Examensarbete utfört i Elektroniksystem vid Tekniska högskolan vid Linköpings universitet

av

Dhurv Chhetri, Venkata Narasimha Manyam LiTH-ISY-EX--11/4436--SE

Linköping 2011

Department of Electrical Engineering Linköpings tekniska högskola

Linköpings universitet Linköpings universitet

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A Continuous-Time ADC and DSP for Smart Dust

Examensarbete utfört i Elektroniksystem

vid Tekniska högskolan i Linköping

av

Dhurv Chhetri, Venkata Narasimha Manyam LiTH-ISY-EX--11/4436--SE

Handledare: Niklas U Andersson

isy, Linköpings universitet

J Jacob Wikner

isy,Linköpings universitet

Examinator: J Jacob Wikner

isy, Linköpings universitet

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Avdelning, Institution

Division, Department

Division of Electronics Systems Department of Electrical Engineering Linköpings universitet

SE-581 83 Linköping, Sweden

Datum Date 2011-05-31 Språk Language Svenska/Swedish Engelska/English Rapporttyp Report category Licentiatavhandling Examensarbete C-uppsats D-uppsats Övrig rapport

URL för elektronisk version

http://www.es.isy.liu.se http://www.es.isy.liu.se ISBN — ISRN LiTH-ISY-EX--11/4436--SE

Serietitel och serienummer

Title of series, numbering

ISSN

—

Titel

Title A Continuous-Time ADC and DSP for Smart Dust

Författare

Author

Dhurv Chhetri, Venkata Narasimha Manyam

Sammanfattning

Abstract

Recently, smart dust or wireless sensor networks are gaining more attention. These autonomous, ultra-low power sensor-based electronic devices sense and process burst-type environmental variations and pass the data from one node (mote) to another in an ad-hoc network. Subsystems for smart dust are typically the analog interface (AI), analog-to-digital converter (ADC), analog-to-digital signal processor (DSP), analog-to-digital-to-analog converter (DAC), power management, and transceiver for communication.

This thesis project describes an event-driven (ED) digital signal processing system (ADC, DSP and DAC) operating in continuous-time (CT) with smart dust as the target application. The benefits of the CT system compared to its conventional counterpart are lower in-band quantization noise and no requirement of a clock generator and anti-aliasing filter, which makes it suitable for processing burst-type data signals.

A clockless EDADC system based on a CT delta modulation (DM) technique is pre-sented. The ADC output is digital data, continuous in time, known as “data token”. The ADC employs an unbuffered, area efficient, segmented resistor-string (R-string) feedback DAC. A study of different segmented R-string DAC architectures is presented. A compar-ison in component reduction with prior art shows nearly 87.5% reduction of resistors and switches in the DAC and the D flip-flops in the bidirectional shift registers for an 8-bit ADC, utilizing the proposed segmented DAC architecture. The obtained SNDR for the 3-bit, 4-bit and 8-bit ADC system is 22.696 dB, 30.435 dB and 55.73 dB, respectively, with the band of interest as 220.5 kHz.

The CTDSP operates asynchronously and process the data token obtained from the EDADC. A clock-less transversal direct-form finite impulse response (FIR) low-pass filter (LPF) is designed.

Systematic top-down test-driven methodology is employed through out the project. Initially, MATLAB models are used to compare the CT systems with the sampled systems. The complete CTDSP system is implemented in Cadence design environment.

The thesis has resulted in two conference contributions. One for the 20th

Euro-pean Conference on Circuit Theory and Design, ECCTD’11 and the other for the 19th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC’11. We obtained the second-best student paper award at the ECCTD.

Nyckelord

Keywords smart dust, Event-driven( ED), continuous time(CT), Delta-modulation(DM),

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Abstract

Recently, smart dust or wireless sensor networks are gaining more attention. These autonomous, ultra-low power sensor-based electronic devices sense and pro-cess burst-type environmental variations and pass the data from one node (mote) to another in an ad-hoc network. Subsystems for smart dust are typically the analog interface (AI), analog-to-digital converter (ADC), digital signal processor (DSP), digital-to-analog converter (DAC), power management, and transceiver for communication.

This thesis project describes an event-driven (ED) digital signal processing system (ADC, DSP and DAC) operating in continuous-time (CT) with smart dust as the target application. The benefits of the CT system compared to its conventional counterpart are lower in-band quantization noise and no requirement of a clock generator and anti-aliasing filter, which makes it suitable for processing burst-type data signals.

A clockless EDADC system based on a CT delta modulation (DM) technique is presented. The ADC output is digital data, continuous in time, known as “data token”. The ADC employs an unbuffered, area efficient, segmented resistor-string (R-resistor-string) feedback DAC. A study of different segmented R-resistor-string DAC architectures is presented. A comparison in component reduction with prior art shows nearly 87.5% reduction of resistors and switches in the DAC and the D flip-flops in the bidirectional shift registers for an 8-bit ADC, utilizing the proposed segmented DAC architecture. The obtained SNDR for the 3-bit, 4-bit and 8-bit ADC system is 22.696 dB, 30.435 dB and 55.73 dB, respectively, with the band of interest as 220.5 kHz.

The CTDSP operates asynchronously and process the data token obtained from the EDADC. A clock-less transversal direct-form finite impulse response (FIR) low-pass filter (LPF) is designed.

Systematic top-down test-driven methodology is employed through out the project. Initially, MATLAB models are used to compare the CT systems with the sampled systems. The complete CTDSP system is implemented in Cadence design environment.

The thesis has resulted in two conference contributions. One for the 20th European Conference on Circuit Theory and Design, ECCTD’11 and the other for the 19th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC’11. We obtained the second-best student paper award at the ECCTD.

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Acknowledgments

First of all, we would like to thank our supervisor and guru, Dr. J Jacob Wikner, for introducing us to the exciting research field of CTDSPs and tutoring us mixed-signal processing systems, in our master’s program. We were always inspired by his style and approach. We would like to offer our sincerest gratitude to him for guiding us throughout the thesis with his knowledge and patience and also providing space to think in our own way. It would not have been possible to complete the thesis project work and write the conference papers without his support. One simply could not wish for a better or friendlier supervisor.

We are also extremely thankful to Niklas U Andersson for his expert knowl-ege and supervision. We would like to thank all the professors and Ph.D. stu-dents at the division of Electronics Systems, Department of Electrical Engineer-ing, Linköping University, especially to Joakim Alvbrant, for extending some quick support to resolve design issues and challenges related to simulations.

We also thank our thesis opponents Sajib Roy and Murad Kabir Nipun for their time and invaluable feedback on the thesis. A very special thanks to all our colleagues in master thesis lab (signal och bild), especially to Sheheryar, Asfandyar and Tanvir, for helpful discussions and suggestions in many practical issues of design and documentation.

We would like to thank Mariya Kurchuk, Ph.D. Student, Columbia University for taking time from her busy schedule to reply to our smallest query with great details.

We thank all people, who are directly or indirectly involved in the completion of this thesis, whose names that we might have forgotten to mention here.

I (Dhurv Chhetri) would also like to thank

• Sanjiv Bhakhura, Navneet Agarwal, Santosh Joshi, Amit Sundariyal, Rajeev Kharbanda and Chetan Rao for continuous support and inspiration.

I (Venkata Narasimha Manyam) would also like to thank

• Sarath, Suresh, Lokesh and Dinakar for being my friends and inspiring me.

Lastly, we would like to show our sincere gratitude towards our beloved parents and family members, who have always believed in us and we thank for their un-conditional support, love and affection.

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Introduction

The target of this project is to study and design a mixed-signal processing sys-tem consisting of an Analog-to-Digital Converter (ADC), Digital Signal Proces-sor (DSP) and Digital-to-Analog Converter (DAC), for the smart dust application, in a top-down, test-driven design methodology. The complete system has to be operated in a CT mode without any sampling. The focus is to achieve low power consumption and area, without sacrificing the overall system performance.

This chapter provides a brief introduction to the thesis work and describes the context of the project. Section 1.1 presents a brief introduction of the smart dust mote, explaining the blocks targeted to be designed in this project. Section 1.2 presents the specifications of the project. Section 1.3 provides the details about the Continuous-Time (CT) processing and section 1.4 mentions the details about the overall project organization.

1.1 Smart dust: A brief introduction

There has been a new phenomenon emerging out in recent past called “smart dust” also known as “motes” or “wireless sensor networks” or “swarming”. Smart dust is a tiny (size and density of a sand particle), ultra-low-power electronic sen-sory autonomous device packed with various sensors, intelligence and even wireless communication capability. A typical scenario could be smart dust motes deployed in large numbers to form an ad-hoc network, called as swarm, detects environment variables such as light, temperature, pressure, vibration, magnetic flux density or chemical levels. This network, formed by few tens or even millions of motes, can communicate with neighboring motes and pass on the data collected from one mote to another in a systematic way, which can be collected and processed fur-ther [1]. Smart dust can derive the energy necessary for its functioning eifur-ther from batteries or from the environment itself, or from both. The power consumption of the smart dust decreases with the shrinkage in the size of the mote. It has to be in the order of few microwatts. This imposes a stringent constraint on the design, and has to be addressed by following various low power design techniques.

Figure 1.1 shows the block level details of a single autonomous smart dust

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8 Introduction Energy harvest High-speed Sensor I/F Energy

storage regulatorSupply Control

Rx Low-speed Sensor I/F Processor Transceiver section Front end Tx Input/ Control Signal Input Signal Tx/Rx data

Figure 1.1: Block diagram of a typical smart dust mote.

mote. A typical smart dust module consists of an energy harvester, energy storage, supply regulator, control, high-speed sensor interface, low-speed sensor interface, DSP and radio transceiver section. Energy harvester generates energy from the environment such as solar radiation, wind or even vibration. The generated energy is stored for future usage, using an energy storage element. The available energy is supplied efficiently, in the form of fixed voltages and currents, to the various circuits of the system with the help of the supply regulator. The control circuitry is responsible for the various control mechanisms involved in a mote, which decides the operation of the mote. The sensors collect the environmental variations of interest and convert them to an equivalent electrical signal, analog in nature. The sensory interfaces are required to perform initial signal conditioning and analog to digital conversion of the sensed data. The data is processed digitally using a DSP. DSPs can essentially perform various kinds of operations on the digital signals, such as filtering, domain transformations, compression, encryption, etc. The processed data is reconstructed back to analog equivalent necessary for transmission, using a DAC (not shown in figure). The transceiver section upconverts the baseband signal to Radio Frequency (RF) signals and transmits them. It also receives the RF signals and downconverts them to the baseband singal.

This project targets the design of the low speed sensor interface and the DSP, as highlighted in figure 1.1.

1.2 Smart dust: specification

The following section presents the specification of the CTDSP system, that is finally going to be deployed in the smart dust motes. The major constraint imposed on the system is that all the blocks in the design should be clockless. Further, the system should be implemented in 65 nm advanced Complimentary Metal Oxide

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1.3 Continuous time processing 9

Semiconductor (CMOS) process. The specifications of the ADC, DAC and the transversal direct-form Finite-Impulse-Response (FIR) Low Pass Filter (LPF) is as shown in table 1.1.

Table 1.1: CTDSP system specification.

Item parameter Min Typ Max Unit

ADC Resolution 3 4 8 bits

Maximum input signal frequency — 20 — kHz

LPF

Sampling frequency — 44.1 — kHz

Passband edge frequency — 5.2 — kHz

Stopband edge frequency — 10 — kHz

Passband ripple — 1 — dB

Stopband attenuation 30 50 — dB

DAC Resolution 3 4 8 bits

Generic Supply voltage — 1.2 — V

Process — 65 — nm

1.3 Continuous time processing

A new emerging field of digital signal processing in CT has been presented by Prof. Yannis Tsividis of Columbia University [2, 3]. It is opposed to the conventional sampled systems where the processing is carried out in discrete time. This CTDSP system processes the data sensed by the analog interface block of the sensor module and produce the output to the RF front-end. As the input data is of burst nature, occurring occasionally, it is highly desirable that the CTDSP system remains idle most of the time and operates only when there is a significant data to process. This is achieved by using level crossing technique, where the ADC operates only if there is a significant variation observed in the input signal. It doesn’t produce a sample if there is a long silence or no data available to process.

1.4 Thesis organization

The thesis is organized in various chapters as explained below. Chapter 2 presents comparison of CT and conventional DSP system. Advantages and drawbacks of both the systems are described briefly. Chapter 3 provides mathematical treat-ment, corroborated by MATLAB simulations. The attention is then given to the details of the sub-systems employed in the ED DSP system, ADC, DSP and DAC. Various different architectures are discussed for the three sub-systems and designs suitable for implementation are chosen.

Chapter 4, 5 and 6 elaborates the implementation details of each sub-system CTADC, CTDSP and CTDAC, respectively. Detailed descriptions of various

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ar-10 Introduction

chitectures of the sub-blocks with the simulation results at various design stages are shown.

Chapter 7 presents the CTDSP system top level simulation results. Chapter 8 presents the future work and conclusions.

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Chapter 2

Conventional versus

Event-driven systems

Signal processing is needed to derive the information content present in the sensed real-world signals. The real-world signals are analog in nature, i.e., continuous in time and amplitude. These signals can be processed by using analog or digital signal processing. A mix of both techniques can also be used, which is known as mixed-signal processing [4]. With the advent of digital computers, backed up by large scale integration of the circuits, digital signal processing has revolutionized the world. Conventionally, the digital signal processing is done only in the discrete-time, with the help of a sampling clock. Hence, conventional DSP systems are also known as sampled data systems. Recently, it has been experimentally shown by Tsividis et al. [2, 5], that the signal processing in digital domain can also be performed in Continuous-Time (CT) domain. These systems are called as CT or ED DSP systems.

In this chapter the basic principle of operation of the conventional clocked and CTDSP systems are presented. The level-crossing quantization technique used in the CT system is briefly explained. The advantages and drawbacks of the two systems are outlined. The chapter is concluded with a comparison of the clocked system to the CT system. The future chapters are based on the motivations and conclusions drawn from the discussions presented in this chapter.

2.1 Conventional clocked DSP systems

A conventional DSP system operates with a global reference or clock signal. The input signal, x(t), is sampled-and-quantized at the rising or falling edge of the clock signal for an edge triggered system. The quantized signal is encoded digitally and processed by the subsequent DSP section. The overall system is completely synchronized with respect to the global clock. In the subsequent sections a detailed description of the conventional clocked system is presented.

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12 Conventional versus Event-driven systems

x(t) y_s(t)

clk

Conventional DSP system

Figure 2.1: Block diagram of the conventional clocked DSP system.

2.1.1 Introduction to the conventional clocked DSP systems

For the clocked DSP systems, the frequency of operation, known as the clock frequency, is limited by the Nyquist criteria or sampling theorem, which states that the sampling rate must be greater than twice the bandwidth of the input signal as given by [4]

fs> 2 · fb, (2.1)

where fsis the sampling frequency and fbis the bandwidth or maximum frequency of the input signal. A simple block diagram of the conventional DSP system is shown in figure 2.1 with the input and output signal description given in table 2.1.

As shown in figure 2.2, the conventional clocked DSP system can be further divided into three sub-systems: the ADC, DSP and DAC. The description of the input and output signal is provided in table 2.2.

The ADC is the first block of the DSP system, which samples and quantizes the input signal, x(t), followed by encoding to produce the digital binary data, bi(n). This digitized data is provided to the DSP sub-section, which process it based on the defined functionality, like low-pass, high-pass or band-pass filtering, domain transformation, encryption, etc. The digitally processed data, dj(n), from the DSP section is provided to the output DAC, which reconstructs it back to the analog equivalent, ys(t), where the subscript “s” represents sampled system output.

Table 2.1: Signal description for the conventional clocked DSP system as shown in figure 2.1.

Signal Description Type (Input/ Output)

x(t) Input signal Input

clk Global clock signal Input

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2.1 Conventional clocked DSP systems 13 Table 2.2: Signal description for the conventional clocked DSP system with an ADC-DSP-DAC sub-systems as shown in figure 2.2.

x(t) Input signal Input

clk Global clock signal Input

bi(n)

ADC out to DSP,

Intermediate signal (In/out) Digitally encoded binary signal

dj(n) DSP out to DAC, Intermediate signal (In/out)

Digitally processed binary signal

Ys(t) Output signal Output

2.1.2 Operational details of the conventional clocked DSP

systems

As mentioned in the previous section, the operation of the conventional clocked DSP systems can be classified as sampling and quantization followed by the digi-tization, processing of the binary data by the DSP and the reconstruction of the digital signal to the analog equivalent by the output DAC. These operations are explained in detail in the following sections.

2.1.2.1 Sampling, quantization and digital encoding

As shown in Fig. 2.2, the ADC is the first sub-system of the conventional DSP system, which converts the input signal, x(t), to the digital equivalent, bi(n), where n represents the time in the discrete domain. The complete operation can be divided into two steps:

• Sample-and-hold and quantization, and

• Digitization.

Fig. 2.3(a) presents the sampling operation. The input signal is sampled at regular interval of 1/fs and the samples are held for one cycle. The data samples are quantized to the nearest pre-defined quantization level by the quantizer. This is

x(t) bi(n) ys(t) clk d_j(n) DSP ADC clk clk DAC

Figure 2.2: Conventional clocked DSP system with the basic building blocks ADC-DSP-DAC, each sub-system is controlled through the global clock signal.

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14 Conventional versus Event-driven systems x(t) Quantization level Sampling Instances ti ti-1 t Q ua nt iz at io n le ve ls x(t) xq(t) Quantization level Sampling Instances t ti ti-1 (a) (b) Q ua nt iz at io n le ve ls

Figure 2.3: Conventional clocked DSP system: (a) sampling (shown by black dots in figure), and (b) quantization (xq(t), also known as amplitude quantization).

known as amplitude quantization and is shown in fig. 2.3(b). The quantized data, xq(t), as shown in fig. 2.3(b), is also known as L-ary digital signal, where L is the total number of quantization levels [6].

The L-ary data can be processed directly by the subsequent DSP section, but it is more practical to have binary signal as an input to the DSP section because of the involved simplicity and the ease of processing. Therefore, L-ary, xq(t), is converted to binary signal, bi(n), using the pulse coding technique [6]. Figure 2.4 shows a 3-bit representation b0, b1and b2of the quantized signal, xq(t). In general, N -bit system has N -binary output lines. The above discussion is based on the most widely used modulation technique called the pulse code modulation. There are other modulation techniques like differential pulse code modulation, delta modu-lation, adaptive delta modumodu-lation, etc., which can be employed to have different binary output representation.

The sampling and quantization generates noise floor in the output spectrum of the signal which is explained next [7–9]. Consider a sinusoidal signal with an input frequency, fb, and sampling frequency, fs. The sampling operation forms the replica’s of the input signal at (n · fs± fb), where n is an integer. This multi-tone signal is passed through the quantizer. The quantizer produces the harmonics of each frequency component along with their inter-modulation components. These harmonics and the inter-modulation terms are spread across the spectrum, includ-ing the in-band and hence, resultinclud-ing in the formation of the quantization noise floor. The Signal-to-Noise Ratio (SNR) due to the noise floor is given by the classical formula [10]:

SN R(dB) = 6.02 × N + 1.76, (2.2)

where N is the number of bits or resolution of the ADC.

As mentioned in section 2.1.1, the minimum clock frequency is limited by the Nyquist theorem. If the sampling criterion, given by equation 2.1, is not met,

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2.1 Conventional clocked DSP systems 15 A m pl it ud e t ti-1 t b0 b1 b2 Sampling instances Quantization level x_qt x t ti

Figure 2.4: Conventional clocked DSP system with sampling and quantization and 3-bit digital output representation; b0, b1 and b2.

than the higher frequency components will fold back into the band of interest and corrupt the data. This condition is known as spectral-folding or aliasing. A special filter known as an anti-aliasing filter with cutoff frequency half the sampling frequency (fs/2, also known as the folding frequency) is required to band-limit the input signal, before taking the samples. If an anti-aliasing filter is not used, then any data in the region fs/2 ± fx will be corrupted, where fx is overlapping tail of the spectrum above fs/2. Additional techniques are required to recover the corrupted data, which demands for an extra hardware.

Note: The practical signals are in general time-limited in nature. It means, that the bandwidth of the signal is infinite (time-limited signals have infinite band-width whereas band-limited signals have infinite duration, a practical signal cannot be time-limited and band-limited at the same time [6]). As mentioned above, the sampling results in the formation of the replicas of the original signal and each replica will have tails spread to infinity due to infinite bandwidth. These tails are always folded back to the band of interest, even if the Nyquist criterion is followed.

2.1.2.2 Conventional digital signal processing and reconstruction The input to the DSP section is the digitized binary data, bi(n), from the ADC section. Based on the application, the DSP system can be designed to perform the

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operations like frequency filtering, domain transformations, compression, encryp-tion, etc. The discussion here is based on the filters, which are in general, used to select the frequency band of interest (Low-pass, high-pass, band-pass or band reject). The filter can be Finite-Impulse-Response (FIR) type or Infinite-Impulse-Response (IIR) type, with their transfer function given as [11]:

H (z) = k=0 X M −1 h [k] · z−k, (2.3) H (z) = P (z) D (z) = p0+ p0· z−1+ p1· z−2+ · · · 1 + d0· z−1+ d1· z−2+ · · · , (2.4)

respectively. The digitally processed data, dj(n), is provided to the output DAC which reconstructs it back to an analog equivalent. There are many different architectures of the DAC which can be used like the binary weighted, thermometer-coded, linear-thermometer-coded, hybrid, etc. Based on the speed and resolution of the system, the circuit level realization of the DAC can be done in the voltage-mode, current-mode or charge-redistribution-current-mode. Different implementation schemes like the current-steering, charge-redistribution, R-2R ladder, resistor-string or switched-current algorithmic DAC can be employed for the circuit level design of the DAC [12]. These DACs can be further modified as segmented versions to achieve lesser hardware [13].

The clock frequency, fs, in general, are kept same for the ADC, DSP and the DAC section. But it is possible to design multi-rate systems where different blocks operates at different frequency. It can be done by increasing the data rate using an interpolator (frequency up-converter used before the DAC) and bringing it down by the decimator (frequency down-converter used after the ADC and before providing the samples to the DSP) [11, 14]. The ADC and DAC obtained using these techniques are also known as oversampled data converters. The interpolator and decimator blocks are part of the DSP core.

2.1.3 Advantages of conventional DSP systems

Synchronized DSP system implementation is a vast topic with lot of research effort already put into it, since its inception. Few major advantages of the conventional DSP systems are as follows:

• The main advantage is the ease of designing the system. The sampling clock period is primarily governed by the critical path of the system, which when decided upon can lead to faster implementation of the system.

• Used in many applications for rapid implementation of complex DSP algo-rithms, for example, using general purpose DSP processor or even on general purpose processor.

• Availability of the design tools to synthesize even advanced optimized DSP algorithms on FPGA as well as ASIC designs and automate whole design process of DSP processor.

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2.1 Conventional clocked DSP systems 17

• Since the data available is sampled at particular sampling rate defined by the system, for example, in CD, the audio is sampled at a sampling rate of 44.1 kHz, storage and retrieval of data becomes easier and cheaper.

Few major drawbacks of the conventional clocked systems are discussed in the next section.

2.1.4 Drawback of the conventional DSP systems

The drawbacks of the conventional DSP systems are as described below:

• A sampled system requires clock generator, which has a large fan-out, since it has to drive gates of many transistors. Hence, making it costly to implement, both in terms of the area and power consumption.

• The sampling frequency is decided based on the highest frequency component of the input signal. It is therefore necessary to implement a band-limiting fil-ter, known as an anti-aliasing filfil-ter, to avoid aliasing, whose implementation might also be a costly affair.

• The sampling results in the aliasing of higher frequency terms to the band of interest, even if the Nyquist theorem is followed.

• The sampling and processing of the data with long silence or no change in the signal results in the wastage of power. This can be mitigated using techniques such as clock gating at the expense of additional hardware. This may decrease dynamic power dissipation, but shall add up to the static power consumption of leakage and obvious area ascension. Hence, conventional DSP system is not apt for applications where signals occur in bursts, with high silence percentage, especially for the wireless sensor motes driven by a small battery, demanding large battery lifetime.

• The deviation from the precise sample timing instances due to the clock jitter and the clock skew can cripple down the system performance to undesired levels, if not designed properly.

The signal to be processed by the smart dust module is of burst nature, which occurs occasionally. The clocked systems, although equipped with many advan-tages, are not an ideal choice for processing the burst-like signals. The drawbacks listed for the clocked system are more dominating compared to the advantages for the smart dust application. In the next section event-driven CT digital signal processing systems are discussed, which operates on the principle of level-crossing and are very suitable for burst-type data processing.

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2.2 Continuous-time or event-driven DSP systems

2.2.1 Introduction to the CTDSP systems

The CT or event-driven Digital Signal Processor (DSP) systems, as the name sug-gests, operates in continuous time mode [2, 9]. The input signal, x(t), is processed by the CTDSP system to produce output, y(t). There is no clock involved any-where in the system. A simple block diagram of a CTDSP system is shown in figure 2.5 with the input and output signal description given in table 2.3.

x(t) y(t)

CTDSP system

Figure 2.5: Block diagram of the continuous-time (CT) DSP system.

Table 2.3: Signal description for continuous-time (CT) system as shown in fig-ure 2.5.

x(t) CT input signal Input

y(t) CT output signal Output

Similar to the conventional clocked systems, a CT system can also be divided into three basic sub-systems: the CTADC, CTDSP and CTDAC. As pointed out above, there is no global clock involved anywhere in CTDSP system. Hence, all the three blocks operates in a CT mode and are represented with a prefix CT [7, 15]. Figure 2.6 shows the block diagram of the CTDSP system with the three sub-systems and table 2.4 presents the description of the input and output signals.

CTADC is the first block in the CTDSP system which quantizes and digitizes the input signal, x(t), to a CT output, bi(t). Unlike conventional system, the input signal is not sampled before quantization. The CT data is then processed by the CTDSP sub-system to produce digital data, dj(t), which is reconstructed to analog signal, y(t), by the CTDAC block. Note that the time domain is represented in “t” as it is always continuous in nature.

In the next section operational details of the CTDSP system is presented. The level-crossing approach, as used in CT system, is explained and the advantages and drawbacks are described.

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2.2 Continuous-time or event-driven DSP systems 19 Table 2.4: Signal description for the CTDSP system with the CTADC-CTDSP-CTDAC sub-systems as shown in figure 2.6.

x(t) CT input signal Input

bi(t) ADC output to DSP, Intermediate signal (In/out)

CT digitally encoded binary signal

di(t) DSP output to DAC, Intermediate signal (In/out)

CT digitally processed binary signal

y(t) CT output signal Output

2.2.2 Operational details of the CTDSP system

The CTDSP system adopts nonuniform sampling approach, where samples are generated only when the event crosses predefined quantization reference level. The operation of the CTDSP system can be classified as quantization by the CTADC block and the processing of the digital (continuous) data by the CTDSP sub-system. The next section presents the details of these operations.

2.2.2.1 CTDSP quantization technique: A level-crossing approach A conventional DSP system adopts uniform quantization technique, where samples are taken and processed at every clock cycle. The maximum frequency of the input signal dictates the minimum possible clock frequency of sample generation. However, it turns out that, for signals with burst-like nature and long period of silence, exhaustive sampling is not required as done in conventional systems. The samples generated either contains no information or repetitive information. Further, additional dynamic power is required for the processing of these samples by the DSP section.

A different class of the quantization technique, called a level-crossing sampling scheme, is suggested by Sayiner et al., [16] and further explained by Tsividis in [2, 3, 7]. It is a nonuniform sampling approach, where the samples are generated only when the event crosses the predefined quantization reference level. Since the quantization is based on the event and is continuous in time, it is called as an

x(t) bi(t) dj(t) y(t)

CTDAC CTDSP

CTADC

Figure 2.6: CTDSP system with the basic building blocks CTADC-CTDSP-CTDAC.

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EDCT quantization [3]. The quantization steps can be uniform or non-uniform and can be customized further based on the application.

To understand the CT quantization technique, let’s consider figure 2.7. As shown, the input signal, x(t), when crosses the predefined quantization reference level, get quantized to signal, xq(t), and produces samples (ti, x(ti)). This is a nonuniform sampling operation, where the signals with faster slope generates samples more frequently (“faster”) compared to signals with lesser slopes. Hence, signal-dependent sampling is achieved simply by utilizing the built-in feature of the quantizer. With this approach, the signal with less variation produces lesser number of samples to be processed by the subsequent DSP section; hence resulting in a signal dependant power consumption. This is a clear advantage of the CT systems, making it very suitable for processing burst type signals.

t A m pl it ud e ti ti-1 (ti , x(ti)) x(t) Quantization level xq(t)

Figure 2.7: Level-crossing quantization technique in CTDSP system.

Perhaps the biggest benefit of the CT sampling is its capability to reduce the in-band quantization noise. In the CT systems, there is no sampling invloved and the quantization process introduces only harmonics with no noise floor, as expected in a discrete-time sampled system, as explained in section 2.1.2.1. Also, it is possible to suppress the even-order harmonics by using a mid-tread quantizer, as explained in section 3.1.1. The reduction of the in-band quantization is achieved by the inherent property of the CT system and no special algorithm or hardware is required [2, 3, 7]. Since there are no replica’s of the signal spectrum formed in the CT system, there will be no aliasing effect observed and hence no requirement of the anti-aliasing filter.

2.2.2.2 Processing of CT digital data and reconstruction

The continuous-time digital output, bi(t), of the CTADC block is processed by the CTDSP sub-system. Since the ADC output is digital in nature, the advantages of the digital signal processing can be utilized in the CT system as well. The design approach for the CTDSP system is described in [9]. Based on the transfer function, a conventional DSP system can be realized using multipliers, adders and

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2.2 Continuous-time or event-driven DSP systems 21

delay taps as basic building blocks. A digital signal processor operating in the CT mode can be mapped from the discrete counterpart by replacing these blocks by the one operating in the CT domain. For Example, asynchronous multipliers and adders, which operates without clock, can be used in the CT system. One method of implementing the delay taps is by using chain of inverters. A better approach is presented in [17, 18], where collection of delay cells connected in series are used to delay and hold the data. Handshaking is used between delay cells to ensure proper data transmission. The usage of these delay blocks are experimentally confirmed in [5, 19].

The CTDSP sub-system produces output, dj(t), as shown in figure 2.6, which is reconstructed back to the analog equivalent, y(t), by the CTDAC module. The CTDAC can be realized using architectures and circuit implementation techniques as mentioned in section 2.1.2.2 for the clocked counterpart. The only difference is that the DAC should operate without clock.

In the next section advantages and drawbacks associated with the CT system are presented.

2.2.3 Advantages of CTDSP systems

The advantages of the CTDSP system operating with level-crossing quantization technique are as listed below:

• There is no requirement of the clock generator as the CT systems are driven by the event or the input signal.

• As there is no sampling involved in the CT system, no replicas of the input signal are formed. Hence, there is no requirement of the anti-aliasing filter as required in the case of conventional clocked system.

• The long period of inactivity of the input signal are very well detected by the CT system and it generates no samples if there is no data available in the input to process. Conventional clocked systems produces samples at every clock cycle and need special technique, like clock gating, to stop the clock generator.

• The CT system provides a very fine tracking of the input signal and there is no waiting time for the sample generation as required in the case of conven-tional DSP system. It means, that the CT system responds to any change in the input immediately.

• The CTADC produces continuous-time digital data, and hence the benefits of digital processing can be utilized in the CT mode as well.

• There is a significant reduction in the in-band quantization noise in the CT processing as no inter-modulation terms are generated. Only source of noise are the harmonics created due to the quantization.

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2.2.4 Drawback of CTDSP systems

The CTDSP system has some drawbacks which are mentioned below:

• The major drawback of the CT system is that it provides a very fine tracking of the input signal. As shown in figure 2.8, if the slope of input signal, x(t), which is proportional to input frequency, is very high, it crosses the quantization levels quickly, producing samples at very fast rate. There can be cases when the CT quantizer produces more samples than the conventional DSP system for a given time period. This is a clear disadvantage of the CTDSP system and it imposes a practical limit on the higher frequency of operation of the CT system.

t

A

m

pl

it

ud

e

x(t) Quantization level Sampling Instances

t

i

t

i-1

Figure 2.8: Level-crossing quantization for the input signal with a high slope/ input frequency, quantizer generates faster samples.

• The second drawback of the CT system is, that the samples are generated randomly as it is an event-driven process. Since there is no clock signal involved, it is difficult, but not impossible [9], to store the data for the future use. Hence, CT systems are limited to real time applications, which require no data storage.

• With the lack of the clock signal, it is difficult for the CT system to achieve required synchronization for data flow from one block to the another and the system requires excessive hand shaking, which makes the design complex. The advantages and drawback of the CTDSP system are presented above. For a continuously changing signal, the samples generated by the CTDSP system are higher compared to the conventional clocked system. But for the burst-type signals, which remains idle for most of the time, the CT system generates lesser samples compared to its counterpart. Hence, CTDSP system is ideal for processing burst type signals.

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2.2 Continuous-time or event-driven DSP systems 23 T able 2.5: Con v en tional DSP v e rsus CTDSP: A comparison. S.no Comparison poin t Con v en tional DSP system CTDSP system Whic h tec hnique is b etter 1 Hardw are require-men t A dditional hardw are is required for clo ck signal generator and an ti-aliasing filter and p ossibly clo ck gating Lesser hardw are as no requir e-men t of clo ck signal gen erator and an ti-aliasing filter CTDSP 2 Noise Sampling and quan tization in tro-duces in band quan tization noise flo or Only harmonics are pro duced due to quan tization, hence less er noise flo or CTDSP 3 Design complexit y Design is simple compared to CT system as ev er ything is sync hro-nized to global clo ck Difficult to design as it requires lot of async hronous and timing con trol due to lac k of clo ck signal Con v en ti onal 4 Area Easy to design in mm 2 range with curr en t arc hitecture in 65nm CMOS tec hnology P ossible to design in mm 2 range with curren t arc hitecture in 65nm CMOS tec hnology Both 5 P o w er consumption Con tin uous p o w er c onsumption if sp ecial tec hniques are not em-plo y ed to stop clo ck wh en no si g-nal is p resen t P o w er consumption is ev en t-driv en as the ADC generates no samples when there is no input CTDSP 6 Signal pro cessing Signal is con v erted to digital and is easy to pro c ess CT signal is in digital format and can b e pro cessed digitally Both

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2.3 Conventional DSP versus CTDSP: A

com-parison

The above discussion about the conventional clocked DSP system and the CTDSP system can be used to make a comparison between the two with respect to the requirement for the smart dust project. It is assumed that the input signal is of burst nature, which occurs occasionally. Also, the conventional clocked systems considered are Nyquist rate systems without any over-sampling. Table 2.5 presents a comparison between the two systems.

2.4 Conclusion

It can be observed that other than the design complexity, the CTDSP system is either a better option or almost equivalent to the conventional clocked systems for processing the burst-type signals for the smart dust. Hence, it is concluded that the CTDSP system is preferred over the conventional clocked systems. Based on the above discussion and comparison made for the conventional and CTDSP system, the CTDSP is selected for designing the required DSP system as a part of this project.

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Chapter 3

Sub module details for the

CTDSP systems

In this chapter functional detail of the three sub-modules, the CTADC, CTDSP and CTDAC of the ED DSP system is presented. Various possible architectures of the sub-modules are discussed and compared with respect to their advantages and drawbacks. The chapter is concluded with the architecture selection for each sub-module which are used in this design.

3.1 Event-driven ADC

The first module in the ED DSP system is the CTADC or the ED ADC. It converts the analog input signal, x(t), provided by the Analog Interface (AI) to CT digital binary output signal, bi(t). A block diagram of the AI and the CTADC is shown in figure 3.1. The AI section consists of a sensor network and an analog filter. The sensor network detects the variation in the input signal (temperature, pressure, humidity , etc. based on the application) and converts it to the electrical signal. The analog filter limits the frequency of the input signal to the operating range of the ADC.

The AI is designed based on the overall specification defined for the smart dust module, for e.g., the sensor interface is selected based on the application and the cutoff frequency of the analog filter is selected based on the frequency of operation

x(t) b_i(t)

Input variations

Analog

Interface CTADC

Figure 3.1: Block diagram of AI and CTADC.

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26 Sub module details for the CTDSP systems

of the system. The design of the AI block is out of scope of this project and it is assumed that the frequency of operation and the operating range of the input signal for the CTADC are taken care by this block. Few constraints that has to be taken care for the design of the input filter of AI are discussed in section 3.2.2. As illustrated in figure 3.1, the AI provides a CT signal, x(t), to the CTADC block. The CTADC consists of a CT quantizer and an encoder, which digitize the signal to, bi(t). The digital output, bi(t), is continuous in time and can be represented in many ways depending on the deployed ADC architecture [3].

The input-output characteristics of the quantizer can be either a mid-tread or mid-rise type. A comparison of the two type of quantizer is presented in sec-tion 3.1.1. Secsec-tion 3.1.2 explains the properties of the mid-tread quantizer. A detailed explanation of the level crossing technique used in the CTADC is elabo-rated in section 3.1.3. The time domain behavior and frequency response of the CT quantizer is explained in section 3.1.3.1. In section 3.1.4 few potential ADC architectures are discussed followed by summary of CTADC in section 3.1.5.

3.1.1 Mid-tread vs mid-rise quantizers

Figure 3.2a and 3.2b shows the respective input-output characteristic of the 3-bit mid-tread and mid-rise quantizers. An N -bit mid-tread and mid-rise quantizers have (2N _{− 1) and 2}N _{quantization levels , respectively, where N is the resolution} of the ADC. The mid-tread quantizer has an odd number of quantization levels and the center-most level is set to the zero level, making it odd-symmetric across the origin. The mid-rise quantizer has an even number of output levels and to maintain the odd-symmetricity in the input-output characteristics, the two center most levels are placed at a distance of ±∆/2 from the origin, where ∆ is the quantization step, and ∆/2 is 1/2 LSB.

Input O ut pu t  2  3  − −2  −3

(a) mid-tread quantizer.

 /2 3 / 2 5 / 2 7 /2 −3/2 −/2 −5/2 −7 /2 Input O ut pu t (b) mid-rise quantizer.

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3.1 Event-driven ADC 27

Since one of the output quantization level of the mid-tread quantizer is always set to zero, small variations due to noise less than ±∆/2 are not picked by the system. Whereas, in the mid-rise quantizers, any variations above ±∆/4 gets quantized to the nearest quantization level located at ±∆/2. Hence, it can be observed that small variations in the input signal do not trigger the mid-tread quantizers and hence, no samples are generated at the output of the quantizer. The generation of the lower samples results in lower processing in the subsequent DSP section. Hence, better noise immunity and power saving can be achieved just by the use of mid-tread type quantizers. Also, the odd-symmetric input-output characteristics of the mid-tread quantizer ensures that the even order harmonics are suppressed in the output. This reduces the in-band quantization noise gener-ated by the quantizer giving better Signal-to-Noise and Distortion Ratio (SNDR). As low power consumption without any compromise to the SNDR is the major requirement for the smart dust application, the mid-tread quantizers are preferred over the mid-rise quantizers as the former provides the better noise immunity, SNDR and power saving compared to the mid-rise quantizers.

3.1.2 Properties of mid-tread quantizers

Figure 3.3 illustrates the detailed input-output characteristics of the mid-tread quantizer. The input and output ranges are normalized to [−1, 1]. As mentioned in the previous section, the total output quantization levels in mid-tread quantizers are (2N − 1). Hence for N = 3, only 7 quantization levels are present [15].

1 -1 Skipped level -x_max x_max 1 -1 Input output  

Figure 3.3: Input-output characteristic of the 3-bit mid-tread quantizer with input and output normalized to [-1,1] [19].

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28 Sub module details for the CTDSP systems

The maximum amplitude of the input signal that maintains the required odd-symmetry and the corresponding step size, ∆, are given by equations 3.1 and 3.2, respectively, as xmax= 1 − 1 2N, (3.1) ∆ = 1 2N −1. (3.2)

The number of steps above level zero, as mentioned in [15], is given by equation 3.3

Nstep= min 2N −1− 1, A + 0.5 · ∆ ∆ , (3.3)

where A is the amplitude of the input signal. min() represents “minimum of ” and ensures that the result is bounded even if the input is out of range.

The more generic forms of equations 3.1 and 3.2 can be given by equations 3.4 and 3.5 as xmax= VT op− Vref 2N +1, (3.4) ∆ = Vref 2N , (3.5)

where VT op is the maximum reference voltage and Vref is the difference between the maximum and the minimum reference voltages given by

Vref = VT op− VBot, (3.6)

where VBotis the minimum reference voltage.

In the next section a level-crossing sampling approach for the CTADC is pre-sented.

3.1.3 Level-crossing sampling for the CTADC

As described in section 2.2.2.1, the CTADC adopts a level-crossing sampling tech-nique. In this section a detailed description of the level-crossing quantization technique is presented.

Figure 3.4 shows the quantization procedure in the CTADC. When the input signal, x(t), crosses a quantization reference level, it gets quantized to the near-est quantization level based on the direction of the input signal. The quantized signal, xq(t), as shown in figure 3.4, is continuous in time and the samples are represented as (ti, x(ti)), where ti−1 and ti represent the time instances of the sample generation, respectively. The quantized signal, xq(t), can be digitized in many ways [3], like the CT binary bits in a flash ADC or by using data token consisting of change and direction (increment/decrement) as in DM [15]. The former approach is illustrated in figure 3.4, where b0, b1 and b2 are the CT binary signals.

The level-crossing sampling is a nonuniform sampling operation, where the faster signals with higher slopes generate samples more frequently (“faster”) com-pared to signals with lower slopes. Hence, a signal-dependent sampling is achieved

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3.1 Event-driven ADC 29 b0 b1 b2 t t A m pl it ud e ( t_i,x(t_i)) Quantization level x_qt x t ti ti-1

Figure 3.4: Level-crossing quantization in the CTADC with 3-bit CT digital output representation; b0, b1and b2.

simply by utilizing the built-in feature of the quantizer. It means, that an input signal with lower variation generates lower number of samples to be processed by the subsequent DSP section, hence achieving lower dynamic power dissipation.

3.1.3.1 Amplitude quantization in the CTADC

As shown in figure 3.4, and as explained in section 3.1.3, the quantized signal, xq(t), is generated when the input signal crosses the predefined quantization reference levels. This process is called as amplitude quantization, which is obtained simply by utilizing the inherent behavior of the quantizer. An important point to note here is that the sample taken at the instance, ti, is exactly the same as the input signal at that instance, unlike the discrete-time signals, where the quantized value depends on the sampling instance and quantization levels.

3.1.3.2 Time and frequency domain analysis of the CTADC quantizer The time and frequency domain analysis of the CTADC is presented next. To make a comparison, the clocked systems operated at Nyquist rate are considered.

A Continuous-Time ADC and DSP for Smart Dust

Institutionen för systemteknik

Department of Electrical Engineering

Examensarbete

A Continuous-Time ADC and DSP for Smart Dust

A Continuous-Time ADC and DSP for Smart Dust

Examensarbete utfört i Elektroniksystem

vid Tekniska högskolan i Linköping

av

Abstract

Acknowledgments

Contents

List of Figures

List of Tables

Acronyms

Chapter 1

Introduction

1.1

Smart dust: A brief introduction

1.2

Smart dust: specification

1.3

Continuous time processing

1.4

Thesis organization

Chapter 2

Conventional versus

Event-driven systems

2.1

Conventional clocked DSP systems

2.1.1

Introduction to the conventional clocked DSP systems

2.1.2

Operational details of the conventional clocked DSP

systems

2.1.3

Advantages of conventional DSP systems

2.1.4

Drawback of the conventional DSP systems

2.2

Continuous-time or event-driven DSP systems

2.2.1

Introduction to the CTDSP systems

2.2.2

Operational details of the CTDSP system

2.2.3

Advantages of CTDSP systems

2.2.4

Drawback of CTDSP systems

t

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t

t

2.3

Conventional DSP versus CTDSP: A

com-parison

2.4

Conclusion

Chapter 3

Sub module details for the

CTDSP systems

3.1

Event-driven ADC

3.1.1

Mid-tread vs mid-rise quantizers

3.1.2

Properties of mid-tread quantizers

3.1.3

Level-crossing sampling for the CTADC