Design of Pipelined Analog-to-Digital Converter with SI Technique in 65 nm CMOS Technology

(1)

Institutionen för systemteknik

Department of Electrical Engineering

Examensarbete

Design of Pipelined Analog-to-Digital Converter

with SI Technique in 65 nm CMOS Technology

Examensarbete utfört i Elektroniksystem vid Tekniska högskolan vid Linköpings universitet

av

Dinesh Babu Rajendran

LiTH-ISY-EX--11/4489--SE

Linköping 2011

Department of Electrical Engineering Linköpings tekniska högskola Linköpings universitet Linköpings universitet SE-581 83 Linköping, Sweden 581 83 Linköping

(2)

(3)

Design of Pipelined Analog-to-Digital Converter

with SI Technique in 65 nm CMOS Technology

Examensarbete utfört i Elektroniksystem

vid Tekniska högskolan i Linköping

av

Dinesh Babu Rajendran

Handledare: Supervisor

Dr. Mark Vesterbacka, Linköpings universitet

Examinator: Examiner

Dr. Jacob Wikner, Linköpings universitet

(4)

(5)

Avdelning, Institution

Division, Department

Division of Electronics Systems Department of Electrical Engineering Linköpings universitet

SE-581 83 Linköping, Sweden

Datum Date 2011-08-22 Språk Language ¤ Svenska/Swedish ¤ Engelska/English ¤ £ Rapporttyp Report category ¤ Licentiatavhandling ¤ Examensarbete ¤ C-uppsats ¤ D-uppsats ¤ Övrig rapport ¤ £

URL för elektronisk version

http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-70579

ISBN

—

ISRN

Serietitel och serienummer

Title of series, numbering

ISSN

—

Titel

Title

Design av Pipelinad Analog-till-Digital omvandlare med SI-teknik i 65 nm CMOS-teknologi

Design of Pipelined Analog-to-Digital Converter with SI Technique in 65 nm CMOS Technology

Författare

Author

Dinesh Babu Rajendran

Sammanfattning

Abstract

Analog-to-digital converter (ADC) plays an important role in mixed signal cessing systems. It serves as an interface between analog and digital signal pro-cessing systems. In the last two decades, circuits implemented in current-mode technique have drawn lots of interest for sensory systems and integrated circuits. Current-mode circuits have a few vital advantages such as low voltage operation, high speed and wide dynamic ranges. These circuits have wide applications in low voltage, high speed-mixed signal processing systems. In this thesis work, a 9-bit pipelined ADC with switch-current (SI) technique is designed and implemented in 65 nm CMOS technology. The main focus of the thesis work is to implement the pipelined ADC in SI technique and to optimize the pipelined ADC for low power. The ADC has a stage resolution of 3 bits. The proposed architectures combine a differential sample-and-hold amplifier, current comparator, binary-to-thermometer decoder, a differential current-steering digital-to-analog converter, delay logic and digital error correction block. The circuits are implemented at transistor level in 65 nm CMOS technology. The static and dynamic performance metrics of pipelined ADC are evaluated. The simulations are carried out by Cadence Virtuoso Spectre Circuit Simulator 5.10. Matlab is used to determine the performance metrics of ADC.

Nyckelord

Keywords Pipelined Analog-to-Digital Converter, Sample and Hold Amplifier, Comparator, Current-Steering Digital-to-Analog Converter, Binary to Thermometer Decoder

(6)

(7)

Abstract

Analog-to-digital converter (ADC) plays an important role in mixed signal cessing systems. It serves as an interface between analog and digital signal pro-cessing systems. In the last two decades, circuits implemented in current-mode technique have drawn lots of interest for sensory systems and integrated circuits. Current-mode circuits have a few vital advantages such as low voltage operation, high speed and wide dynamic ranges. These circuits have wide applications in low voltage, high speed-mixed signal processing systems. In this thesis work, a 9-bit pipelined ADC with switch-current (SI) technique is designed and implemented in 65 nm CMOS technology. The main focus of the thesis work is to implement the pipelined ADC in SI technique and to optimize the pipelined ADC for low power. The ADC has a stage resolution of 3 bits. The proposed architectures combine a differential sample-and-hold amplifier, current comparator, binary-to-thermometer decoder, a differential current-steering digital-to-analog converter, delay logic and digital error correction block. The circuits are implemented at transistor level in 65 nm CMOS technology. The static and dynamic performance metrics of pipelined ADC are evaluated. The simulations are carried out by Ca-dence Virtuoso Spectre Circuit Simulator 5.10. Matlab is used to determine the performance metrics of ADC.

(8)

(9)

Acknowledgments

I am extremely grateful and I thank Professor Mark Vesterbacka for proposing such an interesting topic and supervising me in this thesis work.

I would like to take this opportunity to thank my examiner Dr. Jacob Wikner for his valuable guidance.

I am thankful to my parents and brother for their love, support and prayers. I would like to thank Anusuya for her love, kindness, patience, encouragement and motivation throughout the master programme.

Finally, I thank all my friends for their support.

(10)

(11)

Introduction

1.1 Analog-to-Digital Converter

As signal processing is widely used in various fields, the problem of dealing with both analog and digital signals is common. Data converters serve as an interface between the analog and digital world. An analog-to-digital converter (ADC) is a device used for interfacing the analog and digital domains. The ADC converts an analog signal into a digital code. To be more specific, it converts a continuous-time, continuous-amplitude signal into a discrete-continuous-time, discrete-amplitude signal. This can be considered as a two step process, i.e., sampling the analog signal and quantizing the sampled value.

Current-mode ADCs when compared with voltage-mode ADCs are much more in practise in modern day analog world. Current-mode ADCs have several ad-vantages when compared with voltage-mode ADCs. The circuit implemented in current-mode technique consumes low power, occupies less area, has high speed and less dynamic range. Thus the circuit designed in current-mode technique has gained interest in the past two decades [4].

ADCs play an important role in modern communication systems and signal pro-cessing. ADCs serve many applications based on speed and power consumption. There are several architectures of ADCs which are used for various applications. Flash ADCs, Sigma Delta ADCs, Successive Approximation (SAR) ADCs and Pipelined ADCs are few among the types of ADCs. Flash ADCs are extremely fast when compared to other ADCs. Successive Approximation ADCs and Sigma Delta ADCs are applicable for low power applications. The pipelined ADC, which has high speed, medium-high resolution and low power consumption seems to be the best ADC architecture with the standard CMOS implementation. Therefore it is used extensively in high-quality video systems, high-speed data acquisition systems and high performance digital communication systems where both preci-sion and speed plays a vital role. An ADC can be characterized by the number of bits it can produce over a range of input signal called resolution. An ADC with

N -bit resolution can encode an analog signal into 2N _{levels. The ADC resolution}

(18)

6 Introduction limits the accuracy of a measurement. The higher the resolution (number of bits), the more accurate the measurement.

1.2 Objective of Thesis

In this thesis work, a 9-bit current mode pipelined ADC with switching current (SI) technique is proposed. The goal of the thesis work is to design a pipelined ADC for low power consumption applications. The proposed pipelined ADC is designed in 65 nm CMOS process technology. Based upon the simulation results, the ADC achieves a SINAD of 52.8 dB, SFDR of 71.7 dB and ENOB of 8.48 bits at 100 MHz sample rate with 1.2 V power supply voltage.

1.3 Thesis Organization

The thesis work is documented as shown below.

• Chapter 2 gives a brief description about the performance metrics of ADC.

• Chapter 3 explains about different ADC architectures.

• Chapter 4 presents the implementation of the proposed pipelined ADC in transistor level.

• Chapter 5 shows the performance of ADC based on simulation results.

• Chapter 6 draws conclusions on this work

(19)

Chapter 2

ADC Performance Metrics

The performance metrics of ADCs are explained in this chapter.

2.1 Static Performance Metrics

Static errors are deviation of the ADC transfer characteristic from ideal one. The following metrics helps in understanding the static performance of an ADC.

2.1.1 Offset Error

Offset error [1] is the difference between the first measured transition point and the first ideal transition point. Offset error is also known as Zero Scale Error or

Zero Scale Offset Error. This error can be positive when the first transition point

is higher than ideal or negative when the first transition point is lower than ideal. The offset error of an ADC is shown in figure 2.1 and 2.2.

Figure 2.1: Transfer Curve of an ADC for an Offset Error [1] 7

(20)

8 ADC Performance Metrics

Figure 2.2: Offset Error [1]

2.1.2 Full-Scale Error

In an ADC, the full-scale analog input causes a transition that may differ from the ideal value. Full Scale Error [1] is the difference between the actual full-scale output transition point and the ideal value. Full-scale error occurs because of the offset voltage and error in the slope of the transfer function. Full-scale error is also known as Full-Scale Offset Error and is expressed in terms of an ideal full-scale input. The full-scale error of an ADC is shown in figure 2.3 and 2.4.

(21)

2.1 Static Performance Metrics 9

Figure 2.4: Full-Scale Error [1]

2.1.3 INL

INL [1] is the difference between the ideal code transition point and that of an actual code transition point. The integral non linearity error representation shows the sum of the DNL errors. The figure 2.5 shows the INL error.

Figure 2.5: Integral Non-Linearity [1]

2.1.4 DNL

DNL [1] is the difference between the actual input code width and that of an ideal code. Input code width is a range of given input values that produces the corresponding digital output code. In general, the difference between the ideal 1 LSB and the actual 1 LSB step is very small. The DNL error is shown in the figure 2.6.

(22)

10 ADC Performance Metrics

Figure 2.6: Differential Non-Linearity [1]

2.2 Dynamic Performance Metrics

Static errors do not include any information about noise and high frequency effects. Static error is tested by a DC signal. Dynamic error provides additional informa-tion of ADC performances such as SNR, SFDR, SINAD and ENOB. Dynamic error is tested with a periodic waveform.

2.2.1 SNR

Signal-to-Noise Ratio [1] can be defined in terms of amplitude as the ratio of output signal amplitude to output noise level. At higher input slew rates, the accuracy of the comparator(s) in the ADC degrades. As a result of this, the SNR tends to degrade as the frequency increases. SNR of an ADC with full-scale sine wave input is mathematically expressed as in equation 2.1 and 2.2.

SNR = 20 ∗ log(2(n−1)∗√6) (2.1)

SNR = (6.02n + 1.76)dB (2.2)

2.2.2 SFDR

Spurious Free Dynamic Range, well known as SFDR is defined as the ratio of the value of the desired output signal and the value of the highest spur. The spur is generally an harmonic of the input tone. In general SFDR [1] is measured in terms of dBc (with respect to carrier frequency amplitude) or in dBFS (with respect to ADC full-scale range).

(23)

2.2 Dynamic Performance Metrics 11

2.2.3 SINAD

Signal-to-Noise And Distortion (SINAD) can also be referred to Signal-to-Noise and Distortion Ratio (SNDR) or Signal-to-Noise Plus Distortion (S/N+D). SINAD [1] is a combination of SNR and THD specifications. SINAD is defined as the root mean square value of the output signal to the root mean square value of all of the other spectral components which are below half of the clock frequency, including harmonics but excluding dc. As it compares all undesired frequency components with the input frequency, it is said to be an overall measure of ADC dynamic performance. Mathematically, SINAD is expressed as in equation 2.3.

SINAD = 10 ∗ log[ 1

(10(−SN R/10)_{+ 10}(T HD/10)₎] (2.3)

2.2.4 ENOB

ENOB [1] known as Effective Number Of Bits or Effective Bits is another specifi-cation that helps in measuring the dynamic performance of ADC. The resolution of the ADC is usually specified in terms of bits that represents the analog value. ENOB specifies that the ADC is equivalent to N bits as far as SINAD is concerned. That is, a converter with an ENOB of 7.0 has the same SINAD as a theoretically perfect 7-bit converter. Mathematically, ENOB can be calculated as shown in equation 2.4.

ENOB = SIN AD − 1.76

(24)

(25)

Chapter 3

ADC Architectures

3.1 Flash ADC

Flash ADCs are much faster when compared to other types of ADCs. A Flash ADC [2] uses a bank of comparators and a linear voltage ladder which is used to compare the input voltage with consecutive reference voltages. The reference ladder is generally made from resistors. Flash ADCs are also known as Direct-Conversion ADCs. The output of the comparators are fed as an input to the digital encoder which helps in converting the inputs into corresponding binary values. For an N -bit conversion, a Flash converter requires 2N _{− 1 comparators. The block}

diagram of an N -bit flash ADC is shown in figure 3.1.

Figure 3.1: Block Diagram of an N -bit Flash ADC [2] 13

(26)

14 ADC Architectures Flash ADCs are useful for applications requiring very large bandwidth. In general, Flash ADCs consume more power than other ADC architectures and are limited to 8-bits (255 comparators) resolution. The number of comparators can be reduced by using a folding circuit. In such a circuit, a comparator is used multiple times other than using it only once as in the case of Flash ADC. Flash ADCs have a sample rate in terms of GHz and are used in wide band radio receivers, optical communication links and radar detection.

3.2 Successive Approximation ADC

A successive approximation ADC consists of a Sample and Hold (SH) circuit, a comparator, Digital-to-Analog Converter (DAC) and Successive Approximation Register (SAR).

Figure 3.2: Block Diagram of a SAR ADC [2]

The sample-and-hold circuit helps in keeping the input signal constant during the conversion time. Initially, the input voltage is sampled. The registers are then reset to zero. Conversion takes places in the next step. The MSB is set to 1 by SAR. Digital information is then converted to an output voltage by a DAC. The output voltage is usually half of the reference voltage Vref. The comparator

compares the output voltage with that of the input voltage. If the input voltage is larger than the output voltage, the output is one, or else, the output is 0. The comparator result is loaded in SAR and the value of MSB is registered. The SAR generates the next approximation and the conversion goes on until the LSB has been decided. N clock cycles per conversion are needed for an N -bit SAR ADC. SAR ADC consumes less power than a flash ADC and it is well known for its simple structure. However, it is not suitable for higher resolution as the linearity of DAC increases with increase in resolution. SAR ADCs serves a wide range of applications and are used in portable/battery powered instruments, data/signal acquisition, industrial controls and pen digitizers [2].

(27)

3.3 Sigma Delta ADC 15

3.3 Sigma Delta ADC

In a Sigma-Delta ADC [2], an analog signal is fed as an input to an integrator. The integrator produces a rate-of-change in the voltage or a slope at its output corresponding to its input magnitude. The output voltage is then compared with ground potential by a comparator.

The comparator acts as a 1-bit ADC which produces a 1-bit output (0 or 1) depending upon positive or negative output from the integrator. The output of the comparator is fedback through the 1-bit DAC. The 1-bit DAC creates an average output voltage at the rate of Kfs, where K is a constant and fs is the

sampling frequency. The average voltage is then forced to be equal to the input voltage at the summing point. The number of “ones” in the serial bit stream increases when the input voltage increases towards +Vref, whereas the number

of “zeros” in the serial bit stream increases when the input voltage goes towards

−Vref.

The decimator and the digital filter process the bit stream and produce the final output. This type of ADC is well known for its high accuracy and low cost. The drawbacks of sigma-delta ADC is its moderate speed and complexity in the design of digital filters. This type of ADC is used widely in applications that require high resolution output as in high-fidelity audio and industrial measurements.

(28)

16 ADC Architectures

3.4 Pipelined ADC

A block diagram of 12-bit pipelined ADC [2] with four stages and each stage producing a 3-bit output is shown in figure 3.4.

The sample-and-hold (SH) circuit samples and holds the input Vin. The flash

ADC converts the signal into a 3-bit digital code which is fed into the sub-DAC. The analog output from the sub-DAC is then subtracted from the input voltage. The signal is amplified by a factor of 4 and is given as an input to the next stage. A 4-bit flash ADC which is placed after the fourth stage produces the 4 least significant bits. As the sub-ADC in each stage produces the output at different instances, it is necessary to have timing correction so that all the bits are fed at one instant to the digital error correction block. Pipelining technique helps in increasing the throughput of the system.

Figure 3.4: Block Diagram of 12-bit Pipelined ADC [2]

Pipelined ADCs have high resolution and very good sampling rate. It is widely used in medical and telecommunication applications. The benefits of pipelined ADCs are less power consumption, high speed and high resolution. It is because of these advantages, pipelined ADCs are considered as one of the best ADC archi-tectures.

(29)

3.5 Comparison Between ADC Architectures 17

3.5 Comparison Between ADC Architectures

Table 3.1 shows the comparison of resolution, speed/sample rate and power con-sumption between different types of ADC architectures. Pipelined ADC has a very good resolution with high sample rate and low power consumption. The circuit designed in current-mode technique has gained interest in the past two decades. Current-mode ADCs are implemented widely in modern day mixed signal pro-cessing systems. Current-mode ADC circuits have more vital advantages when compared with ADC circuits implemeted on voltage-mode. The circuit imple-mented in current-mode technique occupies less area, has high speed, consumes low power and less dynamic range [4]. Thus the current mode pipelined ADC has been chosen, designed and implemented in this thesis work.

Table 3.1: Comparison between ADC Architectures

Flash ADC SAR ADC Sigma Delta ADC Pipelined ADC Resolution limited to 8 bits 8 to 16 bits >=16 bits 8 to 16 bits Speed/Sample Rate extremely fast <=5MSps <=1MSps >=500MSps Power Consumption high low low low

(30)

(31)

Chapter 4

Design and Implementation

of Current-Mode Pipelined

ADC

4.1 Proposed Architecture of Pipelined ADC

In this section, the proposed architecture of pipelined ADC based on switched current technique is discussed. Each stage consists of a differential SHA, sub-ADC comprising of a current comparator, a binary-to-thermometer decoder and a differential current-steering DAC.

S&H

ADC

DAC

Stage

2 Stage

n

Stage 1

A

_in

clk

D

₁

D

₂

D

_n

γ

Figure 4.1: Proposed Architecture of Pipelined ADC

(32)

20 Design and Implementation of Current-Mode Pipelined ADC

4.2 Design of Sample-and-Hold Amplifier(SHA)

4.2.1 Basic Principle

The basic principle of Sample-and-Hold (S/H) circuit [5] is to sample the analog input. The sampled input is then held for a certain time. The analog input signal is sampled and held by turning ON and OFF the switch. The switch is controlled by a clock signal. Sample-and-hold is also known as Track-and-Hold as the analog input is tracked in one phase of the clock and the tracked input is held constant in another phase of the clock. A basic sampling circuit is shown in the figure 4.2. The capacitor begins to charge to the input signal level when the switch closes.

Figure 4.2: Simple Sample-and-Hold

The tracked input is present at the output when the switch is closed. In general, the input signal is tracked during the positive half cycle of the clock. The tracked input is held stable during the negative half cycle of the clock. A MOS transistor could be used as a replacement for the switch in order to implement a simple sample-and-hold amplifier. However, capacitor can not be charged completely in a finite time to that of an input level. The on-resistance of the switch determines the speed of the sampling circuit based on switch capacitor. A small capacitor is used to achieve high speed.

4.2.2 Complementary Switch

With increase in the input voltage, the on-resistance of NMOS is increased and that of a PMOS is decreased. Hence it is better to use a complementary switch [6] as shown in figure 4.3. If the NMOS and PMOS in a complementary switch is not turned OFF simultaneously, distortion occurs in the sampled value.

(33)

4.2 Design of Sample-and-Hold Amplifier(SHA) 21

Figure 4.3: Complementary Switch

4.2.3 Error Sources in S/H Circuit

In general, when the MOS transistor is switched OFF, three types of error phe-nomenons occur in the operation of a MOS transistor [5].

4.2.4 Thermal Noise

Thermal noise [5] is also known as kT/C noise. The on-resistance of the switch is the cause of the thermal noise and it occurs at the output of the sample-and-hold circuit. The noise gets stored in the sampling capacitor with the value of the input voltage. Thermal noise can be made negligible by using large capacitors at the cost of speed.

4.2.5 Clock Feed-Through

The sampling capacitor is coupled to the clock’s transition through the gate-source or gate-drain overlap capacitance as shown in the figure 4.4. As a result of this coupling, an error voltage is induced on the sampling capacitor during the OFF state of the switch. The coupling to the sampling capacitor has to be handled though the coupling towards the input is neglected. The error is independent of the analog input level. Hence, the effect is almost equal to a constant offset at the input and as well as at the output. In order to compensate the coupling error, an additional time is provided because of slower gate voltage transition. Thus the clock feed-through error [5] can be made smaller and a trade-off between precision and speed occurs.

4.2.6 Channel Charge Injection

A channel exists beneath the gate when the switch is ON state. The charge beneath the gate exists through the terminals of drain and source when the switch is closed. This phenomenon is known as channel charge injection. As a result of the channel charge injection, the ideal sampled value at output is deviated. The channel charge injection error is directly proportional to the product of oxide capacitance, length

(34)

22 Design and Implementation of Current-Mode Pipelined ADC and width of the transistor. The error is inversely proportional to the capacitor value. Charge injection contributes [5] to non-linearity, DC offset and gain error in the CMOS sampling circuits. DC offset and gain error could be corrected but not non-linearity. The channel chrage injection is shown in the figure 4.5.

Figure 4.4: Clock Feed-Through

(35)

4.2 Design of Sample-and-Hold Amplifier(SHA) 23

4.2.7 Design of SHA

A current-mode differential sample-and-hold circuit is shown in figure 4.6. The differential circuit produces less distortion when compared with that of a single ended circuit. The proposed SHA is implemented at transistor level with low power transistors.

(36)

4.3 Design of Current Comparator

4.3.1 History of Current Comparator

This section focuses on the design of a fast and 1ow power current compara-tor. The first CMOS current comparator was proposed by K. Current and D. Freitas [7]. Later, many high performance current comparators were proposed. A simple and high-speed current comparator in was proposed by H. Traff [8]. The Traff’s comparator output swing could not reach the power supply rails. It is more appropriate to use the comparator proposed by Traff as an input stage rather than a comparator. An offset compensated current comparator was pro-posed by G. Palmisano and G. Palumbo. This comparator helps in compensating the offset-current due to process mismatch. The operating speed was reduced by the compensation capacitors used in the design. The manufacturing cost was in-creased by the use of capacitors. A switched current comparator proposed by V. Boonsobhak, A. Worapishet and J.B. Hughes [8] operated at a sampling frequency of over 100 MHz with 7.5 bit resolution. The offset was not considered and the power efficiency was also low compared to the small input current range.

4.3.2 Ideal Current Comparator

An ideal current comparator is a device that is able to do two main things excep-tionally well. Once a signal is fed as an input, it can react to the signal instantly. The output reaches its peak at the same time the device reacts to the input signal. In analogue and mixed signal systems, the current comparator is one of the key circuits. Though the input signal is current, the circuit does not operate entirely in current-mode as it produces a digital logic or rail-to-rail voltage signal at the output. Obviously there is a prerequisite to transform the input current to a volt-age signal. Therefore, to design a high speed current comparator, voltvolt-age swing should be carefully considered as it directly determines the propagation delay.

4.3.3 Basic Current Comparator

Current-mode comparators [9] are basic building blocks for non-linear ADCs and current-mode signal processing. The large current ranges are an interesting feature for both the above mentioned fields. The detection of efficient small current level is one of the fundamentals for high speed operation in high resolution applications. An example of a current comparator is shown in the figure 4.7.

The comparator consists of two inverters. The output of the first inverter is fed as an input to the second inverter. At the input of the first inverter, the reference current is added to the signal in order to create the difference current, Idif f. The

differential current could be positive or negative which causes the charging of the input of the first inverter. The second inverter is driven by the output of the first inverter thus causing the output of the comparator to go near to Vdd(supply

volt-age) or GN D, depending on whether the difference current is positive or negative. The input to the comparator is the gate of an NMOS and a PMOS transistor. The

(37)

4.3 Design of Current Comparator 25 traditional ratio of PMOS to NMOS sizing for an inverter is 2:1. The input capac-itance could be calculated based on this ratio and it is found to be 3Cgnmos. The

input capacitance varies depending upon the process we use. Assuming that the input of the device to be purely capacitive, the settling time at the input which is proportional to the difference current is worse when Iin is not equal to Iref,

though the gain of the circuit is good. The settling time is at its worst when Iin

is equal to Iref such that the difference current, Idif f=0. If the input capacitance

is reduced to zero, the settling time would improve significantly.

Figure 4.7: Schematic of Basic Current Comparator

4.3.4 Operation of Trio-Current Comparator

Comparators used in most of the signal-processing applications involve the detec-tion of multiple thresholds [10]. A multiple comparator circuit is implemented in this thesis work. The figure 4.8 shows three simple current comparators. The out-put of each comparator is in turn connected to respective inverters. The outout-put of inverters are labeled as vad0, vad1 and vad2.

The operation of comparator A is discussed first, followed by the operation of com-parator B and C. The current Iin is fed as an input to the drain of the transistor

M3. The input current is then reproduced by the transistor M0. A DC reference current is set up by the transistors M6 and M14. Transistor M5 reproduces the reference current in-order to establish the threshold current Ith. If the threshold

current Ithis greater than the input current Iin, the voltage Vds should be a

log-ical LOW, 0 V. As the output voltage should fall to loglog-ical LOW, transistor M3 should be operating in saturation region and transistor M0 should be operating in linear region [10]. The input current Iinis fed to the drain of the diode connected

(38)

26 Design and Implementation of Current-Mode Pipelined ADC M3 in saturation region, Iin= K3· ( W L)3[(Vgs) − (Vth3)] 2 _(4.1) M0 in linear region, Id2= K0· (W L)2(2(Vgs− Vth0)Vds0− Vds0 2 _(4.2)

Figure 4.8: Schematic of Current Comparator

The NMOS transistors M0, M1, M2 and M3 are all identical with same width-to-length ratios. Transistors are assumed to have same threshold voltages Vthand

identical K. Vds is forced to be low enough such that it turns off the gate that

it will be driving. To calculate the value of Vds, the maximum allowable logical

LOW of the output is set to one-third of the NMOS threshold voltage, Vth. The

relationship between the threshold current Ithand the input current Iinis all that

remains to be specified. Let us assume that logical LOW at the output occurs when the input current Iinis 1.1 times as large as the threshold current Ith. Thus,

when the output becomes logical LOW, Iin= Ith. Now that we have related the

(39)

4.4 Design of Current-Steering DAC 27 drain current equations. The width-to-length ratios of the transistors M3 and M0 can be obtained by the values of Vgs and the input current Iin.

4.4 Design of Current-Steering DAC

Digital-to-Analog Converter (DAC) is a device which converts digital codes to analog signals. It is widely used in this modern day digital world. This chapter briefly examines the different architectures of Digital-to-Analog converters.

4.4.1 Types of Digital-to-Analog Converter

Digital-to-Analog Converters can be designed using different topologies. Each topology can be determined based on the architecture, differential non-linearity, integral non-linearity, chip area, matching requirements and settling time. Several different topologies of DAC such as resistor ladder architecture, resistor string ar-chitecture, division arar-chitecture, charge-division arar-chitecture, and current-steering architecture are briefly discussed.

4.4.2 Resistor-Ladder DAC

The Resistor-Ladder architecture [11] is the simplest of the D/A implementations. This architecture of DAC is commonly known as R-2R ladder network as it consists of resistors R and 2R. The Resistor-Ladder architecture is also known as Voltage-Divider architecture.

Figure 4.9: R-2R Ladder DAC [3]

The Resistor-Ladder architecture consists of a string of resistors in series. The top most resistor is connected to Vddand the resistor at the bottom is connected to

the gnd as shown in the figure 4.9. The nodes in between the resistors have differ-ent voltages based on the node’s proximity to Vdd. The nodes which are higher in

(40)

28 Design and Implementation of Current-Mode Pipelined ADC the ladder have higher voltages than the nodes which are lower in the ladder. By using a decoding technique (binary or thermometer) on the digital code, a node can be chosen so as to determine the corresponding analog voltage. The resolution of the resistor-ladder DAC is determined by the number of resistor elements in the architecture. For an N -bit DAC, a ladder with 2N _{resistor elements are required.}

As the number of bits increases, the size of the architecture increases.

Resistor-Ladder DAC has few benefits other than its simplicity of design. The DNL is said to be low when compared to other architectures of DAC. As long as the switches are correctly designed, this DAC tends to be monotonic. Resistor-ladder DACs are not among the favorite architecture of DAC recently for several reasons. The absolute resistor values causes significant differences in power consumption. Due to the lack of matching information, the mismatch ratio determination be-tween resistors in the ladder on the same chip is difficult. Resistor-Ladder DAC is slow in its operation because of the large resistance load at the output. This could be avoided by using small resistor values and large output buffers at the cost of high power consumption. Therefore, this architecture is not best suited for modern CMOS processes.

4.4.3 Resistor-String DAC

The simplest of DAC architectures is the Resistor-String architecture [11]. There exists a difference between R-2R and string architectures. In R-2R architecture, it is possible to obtain a voltage or current output, whereas in a string architecture, it is possible to obtain only a voltage output by using an output buffer. The architecture consists of 2N _{identical resistors and switches.}

Figure 4.10: Resistor-String DAC [3]

(41)

4.4 Design of Current-Steering DAC 29 The accuracy is good for this architecture and it is inherently monotonic. For DACs with a resolution of 8 to 10 bits, this type of architecture is preferred as it tends to be fast enough. The disadvantage in this type of architecture is that the output is always connected to 2N_{-1 switches in “OFF” state and to one switch}

in “ON” state. As the resolution increases, a large parasitic capacitance appears at the output, as a result of which the conversion speed becomes much slower. A large area is occupied by this architecture because of 2N _{resistor elements. For}

DACs with resolution of 10 bits or more, the settling time is large.

4.4.4 Current-Division DAC

Current-division architecture [11] is one of the types of reference division archi-tectures. The operation is based on the division of a reference current among the transistors. A binary implementation is shown in the figure 4.11.

Figure 4.11: Current Division DAC [3]

The device on the right most side draws 1/7 of the reference current and the devices at the center draws 2/7 of the reference current. The leftmost side which consists of four device draws 4/7 of the reference current [11]. The nodes are turned on by the digital input passing the respective current to the output node. The currents are then added and the analog current corresponding to the digital input is obtained. It is desirable to have a voltage output rather than a current output. To obtain a voltage output, a resistor is used between the power and the output node. A transimpedance amplifier can also be used as an alternative approach to convert current to voltage. There are few drawbacks with

(42)

30 Design and Implementation of Current-Mode Pipelined ADC this type of architecture. The output voltage range is reduced by the current-dividing transistors which are positioned above Iref. This is a major drawback

in low voltage circuits. The transistors may go out of saturation region if the output voltage decreases drastically. As the reference current is divided by each transistor, Iref should be N times greater than each of the current output. A

huge device is required to produce the current source. This can be avoided by using binary implementation technique. Area is the primary concern in the binary implementation technique. In-order to avoid these drawbacks, current-steering digital-to-analog converters are implemented by designers rather than current-division DACs.

4.4.5 Charge-Division DAC

Charge division DAC is one of the most common architectures in CMOS technol-ogy. The figure 4.12 shows the architecture of Charge Division DAC. Capacitors C0, C1,...,Cn are all identical in size. The bottom plates of the capacitors switches between Vref and GN D. Thus each capacitor injects an amount of charge to the

output node. The digital thermometer code controls each and every switch. The charge on the output node is thus determined by the number of nodes that are turned “ON”. The circuit performs the operation in two steps [11]. In the first step, the switch S is turned “ON” and the bottom nodes of all the capacitors are connected to the ground. The capacitors are then discharged. In the second step, the switch S is turned “OFF” and the digital code(thermometer) is applied to each switch. Thus, Vref is applied to all the capacitors. This could be implemented in

other topologies in binary version by using different size of capacitors. The control logic and the timing for this architecture is much more complex than for the archi-tectures which are discussed above. The major disadvantage of this architecture is building up of capacitor elements which occupies considerably more area on the chip. This type of DAC is relatively inaccurate because of several non-linearity issues.

4.4.6 Current-Steering DAC

The architecture of DAC implemented in this research work is the current-steering DAC. Current-steering architecture does not divide the current in each branch of the DAC as in the case of current-division DAC architecture. Instead, it replicates a reference current source. Depending on the digital thermometer code, each branch current is switched “ON” and “OFF”. This architecture is complex when compared to other types of DAC. A high speed can be achieved by using this archi-tecture with relatively large power consumption and chip area. The current source is the key part in this type of architecture. There are two types of current-steering DAC: unit element current-steering and binary weighted current-steering DAC. Fig 4.13 and fig 4.14 show the architecture of unit-element and binary weighted current-steering DACs respectively.

In unit-element architecture, 2N _{current source elements are required for an N -bit}

(43)

refer-4.4 Design of Current-Steering DAC 31

Figure 4.12: Charge Division DAC [3]

ence current is multiplied by a factor of 2 and larger currents with exponentially increasing magnitude. An additional current source is turned “ON” if the digital input is increased by 1 LSB. This avoids the simultaneous switching of two signals in opposite directions.

Figure 4.13: Current-Steering DAC-Unit Element [3]

The performance of unit-element current-steering DAC is better than that of the binary weighted current-steering DAC. Unit-element DAC achieves high speed. It can be used in high-speed applications as it has inherently high current. The traditional fabrication was done with bipolar technology and now CMOS is used as an alternative due to the matching of current mirrors. The matching performance

(44)

Figure 4.14: Current-Steering DAC-Binary [3]

in the unit-element architecture is better than in the binary weighted DAC. The current produced in each of the branches is the same because of identical current sources. Unit-element is monotonic, that is, when the digital code is incremented or decremented by 1, only one switch is turned “ON” or “OFF” and the analog input is varied. This helps in reducing the glitches due to less switching activity.

The drawbacks of unit-element architecture are its complexity, large area and large power consumption as it requires 2N _{current sources for an N -bit DAC [11].}

Hence a binary weighted current-steering DAC is implemented in the thesis work.

4.4.7 Building Blocks of Current-Steering DAC

In this section, the design of the building blocks of the current-steering DAC is discussed. The current source, the switch and switch signal generator forms the building block of the current-steering DAC and the implementation at transistor level is briefly explained.

4.4.8 The Current Source

A load resistance of 1 kohm is used. The currents that are produced by the unit sources are switched to the load resistance. Unit current can be calculated by using maximum output voltage swing and the resolution. An output swing of 1.2 V and 7 bits resolution gives a unit current of 9.45 µA calculated from equation 4.3 [12].

Iunit= 1

1K(27_{− 1)} = 9.45µA. (4.3)

The output resistance should be very large in order to obtain a DAC with a very high resolution. The output resistance Rout can be calculated from equation 4.4

(45)

4.4 Design of Current-Steering DAC 33

Rout =rout

A (4.4)

rout is the output resistance of one unit source.

Two types of current source implementation is shown in the figure 4.15 and figure 4.16.

Figure 4.15 shows the single transistor current source [12]. It is the simplest of the current sources.The output resistance of this current source is shown in equation 4.5.

Figure 4.15: Simple Current Source

rout= 1

gds,0 (4.5)

High resolution cannot be obtained with a single transistor current source as the output resistance is not large enough. A single cascode current source is shown in the figure 4.16.

An additional cascode transistor has been added so as to increase the output resistance. The output resistance of a single cascode current source is given by the equation 4.6.

rout= gm,1

gds,1 ·

1

gds,0 (4.6)

The output resistance is increased by 1000 [12]. To further increase the output resistance, more cascode transistors can be added. As we add more cascode tran-sistors, a large voltage drop occurs across the transistors resulting in the decrease

(46)

Figure 4.16: Cascode Current Source

of the DAC’s output swing. A single cascode current source has been chosen for this implementation to achieve a high output resistance.

(47)

4.4 Design of Current-Steering DAC 35

4.4.9 The Switch

Differential structures have many advantages. One such advantage is the decrease in distortion [12]. Hence a differential DAC has been designed. Figure 4.17 shows a simple CMOS switch made up of two transistors. Figure 4.18 shows the differential switching of current sources. The current sources tend to switch between the two terminals named as I+ and I-.

Figure 4.17: Differential CMOS Switch

Figure 4.18: Current Source-Differential Switching

This type of simple CMOS switch has clock feed-through [12]. Channel charge should be removed when the switch is turned “OFF”. If not, an unwanted current peak occurs at the output due to half of the charge. This phenomenon is called clock feed-through. In-order to reduce the clock feed-through, dummy switches are

(48)

36 Design and Implementation of Current-Mode Pipelined ADC used. The dummy transistor acts as a capacitor. When the switching capacitor is turned “OFF”, the dummy transistors stores the channel charge. The charge from the dummy transistor is discharged when the switching capacitor is turned “ON”. The dummy transistor should have the same length L and half the width W as that of the switching transistors. By sizing the dummy transistors, right amount of charge can be stored by the dummy transistors. The differential CMOS switch with dummy transistor is shown in the figure 4.19. Q and Q are the switching signals and the generation of such signals are discussed in the following chapter.

Figure 4.19: Differential CMOS with Dummy Switch

4.4.10 Switch Signal Generator

A few important steps have to be taken care off when switching a current source [12]. The current source should never be turned “OFF” during the course of operation. If it gets turned “OFF”, it might take time to get settled in the correct value when it is turned “ON” again. The switches should never be open at the same time and we must make sure that we have overlapping switch signals. The switching signals can be obtained by using a D-flip flop as shown in the figure 4.20. If one of the outputs are high, the other one is low. Hence it is made sure that the outputs are not LOW at the same time.

4.5 Design of 3-to-7 bit Binary-to-Thermometer

Decoder

A 3-to-7 bit binary to thermometer decoder which has been implemented in the thesis work is discussed in this section. A minimal number of pipeline stages are

(49)

4.5 Design of 3-to-7 bit Binary-to-Thermometer Decoder 37

Figure 4.20: Circuit for Overlapping Switching Signals

used to achieve a high-speed decoding technique with low power consumption. The digital binary code is decoded to a digital thermometer code in order to reduce the glitches. The converters based on thermometer code promises to be monotonic. The advantages of digital thermometer code when compared to digital binary code are as follows:

• Monotonicity is guaranteed.

• Glitches are less.

• Less DNL errors.

4.5.1 Logical Conversion of Binary-to-Thermometer Decoder

The logical conversion of the 3-to-7 bit binary to thermometer decoder is tabulated in table 4.1.

Table 4.1: Logic Operation of the 3-to-7 bit Binary-to-Thermometer Decoder

A0 A1 A2 T6 T5 T4 T3 T2 T1 T0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 1 1 0 0 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1

4.5.2 Logic Expression of Binary-to-Thermometer Decoder

The logic expression of the 3-to-7 bit binary to thermometer decoder is as follows. T6 = A0+A1+A2

(50)

38 Design and Implementation of Current-Mode Pipelined ADC T4 = A0+(A1.A2) T3 = A0 T2 = A0(A1+A2) T1 = A0.A1 T0 = A0.A1.A2

The 3-to-7 bit digital decoder symbol is shown in figure 4.21.

The decoder is designed with logical gates such as inverter, NAND, NOR, AND and OR. The schematic of the decoder is shown in figure 4.22.

BINARY TO THERMOMETER DECODER A2 A1 A0 T0 T1 T2 T3 T4 T5 T6

Figure 4.21: Symbol of Binary-to-Thermometer Decoder

4.6 Delay Logic

The function of the delay component is to store the digital binary signals from different stages of the ADC. The digital signal is then passed on to the digital error correction block when the input signal has passed through all the stages of the ADC. Memory is not implemented as it consumes more power than the delay logic. Memory also occupies more area when compared to the delay logic. It is because of these two reasons delay logic is preferred ahead of a memory block. Different components may be used for delay logic. The most common implementation of a delay logic is a D flip-flop [13].

The logical diagram of a D latch is shown in the figure 4.23. The D latch is a clocked circuit. Two cascaded latches operating on opposite clock phases is used to realize a D Flip-Flop. The digital signal is usually sampled at the rising edge of the clock by the D flip-flop. When the input digital signal to the D flip-flop is sampled, it gets held until the next rising edge of the clock.

The timing waveform of the D flip flop is shown in the figure 4.24. The D flip-flop produces two outputs Q and Q. The Q output produces the same state as that of the D input when the clock is high. It is called as D flip-flop or delay flip-flop as the output is same as the input with a delay of one clock cycle. Q which is an inverted output of Q is not required in this application. The symbol of D flip-flop

(51)

4.6 Delay Logic 39

Figure 4.22: Schematic of Binary-to-Thermometer Decoder

Figure 4.23: D Latch

is shown in the figure 4.25.

The truth table of D Flip-Flop is tabulated in table 4.2.

Table 4.2: Truth Table of D Flip-Flop

.

Input-CLK Input-D Output-Q Output-Q’

HIGH 0 0 1

(52)

Figure 4.24: D Flip-Flop Timing Diagram

Figure 4.25: D Flip-Flop symbol

4.7 Digital Error Correction

The digital error correction technique and its building blocks such as half adder circuit and full adder circuit are briefly discussed in this section.

4.7.1 Digital Error Correction Technique

The inaccuracies in the circuit can be digitally compensated by a technique known as Digital Error Correction [13]. The main purpose of using a digital error cor-rection technique is to improve the linearity of the sub-ADC in each stage. The tolerance of the system is greatly improved by this technique. In general, the range between the high reference current and the low reference current of the compara-tor is an undefined area. When the signal is found to be in the mid interval range by the sub-ADC, the next stage is set to HIGH or LOW. The algorithm of the digital error correction technique is quite simple. The MSB of the current stage is added to the LSB of the previous stage in the digital error correction logic.

4.7.2 Half Adder

The half adder is built from two logic gates: XOR gate and AND gate. The half adder is an example of a simple combinational digital circuit. The output is the carry (C) and sum of two bits (S). The inputs are common to both the gates. Thus when a voltage is applied to the A input of an AND gate, the XOR gate too receives the same voltage. The boolean expression of the sum and carry of a half adder is expressed as in equation 4.7 and 4.8 respectively.

(53)

4.7 Digital Error Correction 41

Sum = (A)XOR(B) (4.7)

Carry = A · B (4.8)

The figure 4.26 shows the schematic of a half adder.

Figure 4.26: Half Adder

The truth table of a half adder is tabulated in table 4.3

Table 4.3: Truth Table of Half Adder

.

Input-A Input-B Output-Sum Output-Carry

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

4.7.3 Full Adder

The full adder is necessary when there is a need to add a carry input with that of the two binary digits in order to obtain the correct sum. In general, a half adder has no input for carries from any of the previous circuits. A basic method of constructing a full adder circuit is to make use of two half adder blocks and an OR gate as shown in figure 4.27. The inputs A and B are applied to XOR and AND gates as in the case of a half adder. These make up one of the half adder blocks. The sum output from this half adder block and the carry output from a previous circuit are the inputs to the next half adder block. The carry output from each of the half adder is applied to an OR gate to produce the carry-out of the circuit. The figure 4.27 shows the schematic of a full adder circuit.

The boolean expression of the sum and carry of a full adder is expressed as in equation 4.9 and 4.10.

Sum = (A)XOR(B)XOR(Cin) (4.9)

(54)

Figure 4.27: Full Adder

The truth table of a full adder is tabulated in table 4.4.

Table 4.4: Truth Table of Full Adder

Input-A Input-B Input-Carryin Output-Sum Output-Carry

0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1

(55)

4.8 Pipelined ADC Stage 43

4.8 Pipelined ADC Stage

In this section, different blocks of the pipelined ADC is briefly described. Each block of the implemented pipelined ADC consists of a differential sample-and-hold amplifier, a current-comparator, a 3-to-7 bit binary to thermometer decoder and a differential current-steering digital-to-analog converter.

Figure 4.28: Pipelined ADC-Stage

The differential sample-and-hold amplifier as discussed in section 4.2, samples and amplifies the input current analog signal. In general, differential circuits have less distortion when compared with single-ended circuits. The current comparator briefed in section 4.3, compares the input current Iin with the reference current

Iref and produces a 3-bit digital output. The 3-bit digital binary data produced

by the comparator is then fed as an input to the decoder. The decoder explained in section 4.5, converts the 3-bit digital binary code into a 7-bit digital thermometer code. A differential current-steering DAC is discussed in section 4.4.6. Each branch of the current-steering DAC has a current source corresponding to the digital thermometer code fed to the branch and the load resistance,R as expressed in equation. The output of the current-steering DAC and SHA is fed as an input to the next stage. Each stage of an ADC produces 3-bits. Four such stages are implemented producing a total of 12 bits. After applying digital error correction technique section 4.7, 9-bits are obtained. The schematic of a single pipelined ADC stage is shown in figure section 4.28.

(56)

(57)

Chapter 5

Simulation

Results/Performance

Evaluation of Pipelined

ADC

5.1 Introduction

In chapter 4, the design and implementation of the proposed 9-bit Pipelined ADC is addressed. In this chapter, the performance of the proposed ADC based on circuit simulations are discussed. Testing environments to check the static and dynamic performance are set up. The conversion time, speed and power consump-tion of pipelined ADC are calculated by setting up suitable test environments.

5.2 Test-Bench of ADC

The analysis of data conversion systems are made much easier as Cadence provides the simulation environment for both analog and digital domains. The test bench is shown in figure 5.1.

Input current, power supply and clock are all given as an ideal source to the ADC. Verilog-A code is used to build a file-write model. The file-write model saves the output data of the 9-bit pipelined ADC. The SHA, Current Comparator, Binary-to-Thermometer decoder, Current-Steering DAC are all designed in transistor-level and simulated by Cadence. The data stored in the file-write model based on the circuit simulation in Cadence is executed in Matlab. Thus, the static performance and the dynamic performance of ADC are calculated.

(58)

46 Simulation Results/Performance Evaluation of Pipelined ADC

Figure 5.1: Test-Bench Setup

5.3 Evaluation of SNR/SFDR/SINAD/ENOB

The dynamic performance metrics of ADC such as SNR, SFDR, SINAD and ENOB can be obtained by the Fast Fourier transform (FFT). A full-range current input sine wave is applied to the pipelined ADC block. The simulation is performed in Cadence and the output data stream is stored in file-write. The data is then imported in Matlab to achieve the Fast Fourier transform (FFT). The FFT will indicate the spectral component and quantization noise corresponding to the input signal. The dynamic performance metrics can be calculated by examining the FFT. The testbench setup is shown in figure 5.2.

Figure 5.2: Test-Bench Setup for Dynamic Performance Metrics

5.4 Evaluation of Offset/INL/DNL Errors

The static performance metrics of ADC such as offset/INL/DNL errors are ob-tained by the transfer curves plotted with input analog signal vs digital output code. The output 9-bit data and the input signal at every positive edge of the clock is stored in the file-write. The data from the file-write is imported in Matlab and the static performance metrics are evaluated as described in 2.1. The testbench

(59)

5.5 Coherent Sampling 47 setup is shown in the figure 5.3. The figure 5.5 and 5.6 displays the INL, DNL and offset errors of ADC.

Figure 5.3: Test-Bench Setup for Static Performance Metrics

5.5 Coherent Sampling

FFT is commonly used to evaluate the performance of data converters. For si-nusoidal input signals, the signal frequency should not be chosen as a rational factor times the sampling frequency. Otherwise, the quantization error can not be modeled as uncorrelated noise [14]. In order to avoid this problem, coherent sam-pling or window samsam-pling should be used. A so called coherent samsam-pling has been chosen to evaluate the dynamic performance of ADC. Mathematically, coherent sampling [14] is expressed as in equation 5.1.

Fin

Fsample =

Nwindow

Nrecord (5.1)

Finis the input frequency.

Fsample is the sampling frequency.

Nwindow is the integer number of cycles within the sampling window. This value

must be an odd or prime number.

Nrecord is the number of data points used to create the FFT. This value must be

a power of 2.

The sampling frequency of the ADC is 100 MHz. The input frequency calculated from equation 5.1 is 22 MHz. Figure 5.4 shows the FFT to evaluate the dynamic performance metrics of ADC. The evaluation result shows that the SINAD to be 52.8 dB and SFDR to be 71.7 dB. The ENOB is evaluated to be 8.48 bits based on SINAD.

(60)

48 Simulation Results/Performance Evaluation of Pipelined ADC

Figure 5.4: FFT for Dynamic Performance Metrics of ADC

Figure 5.5: INL, Offset Error-Static Performance Metrics of ADC

(61)

Chapter 6

Conclusion

Pipeline ADCs are one of the best choices in the applications where high speed and high resolution play an important role. A SI pipelined ADC at 65 nm CMOS technology is designed and implemented for low power with a very good perfor-mance.

Current-mode technique helps in achieving low power and high speed. To reduce the power consumption, a simple trio current-comparator and a current-steering DAC have been implemented.

Comparator plays a vital role as well as it is a critical device in data conversion systems. The comparator implemented in this thesis work consumes little power. In order to reduce the noise effects which directly affects the SNR of the system, a differential Sample-and-Hold Amplifier circuit has been implemented.

Design of switches in the analog circuit is another major concern. The on-resistance of a simple PMOS or NMOS switch changes with respect to the reference voltage. When the switch changes its state from one transition to another, a charge injec-tion error is produced.

A CMOS switch, commonly known as a transmission gate can be preferred as a replacement for a simple PMOS or NMOS switch. A typical CMOS switch cancels the charge injection and also has a constant on-resistance.

Based upon the simulation results, the ADC achieves a SINAD of 52.8 dB, SFDR of 71.7 dB and ENOB of 8.48 bits at 100 MHz sample rate with 1.2 V power supply voltage.

(62)

(63)

Chapter 7

Future Work

Future prospects are as follows:

• To implement Dynamic Element Matching (DEM) technique in the current-steering digital-to-analog converter (DAC) to increase the SFDR.

• The settling time of the comparator can be improved.

• Current-division DAC is to be designed and implemented as an alternative for current-steering ADC.

• As the design is implemented at transistor level, the most important task after this is to proceed with the layout implementation and to analyse the results by post-layout simulations.

• To optimize the design further for low power.

• The resolution and the conversion speed of the SI technique Pipelined ADC is to be optimized further.

(64)

(65)

Bibliography

[1] Nicholas Gray. ABCs of ADCs Analog-to-Digital Converter Basics.

[2] Maxim. Understanding Pipelined ADCs. 2001.

[3] Yang Lin. Design of a 8-bit CMOS Unit-Element Current-Steering Digital-to-Analog Converter.

[4] Yong Sun and Fengchang Lai. Low Power High Speed Switched Current Comparators for Current Mode ADC. 2007.

[5] Behzad Razavi. Design of Analog CMOS Integerated Circuits.

[6] Harcharan Singh. Design of 10-bit Sample and Hold Amplifier. 2006.

[7] Asok Bhattacharyya Veepsa Bhatia, Neeta Pandey. A 4-Bit Expandable Current-Mode ADC Based on Different Current Comparator Architectures.

[8] S. Sitjongsataporn K. Moolpho, J. Ngarmnil. A High Speed Low Input Cur-rent Low Voltage CMOS CurCur-rent Comparator.

[9] James H. Seigel. The Design of a Current Comparator for Video-Rate Analog to Digital Conversion.

[10] K. W. Current D. A. Freitas. CMOS Current Comparator Circuit.

[11] Professor Robert Brodersen Sam Blackman. A Low Power, 8-bit, 200 MHz Digital-to-Analog Converter. 1999.

[12] Ola Andersson. Mismatch Modeling and Design of CMOS Current-Steering Digital-to-Analog Converters. 1999.

[13] Jonas Benjamin Borch. Design of low-power, highspeed A/D converter in CMOS technology.

[14] Maxim. Coherent Sampling. 2004.

(66)

Design of Pipelined Analog-to-Digital Converter with SI Technique in 65 nm CMOS Technology

Institutionen för systemteknik

Department of Electrical Engineering

Examensarbete

Design of Pipelined Analog-to-Digital Converter

with SI Technique in 65 nm CMOS Technology

Design of Pipelined Analog-to-Digital Converter

with SI Technique in 65 nm CMOS Technology

Examensarbete utfört i Elektroniksystem

vid Tekniska högskolan i Linköping

av

Abstract

Acknowledgments

Contents

List of Figures

List of Tables

Chapter 1

Introduction

1.1

Analog-to-Digital Converter

1.2

Objective of Thesis

1.3

Thesis Organization

Chapter 2

ADC Performance Metrics

2.1

Static Performance Metrics

2.1.1

Offset Error

2.1.2

Full-Scale Error

2.1.3

INL

2.1.4

DNL

2.2

Dynamic Performance Metrics

2.2.1

SNR

2.2.2

SFDR

2.2.3

SINAD

2.2.4

ENOB

Chapter 3

ADC Architectures

3.1

Flash ADC

3.2

Successive Approximation ADC

3.3

Sigma Delta ADC

3.4

Pipelined ADC

3.5

Comparison Between ADC Architectures

Chapter 4

Design and Implementation

of Current-Mode Pipelined

ADC

4.1

Proposed Architecture of Pipelined ADC

S&H

ADC

DAC

Stage

2

Stage

n

Stage 1

A

in

clk

D

1

D

2

D

_in

₁

₂

_n