High speed data collection with Blackfin DSP

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(1)2007:238 CIV. MASTER'S THESIS. High speed data collection with Blackfin DSP. Axel Alatalo. Luleå University of Technology MSc Programmes in Engineering Electrical Engineering Department of Computer Science and Electrical Engineering Division of EISLAB 2007:238 CIV - ISSN: 1402-1617 - ISRN: LTU-EX--07/238--SE.

(2) High speed data collection with Blackn DSP Axel Alatalo. September 16, 2007.

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(4) Abstract This report covers a master thesis in embedded systems, the goal of which was to investigate the high speed data collection capabilities with a Blackn DSP. Basic theory about sampling and noise is covered briey from a practical point of view. The theory is intended to be useful for those diving into a ADC datasheet for the rst time. After an investigation of the delimiting factors, suitable components were selected and a prototype ADC PCB was designed from scratch.. The goal. is to design a general low noise data collecting unit compatible with the Blackn DSP. Finally simple DSP software is designed to prove that DSP can handle such a high datastream. Testing the ADC card with the target Blackn platform indicates that the analog parts indeed works.. An analog bandwidth of over 10MHz is. measured at a resolution exceeding 10 bits with respect to noise. The digital parts intended to interleave the two channels digital streams into one blackn unit did not work as intended. Only one channel is supported as of now. The report contains suggestions for future work in this area..

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(6) Contents. 1. 2. 3. 4. 5. 6. Introduction. 1. 1.1. Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1. 1.2. Delimitations. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2. 1.3. Report outline. . . . . . . . . . . . . . . . . . . . . . . . . . .. 2. Theory. 3. 2.1. Basic noise theory. 2.2. Quantization. . . . . . . . . . . . . . . . . . . . . . . . .. 3. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4. 2.3. ADC gures of merit . . . . . . . . . . . . . . . . . . . . . . .. 5. 2.4. Jitter and sampling . . . . . . . . . . . . . . . . . . . . . . . .. 6. Hardware design. 8. 3.1. Overview. 8. 3.2. Selecting ADC and interfacing the Blackn. . . . . . . . . . .. 9. 3.3. Generating the sample clock . . . . . . . . . . . . . . . . . . .. 10. 3.4. Antialiasing ltering and ADC driving . . . . . . . . . . . . .. 11. 3.5. Variable amplication. . . . . . . . . . . . . . . . . . . . . . .. 12. 3.6. Input stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13. 3.7. Power supply. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 16. 3.8. PCB considerations . . . . . . . . . . . . . . . . . . . . . . . .. 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. Software design. 17. 4.1. Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 17. 4.2. Capabilities of Blackn . . . . . . . . . . . . . . . . . . . . . .. 17. 4.3. The uClinux interface. 18. . . . . . . . . . . . . . . . . . . . . . .. Results. 20. 5.1. Input stage characteristics . . . . . . . . . . . . . . . . . . . .. 20. 5.2. Measured analog characteristics . . . . . . . . . . . . . . . . .. 21. Conclusions. 23. 6.1. Meeting the objectives . . . . . . . . . . . . . . . . . . . . . .. 23. 6.2. Further work. 24. . . . . . . . . . . . . . . . . . . . . . . . . . . .. iii.

(7) 7. Appendix A - Schematics. 25. iv.

(8) List of Figures 2.1. Jitter translated into noise. Image from [1] . . . . . . . . . . .. 3.1. Block view of the hardware. 3.2. Timing diagram for BF537 and AD9863. . . . . . . . . . . . .. 10. 3.3. The input stage with protection and buer . . . . . . . . . . .. 14. 3.4. Illustration of an oscilloscope probe with compensation capacitor.. . . . . . . . . . . . . . . . . . . .. 6 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15. 4.1. Chip bus hierarchy. Image from [4] . . . . . . . . . . . . . . .. 18. 5.1. Test setup for input stray capacitance measuring. . . . . . . .. 20. 5.2. Step response. Actual samples together with interpolated line.. 21. 7.1. Schematics for the analog stage . . . . . . . . . . . . . . . . .. 26. 7.2. Power and ADC schematics. . . . . . . . . . . . . . . . . . . .. 27. 7.3. Connections to the BF537-STAMP board. . . . . . . . . . . .. 28. 7.4. Top routing layer, component side.. 29. 7.5. Ground plane, ANGD and DGND connected between ADC. 7.6. Powerplanes.. 7.7. Bottom routing layer.. . . . . . . . . . . . . . . .. and digital buer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. v. 30 31 32.

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(10) List of Abbreviations ADC. Analog to Digital Converter. ADI. Analog Devices Inc.. BF537. Blackn Cpu. BF537-STAMP. Evaluation board for BF537 CPU. BNC. Coaxial connector. CPU. Central Processing Unit. DMA. Direct Memory Access. DSP. Digital Signal Processor. ENOB. Eective Number Of Bits. FIFO. First In First Out. FPGA. Field Programmable Gate Array. IO. Input Output. GPIO. General Purpose Input Output. PCB. Printed Circuit Board. PPI. Parallel Port Interface. RAM. Random Access Memory. RMS. Root Mean Square. SDRAM. Synchronous Dynamic Random Access Memory. SINAD. Signal to Noise And Distortion. SNR. Signal to Noise Ratio. THD. Total Harmonic Distortion. uC. Micro Controller. VCO. Voltage Controlled Oscillator. VCXO. Voltage Controlled Crystal (X-tal) Oscillator. vii.

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(12) Chapter 1 Introduction Rubico AB is specialiced on Analog Devices Blackn series of DSPs. Specifically they focus on uClinux, a linux avor for systems without memory management units. High level software functionality like TCP/IP, Ethernet, Bluetooth and USB is included in uClinux which reduces development time. One thing missing in Rubicos Blackn toolbox is a high speed analog data collection unit. A possible application for a Blackn with analog datacollecting is high frequency (approx. 400kHz) ultrasonic spectrum measurements.. 1.1 Objectives The objective of this work is to develop a general measurement system that could be used in for example high frequency ultrasonics. The system should be compatible with an Blackn evaluation board called BF537-STAMP. The STAMP board includes everything needed to run the ADSP-BF537 CPU, such as SDRAM memory, boot ash memory and a powersupply. The rst part of the work is to determine how fast the BF537-STAMP system can gather data and determine the limiting factors. The second part is do design hardware for analog to digital conversion.. Two channels with an analog. bandwidth of 10MHz or more (giving about a factor ten margin to the 400kHz pulse) would be ideal. The third part is to design a suitable software interface and write uClinux drivers.. Finally a simple proof of concept application. should be written and the analog performance evaluated.. As a summary,. the primary goals for the entire system are: Two analog channels Analog bandwidth of 10MHz Accuracy of 10 bits with respect to noise and distortion. Store enough data (about 10ms) for short range ultrasonic measurements.. 1.

(13) A exible enough system usable in other measuring environments than ultrasonics.. 1.2 Delimitations An early design choice was made to avoid glue logic between the Blackn and the ADC. There are a lot of things one can do with FIFOs and FPGAs, but since the primary objective is to evaluate the Blackn and its capabilities it falls a bit outside the scope of this work.. The objective is to collect data. as fast and accurate as possible using only the Blackn as computational and storage unit.. The uClinux software should be kept simple while still. usable as proof of concept. It does only have to store data into RAM. More advanced functionality is left as future work.. 1.3 Report outline The report is written in a way that an engineer should be able to follow the discussion. Theory not considered general engineering knowledge is refreshed in the Theory chapter. The hardware design chapter gives an overview of the hardware made and then goes into detailed explanation of the design choice made. The chapter on software gives and overview of how the software uses the blackn hardware and briey explains how the software works.. The. software overview is followed by more detailed explanations of uClinux, the driver and software design choice. The Results chapter contain benchmarks of the system all the way from noise characteristics to software benchmarks. Finally the chapter on Conclusions discusses weather the objectives were met or not and the possible reasons to why or why not. The chapter also conciders improvements that could prove useful in a future version of the module.. 2.

(14) Chapter 2 Theory Whats behind the mysterious formula for quantization noise. √. and the infamous unit. V / Hz ?. √ N = q/ 12. These questions as well as others will be an-. swered briey here. Focus of the chapter will be to give an brief and intuitive understanding of theory that may not be common engineering knowledge.. 2.1 Basic noise theory When dealing with noise one often wants to put the noise into relation with the signal, that is calculate the signal to noise ratio, SNR. In order to do a comparison one have to quantify how large a signal is.. In a simple. yS = A ∗ sin(2π1000t) with = B ∗ sin(2π50t) it is easy to compare their SNR (signal to noise ratio) is SN R = A/B .. case with two sinusoidal, say one signal of superimposed 50Hz noise. yN. amplitudes and say that the. How to compare signals with dierent shape then, like a sinusoidal with a sawtooth for example? Comparing the averages of the signals is a bad idea since perfectly symmetrical (around the X axis) signals would average to zero, although they denitely are not zero. One measure useful for periodic signals is the mean square.. M S(y(t)) =. 1 T. T. Z. y(t)2 dt. (2.1). 0. The unit of MS is the square of the input unit, the MS of for instance a voltage would get the unit of. V 2.. The square root of the mean square, RMS,. comes in handy for comparisons since it has the same unit as the input.. s RM S(y(t)) =. 1 T. Z. T. y(t)2 dt. (2.2). 0. The mean square counts all deviations from zero (as opposed to the plain mean value).. Short spikes with large amplitude gets more weight due to. 3.

(15) the square.. The most important property however is that mean squares. y1. superimpose. With the important but that. and. y2. doesn't overlap in. frequency, eq. 2.3 holds.. M S(y1 (t) + y2 (t)) = M S(y1 (t)) + M S(y2 (t)). (2.3). From eq. 2.3 and 2.2 the case for RMS values follows. RM S(y1 (t) + y2 (t)) =. p. RM S(y1 (t))2 + RM S(y2 (t))2. (2.4). Since dierent frequencies superimpose it gets meaningful to talk about amount of mean-square per frequency band. Following this line of thought the expected MS value of noise can be specied with a density function called. N D(f ) with the unit V 2 /Hz . To obtain f 0-f 1 just integrate the spectral density. Z f1 M Sf 0−f 1 = N D(f ) ∗ df. spectral density [5] in a specic band. the MS noise. (2.5). f0 The integral should be interpreted as the sum of the individual MS noise. N D(f )∗df. df . For comparison purposes the N D RM S (f ), is often used in√datasheets. √ The unit of N DRM S (f ) is V / Hz . A gure given in the unit V / Hz cannot in all the small frequency bands. square root of the MS noise density,. be used directly though, it must be turned into spectral density by squaring and then integrated with eq.. 2.5 if the MS of the noise in the integrated. band is to be obtained. As always, the squareroot of the MS can be taken to produce the RMS. This procedure, to square RMS values just to sum and take the squareroot afterwards, may seem unnecessary but follows from the fact that MS superimpose while RMS does not, all according to eq. 2.3. Finally a simple, but useful, special case. Noise in datasheets is is often approximated to be constant in frequency,. N D(f ) = constant.. Performing. the integral 2.5 with constant ND(f ) and taking the square root results in a useful formula for quick calculations when reading datasheets.. RM Sf 0−f 1 = N DRM S ∗. p. (f 1 − f 0). (2.6). 2.2 Quantization In digital sampling a continuous value will be converted to a discrete value. This process is called quantization and infers an error because of the nite number of bits used to store (quantify) the analog value. According to [9] (readable on-line) and [11] the quantization noise can generally be considered white (evenly distributed in frequency). Furthermore if. q = 1LSB. the RMS. of the noise added by the quantization process is. √ N = q/ 12 4. (2.7).

(16) The amplitude of a full scale sinusoidal stored with K bits and. q ∗ 2K /2.. Since the RMS of a sinusoidal is. √ amplitude/ 2. LSB = q. is. the RMS of the. signal is. S=. q ∗ 2K √ 2∗ 2. (2.8). It follows that the SNR is. SN R = S/N = 2K ∗. √. 6/2. (2.9). or measured in dB. SN RdB = 20 ∗ log(S/N ) = 6.02 ∗ K + 1.76dB Eq.. (2.10). 2.10 is an other equation often used in ADC application notes and. datasheets. The theory behind eq. 2.7 is beyond the scope of this report, but given eq. 2.7, eq. 2.10 follows rather straightforward.. 2.3 ADC gures of merit This section will briey describe some common measures of ADC performance. SNR - Signal to noise ratio. The ratio between the signal and noise energies (RMS). Note that this measure does not take harmonic distortion into account. [10]. SN R = SRM S /NRM S SINAD - Signal to noise and distortion.. (2.11). This measure diers from SNR. in that the energy in the harmonics (caused by nonlinearity's) also counts into the noise part. The MS of noise and harmonics is added to form (N+D). The squareroot of (N+D) then produces. (N + D)RM S ,. as explained in section 2.1. The denition is [10]. SIN AD = SRM S /(N + D)RM S THD - Total harmonic distortion.. (2.12). Dened as the power ratio between. the fundamental and its harmonics [10]. The total RMS power of the harmonics is of course the root sum square of the individual harmonics RMS power (recall that RMS power of a sinusoidal is. √ amplitude/ 2). as explained by eq 2.4 in section 2.1. THD is sometimes expressed in percent and sometimes in DB but it is of course the same ratio being measured.. T HD = HarmonicsRM S /F undamentalRM S 5. (2.13).

(17) ENOB - Eective number of bits. As described in section 2.2 quantization sets a maximum theoretical SNR. Turning it the other way around, solving equation 2.10 for the number of bits (as a function of SNR) and using SINAD as noisegure gives a indication of how many bits actually are useful.. EN OB =. SIN ADdB − 1.76 6.02. (2.14). 2.4 Jitter and sampling One easily overlooked factor in high speed sampling systems is the degrading eect jitter on the sampling clock has on SNR. The degradation that can be approximated [1] by eq. 2.15.. SN R = 1/(2 ∗ π ∗ fin ∗ tjitter−RM S ). (2.15). Concider the system of equations formed by the jitter equation 2.15 and and the quantization noise equation 2.9. Solving them by eliminating SNR produces jitter as a function of frequency (fin ) and number of bits (K). Renaming K to the more describing name ENOB (eective number of bits) produces a useful estimate for the maximum allowable clock jitter.. tjitter−RM S =. 1 π ∗ fin ∗ 2EN OB ∗. √. (2.16). 6. The reason for this degradation by jitter is that the samplingtheorem depends on the fact that samples are taken exactly evenly spaced in time. As illustrated in g 2.4 the error in sampling time an error in sampled voltage. Figure 2.1:. dV. dt. (jitter) will generate. (noise). Note that the error,. dV ,. is directly. Jitter translated into noise. Image from [1]. dependant on the slewrate (rate of change) of the input signal. The slewrate. 6.

(18) in turn is related to the input bandwidth. Thus it is not the samplingrate but rather the signal bandwidth (which explains the. fin. factor in eq. 2.15) that. determines how susceptible the system is to clock jitter [1], an important fact when designing for example undersampling systems where the bandwidth can be orders of magnitudes larger than the samplingrate.. The more in-. depth details about jitter is beyond the scope of this report, Analog Devices application note AN-756 [1] is a good place for the interested reader to start.. 7.

(19) Chapter 3 Hardware design This chapter begins with an overview of the constructed hardware.. It is. followed by more in-depth sections explaining the design choises made for each block. Noise considerations are discussed in the Variable amplication section 3.5 since electrical noise from ampliers puts a cap on the amount of meaningful amplication.. 3.1 Overview A voltage measuring board should have a high input impedance not to load the signal source.. An high speed ADC on the other hand in general has. a fairly input impedance (2k dierential for the ADC selected in section 3.2) and usually requires a dierential signal for optimal performance. Furthermore the signal will need scaling and the ADC needs protection from overvoltage. The hardware built forms the glue that brings these contradicting requirements together. Fig. 3.1 gives an overview of the hardware built.. Downscaling is done by giving the input a well dened impedance of 1MΩ and then connecting an external series resistor producing a voltage division (9MΩ gives 10X division).. This is how 10X oscilloscope probes. work and a benet with this solution is that regular oscilloscope probes may be used. Up scaling on the other hand is done with xed gain stages and analog multiplexers deciding which of the dierent amplied versions of the signal to route to the ADC drive circuits. The nal block performs anti alias ltering and converts the signal to a dierential one that the ADC wants. Because high load on the digital outputs of the ADC results in unnecessary current spikes a digital buer (not shown in the gure) is used close to the outputs. The ADC was chosen (see section 3.2) primarily because it could be connected glueless to the PPI port of the blackn, thus there is no glue logic (except the buer) in-between them.. 8.

(20) from probe. Input buffer. 4X Gain. Multiplexer. to clipping. 16X Gain. from multiplexer. Anti Alias Diff driver. Clipping. Figure 3.1:. to Blackfin. ADC. Block view of the hardware. 3.2 Selecting ADC and interfacing the Blackn The blackn PPI (Parallel Periferal Port) has a straightforward digital interface. In input mode (which is the only mode used in this case) it accepts up to 16 bit parallel data, clock and sync inputs. Data and sync is clocked in each clockank (Rising or Falling, congurable in software) [4]. The sync bit can be used in many dierent ways, but in this application it is used as a one shot trigger starting the datatransfer. When using multiple channels with a bitwidth greater then eight and a datarate of. fSAM P. with a datarate of. the channels need to be interleaved into a datastream. fSAM P ∗ channels.. Doing this in hardware would be. fSAM P ∗ channels fSAM P ∗ channels clock, a jitterfree clock fSAM P . In addition some shiftregisters or. troublesome. It requires either a PLL that generates the clock or if one starts with the divider is required to produce. similar logic is needed to perform the interleaving.. Because of the speeds. involved and setup+hold time problems this probably calls for an CPLD or FPGA, a messy solution indeed. There exists however one ADC, AD9863, that performs this task of generating an interleaved digital signal with a clockrate of twice the sampling clock.. Its other specications are okay but not best.. It was chosen solely. because of its promising (but, it would show, non functional, see section 6.1) exible digital interface.. The AD9863 is a mixed mode circuit with dual. channel ADC and DAC. It is only the two ADC channels that is used in this project however. It got an SNR of 67dB that according to eq. 2.10 is the same as 10.8 eective bits, which is enough. The analog bandwidth of 30MHz an maximum samplerate of 50Msamples/s is also enough. The ADC. 9.

(21) fSAM P , fSAM P ∗ 2.. is fed with a low jitter sampling clock. and produces an interleaved. datastream with clock of frequency. One output is used as chan-. nel indicator, this pin is tied to the sync pin of the uC. This way one knows which channel the rst sample (and all even numbered samples) comes from. The interleaving feature makes the AD9863 one of a kind among the over hundred dierent ADCs considered in this work. The BF537 demands on setup and hold times [3] as shown in g. 3.2. together with the AD9863 output timing.. The ad9863 datasheet [2] does. only specify typical values. In addition it is not specied how long time a transition takes, only when it typically occurs. Datasheets indicate that it could work if the data is clocked out on a rising edge and clocked in on the falling edge. Lab testing conrms this.. t−do 1.5ns. t−do 1.5ns. PPI_DATA_OUT. PPI_CLK_OUT. Framesync_in. Data_in. Figure 3.2:. setup. hold. 6.7. 1ns. setup. hold. 3.5. 1.5ns. Timing diagram for BF537 and AD9863. 3.3 Generating the sample clock To generate a sampling clock for the ADC was without question the most dicult part of this work.. 1/(π ∗ 10e6 ∗ 212 ∗. √. Eq.. 6) = 3.2ps. 2.16 tells us that an RMS jitter less than. is needed in order to obtain 12 bits accuracy. at 10MHz. In addition most ADC, AD9863 included, operate internally on both clock anks and have a 45%-55% dutycycle demand. Jitter is not an important parameter for digital logic such as microcontrollers and is generally unspecied. It seems as 100-500ps peak to peak jitter is concidered acceptable in digital logic, as seen in for instance an application note [13] from Xilinx.. Thus there is no reason to believe that digital clocks with. unspecied jitter will be usable as ADC klock source. There are many ways one can construct a low jitter clock source. One. 10.

(22) seemingly common method is to take a relatively noisy clock and lter it trough a PLL built around a VCXO (voltage controlled crystal oscillator). The PLL loop lter acts as a jitter lter as well and the VCXO itself got good jitter characteristics [6].. Another benet by using a clock generator. circuit like AD9510 (contains most hardware needed to build a PLL) is that the sampling frequency can be varied by sending digital commands. Building and evaluating the performance of such a clock generator is almost a master thesis in itself however.. The goal for this work was set to nd the best. possible integrated oscillator. Two seemingly promising oscillator manufacturers are Connor Wineld (osc.conwin.com) and Valpey Fisher (http://www.valpeyfisher.com/). Both manufacturers got oscillators satisfying the demands (3.3V, low jitter, 45%-55% dutycycle). Buying these oscillators in smaller quantities proved to be dicult though. Digikey (www.digikey.com) distributes many models from both manifacturers, but not any model satisfying all demands. 3.3V seemed to be the most dicult criterion, 5V models were more avalible. In the end the swedish company Kvartselektronik (www.kvartselektronik.se) was asked for help. The oscillator they oered, HG2150 from epson-toyocom, met the required dutycycle and voltage with a RMS jitter of 7ps. The jitter specications were not avalible on epson-toyocoms homepage, Kvartslektronik assumingly measured it themselves.. Anyway, this jitter level will. reduce SNR slightly at 10MHz (recall that at most 3ps was acceptable according to eq. 2.16). In the ultrasonic case of 400kHz input however this clock source won't degrade the measurement to any noticable extent and the clock was deemed good enough.. 3.4 Antialiasing ltering and ADC driving An ideal antialias lter should damp a fullscale input signal above the nyquist frequency (fSAM P /2) below the noiseoor, that is a dampingfactor equal to the entire dynamic range of the ADC. This puts tough demands on lter steepness (increasing order and complexity) unless large portions of the nyqvist bandwidth is to be sacriced. Under the assumption that most signals being measured already are reasonably bandlimited (which certainly is true in the ultrasonic case) the demands are quite dierent.. In that case. only noise and low amplitude signals (like ringings) is to be suppressed and the lter need not be so steep. A good tradeo can be accomplished with two cascaded LT6600. LT6600 is a fourth order chebychev like lter from Linear Technologies with xed cuto (2.5MHz, 5MHz, 10MHz and 20MHz versions available). In its simplest setup it requires only two external resistors to set passband gain. LT6600 has fully dierential output and is well suited to drive the ADC. Using LT6600. 11.

(23) is an ecient solution to both the antialiasing and single to dierential conversion issues. One complication is that all the ampliers are driven from. ±5V while the. ADC is driven from +3.3V and denitely should not have its inputs dragged below ground of above +3.3V. Diodes alone make bad protection circuitry since they start conducting (and thus distorting the signal) around 0.5V but doesn't short eciently until after around 0.9V. Also the drivers (LT6600 in this case) get its outputs shorted by the diodes resulting in unnecessary powerdrain. Because of the forwardvoltage. VF ,. the diodes need to be connected. to referencepoints 1V above ground and 1V below +3.3V to eectively limit the signal within 0-3.3V. A far better solution is to use a clipping buer like AD8036. It has sharper clipping characteristics than the diode solution and does not short any outputs. The AD8036 is single ended and must therefore be inserted before the LT6600 lters, this is not a problem however since clipping before the lters also guarantees voltage levels after due to the xed passband gain.. 3.5 Variable amplication As seen in g. 3.1 there are four possible gainsettings, 0x,1X,4X and 16X. 0X is possible since the fourth input of the mux is grounded, which is not shown in the gure. Why the values 4X and 16X? Well at rst a exponential scale has the same percentual dierence between gains. A linear scale on the other hand (such as 1X 8X 16X) gives bad precision at lower gains. Further more in the digital realm factors of two are more even than the perhaps more common, semi logarithmic, 1X 2X 5X 10X. The maximum gain of 16X is chosen because larger gains are not meaningful. At 16X the electrical noise of the input buer (see section 3.6) drowns any noise added by quantization (section 2.2) and the AD9863 (section 3.2). How was this gure of 16 decided?. First the total RMS noise (not noise. density) caused by the ADC is calculated. The ad9863 datasheet promised 67db (equals a factor 2239) SNR (at fullscale sinusoidal input). Full scale. √ 1/ 2 = 0.71VRM S . According to eq. NRM S = 0.71V /2239 = 317uV . How. input is 1V amplitude or. 2.11 the noise. caused by the ADC is. much noise is. added by the analog parts? Comparing noise gures on sees that the input buer OPA656 dominates with its noise gure of. √ 7nV / Hz .. To be able to. compare this against the ADC we could use eq. 2.6. Before we can use eq. 2.6 we must know over which bandwidth the noise density gure. √ 7nV / Hz. is valid. This bandwidth is set by the anti-aliasing lter to roughly 10MHz.. √ N = 7n ∗ 10M V = 22uV caused gain of 317uV /22uV = 14 the noise. Eq. now gives a total RMS noise voltage by the input stage. This means that at. contributed by the analog parts is roughly equal to the noise contributed by the ADC. Adding much more gain is not meaningful since the now domi-. 12.

(24) nant input buer noise is amplied as much as the signal and thus the SNR remains constant. Anyway 16X is the factor of 4 closest to 14, which is why the maximum gain was set to 16X. The dierent gains are meant to be changeable in realtime while measuring. The four input AD8184 analog multiplexer decides which of these gains should be fed into the AD8036 clipper. 0X is ground and functions as mute. 1X comes directly from the input buer. 4X is generated by an OPA843 in non inverting conguration. OPA843 is a unity gain stable OP with an input noise gure of. √ 2nV / Hz. typ. This is lower then the. √ 7nV / Hz. caused by. the input buer and doesn't signicantly degrade SNR. The 16X stage is an OPA847 also in non inverting conguration. OPA847 is stable from a gain of 12 with a noise gure of. √ 0.85nV / Hz .. Thus the OPA847 is well suited. to provide 16X gain. To avoid having higher gainstages clipping and making noise while using the lower ones, the unused stages are muted. The 4X stage is muted with a multiplexer since OPA843 lacks shutdown function.. It is suboptimal to. insert another buer in the signalpath, especially before amplication, but the best solution thought of to address muting.. The 16X stage needs no. multiplexer to mute since OPA847 got a shutdown pin. All ampliers, clippers and lters, except the input buer, are bipolar based. Bipolar inputs generate lower noisegures than eld eect ones, at the cost of higher input current noise and input bias currents in the order of. 10µA.. The current noise is insignicant since the impedances seen by all in-. puts are low. The bias currents need consideration though if DC precision is to be retained. Series resistors are added to the noninverting inputs matching the resistance seen by the inputs of the OPs, this greatly reduces oset and should not be overlooked in bipolar designs. It is easily shown that the oset due to biascurrent in non-inverting conguration is. Vof f = R ∗ Ibias. where R is the larger of the two resistors for all gains greater than two. As an example take R=1kΩ and I=37uA (OPA843), without resistance matching this would generate an oset of 37mV (37mV. 12. ∗ 22VLSB = 76LSB ). p−p. The series. resistors could also help stability by making the output see a more resistive load.. 3.6 Input stage A high input impedance was one of the design objectives. The non-inverting connection of the buer OP will see the same high impedance which puts demand on low bias currents and low current noise. The otherwise well suited OPA847 has a biascurrent of roughly 40uA that would cause 4V oset looking at 100kΩ input impedance. Input noise current of. √ 350nV / Hz. in the same. 100kΩ,. √ 3.5pA/ Hz. would cause. a huge value compared to the. promised by the FET based OPA656.. 13. √ 7nV / Hz. Although OPA656 got signicantly.

(25) Figure 3.3:. The input stage with protection and buer. √. higher voltage noise then OPA847 for instance (7nV /. Hz. vs.. √ 0.8nV / Hz ),. given the demand for high input impedance OPA656 makes the better choice for the input stage. Note that the opposite is true for all the other ampliers in the design. The low impedance after the input stage makes BJT amps the better choice there. Large input signals needs to be divided to avoid clipping. This is done the same way as in oscilloscopes (see g. 3.4). The input is given a well dened resistance to ground with a 1MΩ resistor. The switch on the 1X/10X probe changes the series resistance of the probe between 0Ω and 9MΩ respectively, producing a voltage division. A complication is the stray capacitance from tracks, protection diodes and buer. A quick look in respective datasheets gives an estimate of 5-10pF (Actually around 20pF was measured, see section 5.1). Oscilloscopes usually dene an input capacitance in the range 10pF30pF. Without compensation in the 10X probe a 20pF capacitance would. f = 1/(2 ∗ π ∗ R ∗ C) = 8kHz . The probe compensates C = 20pF/9 (usually trimable) in parallel with its 9MΩ.. give a bandwidth of with a capacitor of. If the capacitances have the same impedance ratios as the resistances the result will be constant division at all frequencies.. In summary the input. impedance is dened by a 1MΩ resistance in parallel with a capacitor that together with strays should produce capacitance around 20pF (so the probes in the lab can be used). Worth noting is also that a 10X probe loads the measured object 10 times less the a 1X, the impedance seen looking into the probe is 10M in parallel with 2.2pF instead of 1M in parallel with 22pF in the 1X case.. 14.

(26) INPUT Probe. 9M. CALIBRATE 2pF. BUFFERINPUT Oscilloscope. 1M. 18pF C_STRAY. GND. Figure 3.4:. Illustration of an oscilloscope probe with compensation capacitor.. There are many things to consider when it comes to overvoltage protection. First and foremost the protection must not cripple bandwidth by adding excessive stray. Schottky diodes or zeners alone are out of the question with strays in the range of 100pF-300pF. Low capacitance diodes like BAT18 (1.2pF max) connected to the voltage rails does not give good enough protection due to the forward voltage. Zeners connected to ground must be used to produce reference voltages to which the BAT18 diodes can be connected. The zeners high capacitance is not a problem since it is connected in series with the low capacitance BAT18. It is important that the zeners are biased to always conduct though, otherwise they will have to be charged trough BAT18 during transients, seriously crippling the response.. Diodes. alone wont do the trick though, a current limiting resistor is also needed. A quarter watt resistor of 640Ω can handle 12V overvoltage continuous. Since the diodes eats about 4V the input can handle. ±16V. continuous and a lot. more in short peaks. The bandwidth given by 640Ω and 5.2pF capacitance (2.8pF op + 2*1.2pF diode) gives a bandwidth of 48MHz which is okay.. 15.

(27) 3.7 Power supply The estimated power consumption is approx. 250mA for +5V and -5V each and 170mA for 3.3V. The regulator on the BF537-STAMP mother board supplies +5V at 4A, +3.3V at 4A. A nominally +7V rectied but otherwise unregulated supply is also available (nominal value depends on the AC adapter being used). Some power is consumed by the STAMP board itself but an amp or two should be available for this ADC expansion card. Since all analog circuits (except the ADC) requires created somehow.. ±5V. a -5V must be. The choice for -5V creation fell on a DC-DC converter. (CC3-0505 from TDK) which accepts 4.5V-9V as input and delivers isolated 5V±3% with about 75% eciency at 600mA. The DC-DC converter should preferably be driven from the unregulated supply to avoid unececeary load on the +5V STAMP regulator. The unregulated supply however is not drawn to the expansion slot of the STAMP board. The user is left with the option to change supply between +5V and external with a jumper.. Closing JP3. takes power from +5V, otherwise a cable can be connected from JP3 (the pin going to the regulator, not the +5V pin) to the top of the board where the unregulated supply is avalible. All supplies +5, +3.3, -5 are ltered trough a LC lter of 100uH and 100uF damping frequencies above. f = 1/(2 ∗ π ∗. √. LC = 1.6kHz .. Some. sensitive supplies are separated with ferrite beads.. 3.8 PCB considerations The expansion board is a four layer PCB. The layers from top to bottom are used as component place and primary routing, ground, supply, secondary routing.. The ground is separated into an analog and a digital part con-. nected at one place. Both digital and analog ground pins of the ADC are connected to the analog ground plane, the name DGND only indicates that it comes from the digital part inside the ADC (usable for connecting decoupling caps), not that it should be connected to the digital groundplane [12]. The analog and digital planes must be connected somewhere though and that somewhere was chosen to be below the digital lines connecting the ADC and buer to minimize the path taken by the digital return currents. Ground return currents try to keep directly below their respective digital signal [7], minimizing the inductance in the loop, and should not nd their way into the analog parts of the card in any greater extent with this ground layout.. 16.

(28) Chapter 4 Software design. 4.1 Overview A simple linux kernel module is written that presents the ADC as a le to the system programmer. The Unix system call read() takes destination memory address and an integer containing the number of bytes requested. A read() will turn on PPI, transfer the data with DMA, sleep, turn o the PPI and return. The PPI DMA channel has higher priority then the core processor when accessing memory meaning that it is guaranteed by design that high CPU load and interrupts won't cause PPI FIFO overows. AC/DC coupling and gain can be changed with the ioctl() system call.. 4.2 Capabilities of Blackn The blackn CPU used, BF537, got two types of memory.. On chip L1. memory running at the core frequency (at least 32Kb running at up to 750MHz) and up to 512Mb optional external SDRAM running at system clock frequency (up to 133MHz). The BF537-STAMP evaluation board used by Rubico contains 64MB SDRAM as well as power supply for the CPU and pinheads for easy lab connectivity.. As shown in g.. 4.1 the PPI got a. dedicated DMA channel into both L1 memory and external SDRAM. By default PPI DMA access to memory got highest priority, thus there is no risk that uClinux interferes with the transfer.. The simplest usage for the. platform is to buer up samples in SDRAM and process them when the sampling process is nished (this scheme is the only one implemented in this thesis). Another possibility is to let DMA stream data into two alternating buers in L1 RAM, process data in realtime (for example LP or BP ltering followed by decimation) and store the compressed result in SDRAM. Fancier details like this however, although relatively easy to implement, is a bit beyond the scope of this work.. 17.

(29) Figure 4.1:. Chip bus hierarchy. Image from [4]. .. 4.3 The uClinux interface Linux dene three basic driver types: stream, memory and network. Only three types may at a rst glance seem oversimplied, but thinking about it almost all devices can be characterized as one of the three types.. A brief. description of the device classes is given here, for more details the book Linux Device Drivers [8] is a good start. Char drivers.. This group is intended for all stream like devices.. A char. device generally does not support jumping back and forth, there is no real sense of position in the data stream (compare with a le on a harddrive where every byte in the le can be accessed in random order). The driver written in this work is of this type. Block devices. This is the category for memory like devices as harddrives and MMC cards. The device is seen as a big array and random memory positions can be read over and over again, as opposed to char devices where data is read from the end of the stream and disappears after being read once. Network devices are tailored to suit the needs of networking. information, see reference [8].. 18. For more.

(30) The types dier in the operations (called system calls) linux oers (and the driver implements) the user. The system calls serves as a common interface to all devices.. The user need not care if the device accessed is a. USB memory stick or a harddrive.. Since both are block devices they are. accessed in the same way from the users point of view, the driver handles the hardware specics. A bit simplied a driver can be seen as a collection of functions, each function representing a system call. When linux receives a system call from a user process it basically just forwards the call to the appropriate driver function which is in charge for actually executing the call. The driver need not implement all calls (for example write() makes no sense in an ADC driver).. If the user calls an unimplemented system call linux returns an. appropriate error code. A description of the system calls implemented in the driver of this work is presented here. open() (fcntl.h) performs some initializing and allocates the PPI for the user. Only one opening at a time is allowed. read() (unistd.h) reads a specied amount of data into a buer. This is done in the following steps:. the data cache is invalidated, a sanitycheck. is done on the buer to avoid overwriting something important like the kernel, the DMA controller is congured, the PPI port is enabled (starting the collection and DMA transfer), the call sleeps for DMA complete interrupt, DMA and PPI is shut down and the call returns. vread() (unistd.h) is short for vector read. Similar to read() but multiple destination memory areas can be specied in a single call. Useful if the memory is fragmented and it is hard to allocate large contiguous memory areas. This call is not implemented by the driver, but mentioned anyway since it could be useful to do so in the future. ioctl() (sys/ioctl.h) is the joker command.. Device specics like ejecting. a CD, changing baudrate on a serial port or changing the gain and AC/DC coupling on a ADC card can be implemented via this command. The ioctl() calls are (as opposed to the system calls) completely device specic and thus ioctl() should be used carefully.. The calls. implemented by the driver of this work are: PPI_SET_COUPLING, PPI_SET_CH0_GAIN, PPI_SET_CH1_GAIN. See the example code for details about how to use. close() (unistd.h) basically just sets a free ag on the ADC card so another process may open it.. 19.

(31) Chapter 5 Results. 5.1 Input stage characteristics Input stage. 100kOhm. 640 Ohm OPA656 Buffer. Vin. Stray1. Stray2. probe. probe GND. Figure 5.1:. Vout. GND. Test setup for input stray capacitance measuring. The test setup used is shown in g. g 3.3. When measuring the total stray,. 5.1.. For complete schematic see. Cstray1+2 ,. the input is assumed to. be a pure capacitance in parallel with a pure 1MΩ resistance, eects of for instance the current limiting resistance is neglected. Also the bandwidth of the OPA656 buer is signicantly higher then the expected -3dB point so its assumed ideal. The reason why the signal must be measured after the buer is that the probe capacitance isn't neglectable compared to the stray. The input frequency was swept until the -3dB point was found at 82kHz. This indicates an input stray capacitance of. Cstray1+2 = 1/(2 ∗ π ∗ f ∗ R) = 19pF ,. a result diering from the expected value of 5.2pF (2.8pF OP + 2*1.2pF diode). If the datasheets are correct, 14pF is added by tracks, connectors and the AC/DC relay.. 20.

(32) The bandwidth of the input stage should primarily be limited by the RC caused by the 640Ω current limiting resistor and strays from protection diodes and OP input,. Cstray2. (see g. 3.3 for details). This fact is used to. measure the stray added by the diodes and OP alone. A 17.5MHz (highest frequency attainable in the lab) sinusoidal was injected (without the 100kΩ resistor) resulting in a gain of 0.81 (0.71 would have been -3dB) from input BNC to output of buer OP. Since the 3dB point could not be found (due to signal generator limitations) a slightly more complicated calculation is needed to arrive at. Cstray2 = (1/G2 − 1)/(R ∗ 2 ∗ π ∗ f ) = 7pF .. 7pF and. 680Ω gives a bandwidth limit caused by the overvoltage protection of 33MHz. 7pF reasonably well corresponds to the expected 5.2pF expected by summing worst case capacitances from diode and op datasheets. This result enforces the theory that the rest of the stray originates from tracks, connectors and the relay.. 5.2 Measured analog characteristics 2500. 2000. 1500. LSB. 1000. 500. 0. −500. −1000. −1500. 0. 1. 2. 3. 4 Time. Figure 5.2:. 5. 6. 7 −7. x 10. Step response. Actual samples together with interpolated line.. The step response is shown in g 5.2. The plot is part of a sampled square wave. The signal reconstructed from the samples should correspond well to the actual analog signal at the ADC since the sampled signal is bandlimited. The overshoot and ringings corresponds to the gures from the LT6600-5 datasheet and is what was expected due to the ltering.. 21. This ringing is.

(33) unwanted if oscilloscope-like behavior is needed for transients. In that case the anti aliasing lter shouldn't be used.. On the other hand the ringings. doesn't matter if the the spectral content around 6MHz isn't of interest (as in the ultrasonic case). For more details about the frequency response of the LT6600-5, consult the datasheet. A common method to measure distortion is to inject a known clean sinusoidal and measures how much noise and harmonics are added by the system. Since no clean enough input sources was readily available in the lab, distortion wasn't measured. In order to get an noise estimate, the output was measured without input signal (grounded input). 20'000 samples were taken and brought into matlab. The RMS of the samples was calculated and the resulting eective number of bits (given by eq. 2.14) showed to be more then 10 in all gain stages, as can be seen in the table below. Gain Ein ADC Density. ENOB. SNR. X0. 352uV (0.72LSB). 144nV/rtHz. 10.7. 66.1dB. X1. 331uV (0.68LSB). 135nV/rtHz. 10.8. 66.6dB. X4. 377uV (0.77LSB). 154nV/rtHz. 10.6. 65.5dB. X16. 499uV (1.02LSB). 204nV/rtHz. 10.2. 63.0dB. It is important to remember that this is an estimate of the electrical noise in the ampliers. Noise caused by jitter (see section 2.4) and distortion (see section 2.3) at high input frequencies is not measured by this test.. 22.

(34) Chapter 6 Conclusions. 6.1 Meeting the objectives Looking back at the objectives outlined in section 1.1 we can see that all but one were met. Two analog channels does not work.. The AD9863 datasheet promises. the ability to interlace data, for example two channels of 25Msamples/s into one 50Msamples/s datastream. I was unable to congure the ADC to work in this mode, it just outputs one of the channels at 25Msamples/s.. The. hardware will need to be redesigned to implement two or more channels. If it isn't necessary to measure the two channels simultaneously (as in the ultrasonic case) one possibility is to use just one ADC and route the analog signal there with analog multiplexers. However the time is up and for now this objective is left as failed. Analog bandwidth of 10MHz is possible if one uses the 10MHz anti aliasing lter. It leaves us with poorer ltering but that should not be an issue if the input signal is already reasonably bandlimited. Because of the lack of low distortion signal generators no distortion gures were measured. However 10 bits accuracy with respect to noise is met (see section 5.2). The blackn is equipped with 64MB RAM. If half is taken by the system 32 is left, at a rate of 50Msaples/s this will give 0.3 seconds of storage which should be more than enough to measure pulses and echoes. The measurement board is quite exible since it got software controlled gainstages and standard BNC connectors compatible with regular oscilloscopeprobes.. With correct software the board could be used as a general. purpose low noise oscilloscope as well.. 23.

(35) 6.2 Further work The driver written, although completely functioning, is primarily intended as a proof of concept. There are many features, slightly outside the scope of this work, that could be useful to implement in a future version. Among these are External trigger to start a sampling sequence could be useful.. Could be. implemented completely in hardware by logically and the sync pin with the external trigger.. The trigger then would decide when the. sync pulse will be let trough and thus start the collection. This way a sampling sequence can be started per sample precision. Use a GPIO pin to indicate start of sampling sequence so external hardware (for example an ultrasonic transducer) can be triggered with greater precision by a read(). Implementing vread() in case the memory is fragmented and allocating large chunks is a problem. In conjunction with vread() it could be useful to use dierent gains for the dierent vectors, an otherwise troublesome timing problem. As it is now the channels are interleaved in the stream, it could be useful to let the DMA controller de-interlace the data into two dierent arrays. Try to build an lower jitter clock around a PLL with the possibility to set sampling frequency digitally.. 24.

(36) Chapter 7 Appendix A - Schematics. 25.

(37) 2. 4. RELAY_CNTRL1. RELAY_CNTRL0. 4. OUT1. DGND. OUT2. OUT2. OUT1. DGND DGND. IN2. IN1. 5. 7. 227161-BNC_JACK. U$7. IN2. IN1. 5. 7. +5V_UNFILTERED. 2. RELAY_CNTRL0. +5V_UNFILTERED. GNDA. 6. V+. V-. 3. GNDA. RELAY_CNTRL1. U$24. 227161-BNC_JACK. 6. V+. V-. 3. R46. 100. P$8. R2. 100. P$1. P$8. P$1. C25. P$6. AGN21003. U$27. P$6. 100nF. P$8. P$1. P$5. P$5. P$7. P$7. P$2. P$2. P$3. P$3. C2. P$6. AGN21003. U$49. P$6. 100nF. P$8. P$1. P$7. P$7. P$2. P$2. P$3. P$3. R47. R3. 1MEG. C1. 22pF. C24. 22pF. GNDA. 1MEG. GNDA. 640. R4. 640. R48. U$29 BAT18 U$11 BAT18. R25. 2. 3. R26. R69. 2. 3. -5V. 100n. C40. 100n. C39. 100n. C37. 100n. C38. OPA656. 6. U$1. +5V. -5V. OPA656. 6. U$21. GNDA GNDA. BZX84C3V3 BZX84C3V3 BZX84C3V3 BZX84C3V3. GNDA U$28 U$30 GNDA U$8 U$13. U$31 BAT18 GNDA U$14 BAT18 GNDA. R57. 100. -5V. R13. -5V. U$18 FDV310N CH2_D1. 7. 6. 5. 4. 3. 2. +5V. 100n. 7. 6. 5. 4. 3. 2. 1. +5V. C66. 100n. C70. 100. U$35 FDV310N CH1_D1. GNDA. 7 4 7 4. GNDA GNDA. GNDA GNDA. R70. GNDA. GNDA. GND0. 100n. C69. +5V. A3. GND2. A2. GND1. A1. A3. GND2. A2. GND1. A1. U$23. -5V. AD8184. D1. D0. OUT. INV_EN. +5V. -5V. U$5 FDV310N. 100n. C65. +5V. AD8184. D1. D0. OUT. INV_EN. U$4. U$34 FDV310N. GND0. A0. +5V 14 VPOS VNEG. A0. 12CH2_D1. 13CH2_D0. 10. 11. 12CH1_D1. 13CH1_D0. 10. 11. GNDA GNDA. R8. 56. R5. 150. R52. 56. R49. 150. 2. 3. 8. 2. 3. 2. 3. 8. 2. 3. DIS. DIS. -5V. OPA847. 6. U$3. +5V. -5V. OPA843. 6. U$2. +5V. -5V. OPA847. 6. U$22. +5V. -5V. OPA843. 6. U$17. +5V. -5V. -5V. 100n. C64. 100n. C44. 100. GNDA 100n. C42. -5V. 100n. C62. R12. 100. R11. 100. 100n. C63. +5V. -5V. R56. 100. R55. 100n. C43. +5V. 100n. C61. +5V. 100n. C41. +5V. 100 R58. 100 R14. 7. 6. 5. 4. 3. 2. 1. 7. 6. 5. 4. 3. 2. 1. -5V. A3. GND2. A2. GND1. A1. GND0. A0. C46. -5V. A3. GND2. A2. GND1. A1. U$32. +5V U$16. 100n. C60. 12CH1_D1. 13CH1_D0. 12CH2_D1. 13CH2_D0. 10. 11. C67. 100n. 100n. C59. R59. 56. +5V. POS_CLIP. 100n. C45. +5V. AD8184. D1. D0. OUT. INV_EN. -5V. 11. 10. +5V. AD8184. D1. D0. OUT. -5V. 100n. GND0. A0. +5V. INV_EN. 14 VPOS. 7 4 7. 8 14 VPOS VNEG 8. P$4. P$4. P$5. P$5. P$4. P$4. GNDA. GNDA GNDA. 4 7 4 7. 4. 560 100 220 1k. GNDA. 56 R15. C48 100n. 100n. C47. +5V. R60. 56. NEG_CLIP. AD8036. 6. U$26. POS_CLIP. 6. 100n. C57. +5V. 100n. -5V. AD8036 NEG_CLIP. R16. 56. -5V. POS_CLIP U$10. GNDA NEG_CLIP. -5V. C58. 2. 3. +5V. C68. 100n. -5V. -5V. 2. 3. +5V 7 8. GNDA R51 R54 R50 R74. GNDA. R71 R1. 120 120. GNDA. R19. R18. R63. R62. R61. R20. C72. R17. R64. C73. C3. -5V. +5V. -. 100n. C56. -5V. VMID. VOCM. +. 100n. C50. -. VMID. VOCM. +. -5V. 1. 7. 2. 8. -5V. C26. 1. 7. 2. 8. +5V. 5. 4. 5. 4. 100n. C55. +5V. LT6600. ON. OP. U$9. 100n. C49. +5V. LT6600. ON. OP. U$25. R24. R23. R68. R67. R65. R22. C71. R21. R66. C74. AVCCA. R72 R73. 1. GNDA GNDA. R75 150 GNDA. GNDA. R53 R76 R7. 1k. R6. 100 560 220 R10 R9. R77 150. GNDA GNDA. GNDA GNDA. 3.3k 1.2k. GNDA R80. 3 V+ V-. GNDA GNDA. R78 R79. 1.2k 3.3k. VNEG 8. GNDA GNDA. 8 14 VPOS. VNEG. GNDA GNDA. GNDA GNDA. 4 5 7 8 4 5. GNDA GNDA. GNDA GNDA. R81 GNDA. GNDA. 6. GNDA 3 V+ 6. 1k 1k AVCCA. R27 R28. C4. C27. 1. 7. 2. 8. 1. 7. 2. 8. +5V. -5V. -. VMID. VOCM. +. +5V. -5V. -. VMID. VOCM. +. 3 V+. +5V. GNDA. V-. GNDA. U$33. U$19. -5V. CH1-. CH1+. 100n. C54. 5. LT6600. ON. OP. 100n. 4. -5V. CH2-. CH2+. C52. 5. 4. LT6600. ON. OP. GNDA. V6 3 V+ V6. GNDA 1k 1k GNDA. Schematics 26 for the analog stage. GNDA. GNDA GNDA. Figure 7.1:. 100n. C53. +5V. 100n. C51. +5V.

(38) DGND. 100n. DVCC C78. Utgående digitala buffer. 100n. 10u. C32. U$40. DR74. DGND. C33. 100u. DGND. 10u. C82. C83. V_UNREG. 1 2. JP3. +. U$38. +. P$2. P$3. P$1. 100u. C79. 100u. C80. CC3-0505. SHUTDOWN. VIN-. VIN+. U$12. +. L4. 10u. C35. GNDA. DR74. AVCCA L3. DIS. OUT-. OUT+. AVCCA. P$6. P$5. P$7. 100n. C34. +5V. 100n. C36. 10u. C31. 10u. C23. 100n. C30. 100n. C22. L5. U$39. DR74. CLK_VCC. ADC Analog matning. 10u. C75. GNDA. L2. +. 10u. C77. AVCCD. ADC Digital matning. 100u. C81. -5V. 100n. C29. SPI_MISO. SPI_CLK. CLK_VCC. 1 3 5 7. P$2. P$4. 10u. C76. En 10U per matningsplan. 10u. C28. GNDA. JP2 2 4 6 8. OE. U$6. JP1 HG2150-CA. GND CLK. VCC. 2 4 6 8 10 P$3. P$1. DGND. 470. +5V_UNFILTERED. GNDA. R31 C18. C17. C20. AVCCD. C16. C15. AVCCA. 100n 100n GNDA. C21. ADCLK. ADCLK AVCCA. GNDA. 100n 100n 100n 100n 100n. C19. DVCC. 100k RX_CLK. GNDA ADC_RESET_INV. GNDA. SPI_MOSI. GNDA. GNDA. 1 3 5 7 9. R29 470. R30. DVCC. P$63. P$15. P$14. P$8. P$9. P$12. P$11. P$59. P$53. P$49. P$13. P$10. P$61. P$51. P$50. P$16. P$7. P$32. P$6. P$31. P$5. P$4. P$47. P$48. P$46. P$18. P$17. P$33. P$3. P$2. P$1. P$64. AD8963. TXPWRDWN. IOUT-B. IOUT+B. IOUT-A. IOUT+A. FSADJ. REFIO. AGND59. AGND53. AGND49. AGND13. AGND10. AVDD61. AVDD51. AVDD50. AVDD16. AVDD7. DRVSS. DVSS. DRVDD. DVDD. ADC_LO_PWR. CLKIN2. CLKIN1. RESET_INV. IFACE3/CLK_OUT. IFACE2_12/24INV. IFACE1_TX/RXINV. SPI_SDO/FD_HDINV. SPI_CLK/INTERP0. SPI_DIO/INTERP1. SPI_CS. U$15G$1. BOTTOM_PAD_GND. SPI_CS. GNDA. 27 P$65. Power and ADC schematics.. U11. RXPWRDWN. REFB. REFT. VREF. VIN-B. VIN+B. VIN-A. VIN+A. L0. L1. L2. L3. L4. L5. L6. L7. L8. L9. L10. L11. U0. U1. U2. U3. U4. U5. U6. U7. U8. U9. U10. P$62. P$52. P$60. P$56. P$55. P$54. P$57. P$58. P$45. P$44. P$43. P$42. P$41. P$40. P$39. P$38. P$37. P$36. P$35. P$34. P$30. P$29. P$28. P$27. P$26. P$25. P$24. P$23. P$22. P$21. P$20. P$19. GNDA. Figure 7.2: C7. 100n. C8. 10u. REFT-ADC C9. VREF-ADC. A[0..11],SYNC. 100n REFB-ADC. CH2-. CH2+. CH1-. CH1+. A0. A1. A2. A3. A4. A5. A6. A7. A8. A9. A10. A11. SYNC. GNDA. C5 100n. C10 100n. 10u. C6. A0. A1. A2. A3. A4. A5. A6. A7. A8. A9. A10. A11. SYNC. RX_CLK. C12. DGND. 100n 100n. C11. DVCC. DGND. R45. R44. R43. R42. R41. R40. R39. R38. R37. R36. R35. R34. R33. R32. 100n 100n. C14. VCC4. VCC3. VCC2. VCC1. 4OE_INV. 3OE_INV. 2OE_INV. 1OE_INV. 4A4. 4A3. 4A2. 4A1. 3A4. 3A3. 3A2. 3A1. 2A4. 2A3. 2A2. 2A1. 1A4. 1A3. 1A2. 1A1. C13. 31. 42. 18. 7. 24. 25. 48. 1. 26. 27. 29. 30. 32. 33. 35. 36. 37. 38. 40. 41. 43. 44. 46. 47. U$20. Y0. Y1. Y2. Y3. Y4. Y5. Y6. Y7. Y8. Y9. Y10. Y11. Y_SYNC. Y_RX_CLK. DGND. 28. 34. 39. 45. 21. 15. 10. 4. 23. 22. 20. 19. 17. 16. 14. 13. 12. 11. 9. 8. 6. 5. 3. 2. Y[0..11]. To expansion conenctor. SN74ALVCH162244. GND4B. GND4A. GND3B. GND3A. GND2B. GND2A. GND1B. GND1A. 4Y4. 4Y3. 4Y2. 4Y1. 3Y4. 3Y3. 3Y2. 3Y1. 2Y4. 2Y3. 2Y2. 2Y1. 1Y4. 1Y3. 1Y2. 1Y1.

(39) Connections to the BF537-STAMP board.. DGND. J1P$73. J1P$74. J1P$75. Y1. Y2. Y3. +5V_UNFILTERED J1P$90. J1P$88. J1P$82. J1P$85. J1P$84. J1P$76. J1P$72. J1P$38. J1P$24. J1P$23. J1P$22. J1P$21. J1P$20. J1P$19. J1P$18. J1P$17. J1P$16. J1P$15. J1P$14. J1P$13. J1P$12. J1P$11. J1P$10. J1P$9. J1P$8. J1P$7. J1P$6. Y0. DGND. DGND. J1P$4. +5V_UNFILTERED J1P$2. 5V_EL$2. 5V_EL_J1_P90. GND_J1_P88. PF4/PB3. PF3/PB2. PF2/PB1. POE_VCC+. PG3/ELVIS_PF5/PPI3. PG2/ELVIS_PF2/PPI2. PG1/ELVIS_PF1/PPI1. PG0/ELVIS_TRIGGER/PPI0. GND_P38. ADDR_$19. ADDR_$18. ADDR_$17. ADDR_$16. ADDR_$15. ADDR_$14. ADDR_$13. ADDR_$12. ADDR_$11. ADDR_$10. ADDR_$9. ADDR_$8. ADDR_$7. ADDR_$6. ADDR_$5. ADDR_$4. ADDR_$3. ADDR_$2. ADDR_$1. GND_P4. 5V_EL_J1_P89. GND_J1_P87. PF7/LED2/PPI_FS3. PF6/LED1. PF5/PB4. POE_VCC-. PF15/CAN_STB-/PPI_CLK. GND_J1_P37. DATA_$15. DATA_$14. DATA_$13. DATA_$12. DATA_$11. DATA_$10. DATA_$9. DATA_$8. DATA_$7. DATA_$6. DATA_$5. DATA_$4. DATA_$3. DATA_$2. DATA_$1. DATA_$0. GND_P3. 5V_EL$1. J1P$1. J2P$56. J1P$43. J1P$89. J1P$87. J1P$80. J1P$81. J1P$83. J1P$77. J1P$71. J1P$37. J1P$54. J1P$53. J1P$52. J1P$51. J1P$50. DGND. DGND. Y_RX_CLK. Y_SYNC. J1P$48. Y11. DVCC. DVCC. J2P$90. J2P$88. J2P$86. J2P$84. J2P$82. J2P$80. J2P$76. J2P$74. J2P$70. J2P$68. J2P$64. J2P$66. J2P$54. J2P$53. CH2_D1. J2P$52. CH2_D0. J2P$51. J2P$50. CH1_D1. CH1_D0. J2P$49. J2P$48. Y9 Y10. J2P$47. J2P$46. Y7 Y8. J2P$45. J2P$44. J2P$43. J2P$11. J2P$9. J2P$12. J2P$10. J2P$25. Y6. Y5. Y4. SPI_CLK. SPI_MISO. SPI_MOSI. RELAY_CNTRL1. J1P$47. J1P$49. J2P$23. RELAY_CNTRL0. J1P$46 J2P$24. ADC_RESET_INV J2P$26. J1P$45. J1P$44. J2P$58. J1P$42. J2P$16. J2P$57. DGND. J2P$4. J2P$2. DGND J2P$14. DVCC. J1P$41. J1P$40. J1P$39. J1P$3. 3V_BP_P90. GND_J2_P88. SWE_INV. SA10. SRAS_INV. ABE0_INV_B. 3V_BP_P76. SMS_INV. AWE_INV. AOE_INV. ABE1_INV. ABE0_INV. PG15/USB_IRQ/PPI15_B. PG14/PPI14_B. PG13/PPI13_B. PG12/PPI12_C. PG11/PPI11. PG10/PPI10_B. PG9_PPI9. PG8/PPI8_B. PG7/UART0_RTS/PPI7. PG6/UART_CTS. PG5/ELVIS_PF7/PPI5. PG4/ELVIS_PF6/PPI4. PF14/CAN_EN/SPI_SS. PF13/CAN_ERR/SPI_CLK. PF12/AUDIO_RESET/SPI_MISO. PF11/LED_06/SPI_MOSI. PF9/LED4/PPI_FS1_J2. PF8/LED3/PPI_FS2. PF7/LED2/PPI_FS3_J2. PF6/LED1_B. PF4/PB3_B. PF3/PB2_B. PF2/PB1_B. PF0/UART0_TX_J2. 3V_BP_P14. GND_J2_P4. 3V_BP_P$2. 3V_BP_P$1. 3V_BP_89. GND_J2_P87. SCLK. SCAS_INV. SCKE. ABE1_INV_B. GND_J2_P75. ARE_INV. ARDY. AMS3_INV. AMS2_INV. AMS1_INV. AMS0_INV. PF14/CAN_EN_B. PJ11/DT0PRI. PJ10/TFS0. PJ9/TSCLK0. PJ8/DR0PRI. PJ7/RFS0. PJ6/RSCLK0. PJ5/CAN_TX. PJ4/CAN_RX. PG15/USB_IRQ/PPI15_A. PG14/PPI14. PG13/PPI13. PG12/PPI12. PG11/PPI11_B. PG10/PPI10. PG9/PPI9. PG8/PPI8. NMI_INV. GND_J2_P13. GND_J2_P3. J2P$89. J2P$87. J2P$85. J2P$83. J2P$81. J2P$79. J2P$75. J2P$69. J2P$67. J2P$59. J2P$61. J2P$63. J2P$65. J2P$55. J2P$38. J2P$40. J2P$42. J2P$37. J2P$39. J2P$41. J2P$36. J2P$35. J2P$30. J2P$32. J2P$34. J2P$29. J2P$31. J2P$33. J2P$28. J2P$27. J2P$17. DVCC. DGND. DGND. J3P$4. J3P$26. J3P$24. J3P$18. J3P$17. J3P$7. J3P$8. J3P$5. J3P$6. DGND. DGND. J3P$88. J3P$85. J3P$83. J3P$81. J3P$66. J3P$44. J3P$42. J3P$41. J3P$29. +5V_UNFILTERED. J3P$27. J3P$25. J3P$30. J3P$28. +5V_UNFILTERED. SPI_CS. DGND. DGND. DGND. DGND. J2P$1 DVCC J2P$3 J2P$13. From digital buffer. GND_J3_P88. BGH_INV. BG_INV. BR_INV. 3V_BP_J3_P66. GND_J3_P44. PJ1/MDIO. PJ0/MDC. CLKBUF. 5V_EL_J3_P27. GND_J3_P25. RESET_INV_B. RESET_INV. 5V_EL_J3_P26. GND_J3_P24. PF10/LED5/SPI_SSEL1. PF6/LED1_J3. PF3/PB2_J3. PF2/PB1_J3. PF1/UART0_RX. PF0/UART0_TX_J3. GND_J3_P4. DONT_USE J3P$71. 28. DONT_USE2 J3P$72. Figure 7.3:. GND_J3_P87. 3V_BP_J3_P65. GND_J3_P43. PH15/CRS. PH14/ERXER. PH13/ERXCLK. PH12/ERXDV. PH11/ERXD3. PH10/ERXD2. PH9/ERXD1. PH8/ERXD0. PH7/COL. PH6/PHYINT. PH5/TXCLK. PH4/EXTEN. PH3/EXTD3. PH2/EXTD2. PH1/EXTD1. PH0/EXTD0. PJ3/SDA. PJ2/SCL. GND_J3_P3. J3P$87. J3P$65. J3P$43. J3P$40. J3P$39. J3P$38. J3P$37. J3P$36. J3P$35. J3P$34. J3P$33. J3P$32. J3P$31. J3P$16. J3P$15. J3P$14. J3P$13. J3P$12. J3P$11. J3P$10. J3P$9. J3P$3. DGND. DVCC. DGND. DGND.

(40) 3/28/2007 09:16:24 /home/axel/exjobb/xjobb eagle/rapport scematics/New_Project_1/exjobb.brd. 29. U$50. U$7. U$36. U$24. U$49. R3. R47. R46 R2 C2. R25. U$14. U$11. U$27. R69. U$31. U$29. C38. U$1. R26. C40. U$21. R70. C37. C39. Top routing layer, component side. 1. www.rubico.se. U$13. C1. R4. U$8. U$30. C24. R48. U$28. C25. R13. R57. U$4. U$23. R8. C66. C65. R52. C70. C69. C44. R5. R49. C62. C64. R77. R6. R53. R54 R50. U$3. U$2. C42. U$22. U$17. R9. C61. R76. C63. R75. C41. R51. C43. R10. R7. R74. R1. U$5. R12. R11. R14. R71. U$34. R56. R55. R58. U$18. C60. U$16 C59. U$35. C46. U$10. R64. R19. C72. R18. R20. U$9. R17. C29. C3. R16. C26 R80. U$25. R61. R15 C58. R63. C73. R62. C48. R59. R60. R24. C71. R23. C57. R68. C74. R67. C28. C55. C56. C67. C49 R81. C50. C47. R79. L2. R22. U$19. R21. C68. R78. R66. U$33. R65. C81. C36. U$39. C53. L4. C27. C4. C75. C76. R27. R28. C54. C51. R72. C35. C82. R73. C52. C79. C34. C7. JP2. JP1. C10. C5. C18. C17. R30. C19. U$12. CC3-0505. C9. C8. U$38. C6. U$26. C21. U$6. C33. R29. C16 C15. C31. L5. C32. R31. L3. C23. C20. C30. C22. C77. C45. R32. R34. R36. R38. R40. R42. R44. R33. R35. R37. R39. R41. R43. R45. U$40. C80. C83. U$32. C11. C14. JP3. Figure 7.4: C78. U$20. C13. C12.

(41) 3/28/2007 09:17:32 /home/axel/exjobb/xjobb eagle/rapport scematics/New_Project_1/exjobb.brd. 30. U$50. U$7. U$36. U$49. R3. R47. C1. R4. U$8. R46. C2. R25. U$14. U$11. U$27. R69. U$31. U$29. C38. U$1. R26. C40. U$21. R70. C37. C39. 2. www.rubico.se. U$13. R2. C24. R48. U$30. U$24. U$28. C25. R13. R57. U$4. U$23. R8. C66. C65. R52. C70. C69. C44. R5. R49. C62. C64. R77. R6. R53. R54 R50. U$3. U$2. C42. U$22. U$17. R9. C61. R76. C63. R75. C41. R51. C43. R10. R7. R74. R1. U$5. R12. R11. R14. R71. U$34. R56. R55. R58. U$18. C60. U$16 C59. U$35. C46. U$10. R64. R19. C72. R18. R20. U$9. R17. C29. C3. R16. C26 R80. U$25. R61. R15 C58. R63. C73. R62. C48. R59. R60. R24. C71. R23. C57. R68. C74. R67. C28. C55. C56. C67. C49 R81. C50. C47. R79. L2. R22. U$19. R21. C68. R78. R66. U$33. R65. C81. C36. U$39. C53. L4. C27. C4. C75. C76. R27. R28. C54. C51. R72. C35. C82. R73. C52. C79. C34. C7. JP2. JP1. C10. C5. C18. C17. R30. C19. U$12. CC3-0505. C9. C8. U$38. C6. U$26. C21. U$6. C33. R29. C16 C15. C31. L5. C32. R31. L3. C23. C20. C30. C22. C77. C45. R32. R34. R36. R38. R40. R42. R44. R33. R35. R37. R39. R41. R43. R45. U$40. C80. C83. U$32. C11. C14. JP3. Figure 7.5:. Ground plane, ANGD and DGND connected between ADC and digital buer. C78. U$20. C13. C12.

(42) Figure 7.6:. Powerplanes.. 3/28/2007 09:18:49 /home/axel/exjobb/xjobb eagle/rapport scematics/New_Project_1/exjobb.brd. 31. U$50. U$7. U$36. U$49. R3. R47. C1. R4. U$8. R46. C2. R25. U$14. U$11. U$27. R69. U$31. U$29. C38. U$1. R26. C40. U$21. R70. C37. C39. 3. www.rubico.se. U$13. R2. C24. R48. U$30. U$24. U$28. C25. R13. R57. U$4. U$23. R8. C66. C65. R52. C70. C69. C44. R5. R49. C62. C64. R77. R6. R53. R54 R50. U$3. U$2. C42. U$22. U$17. R9. C61. R76. C63. R75. C41. R51. C43. R10. R7. R74. R1. U$5. R12. R11. R14. R71. U$34. R56. R55. R58. U$18. C60. U$16 C59. U$35. C46. U$10. R64. R19. C72. R18. R20. U$9. R17. C29. C3. R16. C26 R80. U$25. R61. R15 C58. R63. C73. R62. C48. R59. R60. R24. C71. R23. C57. R68. C74. R67. C28. C55. C56. C67. C49 R81. C50. C47. R79. L2. R22. U$19. R21. C68. R78. R66. U$33. R65. C81. C36. U$39. C53. L4. C27. C4. C75. C76. R27. R28. C54. C51. R72. C35. C82. R73. C52. C79. C34. C7. JP2. JP1. C10. C5. C18. C17. R30. C19. U$12. CC3-0505. C9. C8. U$38. C6. U$26. C21. U$6. C33. R29. C16 C15. C31. L5. C32. R31. L3. C23. C20. C30. C22. C77. C45. R32. R34. R36. R38. R40. R42. R44. R33. R35. R37. R39. R41. R43. R45. U$40. C80. C83. U$32. C11. C14. JP3. C78. U$20. C13. C12.

(43) 3/28/2007 09:14:24 /home/axel/exjobb/xjobb eagle/rapport scematics/New_Project_1/exjobb.brd. 32. U$50. U$7. U$36. U$49. R3. R47. C1. R4. U$8. R46. C2. R25. U$14. U$11. U$27. R69. U$31. U$29. C38. U$1. R26. C40. U$21. R70. C37. C39. Bottom routing layer. 4. www.rubico.se. U$13. R2. C24. R48. U$30. U$24. U$28. C25. R13. R57. U$4. U$23. R8. C66. C65. R52. C70. C69. C44. R5. R49. C62. C64. R77. R6. R53. R54 R50. U$3. U$2. C42. U$22. U$17. R9. C61. R76. C63. R75. C41. R51. C43. R10. R7. R74. R1. U$5. R12. R11. R14. R71. U$34. R56. R55. R58. U$18. C60. U$16 C59. U$35. C46. U$10. R64. R19. C72. R18. R20. U$9. R17. C29. C3. R16. C26 R80. U$25. R61. R15 C58. R63. C73. R62. C48. R59. R60. R24. C71. R23. C57. R68. C74. R67. C28. C55. C56. C67. C49 R81. C50. C47. R79. L2. R22. U$19. R21. C68. R78. R66. U$33. R65. C81. C36. U$39. C53. L4. C27. C4. C75. C76. R27. R28. C54. C51. R72. C35. C82. R73. C52. C79. C34. C7. JP2. JP1. C10. C5. C18. C17. R30. C19. U$12. CC3-0505. C9. C8. U$38. C6. U$26. C21. U$6. C33. R29. C16 C15. C31. L5. C32. R31. L3. C23. C20. C30. C22. R32. R34. R36. R38. R40. R42. R44. R33. R35. R37. R39. R41. R43. R45. U$40. C80. C83. C45. C11. C14. JP3. U$32. C77. Figure 7.7:. C78. U$20. C13. C12.

(44) Bibliography [1] Brad Brannon. An-756: Sampled systems and the eects of clock phase. http://www.analog.com/en/Search/productSearch. asp?queryText=an756 (2007-03-16).. noise and jitter.. [2] Analog Devices. Ad9863 datasheet.. www.analog.com. (2007-03-20).. [3] Analog Devices. Adsp-bf534/adsp-536/adsp-537 blackn embedded processor data sheet (rev.c). [4] Analog Devices.. www.analog.com. (2007-03-20).. ADSP-BF537 Blackn Processor Hardware Reference.. Analog Devices, 2.0 edition, 2005. [5] Clare D. McGillem George R. Cooper.. and System Analysis.. [6] Ted. Harris.. Probabilistic Methods of Signal. Oxford University Press, 3rd edition, 1999.. Generating. multiple. clock. outputs. from. the. http://www.analog.com/en/Search/productSearch. asp?queryText=an769 (2007-03-20). ad9540.. [7] Martin Graham Howard Johnson.. High-Speed Digital Design.. Prentice. Hall, 1993. [8] Greg Kroah-Hartman Jonathan Corbet, Alessandro Rubini.. vice Drivers.. [9] Walt Kester.. Linux De-. O'Reilly, 3rd edition, 2005. Mt-001:. Taking the mystery out of the infamous. http:// www.analog.com/en/content/0,2886,760%255F%255F88014,00.html formula,. snr=6.02+1.76db,. and why you should care.. (2007-03-16). [10] Walt Kester. Mt-003: Understand sinad, enob, snr, thd, thd + n, and. http://www.analog.com/ en/content/0,2886,760%255F%255F91250,00.html (2007-03-16). sfdr so you don't get lost in the noise oor.. [11] Rudy van de Plassche.. to Analog Converters.. CMOS Integrated Analog to Digital and Digital Kluwer Academic Publishers, 2nd edition, 2003.. 33.

(45) [12] James Bryant walt Kester. Grounding in high speed systems.. search.analog.com/search/default.aspx?query=tv7b. http://. (2007-03-20),. TV7B.pdf. [13] Xilinx.. Superior jitter management with dlls.. com/products/virtex/techtopic/vtt013.pdf. 34. http://www.xilinx. (2007-03-20)..

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