Institutionen för systemteknik
Department of Electrical Engineering
Design of a Time-to-Digital Converter for an
All-Digital Phase Locked Loop for the 2-GHz Band
Examensarbete utfört i Elektroniksystem vid Tekniska högskolan i Linköping
Balamurali Radhakrishnan Naveen Wali
Department of Electrical Engineering Linköpings tekniska högskola Linköpings universitet Linköpings universitet SE-581 83 Linköping, Sweden 581 83 Linköping
Design of a Time-to-Digital Converter for an
All-Digital Phase Locked Loop for the 2-GHz Band
Examensarbete utfört i Elektroniksystem
vid Tekniska högskolan i Linköping
Balamurali Radhakrishnan Naveen Wali
Handledare: Muhammad Touqir Pasha
ISY, Linköpings Universitet
Examinator: Dr. J Jacob Wikner
ISY, Linköpings Universitet
Division of Communication Systems Department of Electrical Engineering Linköpings universitet
SE-581 83 Linköping, Sweden
Datum Date 2013-06-14 Språk Language Svenska/Swedish Engelska/English Rapporttyp Report category Licentiatavhandling Examensarbete C-uppsats D-uppsats Övrig rapport
URL för elektronisk version
http://www.commsys.isy.liu.se http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-ZZZZ ISBN — ISRN LiTH-ISY-EX--13/4684--SE
Serietitel och serienummer
Title of series, numbering
Design of a Time-to-Digital Converter for an All-Digital Phase Locked Loop for the 2-GHz Band
Balamurali RadhakrishnanNaveen Wali
An all-digital phase locked loop for WiGig systems was implemented. The developed all-digital phase locked loop has a targeted frequency range of 2.1-GHz to 2.5-GHz. The all-digital phase locked loop replaces the traditional charge pump based analog phase locked loop. The digital nature of the all-digital phase locked loop system makes it superior to the analog counterpart.There are four main parts which constitutes the all-digital phase locked loop. The time-to-digital converter is one of the important block in all-digital phase locked loop.
Several time-to-digital converter architectures were studied and simulated. The Vernier delay based architecture and inverter delay based architecture was designed and evaluated. There architectures provided certain short comings while the pseudo-differential time-to-digital converter architecture was chosen, because of it’s less occupation of area. Since there exists a relationship between the size of the delay cells and it’s time resolution, the pseudo-differential time-to-digital converter severed it’s purpose.
The whole time-to-digital converter system was tested on a 1 V power sup-ply, reference frequency 54-MHz which is also the reference clock Fref, and
a feedback frequency Fckv 2.1-GHz. The power consumption was found to
be around 2.78 mW without dynamic clock gating. When the clock gating or bypassing is done, the power consumption is expected to be reduced considerably. The measured time-to-digital converter resolution is around 7 ps to 9 ps with a load variation of 15 fF. The inherent delay was also found to be 5 ps. The total output noise power was found to be -128 dBm.
An all-digital phase locked loop for WiGig systems was implemented. The devel-oped all-digital phase locked loop has a targeted frequency range of 2.1-GHz to 2.5-GHz. The all-digital phase locked loop replaces the traditional charge pump based analog phase locked loop. The digital nature of the all-digital phase locked loop system makes it superior to the analog counterpart.There are four main parts which constitutes the all-digital phase locked loop. The time-to-digital converter is one of the important block in all-digital phase locked loop.
Several time-to-digital converter architectures were studied and simulated. The Vernier delay based architecture and inverter delay based architecture was de-signed and evaluated. There architectures provided certain short comings while the pseudo-differential time-to-digital converter architecture was chosen, because of it’s less occupation of area. Since there exists a relationship between the size of the delay cells and it’s time resolution, the pseudo-differential time-to-digital converter severed it’s purpose.
The whole time-to-digital converter system was tested on a 1 V power supply, reference frequency 54-MHz which is also the reference clock Fref, and a feedback
frequency Fckv 2.1-GHz. The power consumption was found to be around 2.78
mW without dynamic clock gating. When the clock gating or bypassing is done, the power consumption is expected to be reduced considerably. The measured time-to-digital converter resolution is around 7 ps to 9 ps with a load variation of 15 fF. The inherent delay was also found to be 5 ps. The total output noise power was found to be -128 dBm.
We would like to thank a lot of people:
Dr. J Jacob Wikner for his precious help and support throughout the span of master thesis at different stages technically as a mentor and examiner.
Muhammad Touqir Pasha for supervising throughout the project providing study materials and basic knowledge on work. Also we would like to thank Niklas U Andersson for his help.
Family and friends for their all kinds of help and support.
1 Introduction 5
1.1 Motivation- Moving to Time Domain . . . 5
1.2 Project Specification . . . 6
1.3 Contributions of the Thesis . . . 7
1.4 Organization of Thesis . . . 8
2 Phase locked loops 9 2.1 Introduction . . . 9 2.2 Applications . . . 10 2.2.1 Clock Generation . . . 10 2.2.2 Clock Recovery . . . 10 2.2.3 De-skewing . . . 10 2.2.4 Jitter reduction . . . 10
2.3 Analog Phase Locked Loop . . . 10
2.3.1 Phase/Frequency Detector . . . 11
2.3.2 Charge Pump . . . 12
2.3.3 Phase/Frequency Detector with Charge Pump . . . 14
2.3.4 Loop Filter . . . 14
2.3.5 Voltage Controlled Oscillator . . . 15
2.3.6 Frequency Divider . . . 16
2.3.7 Linear Model of Analog PLL in S-Domain . . . 17
2.4 Digital Phase Locked Loop . . . 18
2.4.1 Time-to-Digital Converter . . . 18
2.4.2 Digital Loop Filter . . . 23
2.4.3 Digitally Controlled Oscillator . . . 24
2.5 Comparison of Analog and Digital Phase Locked Loop . . . 27
2.6 Results . . . 27
2.6.1 Analog PLL - High-level Design . . . 27
2.6.2 Performance Parametric of DPLL . . . 28 2.7 Conclusion . . . 32 3 Time-to-digital converters 33 3.1 Introduction . . . 33 3.2 TDC Working Principle . . . 33 ix
3.3 TDC Resolution . . . 34
3.4 Buffer Delay Line Based TDC . . . 35
3.5 Vernier Delay Line Based TDC . . . 36
3.6 Inverter Delay Line Based TDC . . . 36
3.7 Conclusion . . . 37
4 Pseudo-differential TDC building blocks 39 4.1 Introduction . . . 39
4.2 Time Quantizer . . . 39
4.2.1 An Inverter as an Time Quantizer . . . 39
4.2.2 Inverter mismatch . . . 40
4.2.3 Inverter Jitter . . . 40
4.2.4 Power consumption . . . 41
4.2.5 Sense amplifier flip flop (SAFF) as comparators . . . 41
4.2.6 Switching speed . . . 42
4.2.7 Metastability . . . 44
4.2.8 DC Offset voltage occurrence . . . 45
4.2.9 Offset cancellation Architectures . . . 46
4.2.10 SAFF Jitter Variance . . . 46
4.2.11 Power Consumption . . . 47
4.3 Effect of noise on TDC . . . 47
4.3.1 Quantization Error Power . . . 47
4.3.2 Jitter effect on TDC . . . 47
4.3.3 Power consumption of TDC system . . . 48
4.4 Conclusion . . . 48
5 Implementation, Simulation and Performance 49 5.1 Inverter Chain Schematic . . . 49
5.2 Results for Inverter delay chain . . . 49
5.2.1 Inverter mismatch . . . 50
5.2.2 Inverter Jitter . . . 50
5.3 Sense Amplifier Flip Flop . . . 51
5.3.1 Sense Amplifier Flip Flop Implementation . . . 51
5.3.2 Sampling Window . . . 54
5.3.3 Simulation of DC Offset Voltage . . . 55
5.4 Pseudo-Thermometer Code Edge Decoder . . . 56
5.4.1 Implementation and Performance . . . 56
5.5 Power Consumption of TDC . . . 58
5.6 Conclusion . . . 58
6 Conclusion 61 6.1 Conclusion . . . 61
A Appendix 63
A.1 Verilog A source code of PFD with CP  . . . 63
A.2 Verilog A source code of VCO  . . . 65
A.3 Verilog A source code of divider  . . . 66
A.4 Verilog A source code of PFD-CP jitter  . . . 67
A.5 Verilog A source code of VCO-FDN jitter  . . . 68
A.6 Verilog A source code of Thermometer to Binary Encoder  . . . 70
List of Figures
1.1 Digital signal processing system in a mixed signal shell for analog
interfacing. . . 6
1.2 Block diagram of analog-to-digital converter . . . 6
2.1 Basic block diagram of analog phase locked loop. . . 9
2.2 Frequency Synthesis based analog phase locked loop. . . 11
2.3 Characteristics of Phase/Frequency Detector . . . 12
2.4 Output of XOR gate as Phase/Frequency Detector . . . 12
2.5 Implementation of XOR as phase/frequency detector . . . 13
2.6 Structure of charge pump with current sources . . . 13
2.7 Structure of phase/frequency detector with charge pump . . . . 14
2.8 Output response of phase/frequency detector with charge pump . 15 2.9 First order RC low pass filter. . . 15
2.10 Block diagram of voltage controlled oscillator. . . 16
2.11 Characteristics of voltage controlled oscillator . . . 16
2.12 Block diagram of frequency divider. . . 17
2.13 Linear Model of 1st type PLL in S-domain. . . 17
2.14 Block diagram of TDC based ADPLL . . . 19
2.15 Block diagram of accumulator based ADPLL . . . 19
2.16 Block diagram time-to-digital converter with normalization . . 20
2.17 Fractional positive phase error estimation . . . 20
2.18 Fractional negative phase error estimation . . . 20
2.19 General block diagram of phase detection. . . 22
2.20 Block Diagram of FIR and IIR filter . . . 24
2.21 Capacitance change of an LC oscillator . . . 26
2.22 MOS varactors vs. control voltage (deep-sub micron)  . . . 26
2.23 Test Bench of high-level Analog PLL. . . 28
2.24 Output Frequency of VCO in analog PLL. . . 28
2.25 Tuning Range of VCO in analog PLL. . . 29
2.26 Simulation window of CppSim. . . 29
2.27 Output of closed loop frequency response. . . 30
2.28 Output phase noise of synthesizer. . . 31
2.29 Closed loop pole and zero locations in S-plane. . . 31
2.30 Closed loop step response. . . 32
3.1 Working principle of TDC . . . 34
3.2 Quantized transfer characteristics of TDC . . . 35
3.3 Buffer delay line based TDC . . . 35
3.4 Dual chain vernier delay line based TDC . . . 36
3.5 Inverter based pseudo-differential TDC . . . 37
4.1 Circuit-level of current controlled sense amplifier. . . 42
4.2 Modified sense amplifier flip-flop . . . 43
5.1 Schematics of cascaded inverter stages to increase drive strength. . 50
5.2 Monte Carlo analysis of single inverter delay cell mismatch. . . 51
5.3 Edge-to-Edge jitter variance in inverter chain, JEE. . . 52
5.4 Cycle-to-Cycle jitter variance in inverter chain, JCC . . . 52
5.5 Total output noise of inverter delay cells. . . 53
5.6 Circuit implementation of SAFF stage1 as pulse generator. . . 53
5.7 Circuit implementation of SAFF Stage2 as slave latch. . . 54
5.8 Test bench of sampling window technique. . . 54
5.9 SAFF outputs with a load of 200 fF. . . 55
5.10 Monte Carlo histogram of offset voltage mismatch. . . 56
5.11 Timing diagram of TDC core signals . . . 56
5.12 Test bench of pseudo-thermometer decoder. . . 57
5.13 Synthesized circuit of 6-bit pseudo-thermometer decoder. . . 57
5.14 Results of 6-bit pseudo-thermometer decoder. . . 58
5.15 Simulated result of TDC transfer function. . . 59
5.16 Power consumption of TDC at various frequencies. . . 59
List of Tables1.1 Project specification. . . 7
PLL Phase Locked Loop
VCO Voltage Controlled Oscillator PFD Phase Frequency Detector RF Radio Frequency
LPF Low Pass Filter CP Charge Pump
DCO Digitally Controlled Oscillator DPLL Digital Phase Locked Loop ADPLL All-Digital Phase Locked Loop TDC Time to Digital Converter
DLF Digital Loop Filter
FCW Frequency Command Word
CMOS Complementary Metal Oxide Semiconductor MOS Metal Oxide Semiconductor
VLSI Very Large Scale Integrated Circuits dB Decibel
CRC Clock Recovery Cycle FIR Finite Impulse Response IIR Infinite Impulse Response OTW Oscillator Tunning Word PVT Process Voltage Temperature LSB Least Significant Bit
ADC Analog to Digital Converter SAFF Sense Amplifier Flip Flop DC Direct Current
Motivation- Moving to Time Domain
Time-to-digital converters (TDC) certainly these days have been linked only to all-digital phase locked loop (ADPLL) where, a TDC acts as phase detector, but interestingly time-to-digital converters have been used for more than 20 years in the field of particle and high-energy physics, where precise time-interval measure-ments are required . Also, there are other applications which require time calibrations such as digital oscilloscopes and logic analyzers. All these above men-tioned applications require very precise and accurate time measurements which makes TDC an essential component. Keeping these things in mind currently the micro-electronics community have rediscovered time-to-digital converters. While the all-digital phase locked loop is the most famous application of TDC due to which other applications follow rapidly. TDC based analog-to-digital converter shows that TDCs are not only used as phase detectors but useful in other impor-tant areas as well. That being said the motivating question now why, TDCs have become popular in the mainstream of microelectronics. The reason for this are the various advantages of the digital solutions compared to the analog circuits. The design of digital circuits are highly automated and as a result of which we obtain high productivity and design efficiency. However, the main advantage of digital signal processing is the inherent robustness of the digital signals against any disturbances such as noise and matching. On the other side signal integrity and variability are critical issues in digital circuits. But even then comparing to analog realizations digital solution are still robust . These signal integrity and variability issues are tackled efficiently these days by many techniques which makes the digital solution an ideal medium. All these advantages of most digital signal processing systems are realized according to the Figure1.1  .
It describes how the mixed signal shell provides the interfacing between analog and the digital core. While the data conversion is done by the mixed signal inter-face, the actual signal processing task is done in the digital domain. This generic system has been successful for many years and produced results, but what makes the time-to-digital converters a necessity is the reason in the technology scaling in
Figure 1.1. Digital signal processing system in a mixed signal shell for analog
the ultra deep sub-micron process. With each technology generation the intrinsic gain of the transistor namely the gm
gds decreases. This results in parasitic short
channel effects and the fundamental MOS theory is being challenged. As shown in the figure 1.2, an ADC is the component which converts the analog value to a digital value. This is done by sampling process, which is the discretization of the time domain done using a sample and hold circuit. After which the discrete set of values are quantized, which is normally done by comparators. This quantized data represents the digital equivalent of the analog signal .
Figure 1.2. Block diagram of analog-to-digital converter .
In this thesis, we are interested in the applications of time-to-digital converters in all-digital phase locked loop. Also, the discussion of digital PLL over analog PLL will also be discussed because of the TDCs role in the latter.
In this project, design and simulations of TDC of an All-digital PLL are carried out in 65nm process node can be seen in Table 1.1. The input reference frequency is given to be 54-MHz. Various TDC architectures are discussed in the work. The TDC is tested for different process corners.
1.3 Contributions of the Thesis 7
Table 1.1. Project specification.
Item Min Typ Max Unit Supply voltage - - 1 .0 V Reference frequency - 54 - MHz
Output frequency 2 - 3 GHz Long-term jitter - < 3 - ps Temperature range 40 - 120 deg 1
Time resolution 7 - 10 ps
Contributions of the Thesis
The main objectives carried out in this work are as follows.
• Selection of appropriate architecture for TDC in all-digital PLL..
– The selection of the appropriate architecture is based on the
specifica-tions like reference frequency, output frequency, time resolution, area and power consumption. Considering all the above requirements and choosing a less complex but effective architecture on area and power consumption is the pseudo-differential TDC architecture .
• Modeling of chosen TDC architecture in Verilog-A using Cadence.
– Following the top down design approach, the chosen architecture has to
be tested using a high level modeling such as Verilog-A. Before testing the chosen architecture some of the well known architectures like the vernier delay line and buffer delay line architectures were modeled to so see whether they can be used in the ADPLL system. The constraint with the above said architectures is that it consumes huge delay chain thereby taking up a huge area and power consumption. Unless if there is an efficient way to dynamically switch off some of the components in the delay chain this proves inefficient, when incorporated in a big system. There are other architectures like time windowed and time interleaved TDCs which can be used as stand alone system rather than in ADPLL because of it’s complex design.
• Design and implementation of schematic level circuits of TDC and sub-blocks for a better performance to fulfill the required specifications.
– The high level model of the pseudo-differential TDC was modeled and
tested and moved to schematic modeling. One of the most important block is the sense amplifier flip flop (SAFF) which ensures the symmetry at the outputs thereby avoiding metastable states.
• To design a TDC for an all-digital PLL system to achieve a resolution of 7 ps to 10 ps.
– A time resolution of 7 ps to 10 ps was achieved to cover one full DCO
cycle so that, the difference signal is time quantized to achieve the required number of bits.
Organization of Thesis
The thesis will be organized as follows. • Chapter 1
– gives the motivation behind the thesis work, main contributions and
organization of the work. • Chapter 2
– shows the over-all idea and working of analog PLL and digital PLL with
their sub-blocks. It also explains how digital PLLs are advantageous over analog PLL. Simulations results of integrated analog PLL and performance para-metrics of DPLL are shown.
• Chapter 3
– discusses the working principle and time resolution of TDC. Various
TDC architectures are explained in detail based on their working, ad-vantages and disadad-vantages compared to others, mainly discussed with respect to time resolution.
• Chapter 4
– shows the detailed explanation of chosen pseudo-differential TDC
ar-chitecture and its sub-blocks like sense amplifier based flip flop and inverter. It also gives the idea of how the performance para-metrics like metastability, DC offset, jitter, power consumption, and switching speed.
• Chapter 5
– evaluates the schematic design and implementation of TDC sub-blocks
like inverter chain, SAFF, pseudo-thermometer edge decoder. Simu-lation results are shown on how the performance varies depending on these parameters.
• Chapter 6
Phase locked loops
In 1930’s the major issue of synchronizing different signals in electronics and com-munication field was resolved by the phase locked loop (PLL). Phase locked loop are used in many applications like frequency synthesis, clock recovery, clock gen-eration, de-skewing, jitter reduction etc . Is a feedback control system which generates the output signal whose phase is compared with the phase of the input signal. The circuit compares the phase of the input signal with the phase of the signal obtained by the oscillator and adjusts it with respect to input signal in order to keep the phase matched . The basic PLL circuit consists of phase detector (PD), loop filter (LP), and voltage controlled oscillator (VCO) as shown in figure 2.1.
Figure 2.1. Basic block diagram of analog phase locked loop.
In basic PLL, the input reference signal (Fref) and the VCO output signal (Fout) are compared to give error signal. The output of the phase detector is low pass filtered by the loop filter (LP) and give the control signal, which is used to drive the voltage controlled oscillator (VCO). The comparison is made frequently till the system gets locked i.e., when both reference signal and output signal are almost equal or zero.
10 Phase locked loops
Phase locked loop’s are widely used for frequency synchronization and signal con-ditioning, clock recovery, clock generation, clock distribution, de-skewing, jitter and noise reduction and so on .
Different electronic systems including processors operate at various frequencies. A PLL is used to generate clocks for these systems. These phase locked loop multiply a lower-frequency reference clock up to the operating frequency of the processor. The multiplication factor is quite high .
High serial data streams are sent to the receivers without any clock, from the magnetic head of a disk drive to the receiver. At the receiving end, a clock has been generated from the data which is almost equivalent to the frequency of the reference signal and eventually the phase locked loop (PLL) aligns the transitions in data stream which is said to be clock recovery. To work properly the stream of data must have a transition frequency which is sufficient enough to rectify the drift in the phase locked loop oscillator .
The difference variation in arrival time of a clock signal is known as clock skew. Process variation like voltage and temperature results in finite delay between the clock edge and received data. The clock signal should be received and amplified before the data is driven by the flip-flops, specially where the signal and data are to be sent in parallel. The PLL at the receiver end must be set, such that the clock at each flip-flop is phase matched to the received clock to eliminate the delay .
One of the major concerns of the PLL. Clock jitter refers to the temporal variation of the clock period at a given point on the chip i.e. the clock signal can be reduced or expanded on the cycle basis. Clock recovery circuit (CRC) produces the clock from the data itself. Phase locking with a narrow loop band width, input jitter effect of the recovered clock will be reduces by the clock recovery circuit .
Analog Phase Locked Loop
The block diagram of frequency synthesis based PLL is as shown in figure 2.2. This PLL consists of phase/frequency detector (PFD), charge pump (CP), analog loop filter (LPF), voltage controlled oscillator (VCO) and frequency divider with a division ratio of N.
2.3 Analog Phase Locked Loop 11
Figure 2.2. Frequency Synthesis based analog phase locked loop.
In this system, the phase/frequency detector (PFD) compares the phase of the input reference signal (Fref) and the phase of the output signal (Fout) to give an error signal. This error signal is applied to the charge pump which in turn charges or discharges the loop filter (LPF). The loop filter gives control signal by removing unwanted high-frequency signals. This control voltage is used to drive voltage controlled oscillator (VCO). The frequency of the VCO is then divided by frequency divider (FD) with a ratio of ’N’. The output of the divider is again compared with the input reference signal. The control signal of the VCO changes as the error signal changes. The system is said to be in locked state, when the error signal is too small or zero.
Equation (2.1) determines the condition for the locked state.
The phase/frequency detector is the main block of the PLL. It plays a vital role be-cause of its non-linearity issues. The PFD is a circuit which compares two different input signals producing a difference signal. This difference signal is proportional to the phase difference of the two signal applied. These two signals are input reference signal and signal from voltage controlled oscillator which is divided by the frequency divider of ratio ’N’. The average output Vout of the PFD is linearly
proportional to the phase difference ∆φ. The characteristics of phase/frequency
detector is shown in figure 2.3. The gain of the phase detector is Kpd expressed in
The simple basic phase detector is designed using exclusive OR (XOR) gate. The width of the output pulse is proportional to the phase difference between the input pulses. The XOR circuit produces both rising and falling edges . The output of the XOR gate as phase/frequency detector is shown in figure 2.4.
The simple implementation of phase frequency detector (PFD) is done using edge-triggered, resettable D-flip flops with its D input always connected to logic ’1’. The Inputs A and B are used as clocks for the flip-flops and QA and QB are
12 Phase locked loops
Figure 2.3. Characteristics of Phase/Frequency Detector .
Figure 2.4. Output of XOR gate as Phase/Frequency Detector .
QA= 0 and QB = 0
QA= 1 and QB = 0
QA= 0 and QB = 1
QA= 1 and QB = 1
When both QA and QB are logic ’1’ then, the circuit is reset. Thus, QA and
QBare simultaneously high for a short duration of time but the difference between
their average values represents the input phase difference correctly.
A charge pump is a circuit mainly used for voltage to current conversion. The circuit mainly consists of two current switches S1 (source current) and S2 (sink
current) connected in series as shown in figure 2.6. The switches S1 and S2 are
used to pump-in or pump-out the current into the loop filter respectively. If the Input reference signal leads output signal, the up signal gets activated and which in turn pumps-in current into the filter. If the output signal leads the input reference signal, the down signal gets activated which in turn pumps-out the current from
2.3 Analog Phase Locked Loop 13
Figure 2.5. Implementation of XOR as phase/frequency detector .
Figure 2.6. Structure of charge pump with current sources .
14 Phase locked loops
The output of PFD is given to the charge pump to convert the pulses into current which is then used by the loop filter. The PFD outputs up and down signals to the charge pump. If the charge pump receives an up signal, current is driven into the loop filter. Conversely, if it receives a down signal, current is drawn from the loop filter .
Phase/Frequency Detector with Charge Pump
The phase frequency detector is connected to a charge pump which consists of two current sources S1and S2 followed by driving capacitor CP as shown in figure 2.7
and 2.8. The working of PFD with a charge pump is shown in table 2.3.3. Where
I1 and I2are source and sink current respectively.
Figure 2.7. Structure of phase/frequency detector with charge pump .
Table 2.1. Working of PFD with CP .
PFD Outputs (QA and QB) Switches (S1and S2) Charge pump output (Vout)
QA=0, QB=0 S1=OFF, S2=OFF Vout remains constant.
QA=1, QB=0 S1=ON, S2=OFF I1 charges cap. CP.
QA=0, QB=1 S1=OFF, S2=ON I2 discharges cap. CP.
The loop filter basically used is low-pass filter which passes the low-frequency sig-nals attenuating high frequency sigsig-nals. The main principle is the cut-off frequency of the filter is approximately equal to the maximum frequency of the VCO, which
2.3 Analog Phase Locked Loop 15
Figure 2.8. Output response of phase/frequency detector with charge pump .
means the filter rejects the frequencies above maximum frequency of the VCO . The filter used here is a first-order RC filter as shown in figure 2.9, which receives the current from the charge pump and gives the control voltage to VCO for oscillation.
Figure 2.9. First order RC low pass filter.
Voltage Controlled Oscillator
A voltage controlled oscillator is an electronic oscillator designed to control the oscillation frequency by voltage input . This block is considered as the heart of the PLL. The oscillation frequency changes depending on the input voltage applied to it. The output of VCO is given to PFD using a closed loop feedback system. The block diagram of the VCO is shown in figure 2.10.
An ideal voltage controlled oscillator is a circuit whose output frequency is linear function of its control voltage .
16 Phase locked loops
Figure 2.10. Block diagram of voltage controlled oscillator.
KV CO = ω1− ω2 V1 (2.3) φO= V1 KP d = ω1− ω2 KV coKP d (2.4)
Figure 2.11. Characteristics of voltage controlled oscillator .
The characteristics of voltage control oscillator is plotted between output fre-quency ωOut versus input voltage VCntrl as shown in figure 2.11. The frequency
range, (ω1 - ω2) , is called tunning range. The oscillation frequency increases as
the voltage increases .
A frequency divider is placed after VCO in a feedback loop which divides the output frequency ωOut by a factor of N. The divider output is connected to the
PFD. The output of frequency divider is Fdivider =FOutN is equal or nearly equal to
the input reference signal Fref. The block diagram of frequency divider is shown
2.3 Analog Phase Locked Loop 17
Figure 2.12. Block diagram of frequency divider.
Linear Model of Analog PLL in S-Domain
A simple linear model of 1st type PLL is modeled. The PFD output contains both dc component and the high frequency components, whose dc component is approximately equal to, KP D (φout - φinput) and the high frequency components
are attenuated by LPF. The PFD is modeled using a substractor whose output is amplified by gain Kpd. The transfer function of LPF and VCO is given by 1+SRC1
where, ω = 1
S respectively. A linear model of 2nd order PLL is as
shown in figure 2.13.
Figure 2.13. Linear Model of 1st type PLL in S-domain.
The open loop transfer function is given by,
H(S)open= φout φinput (S) = (1 + S ωLP F )KP DKV CO S (2.5)
with one pole at S = - ωLP F and another at S = 0. Since the loop gain contains
one pole at the origin, hence the system is called 1st type PLL. The closed loop transfer function is given by,
18 Phase locked loops H(S)closed= 1 + (1 + S ωLP F )KP DKV CO S = KP DKV COωLP F (S2+ Sω LP F+ KP DKV COωLP F) (2.7) H(S) = ω 2 n (S2+ 2ζω nS + ω2n) (2.8) ωn= p KP DKV COωLP F (2.9) ζ = 1 2 r ω LP F KP DKV CO (2.10)
comparing equation 2.7 and 2.8, we get, natural frequency ωn and damping ratio
Digital Phase Locked Loop
Due to the rapid growth of integrated circuits with increasing performance, speed, reliability and decreasing size, cost has shifted its strong interest from analog to digital domains. Previously, the phase locked loop where designed in both analog and digital domains. A digital version of the phase locked loop have resolved the problems with its analog counterpart. The main reason behind hopping to digital domain is due to its flexibility and versatility with different components. One of the main advantage of digital phase locked loop above analog counterparts is that they remove the need of large capacitors within the loop filter by utilizing digital circuits to achieve the desired filtering function .
In ADPLL, the time-to-digital converter (TDC) is replaced by phase frequency detector (PFD) and charge-pump (CP), digital loop filter (DLF) with analog fil-ter and digitally controlled oscillator (DCO) replacing voltage controlled oscilla-tor (VCO). ADPLL architectures can classified into TDC-based and accumulaoscilla-tor based, as shown in figure 2.14 and 2.15 respectively .
The main difference between these two architectures is how the phase error is between the reference and feedback signals is generated. In TDC-based ADPLL, the TDC output is proportional to the phase error. In this case, the phase error is achieved by measuring the delay between the positive (or negative) edges of the reference oscillator and the divider. In accumulator-based ADPLL, the phase error is determined by means of difference between the reference and feedback phase signals. In this case, the phase accumulators generate the phase signals directly.
Time-to-digital converter (TDC) is most critical block from the digital-phase locked loop (DPLL). The main principle of TDC is to measure the edge time
2.4 Digital Phase Locked Loop 19
Figure 2.14. Block diagram of TDC based ADPLL .
Figure 2.15. Block diagram of accumulator based ADPLL .
difference between the reference frequency and the high-speed DCO clock. The other condition is to lock the two signals and produce zero phase, if both DCO clock signal and reference signal are of same phase.
The TDCs fractional delay difference ε between the reference clock (Fref) and the next significant edge of the DCO clock (Fckv) is measured using time-to-digital converter (TDC) with a time quantization resolution ∆tres of an inverter
delay tinv and the digital word is time difference. The integer output of
time-to-digital converter (TDC) cannot be used in system during its process because the time resolution is a varying parameter. Thus, it is normalized by the DCO clock period. Only the fractional error is used by the phase detector . The working operation of the TDC is shown in figure 2.16, 2.17 and 2.18.
The smallest time interval that has to be readily resolved in digital fractional phase detector is TDC inverter delay tinv . The number of buffers or inverters
20 Phase locked loops
Figure 2.16. Block diagram time-to-digital converter with normalization .
Figure 2.17. Fractional positive phase error estimation .
Figure 2.18. Fractional negative phase error estimation .
In digital deep-sub micron CMOS, the inverter could be considered as basic pre-cision time-delay cell with fully digital-level regenerative properties . It is possible to achieve better resolution than inverter delay for the TDC function. The improvement of resolution of can be achieved by using a vernier delay line with two non-identical buffer chains. The slower chain is stabilized by negative
2.4 Digital Phase Locked Loop 21
feedback through a delay line. The time difference between the buffer of the upper chain and lower chain gives the resolution. The disadvantage of this method is because of higher power consumption and extra analog circuit.
Reference Edge Estimation to reduce Power Consumption
The prediction of reference signal Fref of TDC reduces the power consumption. This actually works due to periodic gating of the digitally controlled oscillator (DCO) clock in TDC by predicting the next reference edge lies because all the information is available from the edges of the Fref clock. After certain time of execution, the information which is far could be gathered in both clock phases which in turn reduces the power consumption and noise .
Phase Error Detector
Frequency synthesizer is a circuit which generates one or more frequencies fV
from a reference frequency fR.To achieve required DCO frequency fV , the FCW
(Frequency Command Word) must be pre-defined and then used as an input to the ADPLL system by the equation ,
F CW = fV fR
The FCW determines how many number of high-speed clocks are stored in one reference frequency fR. In a system, the phase error is obtained by comparing
ref-erence phase and variable phase. The phase error of the detector is mathematically written as,
φE[k] = RR[k] − RV[k] + ε[k] (2.12)
The block diagram of phase detector is shown in figure 2.19. This phase de-tector consists of three phase sources like reference phase RR[k], variable phase
RV[k] and fractional error correction ε[k]. The variable phase RV[k] works by
DCO clock (CKV) and is later re-clocked by CKR clock. Later in the end all the three phase sources are synchronized with CKR clock .
Reference Phase Block
This reference accumulator block is implemented by RR. It can be obtained by
accumulating frequency command word (FCW) as in equation 3.3.
RR[k] = k
22 Phase locked loops
Figure 2.19. General block diagram of phase detection.
Variable Phase Block
Variable phase accumulator RV[k] is implemented with first stage with an
accu-mulator and flip-flop at the second stage. The main purpose of variable phase accumulator is to count the increments of the DCO clock .
RV[i] = i
Fractional Error Correction
Fractional error correction (ε) is measured by means of time-to-digital converter (TDC) between reference signal (Fref) and DCO clock (Fckv). The TDC has a chain, if inverters with propagation delay as the time reference. Resolution of one of the inverter delay tinv is the time quantization resolution of the TDC, ∆tres.
In operation, the inverter in within the chain will have variance in propagation delay. Therefore, the digital representation of the TDC output could not be used directly as fractional error correction (ε). The digital output code of TDC must be normalized by the oscillator clock period (Tv).
ε = 1 − (∆tr Tv
From figure 2.17 and 2.18, ∆tris quantized time delay between the rising edge
of the DCO clock and the FREF sampling edge, whereas ∆tf is the time delay
2.4 Digital Phase Locked Loop 23
resolution of tinv. In this system, ∆tr and ∆tf are determined by the transition
from 1 to 0 and 0 to 1 respectively.
∆tr− ∆tf ∆tr≥ ∆tf
∆tf− ∆tr otherwise
Information regarding rise time ∆tr and fall time ∆tf of TDC can be used to
calculate the half period of DCO clock using the condition above mentioned.
Digital Loop Filter
In an ADPLL, a digital loop filter is used after time-to-digital converter, which is used to remove the unwanted frequency components. The main principle of the filter is for signal separation and restoration. The signal separation is to remove interferer (unwanted signal) from the wanted signal and restoration signal is to remove the distortions from the received signal to get the actual required signal.
The low-pass filter is a system whose magnitude attenuates with the increase in frequency. The filter allows low-frequency signals attenuating the high-frequency above the cut-off frequency. Cut-off frequency is the frequency at which the filter’s frequency response drops by 3 dB below the pass band. The amount of attenuation for each frequency is not constant. It varies from filter to filter.
A digital filter performs mathematical computations on the discrete- time signal to modify the properties of that signal whereas, analog filter uses continuous time signals. The continuous time signal can also be processed by digital filters by first digitizing and converting to a sequence of numbers and then passed through the digital filter. The output of the digital filter is converted back to analog signal. The output from the digital filter is converted back to an analog signal. The design and features of a digital filter depend upon the application for which the filter is employed.
Characterization Of Digital Filters
To characterize the digital filter, a transfer function is used. Transfer function determines the relation between the input and output of the linear time invari-ant (LTI) system. Designing a filter requires the knowledge about its frequency response, impulse response, stability and so on. The transfer function of the LTI digital filter expressed in Z-domain is shown below ,
H(Z) = Y (Z) X(Z) = Y0+ Y1Z −1+ Y 2Z−2+ ... + YNZ−N 1 + X1Z−1+ X2Z−2+ ... + XMZ−M (2.16)
From above equation, the order of filter is greater than N or M. The above transfer function of the filter with numerator (output) and denominator (input) represents infinite impulse response (IIR) filter, whereas if the denominator is made to unity i.e. no feedback, which represents finite impulse response (FIR) filter.
24 Phase locked loops
Types of Digital Filters
Filters are usually classified in several groups like impulse response, frequency response and step response, depending on which criteria are used for classification. The two major classification are impulse response digital filters (FIR filters) and infinite impulse response digital filters (IIR filters) .
Both the filters have some pros and cons, which are carefully considered when designing a filter. Basically, it is important to consider all the fundamental char-acteristics of a signal to be filtered, which will be very important factor in deciding which filter to use. In many cases, the only important characteristics that matters is linear phase characteristic of the filter or not.
The basic characteristics of FIR filters are, • Linear phase characteristics
• High filter order (more complex circuits) and • Stability.
The basic characteristics of IIR filters are, • Non-linear phase characteristics
• Low filter order (less complex circuits) and
• Resulting digital filter has the potential to become stable.
Figure 2.20. Block Diagram of FIR and IIR filter .
Digitally Controlled Oscillator
A digitally controlled oscillator (DCO) is implemented using only digital compo-nents. It is a key component used in ADPLL. From theoretical information, this is a efficient mechanism to represent a signal containing both phase and frequency. The time-domain resolution is more superior than the voltage-domain resolution. The digitally controlled oscillator implemented consists of digital outputs and in-puts operating in discrete-time domain, even though the main functionality is continuous time and amplitude in nature. This important consideration is such that it stops the analog nature .
A digitally controlled oscillator (DCO) is mainly used to perform digital-to-frequency conversion (DFC). It outputs a periodic waveform, whose digital-to-frequency ’f’ is a function of the input oscillator tunning word (OTW).
2.4 Digital Phase Locked Loop 25
f requency, f = F (OT W ) (2.17) F(OTW) is a non-linear function of an input, which traces the digital input to the frequency oscillation. The frequency setting function was not known precisely and differ with the process spread, voltage and temperature. An instantaneous value of the frequency lies on power or ground and substrate noise, flicker noise and thermal noise as well .
Digitally Controlled Oscillator Gain and Transfer Function
Digitally controlled oscillator is the important part of the frequency synthesizer, which is designed with digital components. It generates the output frequency of oscillation fv, which is inherent function of digital oscillator tunning word (OTW).
fv= F (OT W ) (2.18)
It can be considered as a linear function in the limited operating range. The DCO gain can be represented as kDCO.
fv= fo+ kDCO(OT W ) (2.19)
From above equation, ∆fv is frequency deviation of center frequency and fo is
adjustable center frequency. kDCO is a frequency deviation of ∆fv in hertz from
a certain oscillating frequency fv in response to 1 LSB input change. Due to this,
kDCO is same as ∆f frequency resolution. In the linear operating range, the gain
of the oscillator is expressed as:
KDCO(fv) = ∆fv ∆(OT W ) (2.20) KDCO(fv, (OT W )) = ∆fv ∆(OT W ) (2.21) So in a limited range, kDCO must be linear with respect to the input. Since the
DCO gain is also a function of (OTW) , kDCO can be written as in the Equation
Digitally Controlled Oscillator Tunning Word Re-timing
DCO input tuning word re-timing method is an idea based on changing the tuning control input of a digitally controlled oscillator to adjust its phase and frequency in normal operation of the PLL. The normal operation of the PLL was considered as a disturbing action that produces an output with huge jitter or phase noise. This could be very well recognized in the DCO, where the frequency oscillation changes with respect to discrete intervals. Since the oscillating frequency of a LC tank was controlled by varactors which does the function of voltage to capacitance conversion.
The total charge should be stored, by changing the capacitance at these time causes the electrical potential to exhibit the largest change ∆V = ∆CQ , as shown
26 Phase locked loops
in figure 2.21. These perturbations were translated by the oscillator circuit into timing jitter. By changing the capacitance of the varactor during the time when it gets discharged entirely would affect the voltage slightly and thus eventually contribute very little to the oscillating jitter .
Figure 2.21. Capacitance change of an LC oscillator .
Design of varactors in deep-sub micron CMOS process
Figure 2.22. MOS varactors vs. control voltage (deep-sub micron) 
The challenging task of the low-voltage deep-sub micron CMOS oscillator is frequency tunning, due to its highly non-linear frequency vs. voltage character-istics, thus oscillator must be carefully designed. The characterization of MOS varactors vs. control voltage for both traditional and deep-sub micron process is
2.5 Comparison of Analog and Digital Phase Locked Loop 27
shown in figure 2.22. Thus, a large linear range gives the oscillator a wide and precise tunning of a frequency.
Comparison of Analog and Digital Phase Locked
The typical analog PLL implementation exhibits more problems in most of the applications. Firstly, they are very sensitive to process variations and also the problem increases once the implementation of analog PLL progress in the deep-sub micron. The cost implementation is also too high due to the capacitors placed in the analog circuitry which occupies more space in the chip even-though the filter used is of first order. Thus increase in the order of PLL increases filter order resulting high capacitor size which occupies larger area in the chip.
The phase locked loop in the form of digital circuitry has more advantages than the analog PLL. In digital circuits, the blocks implemented can be scaled down easily as the technology improves further. The circuits can even perform better at lower supply voltages. As a matter of linearity aspects, digital circuits are much better than the analog, whereas the linearity is very high for analog circuits. Digital PLL has shorter lock time compared to analog PLL. Digital PLL have low jitter and noise compared to analog PLL.
Analog PLL - High-level Design
Figure 2.23 below is the test bench analog PLL designed in cadence. The sub-blocks like PFDCP, VCO and frequency divider are implemented and integrated in high-level design using Verilog-AMS. The division ratio of frequency divider ratio is set to 28. The input reference frequency was set to 54-MHz. The VCO tunning range was designed to be 1.5-GHz to 2-GHz. As we know fact, the loop bandwidth of the filter is one tenth of the reference frequency, thus it is set to be 10 kHz and also the capacitor and resistor component values are calculated based on it using online calculator. The chosen values are given below:
Capacitor, C1 = 2.26nF. Capacitor, C2 = 33.9nF. Resistor, R = 187.7 Ohm.
Figure 2.24 and 2.25 demonstrates the simulation results of the VCO output frequency and tuning range of analog PLL respectively. The control voltage of the VCO is obtained from the loop filter output, which is the error signal in phase and frequency between the reference frequency and the VCO frequency.
Loop bandwidth of a filter determines the lock time of the PLL. It would be necessary to determine the key performance parameters like phase noise, stability, lock time and reference spurs. A trade-off arises when the stability of the PLL and their settling time appears. Faster the lock time, wider the loop bandwidth
28 Phase locked loops
Figure 2.23. Test Bench of high-level Analog PLL.
Figure 2.24. Output Frequency of VCO in analog PLL.
but the stability is better for narrow bandwidth. Thus, initially PLL has a larger bandwidth and later it switches to lower bandwidth as is approaches lock time.
Performance Parametric of DPLL
Various performance parametric results of Digital phase locked loop are designed using a tool called CppSim. This tool is simple and fast in designing the phase locked loop at transfer function level. This simulator uses closed loop transfer function description as a input to determine open loop parameters which are used in designing the desired PLL. Different parameters like output phase noise, poles and zeros location, closed loop frequency and step response results are plotted. The simulation window where the results of different parameters for PLL are ob-tained is shown in figure 2.26. The following are input specification of the DPLL:
2.6 Results 29
Figure 2.25. Tuning Range of VCO in analog PLL.
• Output Frequency = 2.1-GHz. • Loop Bandwidth = 100 kHz. • Filter Order = 2.
• DCO Phase Noise = -115 dBc/Hz at 1 MHz offset . • TDC Phase Noise = - 95 dBc/Hz.
30 Phase locked loops
Closed Loop Frequency
Frequency response relates to the measure of output spectrum of system in re-sponse to the stimulus, and used to characterize the system dynamics. The closed loop frequency is defined as signal frequency whose magnitude drops by 3 dB from its initial value. Figure 2.27 shows the plot of closed loop frequency response obtained from input values in CppSim.
Figure 2.27. Output of closed loop frequency response.
Output Phase Noise
Figure 2.28 shows the plot of output phase noise in CppSim. Phase noise is the frequency domain representation of rapid, short-term, random variation in the phase due to to the time instabilities . It causes the spectral purity degrada-tion. Its is an important parameter in many oscillators, which affects the system performance. Phase noise can be reduced by the noise characterization through modeling and simulation of the design. The factors affecting the noise are passive components selection and resonators modeling.
Poles and Zeros Location
Pole-zero plot is a graphical representation of transfer function of a dynamic system in a complex plane . The poles are indicated as X and zeros as O in the plot. Pole-zero plot can be represented in continuous-time (CT) or discrete-time (DT system) . Figure 2.29 plot is located in a S-plane.
2.6 Results 31
Figure 2.28. Output phase noise of synthesizer.
Figure 2.29. Closed loop pole and zero locations in S-plane.
Output Step Response
Step response is also known as the time behavior of the output of the system when, its input changes from zero to one in a short period of time. Practically, one should know how the system responds due to the quick inputs is important. Such large and fast deviations for a long term steady state might effect the system
32 Phase locked loops
itself and component . To overcome such act the component must settle down to some state. This gives the information on the stability of the system. Figure 2.30 gives the idea of it.
Figure 2.30. Closed loop step response.
In first section, analog PLL are explained in detail with their sub blocks, func-tionalities, architectures and applications in order that readers could have a good knowledge on PLL. As the discussion continues, Digital phase locked loop sub blocks like TDC, digital loop filter and DCO are briefly explained. High-level analog PLL is implemented in Cadence using Verilog-AMS. A brief justification is given, how digital PLL circuits are more advantageous than the analog PLL.
In the past decades, time-to-digital converters (TDCs) are widely used for time measurement many fields like space science, instrumentation test, high-energy physics and soon. TDC is used to measure the phase error between the refer-ence signal and the feedback signal in time domain, which directly outputs the phase error in digital format that can be processed by an on-chip programmable digital loop filter . Due to this filter, the loop dynamics of the digital PLL can be easily programmed and thus to achieve low phase noise and fast settling time at the same time. It can also provide accurate loop dynamics that are less sensi-tive to process, voltage and temperature (PVT) variations and more immune to supply and substrate noise. In addition, the area of DPLL can be reduced by large capacitors used in loop filters. Similar to other sampling circuits, TDC generates quantization noise while digitizing the time interval between the two signals. The quantization noise is associated with the TDC resolution which limits the in-band noise of the DPLL. In other words, the finer the TDC resolution is, the better in-band noise can be achieved.
TDC Working Principle
The working principle of time-to-digital converter based on digital delay line is shown in figure 3.1. The start signal is passed through a array of delay elements and are sampled at the arrival of the rising edge of the stop signal. The sampling process can be accomplished by implementation of flip-flops which freezes the state of the delay line as the stop signal occurs. The output of flip-flop will be of high value (1s) if the start signal allows the delay stages and flip-flop generates low value (0s) if the delay stages have not been passed by the start signal. As a result, the decoder measures the position of high to low transition indicating how far the start signal can be propagated in the time interval by start and stop signal.
34 Time-to-digital converters
Figure 3.1. Working principle of TDC .
Time resolution is the important parameter in designing of TDC. Its is derived from the time difference between the reference signal and DCO clock. The transfer characteristics of TDC is shown in figure 3.2. The phase error of TDC is linear and similar to typical analog PLL. It is quantized ∆tres time units.
L ≥ max(Tv) min(tinv)
∆tres= tinv (3.2)
The TDC quantum step is ∆tres determines the step of the fractional error
correction, which is expressed in normalized as
Since, the reference signal period TREF remains unchanged over time, the time
resolution of TDC ∆T DC can be converted in to a phase resolution of the phase-to
digital converter ∆Φ as:
∆Φ = 2Π∆T DC
3.4 Buffer Delay Line Based TDC 35
Figure 3.2. Quantized transfer characteristics of TDC .
Buffer Delay Line Based TDC
After a sufficient time of research done in past years to find a way to build a high resolution time time-to-digital converter. The simplest TDC is based on a delay line composed of buffers with delay time TDEL is shown in figure 3.3. Inverters
are used in the delay line. As the start signal travels through the delay line, the output of each buffer is flipped after time TDEL. When the stop signal arrives,
the outputs of all the buffers are stored in to a register and then decoded. One advantage of this TDC is that it cane designed fully digital. This architecture is elegant ans simple to implement, but it suffers from poor timing resolution due to the use of non-inverting delay elements.
36 Time-to-digital converters
Vernier Delay Line Based TDC
Figure 3.4. Dual chain vernier delay line based TDC .
To improve the time resolution of the buffer delay line based TDC, vernier delay line based TDC is used which is capable of measuring of time interval with sub-gate resolution. The vernier delay line structure consists of a pair of tapped delay chains with a flip-flop at each corresponding pair of taps as shown in figure 3.4. The upper delay chain consists of buffers with a delay of TDEL1 while the
lower delay chain has buffer with a delay of TDEL2. Assuming that FREF arrives
before FCKV and TDEL1 is greater than TDEL2. As the reference signal FREF
and clock signal FCKV travels through the delay lines, the time difference between
these two delay chains decreases after each stage and is given by:
T imeResolution, TR= TDEL1− TDEL2 (3.5)
Therefore, the resolution depends on difference between the two delay stages instead of one delay element. Although the vernier delay line TDC improves reso-lution effectively, the power consumption and area are increased. This is because each stage costs of two buffers and a flip-flop.
Inverter Delay Line Based TDC
The time resolution of inverter-based TDC is the delay of the inverter whose resolution is double compared to the buffer delay line. This architecture also known as Pseudo-differential TDC as shown in figure 3.5. In buffer-based TDC, the inconsistent transition of the rising and falling edges of the delayed signals and unbalanced metastability of the flip-flops occurs. This destroys the characteristics of TDC resolution such that inverter-based delay line TDC is more advantageous
3.7 Conclusion 37
Figure 3.5. Inverter based pseudo-differential TDC .
over the buffer-based TDC. The structure is also used to avoid any mismatch between rising and falling edge transitions. The resolution is almost equal to the CMOS inverter propagation delay, which is less than 10 ps in this CMOS process and is expected to improve as the process technology advances.
Time-to-digital converters are considered as important block in All-digital PLL. First section gives in depth knowledge of TDC, its working principle, functionality and most important parameter time resolution associated with it. Different types of TDCs like buffer-based, vernier-based and inverter-based are explained with their pros and cons compared to each other. In second section, inverter-based TDC is chosen for thesis work because of its improved time resolution, conversion time, mismatch and soon. Detailed explanation and working of inverter-based TDC and its sub-blocks are discussed in chapter four.
The architectures like pseudo-differential TDC are widely used because of their insensitivity towards NMOS and PMOS mismatches. The uniqueness of this ar-chitecture mainly depends on the limitation of the intrinsic delay of the buffer elements and the improved resolution below sub-gate delay. The proposed pseudo-differential TDC takes the advantage of deep-submicron process strengths in fast logical switching and finest logic-level regenerative timing of the inverter propa-gation delay. This minimizes the load on the inverter delay chain, the resolution similar to the inverter propagation delay.
An Inverter as an Time Quantizer
In an ADC system, resistors behaves as an reference voltage which carries out the quantization process. In any TDC system, inverters are used as the delay elements which performs the quantization process, but in the time domain. The propagation delay characteristics of an inverter is made used to perform the time quantization. The expression for inverter delay is given by the following equation 4.1 . Where, CL is the total load capacitance, VDD is the supply voltage, and
βnand βpare the device trans-conductance of the NMOS and PMOS respectively.
VT N and VT P are the threshold voltage of NMOS and PMOS respectively .
tpd = 1 2(CL VDD βn(VDD− VT N)α + CL VDD βp(VDD− VT P)α ) (4.1)
Various parameters like PVT variations, mismatch and jitter affects the prop-agation delay, tpd which in turn these parameters have independent and
40 Pseudo-differential TDC building blocks
lated effects on the it. Thus it becomes important to consider all the factors of inverter propagation delay tpd, which might affect the whole TDC system with
some undesirable results. The mismatch and jitter combined together will intro-duce phase noise on the TDC system. The TDC linearity will also be affected by all these factors. When incorporated in ADPLL system, the non-linearity is caused due to the mismatches will cause fractional spurs and will affect the other connecting blocks such as the digital loop filter and so on. Also, the delay variance due to PVT will introduce gain error . The following sections will cover these details.
The delay mismatches in an inverter are threshold voltage VT, device
transconduc-tance β, and drain current Id which produces uncertainties in propagation delay,
resulting output skew from one delay cell to another. Thus linearity error appears due to uncertainties at the output . The mismatch variance can derived from Equation 4-1 . The derivative of the Equation 4-1 gives us the variances such as VT N, VT P, βn, βp, and CL respectively. σtpd,mis2 = t 2 pd 4 ( 2σ2 CL C2 L +σ 2 βn β2 n + α 2σ2 VT N (VDD− VVT N) α + σ2 βp β2 p + α 2σ2 VT P (VDD− VVT P) α) (4.2)
From the above equation it is clear that decrease in delay variance, increases the CL, VDD and β.
The standard deviation of the inverter cells vary independently due to local variations and as a result of which these variations are accumulated throughout the TDC chain of inverters. The mismatch at the N-th inverter chain can be given by the Equation 4-3   .
N σtpd (4.3)
The total mismatch of the TDC can be found out by the sum of inverter chain mismatch variance and sense amplifier flip flop variance, as in Equation 4-4  .
σtotal,mismatch2 = σ2SAF F,mismatch+ σtpd,mismatch2 (4.4)
The total mismatch variance has to be kept low or at least lower than that of the TDC resolution so that the integral error is less than one LSB  , . The design of the TDC system should be based on following factors.
Jitter is defined as the short term variations of a digital signal’s significant time instants from their ideal positions . It can also be defined as the time domain manifestation .