Department of Science and Technology Institutionen för teknik och naturvetenskap
LiU-ITN-TEK-A--18/022--SE
Design and verification of
automotive power supply
Johan Andersson
Adam Schelander
LiU-ITN-TEK-A--18/022--SE
Design and verification of
automotive power supply
Examensarbete utfört i Elektroteknik
vid Tekniska högskolan vid
Linköpings universitet
Johan Andersson
Adam Schelander
Handledare Jonte Bernhard
Examinator Magnus Karlsson
Upphovsrätt
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http://www.ep.liu.se/Abstract
In the current and next generation automotive telematic platforms, high de-mands are put on high eiciency power supplies. This thesis investigates diferent switch mode power converter solutions that operates with high ei-ciency for both low and high power loads. A market survey was conducted alongside meetings with ACTIA Nordic and their subcontractors. Three so-lutions from the market survey were selected for further investigation. One solution from the investigation was selected and implemented as a demonstra-tion platform for further testing. The result shows a full test sequence for the designed power supply solution.
Preface
Thanks to Tomas Westlund at ACTIA Nordic AB in Linköping and Per Järmark at ÅF AB in Linköping for providing the project and support. Special thanks to Jonas Persson and the hardware group at ACTIA Nordic AB for supervision and guidance. Thanks to Magnus Karlsson at the department of science and technology at Linköping University for guidance and support during this MSc thesis project.
Thanks to all alicted subcontractors of ACTIA Nordic for providing material and support.
Acronyms
BCM Boundary Conductive Mode. 9, 42 BOM Bill of Materials. 8, 31
CCM Continuous Conductive Mode. 9, 11, 12, 42
CISPR22 Comite International Special des Perturbations Radioelectriques -
Inter-national special Committee on Radio Interference. 20, 25, 57, 60–62, 75, 77, 78, 80, 81, 85
DCM Discontinuous Conductive Mode. 9–12, 41, 42 DHU Data Handling Unit. 1, 2, 5, 81
DUT Device Under Test. 63, 77
EMC Electromagnetic Compatibility. 1, 2, 29, 59, 60, 80, 81, 85
EMI Electromagnetic Interference. 8, 20–22, 24, 25, 29, 45, 46, 52, 53, 59, 81 ESD Electrostatic Discharge. 30, 83
ESL Equivalent Series Inductance. 21
ESR Equivalent Series Resistance. 14, 16, 17, 27, 44 GNSS Global Navigation Satellite System. 1
IC Integrated Circuit. 8, 13, 21, 30, 31, 36, 46, 48, 79, 85 IEC International Electrotechnical Commission. 1
ITE Information Technology Equipment. 60 LDO Low-Dropout regulator. 32–34, 37, 79, 82 LISN Line Impedance Stabilization Network. 60, 75 LP Low-Pass. 19
MOSFET Metal Oxide Semiconductor Field Efect Transistor. vi, 5, 8, 9, 12, 13,
PCB Printed Circuit Board. 1–3, 8, 31, 43, 52, 53, 55, 85 PFM Pulse Frequency Modulation. 10–12, 35, 36, 71, 79 PWM Pulse Width Modulation. 10–13, 71
QFN Quad Flat pack No lead. 23 QP Quasi-Peak. 60
RMS Root Mean Square. 33
RPP Reverse Polarity Protection. x, 19, 37, 50, 67, 78, 82 SMPS Switch Mode Power Supply. 5, 15, 24
Contents
1 Introduction 1 1.1 Purpose . . . 1 1.2 Problem Formulations . . . 1 1.3 Limitations . . . 2 1.4 Outline . . . 21.5 Materials and Sources . . . 3
1.5.1 Sources . . . 3
1.5.2 Materials . . . 3
1.5.3 Software . . . 3
2 Theoretical Background 5 2.1 DC/DC Buck Converter . . . 5
2.1.1 Integrated Buck Converter . . . 8
2.1.2 Buck Controller with External Switches . . . 8
2.1.3 Flyback Converter . . . 9
2.2 Control and Stability of the DC/DC Converter . . . 9
2.2.1 Boundary Conduction Mode . . . 9
2.2.2 Switch Control Signal . . . 10
2.2.3 Feedback Control . . . 12
2.2.4 Stability . . . 15
2.3 Reverse Polarity and Over Voltage Protection . . . 19
2.4 EMC and EMI . . . 20
2.4.1 Reducing Radiated EMI in Buck Converter . . . 20
2.4.2 Switch Node Ringing . . . 21
2.4.3 Conducted EMI . . . 24
2.4.4 Input Filter . . . 25
3 Implementation 29 3.1 System Requirements . . . 29
3.2 Power Converter Market Survey . . . 30
3.3 Choice of Power Converter . . . 31
3.3.1 LDO pre-stage . . . 33
3.4 System Layout . . . 35
3.4.1 Layout of LTC7801 . . . 35
3.4.2 Layout of MAX17506 with LDO . . . 36
3.4.3 Layout of Flyback Converter . . . 39
3.4.4 Choice of Converter Layout . . . 41
3.5 System Design . . . 41
3.5.1 The Output Inductor . . . 41
3.5.3 Input Filter . . . 45
3.5.4 Switching MOSFETS . . . 46
3.5.5 Loop Compensation . . . 48
3.5.6 Reverse Polarity Protection . . . 50
3.5.7 Reducing EMI in Buck Converter . . . 52
3.5.8 Circuit Layout . . . 53
3.5.9 PCB Layout . . . 55
4 Test and Veriication 57 4.1 Electrical Characteristics . . . 57
4.1.1 Eiciency . . . 57
4.1.2 Switch Node Ringing . . . 57
4.1.3 Startup Cases . . . 57
4.1.4 Turn On/Of Voltages and Times . . . 57
4.1.5 Output Voltage Ripple and Noise . . . 58
4.1.6 Output Line and Load Regulation . . . 58
4.1.7 Output Transient Response . . . 59
4.1.8 Temperature Evaluation . . . 59
4.2 Feedback Loop Stability Testing . . . 59
4.3 EMC Testing and Regulations . . . 59
4.3.1 Conducted Emissions . . . 60
4.3.2 Radiated Emissions . . . 62
5 Results 65 5.1 Results from Test and Veriication . . . 66
5.1.1 Eiciency . . . 66
5.1.2 Line and Load Regulation . . . 68
5.1.3 Switch Node Ringing . . . 68
5.1.4 Turn On and Of Voltage and Time . . . 70
5.1.5 Output Voltage Ripple and Noise . . . 71
5.1.6 Output Transient Response . . . 72
5.1.7 Feedback Loop Stability . . . 73
5.1.8 Conducted Emissions . . . 75
5.1.9 Radiated Emission . . . 77
5.1.10 Summary . . . 78
6 Discussion 79 6.1 Market Survey Discussion . . . 79
6.1.1 Output Inductor Market Survey Discussion . . . 79
6.1.2 Metal Oxide Semiconductor Field Efect Transistor (MOS-FET) Market Survey Discussion . . . 80
6.2 System Discussion . . . 80
6.2.2 Stability and Loop Response Discussion . . . 82 6.2.3 Result Discussion . . . 82
7 Conclusion 85
Appendices A-1
A Switch Node Ringing Measurements . . . A-1 B Output Voltage Ripple Measurements . . . B-1 C Radiated Emission Measurements . . . C-1 D Setup for Conducted Emission Measurements . . . D-1 E Bill of Material . . . E-1
List of Figures
1 Simpliied buck converter model . . . 5
2 Buck converter waveforms in CCM . . . 6
3 Output ripple of a buck converter . . . 7
4 Integrated buck converter . . . 8
5 Disctrete buck controller with external MOSFET´s . . . 8
6 Buck converter characteristics keeping Vo constant . . . 10
7 PWM generator signals . . . 11
8 PFM generator signals . . . 11
9 Voltage mode control feedback loop . . . 12
10 Current mode control feedback loop . . . 13
11 Hysteresis mode control feedback loop . . . 14
12 Converter feedback loop gain without compensation network . . . 15
13 Closed loop system schematic of buck converter . . . 16
14 Open loop buck converter system . . . 17
15 Type II feedback compensation . . . 18
16 Type II compensation gain and phase . . . 18
17 Buck converter current loops . . . 20
18 Frequency spectrum of switch pulses . . . 21
19 Switch node ringing . . . 22
20 TSSOP Package . . . 23
21 QFN Package . . . 23
22 RC Snubber connected to switch node . . . 23
23 Conductors with both common and diferential-mode currents . . . . 24
24 Undamped LC-ilter . . . 25
25 Gain of LC-ilter . . . 26
26 Damped LC-ilter . . . 27
27 Input current waveform of a buck converter . . . 34
28 Schematic for the LTC7801 solution . . . 35
29 Schematic for MAX17506 . . . 36
30 Schematic for LT4356-2 . . . 37
31 Integrated buck converter solution with LDO pre-stage . . . 38
32 Schematic of Flyback solution . . . 39
33 Eiciency curve lyback converter . . . 40
34 Eiciency at low current of lyback converter . . . 40
35 Output current waveform at diferent loads . . . 42
36 BCM current level at diferent output inductances . . . 42
37 Output voltage ripple at diferent capacitances . . . 44
38 Input ilter design . . . 45
39 Input ilter simulation LT Spice . . . 46
41 Loop gain and phase for the selected compensation components . . . 49
42 Compensation network schematic values . . . 50
43 Topologies for reverse polarity protection; (a) Schottky-diode Reverse Polarity Protection (RPP), (b) PMOS RPP and (c) NMOS RPP . . 50
44 Power dissipation in diferent RPP solutions . . . 51
45 Main current loops on PCB . . . 52
46 Secondary current loop PCB . . . 53
47 Buck controller solution with RPP and input ilter . . . 54
48 PCB layer stack . . . 55
49 PCB Top Layer . . . 56
50 PCB Signal Layer . . . 56
51 QP-detector . . . 61
52 CISPR22 Limits for conducted emissions [24] . . . 61
53 CISPR22 Limits for radiated emissions [24] . . . 62
54 CISPR22 Measurement setup for radiated emissions [24] . . . 63
55 PCB 3D model of the buck converter test board viewed from the side 65 56 PCB 3D model of the buck converter circuit . . . 65
57 Photography of the designed power supply circuit . . . 66
58 LTC7801 measured eiciency . . . 67
59 LTC7801 modiied eiciency plot, No RPP . . . 67
60 Switch node ringing at 12 V input voltage . . . 69
61 Switch node ringing at 48 V input voltage . . . 69
62 Turn on time . . . 70
63 Turn of time . . . 71
64 Output voltage ripple with 48 V input voltage in PWM mode . . . . 71
65 Output voltage ripple with 48 V input voltage in PFM mode . . . 72
66 Output transient response, rising edge . . . 73
67 Output transient response, falling edge . . . 73
68 Measured closed loop gain/phase using Bode 100 . . . 74
69 Conducted EMI result for 1.7A PWM mode operation . . . 75
70 Conducted EMI result with two added capacitors . . . 76
71 Conducted EMI result with added gate resistor . . . 76
72 Radiated emission with antenna aligned vertically . . . 77
73 Radiated emission with antenna aligned horizontally . . . 77 A.1 Switch node ringing 12 V input voltage, 3.9 Ω top gate resistor . . . . A-1 A.2 Switch node ringing 48 V input voltage, 3.9 Ω top gate resistor . . . . A-1 A.3 Switch node ringing 12 V input voltage, 2 Ω boot strap resistor . . . A-2 A.4 Switch node ringing 48 V input voltage, 2 Ω boot strap resistor . . . A-2 A.5 Switch node ringing 12 V input voltage, 390 pF, 1 Ω snubber . . . A-3 B.1 Output voltage ripple at 12 V input voltage and 10 mA output currentB-1 B.2 Output voltage ripple at 12 V input voltage and 400 mA output currentB-1 B.3 Output voltage ripple at 12 V input voltage and 4 A output current . B-2
B.4 Output voltage ripple at 24 V input voltage and 10 mA output currentB-2 B.5 Output voltage ripple at 24 V input voltage and 400 mA output currentB-3 B.6 Output voltage ripple at 24 V input voltage and 4 A output current . B-3 B.7 Output voltage ripple at 48 V input voltage and 400 mA output currentB-4 B.8 Output voltage ripple at 48 V input voltage and 4 A output current . B-4 C.1 Radiated emission with antenna aligned vertically, 48 V input voltage C-1 C.2 Radiated emission with antenna aligned vertically, 60 V input voltage C-1 D.1 Setup for Conducted EMI measurements . . . D-1 E.1 Bill of material for the LTC7801 design . . . E-1
List of Tables
1 System requirements . . . 29
2 Customer requirements - electrical components . . . 30
3 Buck converter market survey . . . 32
4 LDO calculations . . . 34
5 Output Inductors 8.2 µH market survey . . . 43
6 NMOSFET . . . 47
7 Limits for conducted disturbance at the mains ports of class B ITE . 60 8 Limits for radiated disturbance of class B ITE at measuring distance of 10 m . . . 62
9 measured line regulation . . . 68
10 Measured load regulation . . . 68
11 Reduction of switch node ringing . . . 70
12 Output voltage ripple . . . 72
13 Feedback loop stability testing . . . 74
1 Introduction
ACTIA Nordic AB is a company that develops and designs products and solutions for the automotive industry. A customer of ACTIA wants to collect and monitor data from their warehouse trucks. ACTIA ofers a solution, called Data Handling Unit (DHU), that collects data from all the sensors mounted on the warehouse trucks and transmits it wireless to a monitoring system.
The DHU is a ”black box” solution connected to the warehouse trucks for data handling. It communicates with a cloudbased telematic server through 4G. In addi-tion the DHU receives Global Navigaaddi-tion Satellite System (GNSS) signals to track the truck position.
1.1 Purpose
In the current and next generation telematics platforms, high demands are put on high eiciency power supplies, which must operate at a higher eiciency than pre-vious generations and must be accommodated on smaller Printed Circuit Board (PCB) layout.
This thesis will include the deinition, design and validation of the main voltage converter of the DHU system. The converter has to be able to handle tough envi-ronments such as voltage pulses, voltage surges and Electromagnetic Compatibility (EMC) requirements.
The design will include electrical schematics and PCB layout. Validation includes electrical and stability testing at ACTIA and EMC testing at external part.
The assignment also includes communication with ACTIA’s subcontractors, internal purchasing organization and other hardware designers.
1.2 Problem Formulations
The main questions of this master thesis includes both a theoretical part and a design and validation part. The main issues of the thesis are compiled in the following research questions:
• How should the design be realized in order to meet the requirements.
The power supply has to meet the requirements from both the customer and ACTIA, but also the International Electrotechnical Commission (IEC) stan-dards.
The power supply is a part of telematic and automotive equipment which includes hard regulations in the ield of EMC.
• How to maximize the eiciency of the power supply.
The product is fed by the warehouse truck battery and therefore has to have high eiciency. Being able to deliver high eiciency even at low power outtake is of great importance.
• How to minimize the size of the PCB layout.
The size of the PCB layout for the power supply is important to give space to the rest of the system because of the size limitations required by the customer.
1.3 Limitations
The power supply in this thesis is limited to the main converter which converts the battery voltage to the highest voltage used by other circuits in the DHU. The power supply is complemented by ilters and protection circuits to ensure safe operation of the system. This thesis includes background theory, design and testing of DC/DC buck converters.
1.4 Outline
• 1. Introduction
Describes the purpose of this thesis along with problem formulation and limi-tations.
• 2. Theoretical Background
Provides the necessary theory needed for the implementation. The theory is limited to theory speciic for this thesis.
• 3. Implementation
The implementation chronologically describes the worklow starting with a market survey, followed by choice of components, schematic, layouts and PCB design.
• 4. Test and Veriication
Provides the sequence of tests performed on the system and the purpose of each test. The test sequence contains electrical, stability and EMC testing. • 5. Result
Shows the inal system schematic and PCB. All the results from the system testing is shown in this chapter.
• 6. Discussion
This chapter presents a discussion with the authors thoughts about the imple-mentation process and the result of the project.
• 7. Conclusion
The conclusion chapter answers the problem formulation. This chapter con-tains conclusions about the solutions found in the market survey, the diferent design layouts and the manufactured design.
1.5 Materials and Sources
The following section presents the materials and sources used in this thesis.
1.5.1 Sources
Sources used in this thesis were found using the database library at Linköping Uni-versity with databases such as IEEE Xplore: Digital Library. Other sources such as data sheets and design recommendations were found at manufacturer websites.
1.5.2 Materials
To reach the inal design solution, evaluation kits from diferent manufacturers were provided. In house components at ACTIA were used to reconigure the evaluation kits. The inal design solution were manufactured to be tested.
1.5.3 Software
To draw electrical schematics and PCB netlists the software OrCad Capture CIS software were used [1]. The PCB layout were done using Altium Designer software[2] with imported netlists from OrCad Capture CIS. Electrical simulations were done using EE-Sim from Maxim Integrated [3], WEBENCH® from Texas Instruments [4],
LTspice® [5] and LTpowerCAD® [6] from Analog Devices. Calculations and graphing
2 Theoretical Background
The main component of the power supply is a Switch Mode Power Supply (SMPS) DC/DC buck converter [8]. It has the ability to step-down the nominal input voltage from the battery to an output voltage of 5 V , which is the highest voltage used in the DHU system.
2.1 DC/DC Buck Converter
To describe the basic function of a buck converter, a simple model with basic com-ponents is used, shown in Figure 1. The model contains a DC-voltage source, free-wheeling diode, inductor, capacitor and a resistive load. The switch in this case is in reality a MOSFET and the diode is often changed to a MOSFET with inverted control signal compared to the switch. The circuit with the freewheeling diode is an asynchronous solution and the dual MOSFET solution is synchronous. Beneits with the synchronous solution is that the voltage drop over a MOSFET is much lower than over a diode. This leads to lower power losses and higher eiciency with the synchronous solution at high output currents. Asynchronous converters could however lead to higher eiciency than the synchronous at low currents due to power savings without the gate driver [9].
Figure 1: Simpliied buck converter model
Figure 1 shows the current paths in the buck converter model in the cases when the switch is either open or closed. When the switch is closed the current lows from the source to the load through the inductor. When the switch is opened the current continuous to low through the load through the freewheeling diode. This results in that the average output voltage is given by equation 1, where D is the switching duty cycle and Ts is the switching period time [8].
Vo= 1 T s ∫ Ts 0 vo(t)dt = 1 Ts (∫ ton 0 Vindt+ ∫ Ts ton 0dt ) = ton Ts Vin = Vin· D (1)
Figure 2 shows the waveforms of a buck converter. The current through the inductor is shown as a triangle wave due to the current inertia of the inductor. In the on state the output voltage is given by Vo = (Vin− VL), where the inductor voltage is
given by VL= L · di/dt. In the of state the output is disconnected from the input
voltage source, which means that the inductor starts to discharge. The current keeps lowing through the freewheeling diode and the output voltage is therefore equal to the negative of the inductor voltage.
As seen in equation 1 the average output voltage is only dependent on the input voltage and the switching duty cycle and not on the inductor value. This is due to the fact that in steady state operation the average inductor voltage is zero. This is shown in Figure 2, and calculated in equation 2, where the positive and negative side areas of the inductor voltage are the same [8].
Figure 2: Buck converter waveforms in CCM
∫ Ts 0 VLdt= ∫ ton 0 VLdt+ ∫ Ts Ton VLdt= 0 (2)
The values of the inductor and capacitor are still important even though they do not have an impact on the average output voltage. The values of the components decides the waveform of the output voltage and how much voltage and current ripple there will be. The output current ripple of the converter is derived in equation 3. VL = L dI dt ↔ ∆I = VL· dt L ↔ ∆I = (Vin− Vout) · D Lfs (3) The output voltage ripple of the buck converter depends of the current ripple derived in equation 3. Figure 3 shows the relation between the current ripple and the change in charge of the capacitor. The bottom graph of the igure shows the impact the change in capacitor charge has on the output voltage ripple.
Figure 3: Output ripple of a buck converter
Equation 4 shows the relation between voltage and current ripple out of the converter. The charge level of the output capacitor depends on the current ripple through the inductor as shown in Figure 3. Output voltage ripple is then given by the change in charge divided by the capacitance, that with the help of Figure 3 gives the expression in equation 4 [8].
∆Vout = ∆Q C = 1 C 1 2 ∆IL 2 Ts 2 = T2 s 8C Vout L (1 − D) (4)
2.1.1 Integrated Buck Converter
There are many diferent topologies of buck converter. One of them is called an integrated buck converter. It has the switching MOSFET’s built into the Integrated Circuit (IC) which reduces the number of components on the PCB. It also reduces the layout size of the design as the MOSFET’s are among the larger components in the converter. Electromagnetic Interference (EMI) is also reduced by using an integrated buck converter as the switching loop areas is reduced a lot with the built in switches as well as the stray inductance in the MOSFET’s. With built in MOSFET’s the current is limited and is in most cases lower than by using external MOSFET’s. An example of an integrated buck converter is shown in Figure 4.
Figure 4: Integrated buck converter
2.1.2 Buck Controller with External Switches
A buck controller, with the diference from the integrated converter, has the switch-ing MOSFET’s externally. This leads to increased Bill of Materials (BOM) and assembly costs. A buck controller solution however allows selection of the power transistors. This enables the buck solution to be more lexible and allows it to handle tougher requirements such as wide input voltage ranges and higher currents. One problem with external switches is that the current loop areas increases, which will be described in section 2.4.1.
2.1.3 Flyback Converter
A lyback converter is working in the same way as the converter in section 2.1 with the diference that the inductor of the converter is replaced with a transformer. The primary side of the transformer consists of a MOSFET driver that chops the voltage and the secondary side consists of a synchronous rectiier and/or a ilter. In this way it is possible to electrically isolate the input from the output via the transformer. Using a transformer will however introduce higher power losses which will decrease the eiciency of the converter [13].
2.2 Control and Stability of the DC/DC Converter
This section is about how to control the switching duty cycle of the converter and how to keep the switching in the stability region.
There are three diferent conduction modes of operating a DC/DC converter; Continuous Conductive Mode (CCM), Discontinuous Conductive Mode (DCM) and Boundary Conductive Mode (BCM). The mode used in section 2.1 to describe the basic functionality of the converter was the CCM. CCM is when the current trough the inductor never reaches zero. DCM is the mode when the current sometime under the switching period is zero. BCM is the boundary between the other modes, this means that BCM is a continuous mode on the boundary on becoming discontinuous [8],[10].
2.2.1 Boundary Conduction Mode
The condition for the boundary between CCM and DCM is when the average current through the inductor is equal to half the current ripple. Derived from equation 3 gives the expression shown in equation 5.
IL= 1 2∆I = (Vin− Vo) · D 2Lfs = TsVo 2L (1 − D) (5) This means that all currents below the half of the ripple will put the converter in discontinuous mode. Maximum inductor current in boundary mode, at constant output voltage, is given when the switching duty cycle is zero. The boundary is shown in Figure 6.
Figure 6: Buck converter characteristics keeping Vo constant
Figure 6 shows that the low current low forces the converter to operate in DCM region, which in some cases introduces more ripple, noise and emissions [10].
2.2.2 Switch Control Signal
There are two methods often used to produce the switch control signal to the con-verter, Pulse Width Modulation (PWM) and Pulse Frequency Modulation (PFM) [12].
PWM consists of a comparator that compares the loop feedback voltage to a gen-erated sawtooth reference. If the feedback voltage is below the sawtooth voltage the control signal turns high and vice versa. In this way the switching frequency is constant and it is only the pulse width that is modulated. Figure 7 shows an example of PWM with a constant output voltage.
Figure 7: PWM generator signals
PFM is another method to generate the control signal to the switch circuit. The diference from PWM is that now the pulse width is kept constant and the frequency between pulses is modulated. Figure 8 shows the same example as Figure 7, but now in PFM mode. Now it is the diference between the sawtooth reference and the output voltage that decides the switching frequency. The sawtooth reference as in the examples is used in many application but can be changed to any oscillating signal that its the purpose.
Figure 8: PFM generator signals
In normal operation mode when the converter is operating in the CCM region the PWM method is often used. When the converter is forced into DCM, some con-verters have the ability to switch modes and start to operate with PFM in order
to maintain high eiciency at low current outtake. These converter changes mode when the current through the inductor reaches zero . In this way the converter can enter a energy saving mode between the switching pulses which reduces the quies-cent current of the converter which increases the eiciency [12].
Why PWM is unable to operate at high eiciency in this region is due to switching duty cycle reaching towards zero, which puts the output current in DCM. At to low duty cycles the MOSFET’s wont be fast enough, which leads to operation in the linear region. This is why some converters switch to PFM in this region, to maintain constant pulse width and only change the frequency to keep the converter in CCM. Why PFM is not used all the time is because the output inductor and capacitance will change characteristics as the frequency changes and the output ripple levels will become unreliable.
2.2.3 Feedback Control
Switching DC/DC converters uses a feedback loop in order to maintain the output voltage level. This control loop can be designed in three diferent ways; voltage, current or hysteresis mode [14]. Voltage division is used in all designs to change the desired voltage output.
Voltage mode consists of an error ampliier that compares the output voltage with a programmed reference voltage. The diferential signal from the error ampliier is then connected to a comparator that compares the voltage with an internal control signal, a triangle wave in the PWM case. A model of the voltage control mode is shown in Figure 9.
Voltage control mode is an easy control method and has a high tolerance to external noise but it requires a complex compensation network to maintain stability [14].
Current mode is much alike the voltage mode control. Instead of comparing the error ampliier voltage with a triangle wave in the PWM generator, it is compared with a current sensing circuit that converts the inductor current to voltage. The output current can be measured in diferent ways by measuring the current through the inductor, by measuring the resistance of the primary MOSFET or by using a high resistive voltage divider on the output. An example of the current mode feedback is shown in Figure 10.
Figure 10: Current mode control feedback loop
Advantages of using current control mode is that it requires a very simple
compensation network due to high stability in the feedback loop. In this mode the compensation network is often built in to the IC. Current mode control also responds faster than voltage mode to fast load transients which gives a faster voltage regulation [14].
In hysteresis mode control, the output voltage is compared directly with the reference voltage in a comparator. The comparator is then connected straight to the switch control circuit as shown in Figure 11.
Figure 11: Hysteresis mode control feedback loop
Hysteresis mode control has the fastest load transient response of the three
methods and the feedback loop is very stable and does not require a compensation network. Drawbacks of the hysteresis mode control is that it requires a high Equivalent Series Resistance (ESR) output capacitor, which will generate a high output voltage ripple due to the high ESR [14].
2.2.4 Stability
In order to ensure a stable loop response, a compensation network needs to be implemented. The purpose of a compensation network is to achieve the wanted phase and amplitude margins to get stability. For a typical SMPS, stability is basically deined as when the phase margin is greater than 45° and the gain margin is greater than 6 dB. In other words, the overall gain of the system should cross 0 dB with a slope of -20 dB/decade. Figure 12 shows the loop gain of a typical buck converter were it crosses 0 dB with -40 dB/decade [15]. This is not stable and a Type II compensation network is needed. There is a Type III network which is a more complex solution and mostly used in voltage controlled mode. For the current controlled buck converter, the Type II compensation network satisies the requirements regarding phase/gain margin and bandwidth.
Figure 12: Converter feedback loop gain without compensation network The synchronous current mode controlled buck converter mainly consists of three elements concerning compensation. The Modulator, output ilter and compensation network is shown in Figure 13 [16].
Figure 13: Closed loop system schematic of buck converter
The modulator compares the output of the error ampliier with the reference. The switch node is the output of the modulator. The gain of the modulator is given by equation 6 [17], where ∆Vosc is the comparator reference voltage.
Gainmod= 20 · log
( Vin
∆Vosc
)
(6) The output ilter consists of the main output inductor and decoupling capacitors. The input of the ilter is the switch node and it outputs the regulated output, and has has a transfer function of a standard LC ilter shown in equation 7 [17].
GainF ilter = 1 + ESR · C out
1 + s(ESR + DCR) · Cout+ s2· Cout· Lo
(7) Adding the modulator and the output ilter together results in the open loop system shown in Figure 14. The gain of the open loop system as shown in Figure 12 with frequency markings fp and fz corresponding to the LC double pole and ESR equal
Figure 14: Open loop buck converter system
The frequency fLC comes from the resonance frequency of the LC output ilter and
fESR is related to the ESR of the output capacitor, which can be seen in equations
8 and 9 [15]. fLC = 1 2π√Lo· Cout (8) fESR = 1 2π · ESR · Cout (9) In order to achieve a stable system during input voltage luctuations and load per-turbations, the open loop needs to be closed by a compensation network. The Type II compensation network shown in Figure 15, has the transfer function shown in equation 10 [17].
Figure 15: Type II feedback compensation GainT ypeI I = 1 R1· C1 ( s+R1 2·C2 ) s ( s+C1·C2·R2 R1·C1 ) (10)
Figure 16 shows the bode plot of the Type II compensation gain and phase. The compensation networks gives a phase boost of 90° to help countering the resonant efect at the double pole [17]. Adding the three elements together results in a closed loop system shown in Figure 13. The compensation network inputs the buck converter output voltage and delivers the error ampliied signal back to the modulator.
2.3 Reverse Polarity and Over Voltage Protection
An important aspect to take into consideration when designing a power supply cir-cuit is the ability to handle over voltage and reverse polarity voltage.
The easiest way to design a RPP circuit is by simply putting a Schottky diode in series with the power supply. This will prevent current from lowing in the re-verse direction. The downside of this solution is voltage drop over the diode in normal operation which leads to high power loss at high currents. At high power loss the diode also intends to get very hot.
One solution that works similar to using a Schottky diode is by using a P-channel MOSFET circuit. The PMOS is simply connected with drain-source in series with the power supply and the gate connected to the return. In this way the PMOS is always open at normal working condition and closed at reversed polarity voltage. In this way the forward voltage drop is much lower, which leads to higher eiciency and lower temperature evaluation. It is also possible to use a N-channel MOSFET connected on the return path to prevent reverse polarity voltage. The downside with this solution is that it introduces ground shifting to the circuit, which can disturb sensitive systems like automotive telematic systems. The NMOS however has a much lower drain-source resistance than a PMOS and would almost work as an ideal diode in this case.
To be able to use a NMOS in series with the positive side of the power supply there has to be a control unit containing a charge pump to increase the gate voltage of the transistor. This coupling is called an ideal diode due to the low forward power loss [19].
There are diferent ways to block high voltages to reach the buck converter. An easy way to prevent fast voltage burst is to use a Low-Pass (LP)-ilter, which will block high frequencies. Another way is to use surge protection circuits which will either block or short circuit over voltages.
2.4 EMC and EMI
Regarding EMI it is crucial that the converter meets the requirements from the Comite International Special des Perturbations Radioelectriques - International spe-cial Committee on Radio Interference (CISPR22) EN55022:2006 [20] to prevent it from interfering with other operating devices. Diferent techniques and methods can be used to achieve a lower level of radiated and conducted emission.
2.4.1 Reducing Radiated EMI in Buck Converter
The goal of minimizing the radiated ields, is achieved by primarily reducing the high current loop areas A1 and A2 shown in Figure 17 [21] ,[22].
These high switching current loops caused by the high and low side MOSFET’s can be seen as one turn inductors and acts as antennas radiating electromagnetic waves [23].
Figure 17: Buck converter current loops
Equation 11 shows how the radiated ield for diferential mode currents is propor-tional to the frequency(f) squared, current loop area(A), the current(I) and the distance from the current loop to the receiving antenna(d) [24].
|Edm| = 1.316 · 10−14·
f2· A · I
d (11)
An efective and easy way to reduce EMI is by placing a bypass capacitor Cin close
to the high-side MOSFET, in order to minimize the current area. Additionally, a ground plane can be added providing better return paths resulting in reduced cur-rent area. By adding a ground plane high frequency curcur-rents will induce opposing
currents in the ground plane, canceling the magnetic ield [23].
Another way to reduce EMI is by slowing down the rise/fall time of the high-side MOSFET. By slowing down the rise/fall times, the higher frequency components will be reduced resulting in improved EMI performance. Figure 18 shows the fre-quency spectrum of the switching pulses. By increasing rise and fall times will shift the 1
πτRI SE point to a lower level making the higher frequency components drop of
earlier with -40 dB/decade [21].
Figure 18: Frequency spectrum of switch pulses
Slowing down the rise/fall times can also be done by adding a resistor in series with a bootstrap capacitor that powers the gate of the high-side MOSFET. A resistor connected to the high-side gate is also an option for slowing down the rise/fall times. However, slowing down the rise and fall times will lead to additional power loss since the MOSFET spends more time in the linear region. This trade of between EMI and power loss needs to be taken into consideration if the rise time is to be modiied [25].
2.4.2 Switch Node Ringing
The second source of EMI is the switching node (SW), the connection point between the inductor and the two MOSFET’s. A combination of the MOSFET’s parasitic capacitances, the input ilter Equivalent Series Inductance (ESL) and the IC bonding wires, will cause the frequency ringing on the switching waveform [21]. Figure 19 shows the high frequency ringing for the rising and falling edge which has a much higher frequency than the operating switching frequency [28].
Figure 19: Switch node ringing
When the high-side MOSFET is switched on, the parasitic capacitance of the low-side MOSFET and the parasitic inductance of the MOSFET’S switching loop will cause frequency ringing in the rising edge [26].
When the high-side MOSFET switches of, the frequency ringing will be caused by its own parasitic capacitance and the low-side MOSFET’s parasitic inductance from source to ground [27]. The resonant frequency of the current loops is given by equation 12 [29]. Lloop is the total inductance in the current loop and Coss is the
small signal output capacitance of the MOSFET that is in of state [11], [21]. fres =
1 2π√LloopCoss
(12) To minimize broad band EMI the resonant frequency should be as high as possible. There is multiple options on how to increase the resonant frequency. One way is to reduce the loop area, as the loop inductance can be seen as a one turn inductor that is directly proportional to loop area. By increasing the resonant frequency the switch node ringing can be reduced in amplitude. This is due to the rise time of the switching MOSFET, which is typically in the range of 1-30 ns. With the higher resonant frequency the frequency from the switch node is avoided and is thereby not ampliied. As mentioned in section 2.4.1 the rise time of the MOSFET can be increased by applying a resistor in series with the gate pin. In this way the frequency of the switch node ringing is reduced. This method should only be used if the res-onant frequency can not be pushed high enough as the eiciency of the converter will be reduced with the longer rise time.
The choice of MOSFET’s also afects the resonant frequency as it is proportional to the Coss capacitance in of state. The package types of the converter and
MOS-FET’s has diferent designs with diferent pin conigurations which also afects the frequency ringing. Some are using wire bond packages(Thin Shrink Small Outline Package (TSSOP) shown in Figure 20 and some are using lip-chip packages(Quad Flat pack No lead (QFN)) shown in Figure 21.
Figure 20: TSSOP Package Figure 21: QFN Package
The QFN package type has a better performance compared to the TSSOP type due to the much shorter connection pads. The TSSOP has longer wire bonds and therefore a higher per-unit-length inductance, which is desired to be minimized in order to reduce high frequency ringing. On the other hand the TSSOP handle heat in a more eicient way than the QFN package type [21].
Another way to reduce the high frequency ringing is to use a RC snubber circuit connected close to the switch node, shown in Figure 22 [30].
Figure 22: RC Snubber connected to switch node
The RC snubber allows for attenuation of the parasitic resonant LC circuit which results in lower frequency ringing. The RC snubber is able to discharge the MOSFET of its junction charge during on and of switching [21]. High frequency currents will
still pass through the RC snubber so leads needs to be short and placed very close to the MOSFET. Equation 13 shows how the resistor value of the snubber depends on the parasitic inductance and capacitance, ξ is the damping factor ranging from 0.5 for slight damping, to 1 for heavy damping [21].
Rs = 1 2ξ √ Lp Cp (13) In comparison to slowing down the top MOSFET with gate or bootstrap resistor, the snubber is the least power efective solution. The power loss of the snubber is given by equation 14 [32].
PLoss = Cs· Vin2 · f (14)
The snubber capacitance value Cs needs to be dimensioned so that the resistor can
achieve a steady resonance damping during falling and rising edge, though not too large since it would increase the power loss.
2.4.3 Conducted EMI
Conducted EMI originates from the switching operation of the SMPS, resulting in discontinuous currents at the input of the DC/DC-converter. A voltage ripple which is generated by these discontinuous currents, can travel down the conductor inter-fering and compromising other circuits in the system. In order to reduce this noise a ilter is necessary to implement at the input of the converter [24].
Conducted EMI is divided into two sub-categories, diferential-mode and common-mode. Common-mode noise signals has typically the same phase and amplitude on both the conductor (Line 1) and return path (Line 2) with respect to safety ground. In diferential-mode the noise signal exist between the Line 1 and Line 2. These diferent noises are described by equation 15 [24].
Icm =
ILine1+ ILine2
2 Idm=
ILine1− ILine2
2 (15)
For typical non-isolated SMPS with two input lines, any current going in through Line 1 is intended to go out on Line 2. Due to parasitics in the circuits there is unintended common mode currents that is not needed for the circuitry to work. Common-mode currents is usually very small and diferential-mode noise is there-fore the main focus when reducing conducted EMI [31]. Conducted EMI is only dependent on current level and not voltage, so lower input voltage gives a higher current for same power level resulting in worse conducted EMI [31]. In order to pass the CISPR22 limits for conducted emission, an input ilter is necessary.
2.4.4 Input Filter
An input ilter is a crucial part in the buck converter design and has to be evaluated and understood in order to pass the EMI requirements. The purpose of the ilter is to prevent electromagnetic interference on the power line caused by the switching source. It is also used to iler out high frequency voltages on the power line from reaching the output [33]. In order to achieve this, a low-pass LC-ilter needs to be implemented between the power source and input of the buck converter. Figure 24 shows the schematic for an undamped LC-ilter.
The ideal LC-ilter has no gain before the cutof frequency f0 and normally declines
with -40 dB/decade after f0 for a 2nd order Butterworth ilter [34]. A Chebyshev or
an Elliptic ilter, ofers a steeper declination than the Butterworth ilter. The cutof frequency is dependent on the inductance and capacitance values given by equation 16 [34].
f0 =
1
2π√LC (16)
The gain of the LC-ilter has a peak at the cutof frequency which originates from the characteristic impedance of the ilter being ininite at the cutof frequency. This is illustrated in Figure 25 [35]. If the gain is large at the cutof frequency it could cause trouble and amplify the noise. This ampliication is not desirable, which means that the ilter needs attenuation at the cutof frequency.
Figure 25: Gain of LC-ilter
The amount of damping at the cutof frequency is given by the damping factor ξ shown in equation 17 [35]. When ξ = 1 there is maximum damping at the cutof frequency. As ξ then gets smaller, the gain peak increases which is shown in Figure 25.
ξ = L 2 · Rload
√
Its common that the undamped ilter fails to meet the requirements regarding peak gain at the cutof frequency, which means that a damping circuit is needed. In order to reduce the peak impedance at the cutof frequency a RC circuit is connected in parallel to supply suicient damping to the ilter [35]. The resistor reduces the peak impedance and the capacitor is used for reducing power dissipation in the resistor[35]. The damped LC-ilter is shown in Figure 26.
Figure 26: Damped LC-ilter
The ESR of the electrolytic capacitor Cd is usually large enough to work as the damping resistor Rd.
3 Implementation
In order to achieve an eicient power converter for the described system, a market survey was conducted taking into account the requirements made on the system. The market survey was also used to get deeper knowledge of parameters that afect the power converter such as EMI, eiciency and layout size. From the market survey multiple designs were made and compared to each other. From the comparison, one solution were chosen to be manufactured and fully tested.
3.1 System Requirements
There are multiple requirements put on the design regarding voltage and current levels, temperature and EMC. Table 1 shows the electrical requirements put on the power converter and Table 2 shows the general requirements on electrical nents from the customer. Apart from the requirements in the tables, all the compo-nents has to be automotive classiied. This classiication contains compocompo-nents with higher temperature tolerance and are more robust to better handle vibrations.
Table 1: System requirements
Parameter Speciication Conditions Comments Current
con-sumption standby
Max 5 mA At nominal supply volt-ages
Nominal
sup-ply voltages 12 V, 24 V and 48 V Fluctuations 0.7 - 1.25 xnominal supply voltage
Over voltage 1.5 x nominal supply
voltage 10 s every 2 minutes Full functionality isneeded in this region
Under voltage 0.5 x nominal supply
voltage 50 ms
Estimated
Out-put Power >20 W At 5 V output voltageand 4 A output current
Operation
tem-perature -35 - +70 °C Ambient temperature Minimum
ei-ciency >80 % >10 mA output current ∼ 90 % at full load Reversed
polar-ity 1.2 x nominal supplyvoltage -60 V at 48 V supplyvoltage
Output current
ripple <30 % Percentage of averageoutput current At maximum outputcurrent
Output voltage
ripple <10 % Percentage of nominaloutput voltage
Load transients Max 2 A Abrupt change in out-put current
System
Table 2: Customer requirements - electrical components Component test Comments
Radiated
emis-sion EN 55022:2006, class B 30-230MHz:30 dBµV/m 230-1000 MHz:37 dBµV/m
The test component, shall be con-nected to cables with a length that corresponds to a real installation in a truck
Conducted
emission EN 55022:2006, class B 0.15-0.5MHz: quasi-peak 79 dBµV average 66 dBµV 0.5-30 MHz: quasi-peak 73 dBµV average 60 dBµV
Measurements shall be performed on the power supply leads to the compo-nent
Radiated
immunity EN 61000-4-6:2006 27-1000 MHz:30V/m 1000-2700 MHz 15 V/m The tested component, shall be con-nected to cables with a length that corresponds to a real installation in a truck, and at least one meter of the length shall be exposed to the ield
Conducted
im-munity EN 61000-4-6:2009 0.15-27 MHz: 10V Tests shall be performed on powerand signal lines separately
Fast transients EN 61000-4-44:2004 Test level 2 Tests shall be performed on power and signal lines separately
ESD immunity
powered up EN 61000-4-2:2009 Test level 4: ± 8kV contact discharge ± 15 kV air dis-charge
The lower test levels according to EN 61000-4-2 must also be tested and ful-illed. Indirect discharges shall also be applied towards coupling planes (HCP and VCP).
ESD immunity
unpowered ISO 10605:2008 paragraph 9 ± 8 kVcontact discharge ± 15 kV air dis-charge
The lower test levels according to ISO 10605 must also be tested and fulilled
Immunity
magnetic ield EN 61000-4-8:2010 50 Hz: 100 A/m Applicable only to devices susceptibleto magnetic ield
3.2 Power Converter Market Survey
The initial stage of the market survey was to compile all the requirements placed on the power converter from both ACTIA and the customer, shown in Table 1. EMC and EMI requirements from the customer were taken into account for the diferent power converter designs, sown in Table 2. The research for a compatible power converter was performed using the requirements parameters as inputs to the IC manufactures products. ACTIA had some initial suggestions regarding manufac-tures and power converters to investigate further. With a wide input voltage range combined with a high eiciency requirement for both low standby currents and high operating currents, many of the power converters could be neglected from the early phase of the research. This limited the number of manufactures to a few, including Texas Instruments, Maxim Integrated and Analog Devices. The three manufac-turer each has simulation tools for their converters which were used to simulate the component values of the designs. The softwares are presented in section 1.5.3.
In addition to get an even clearer and better view of the power converter market, meetings were held with the diferent IC manufactures. This was done for more detailed information about their circuits and solutions. Meetings were held with representatives from Texas Instruments, Maxim Integrated and Analog Devices.
3.3 Choice of Power Converter
Choosing a suitable buck converter were done based on the market survey. The choice was done based on;
• BOM
The total number of components required in the design and the total cost. The cost of the power converters presented, are taken from the distributer websites and is not the large scale prices ofered by the distributer.
• Size
The estimated physical size of the PCB • Eiciency
Estimated eiciency under the operating conditions given by the requirements. • Input and output power
That the converter is able to handle the total range of input voltage required to meet the speciications, or if it needs to be combined with other circuitry. It also has to meet the output power requirements of 20 W at 5 V and 4 A. The resulting components from the market survey is shown in Table 3.
Table 3: Buck converter market survey
Model Vin/Iout Quiescent
current Estimatedeiciency Price Reference
LTC7801
Controller 4-140 V> 5 A 40 µAshutdown = 10 µA ∼ 80 % at 5 mA ∼ 90 % at 10 mA > 90 % at > 10 mA $4.46 [37] MAX17536 Integrated converter 4.5-60 V 4 A 128-168 µA ∼ 70 % at 5 mA∼ 78 % at 10 mA >85 % at > 100 mA $2.95 [38] MAX17506 Integrated converter 4.5-60 V 5 A 128-168 µA ∼ 75 % at 5 mA∼ 80 % at 10 mA >85 % at >100 mA $3.60 [39] LM5141
Controller 3.8-65 V>5A 35 µAshutdown = 10 µA ∼ 70 % at 10 mA ∼ 85 % at > 10 mA $ 2.53 [40] LM5161 Integrated converter 4.5-100 V 1A 50-90 µA ∼85 % at 100 mA $2.07 [41] LT4356-2
Surge stopper -60-100 V 60 µA (Linear regulation) $2.00 [42]
MAX17597 Flyback, pri-mary side 4.5-36 V 2 mA shutdown = 20 µA ∼ 90 % at 1 A $0.68 [43] MAX17606 Flyback, sec-ondary side 4.5-36 V 4 A 320 µA ∼ 90 % at 1 A $0.71 [44]
From the market survey two diferent converters were chosen and designed to see which were the better. The irst one, circled in red in the table, LTC7801 is a buck controller that is able to handle more than the required input voltage range on its own. The second, circled in blue, is MAX17506 that is an integrated buck converter that needs only a few external components in the design. MAX17506 covers the input voltage of 4.5-60 V, but needs a pre-converter to handle the highest voltages. The chosen pre-converter, also circled in blue in the table, is LT4356-2 from Analog Devices, which is a surge stopper that can be conigured as a Low-Dropout regulator (LDO).
A third solution was also evaluated and tested, marked in green in the table. This buck converter solution was based on an evaluation kit provided by Maxim Inte-grated that was reconigured. The evaluation kit consisted of a lyback converter with a synchronous rectiier.
From the requirements and market survey the switching frequency were decided to be 500 kHz. The choice were based on maintaining the required eiciency and still keep the solution size small [48].
3.3.1 LDO pre-stage
One major problem with the power supply circuit requirements were the wide range of input voltage. There are only a few converters on the market that can handle the high input voltage of 72 V and convert it down to 5 V at 4 A. One solution was therefore to use a linear regulator or a LDO before the buck
converter. In this way the input voltage of the buck converter could be limited to about 60 V where there are a lot of converters on the market.
A linear regulator acts like a variable resistor that varies with the load. The linear regulator is connected like a voltage divider to maintain constant output voltage. The downside with this solution is that the linear regulator converts the residual power to heat which gives a low eiciency and high power loss. The linear
regulator is supposed to cut the long durational over voltages and is inactive at nominal voltages.
To calculate the expected worst case scenario of the power dissipation of the LDO, maximum load current is expected. Maximum voltage drop over the LDO is 12 V. The duty cycle of the switching buck converter is also needed to calculate the power dissipation as the current is discontinuous. The duty cycle is calculated using equation 1, which gives D = 1/12. With the given information the Root Mean Square (RMS) values for the current trough and the voltage across the LDO is calculated using equation 18 and 19.
Iin,RM S = √ 1 T ∫ T 0 i2(t)dt =√ 1 T[t · i 2(t)]T D 0 (18) Vdrop,RM S = √ 1 T ∫ T 0 v2(t)dt =√ 1 T[t · v 2(t)]T D 0 (19)
With the RMS and peak values of the voltage and current known, the average and peak value of the power dissipation is calculated using equation 20 and 21.
PLDO,peak = Iin,peak· Vdrop,peak (21)
Table 4 shows the power, voltage and current levels, calculated using the previous equations.
Table 4: LDO calculations
Iin,RMS 1.155 A Vdrop,RMS 3.414 V PLDO,AVG 4 W PLDO,peak 48 W
According to the calculations and the requirements the LDO has to be able to handle a power dissipation of 4 W in 10 seconds every 2 minutes. The LDO also has to be able to handle peak power dissipation of 48 W at 4 A output current. The input/output current relation in the circuit is shown in Figure 27. The input current follows the output current when the buck MOSFET is open and is close to zero when the MOSFET is closed.
3.4 System Layout
This section will show the layouts of the three diferent converter solution and discuss which one used for the inal design.
3.4.1 Layout of LTC7801
The irst design was made using the LTC7801 controller from Analog Devices [37]. LTC7801 has among the highest eiciencies of the buck converters from the market survey. As the controller can handle voltages up to 140 V all the way down to 4 V, there is no need of a pre-converter.
LTC7801 has a mode called burst mode, which is a pulse skipping mode to maintain high eiciency at light loads. As seen in Table 3, it has an eiciency of 80 % at output current as low as 5 mA. The controller has a low current consumption of 2.5 mA in active mode, 40 µA in sleep mode and 10 µA in shutdown. Active mode is when the controller operates at nominal switching condition. Sleep mode is when the controller operates in PFM mode, which means that the controller enters a low power mode between the switching pulses. Shutdown is a mode that the controller enters when overheated or over voltage occurs, which means that most of the circuits in the controller is shutdown to prevent damage. A duty cycle of 100 % is possible which means that the design can handle to maintain nominal output voltage at the same level as the input voltage. The LTC7801 circuitry is shown in Figure 28.
3.4.2 Layout of MAX17506 with LDO
The second design was based on the converter MAX17506 from Maxim Integrated [39]. It is an integrated buck converter with an input voltage range of 4.5 to 60 V, which means that it had to be combined with another converter circuit.
MAX17506 does not require a complex external circuit to use, with most of the components built in to the IC. It has its compensation network build into the chip and only has to be complemented by an external capacitor at certain switching frequencies. It has the top side switch built into the chip as well, but has to be com-plemented by an external low side switch. MAX17506 can be conigured to work in PFM at low current outtake to increase the eiciency by reducing the frequency. Figure 29 shows the schematic for the MAX17506 design that is able to work up to 60 V of input voltage.
Figure 29: Schematic for MAX17506
The LT4356-2 from Analog Devices [42] was used as a pre-converter in the design based on MAX17506. It is used to prevent the voltage of the main converter to rise above 60 V. Figure 30 shows the schematic for the pre-converter circuit.
Figure 30: Schematic for LT4356-2
The pre-converter is a surge stopper that was conigured as a LDO. The converter is able to work at duty cycles up to 100 % which means that at voltages below 60 V the MOSFET is always open. The NMOS gate driver was also used to drive the gate of an NMOS RPP circuit that is shown in the left hand side of Figure 30. With n-channel MOSFET’s the series resistance in normal working conditions is very low. In the top of the igure there is a pnp transistor which is controlled by an internal ampliier. This was used as a linear regulator to save power in low current modes. The ampliier is still on when the LT4356-2 enters shutdown mode, which leads to a current consumption of only 60 µA and still keeps the output voltage at 5 V. The design with the integrated converter MAX17506 from Maxim Integrated re-sulted in a layout with few components in the case from 60 to 5 V. LT4356-2 was conigured as a LDO to handle the higher input voltages and the number of com-ponents in the design were doubled. The total price of the solution got higher than the LTC7801 controller solution that can handle the whole input voltage range on its own. Figure 31 shows the inal schematic for the solution.
3.4.3 Layout of Flyback Converter
The lyback layout was based on the MAX17606 evaluation kit from Maxim Inte-grated [45]. It is an isolated lyback converter with a synchronous rectiier and an optocoupler feedback circuit. The evaluation kit can handle input voltages up to 36 V so changes were made to the design to be able to handle higher input voltages and also rise the eiciency at low current outtake.
The Flyback converter evaluation kit for MAX17606 from Maxim Integrated was reconigured as shown in Figure 32. The changes done to make the converter handle higher input voltages were to add a large resistance on the input of the primary side controller and couple the output voltage directly to the input port. In this way the primary side converter is driven by the 5 V output voltage and a small current runs through the resistor to start up the circuit. The secondary side rectiier was also re-conigured to be driven from the output voltage through a small resistor. To reduce the amount of component the converter was reconigured to be non isolated to get rid of the optocoupler circuit. The non isolated design also has some modiications on the compensation and feedback loop to stabilize the new design.
Isolated power supplies are often used in systems were there is human touch in-volved to prevent injuries. It is also used in systems like a microcontroller driving a high current motor. Isolated power supplies are used for preventing high voltage spikes in the input side to reach the output. In this project the there is no need for an isolated power supply, to save space and power consumption the optocoupler circuit was removed.
Figure 32: Schematic of Flyback solution
even with the modiications. The modiications however increased the eiciency at currents above 0.5 A. Measuring results are shown in Figure 33 and Figure 34.
Figure 33: Eiciency curve lyback converter
3.4.4 Choice of Converter Layout
The schematics gave a better view on the total number of components in each design, to estimate cost and layout size of the solutions. Estimations along with some measurements, the chosen design to look further into was the LTC7801 converter design.
3.5 System Design
The following section presents how the main components of the design were chosen from market surveys, simulations and calculations.
3.5.1 The Output Inductor
After the power converter was chosen, the next important component to choose was the output inductor. As shown in section 2.1 the inductor decides how large the output current ripple will be. The requirements on output current ripple is shown in Table 1, and has to be below 30 % at nominal input voltage. The largest possible ripple is produced at maximum input voltage, as the voltage drop over the inductance is at maximum in this case. The inductor current ripple is given by equation 22
∆I = (Vin− Vout) · D Lfs
(22) The choice of inductor will decide at which output current the converter will enter DCM as the ripple is independent of the average output current. Figure 35 shows current waveform of the buck converter with an input voltage of 48 V with an output inductor of 8.2 µH at 500 kHz.
Figure 35: Output current waveform at diferent loads
As shown in Figure 35 the BCM is at an average output current of 0.5 A. All cur-rents below this value will put the converter in discontinuous mode.
Figure 36 shows the BCM current level of the converter with diferent output in-ductances. Average output currents above the BCM line puts the converter in CCM and lower currents puts the converter in DCM.
Figure 36: BCM current level at diferent output inductances
The choice of inductor was made from ive diferent parameters along with the automotive classiication.
• Inductance
Decide the current ripple and BCM level • Series resistance (DCR)
witch afects the eiciency due to power loss • Size
The physical size of the inductor which afects the PCB layout size • Shielding
If the case of the inductor is is magnetically and/or E-ield shielded • Price
The inductance was chosen to be 8.2 µH, which gives an estimated output current ripple of 30 % at maximum load.This value was chosen to keep some current ripple at low input voltages as the controller is current controlled and need some current ripple to work. Table 5 shows the result from the inductance market survey.
As shown in the table the physical size and resistance is directly proportional due to the diameter of the copper wire in the inductors.
Table 5: Output Inductors 8.2 µH market survey
Model Current Irated/Isat RDC Case/Size Price 784771082 Würth Elektronik 5.05 A / 5.5 A 20 mΩ Magnetically shielded 12 x 12 mm $ 1.00 7843330820 Würth Elektronik 7.2 A / 12.8 A 15.9 mΩ Magnetically capsuled 10.6 x 10.6 mm $2.04 XAL6060-822
Coilcraft 6 A / 8.4 A 24 mΩ MagneticallyShielded
6.36 x 6.56 mm
$0.66
XAL1010-822
Coilcraft 12.9 A / 18.3 A 11.7 mΩ MagneticallyShielded
10 x 11.3 mm $1.40 IHLE-3232DD-5A (10µH) Vishay 5.1 A / 5.2 A 50 mΩ Magnetic/ E-ield ShE-ielded 8.7 x 8.9 mm $ 0.93 IHLP-5050EZ-A1
Vishay 9.5 A / 18 A 18.9 mΩ Magneticallyshielded
13.2 x 12.9 mm
$3.22
The inductor XAL6060-822 [46] from Coilcraft was chosen to be used in the design, marked in red. It was chosen due to the small footprint which will reduce the size of the PCB. The DC-resistance of the inductor is low with respect to the size of the casing.
3.5.2 Output Capacitors
The next step was to select the output capacitance which decides the output voltage ripple. The output capacitor was also chosen large enough to handle the current ripple in the inductor. The output voltage ripple can be derived from equation 4 in section 2.1, with the diference that the ESR of the capacitors is taken into consideration. The new expression for the output voltage ripple is shown in equation 23. ∆Vout = ∆IL ( Ts 8C + ESR ) (23) Figure 37 is a MATLAB plot based on the previous equation and shows the output voltage ripple in percentage versus the output capacitance, with the resistive and capacitive parts plotted separately. ESR were estimated to be around 50 mΩ and capacitance varied. As seen in the igure the ripple goes from being dominated by the capacitive part to the resistive part. This means that to lower the ripple the resistive part needs to be minimized as well as using a large value capacitance.
Figure 37: Output voltage ripple at diferent capacitances
To achieve low output ripple multiple capacitors were put in parallel to increase the capacitance and lower the ESR.
