Institutionen för systemteknik
Department of Electrical Engineering
Examensarbete
Eye opening monitor for
optimized self-adaptation of low-power equalizers
in multi-gigabit serial links
Master Thesis in Division of Electronics Systems
at Linköping Institute of Technology
by
Anand Narayanan
LiTH-ISY-EX--13/4732--SE 22November, 2013TEKNISKA HÖGSKOLAN
LINKÖPINGS UNIVERSITET
Department of Electrical Engineering Linköping University
Linköpings tekniska högskola Institutionen för systemteknik
Master thesis performed at
Fraunhofer Institute for Integrated circuits (IIS)
Erlangen, Germany
Eye opening monitor for
optimized self-adaptation of low-power equalizers
in multi-gigabit serial links
Master thesis in Division of Electronics Systems
at Linköping Institute of technology
by
Anand Narayanan
LiTH-ISY-EX--13/4732--SE
Supervisor:
Conrad Zerna, Dipl.-Ing., Optical Sensors And Communications Fraunhofer Institute for Integrated circuits (IIS)
Erlangen, Germany conrad.zerna@iis.fraunhofer.de
Examiner:
Dr J. Jacob Wikner
Department of Electrical Engineering Linköping University
Linköping, Sweden jacob.wikner@liu.se
URL, Electronic Version
http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-106580
Publication Title
Eye opening monitor for optimized self-adaptation of low-power equalizers in multi-gigabit serial links
Author(s)
Anand Narayanan
Abstract
In modern day communication systems, there is a constant demand for increase in transmission rates. This is however limited by the bandwidth limitation of the channel. Inter symbol interference (ISI) imposes a great threat to increasing data rates by degrading the signal quality. Equalizers are used at the receiver to compensate for the losses in the channel and thereby greatly mitigate ISI. Further an adaptive equalizer is desired which can be used over a channel whose response is unknown or is time-varying.
A low power equalizing solution in a moderately attenuated channel is an analog peaking filter which boosts the signal high frequency components. Such conventional continuous time linear equalizers (CTLE) provide a single degree of controllability over the high frequency boost. A more complex CTLE has been designed which has two degrees of freedom by controlling the high frequency boost as well as the range of frequencies over which the boost is applied. This extra degree of controllability over the equalizer response is desired to better adapt to the varying channel response and result in an equalized signal with a wider eye opening.
A robust adaptation technique is necessary to tune the equalizer characteristics. Some of the commonly used techniques for adaptation of CTLEs are based on energy comparison criterion in the frequency domain. But the adaptation achieved using these techniques might not be optimal especially for an equalizer with two degrees of controllability. In such cases an eye opening monitor (EOM) could be used which evaluates the actual signal quality in time domain. The EOM gives an estimate on the signal quality by measuring the eye opening of the equalized signal in horizontal and vertical domain. In this thesis work a CTLE with two degrees of freedom with an EOM based adaptation system has been implemented.
Keywords
Inter-symbol interference , Adaptive Equalizer, Eye opening monitor, Receiver, Continuous time linear equalizer.
Language
English
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Number of Pages 81 Type of Publication Licentiate thesis Degree thesis Thesis C-level Thesis D-level Report
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ISBN (Licentiate thesis)
ISRN:LiTH-ISY-EX--13/4732--SE
Title of series (Licentiate thesis) Series number/ISSN (Licentiate thesis)
Linköping University Electronic Press
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Firstly I would like to thank God Almighty for his grace and blessings throughout the tenure of my studies.
I would like to thank my supervisor Dipl.-Ing. Conrad Zerna and Fraunhofer IIS for this wonderful thesis opportunity. His guidance, inspiration and constructive criticism have been the main driving force for successful completion of this thesis work. I would like to thank him for all the time he has spent with me between his busy schedules.
I would also like to extend my sincere thanks to Dr. Jacob Wikner, for his support and advice throughout the course of the project. It is an honour for me to have him as my supervisor.
Finally, I would like to express my gratitude to all my friends and family for their support during my studies at Linkoping University.
Abstract
In modern day communication systems, there is a constant demand for increase in trans-mission rates. This is however limited by the bandwidth of the channel. Inter symbol interference (ISI) imposes a great threat to increasing data rates by degrading the signal quality. Equalizers are used at the receiver to compensate for the losses in the channel and thereby greatly mitigate ISI. Further an adaptive equalizer is desired which can be used over a channel whose response is unknown or is time-varying.
A low power equalizing solution in a moderately attenuated channel is an analog peaking filter which boosts the signal high frequency components. Such conventional con-tinuous time linear equalizers (CTLE) provide a single degree of controllability over the high frequency boost. A more complex CTLE has been designed which has two degrees of freedom by controlling the high frequency boost as well as the range of frequencies over which the boost is applied. This extra degree of controllability over the equalizer response is desired to better adapt to the varying channel response and result in an equalized signal with a wider eye opening.
A robust adaptation technique is necessary to tune the equalizer characteristics. Some of the commonly used techniques for adaptation of CTLEs are based on energy comparison criterion in the frequency domain. But the adaptation achieved using these techniques might not be optimal especially for an equalizer with two degrees of controllability. In such cases an eye opening monitor (EOM) could be used which evaluates the actual signal quality in time domain. The EOM gives an estimate on the signal quality by measuring the eye opening of the equalized signal in horizontal and vertical domain. In this thesis work a CTLE with two degrees of freedom with an EOM based adaptation system has been implemented.
Acknowledgement v Abstract vi 1 Introduction 1 1.1 Motivation . . . 1 1.2 Thesis Objective . . . 3 1.3 Thesis Organization . . . 3
2 Continuous time linear Equalizers 5 2.1 Basics of Equalization . . . 5
2.2 CTLE Target specification . . . 9
2.3 Selected CTLE Architectures . . . 9
2.3.1 Equalizer-I . . . 9
2.3.2 Equalizer-II . . . 12
2.3.3 Equalizer-III . . . 14
3 Equalizer adaptation techniques 18 3.1 Least mean square adaptation . . . 18
3.2 Non data aided techniques . . . 19
3.2.1 Conventional continuous time adaptation technique . . . 19
3.2.2 Spectrum balancing technique . . . 20
3.3 Eye opening monitor for adaptive equalization . . . 22
4 Eye Opening Monitor 24 4.1 EOM principle of operation . . . 24
4.2 EOM architecture . . . 26
Chapter0 CONTENTS 4.2.2 CML latch . . . 28 4.2.3 DC offset . . . 29 4.2.3.1 Offset simulation . . . 30 4.2.3.2 Offset compensation . . . 30 4.2.3.3 Offset deviation . . . 33
4.2.4 CML latch kickback noise . . . 33
4.2.5 Synchronization Unit . . . 34
4.2.6 Clock Data Recovery . . . 34
5 Adaptation Controller 37 5.1 Algorithm for Equalizers-I and II . . . 38
5.2 Algorithm for Equalizer-III . . . 38
6 Layout and Simulation Results 43 6.1 Data Generation and Channel modeling . . . 43
6.1.1 Data Generation . . . 43
6.1.2 Channel Modeling . . . 44
6.2 Equalizer layout and results . . . 45
6.2.1 Equalizer-I . . . 45
6.2.2 Equalizer-II . . . 45
6.2.3 Equalizer-III . . . 47
6.3 EOM layout and results . . . 48
6.4 Equalizer with adaptation system results . . . 54
7 Conclusion 58 7.1 Future work . . . 59
A Appendix 61 A.1 Cadence SKILL code for Eye-width measurement . . . 61
A.2 Eye width values . . . 64
2.1 CTLE target specification . . . 9 5.1 Adaptation algorithm control parameters for equalizers-I & II . . . 39 6.1 Characteristics of channel models used for simulation . . . 44 6.2 Simulation results over corner variations for equalizer-I with digitally
tun-able source degeneration capacitance . . . 47 6.3 Simulation results over corner variations for equalizer-II with source
de-generation MOS resistor . . . 49 6.4 Simulation results over corner variations for equalizer-III with two parallel
input source degeneration stages . . . 49 6.5 Simulation results over corner variations for fully differential difference
amplifier . . . 51 6.6 Simulation results over corner variations for CML Latch . . . 53 A.2 Eye width values measured at 150mV reference level over corner variations
for equalizer-III with corresponding control settings . . . 65 A.4 Eye width values measured at 150mV reference level over corner variations
for equalizer-II with corresponding control settings . . . 66 A.6 Eye width values measured at 150mV reference level over corner variations
List of Figures
1.1 Basic communication system . . . 1 1.2 Channel-Equalizer frequency response . . . 2 2.1 Effect of eye-closure due to over-compensation and under-compensation . . 6 2.2 Conventional source degenerated differential pair equalizer structure . . . . 8 2.3 Frequency response of first order CTLE . . . 8 2.4 Schematic of equalizer-I with digitally tunable source degeneration capacitor 10 2.5 Frequency response of equalizer-I for different degeneration capacitance
settings (Cs) . . . 11 2.6 Schematic of equalizer-II with source degeneration MOS resistor . . . 12 2.7 Frequency response of equalizer-II for different degeneration resistance
settings (Vctrl) . . . 13 2.8 Schematic of equalizer-III with two parallel input source degenerated
dif-ferential pair stages . . . 15 2.9 Equalizer-III frequency response for different degeneration capacitance
settings (<Bi> sweep) of both stages . . . 16
2.10 Equalizer-III frequency response for different degeneration resistance set-tings (Vctrl sweep) of stage2 . . . 17 3.1 Block diagram of conventional continuous time adaptation technique . . . . 20 3.2 Effect of under-equalization and over-equalization on spectrum of NRZ
coded ideal random binary sequence [1] . . . 21 3.3 Block diagram of spectrum balancing equalization technique . . . 21 3.4 Difference in eye diagram of signal with and without ISI . . . 22 4.1 Mask error detection in a two dimensional EOM with rectangular mask . . 25 4.2 Architecture of the two dimensional EOM designed . . . 27
4.3 Schematic of the fully differential difference amplifier used for reference
subtraction . . . 28
4.4 Schematic of CML latch . . . 29
4.5 Offset simulation technique used to measure the input referred offset volt-age of the latched comparator . . . 31
4.6 Module for combined offset compensation of latched comparator . . . 32
4.7 Offset voltage deviation with temperature drift after calibration at 25oC . . 33
4.8 Neutralization technique for CML latch kickback noise reduction . . . 34
4.9 Synchronization unit block diagram and timing . . . 35
4.10 CDR block diagram . . . 35
5.1 Block diagram of equalizer adaptation system . . . 37
5.2 Surface plot of eye-width measured at 150mV reference level for equalizer-III control setting sweep . . . 40
5.3 Flowchart of algorithm used for adaptation of Equalizer-III . . . 41
6.1 Block diagram of LFSR used to generate PRBS-7 . . . 44
6.2 Simulation testbench setup block diagram . . . 44
6.3 Layout of equalizer-I . . . 45
6.4 Frequency response of equalizer-I over channel models for control setting yielding the widest eye opening . . . 46
6.5 Layout of equalizer-II . . . 48
6.6 Frequency response of equalizer-II over channel models for control setting yielding the widest eye opening . . . 50
6.7 Layout of equalizer-III . . . 51
6.8 Frequency response of equalizer-III over channel models for control setting yielding the widest eye opening . . . 52
6.9 Layout of fully differential difference amplifier . . . 53
6.10 Layout of CML latch . . . 54
6.11 Eye width comparison for each equalizer on different channels with and without the adaptation algorithm for typical corner . . . 55
6.12 Eye width comparison for each equalizer on different channels with and without the adaptation algorithm for fast corner . . . 56
6.13 Eye width comparison for each equalizer on different channels with and without the adaptation algorithm for slow corner . . . 56
Chapter 1
Introduction
In modern day broadband communication systems a major bottleneck in increasing data-rates is imposed by the bandwidth limitation of transmission channels. A basic data com-munication system consists of 3 blocks namely, the transmitter, channel and receiver as shown in figure 1.1. A fundamental issue that needs to be addressed in such systems is the frequency dependent attenuation experienced by a signal which is transmitted through a bandwidth limited channel. Such losses distort the signal and hinder proper data recovery at the receiver.
1.1
Motivation
In high speed digital communication, inter-symbol interference(ISI) plays a crucial role in degrading the bit error rate (BER) for multi-gigabit transmission. ISI is a form of distortion of a signal in which one symbol interferes with the subsequent symbols. Many practical channels have a low-pass behavior and are bandwidth-limited due to inherent losses in the channel. For example, in electrical channels like unshielded twisted pair(UTP) cables, shielded twisted pair (STP) cables and coaxial cables, the main contribution to bandwidth limitation is caused by skin effect and dielectric losses[2]. Skin effect is the phenomenon
Figure 1.2: Channel-Equalizer frequency response
in which the induced magnetic field in an electrical channel when a high frequency signal passes through it causes the current to flow through the surface of the conductor and current density decreases exponentially towards the interior. Dielectric loss is the loss of electromagnetic power (e.g. in the form of heat) due to the non-ideal characteristics of the dielectric material during electromagnetic wave propagation. The bandwidth limitation of the channel due to these losses causes ISI. Another dominant source of ISI is multi-path propagation, where the transmitted signal reaches the receiver through different paths with different delays. An example for this is the modal dispersion occurring in multi-mode fiber (MMF), where the signal is spread in time since the different components of the signal arrive at different times.
Equalizers provide a simple and cheap solution to compensate for the loses due to ISI imposed by the channel in a communication system and facilitate error free data recovery. The equalizer is ideally supposed to provide the inverse frequency response of the chan-nel such that the chanchan-nel-equalizer combination achieves a flat frequency response up-to Nyquist frequency as shown in figure 1.2.
The channel characteristics are subject to variations due to various factors like temper-ature, material properties etc, which are discussed in detail in Chapter 2. So it is desired to have an equalizer whose properties can also be varied/adapted to compensate for the changing channel response. Such an adaptive equalizer is preferred also because it can be used over a wide range of channel types and lengths.
Chapter1 1.2. THESIS OBJECTIVE
Many techniques exist for the adaptation of equalizer characteristics. The principle behind the operation of these techniques is to generate an error signal that is related to the signal quality and try to tune the equalizer transfer function so as to minimize this error. Some of these techniques evaluate the signal quality in frequency domain and some others in time domain. A study on the various architectures is done and one of them has been selected for implementation in this work. The results of the work focus on how well the adaptation circuit performs in tuning the equalizer to a setting which yields the best signal quality over various channel models.
1.2
Thesis Objective
The objectives of this thesis are as follows:
• Investigate different architectures of continuous time linear equalizers
• Implement an Eye diagram monitoring circuit, which provides information on the received signal quality
• Develop an iterative algorithm to set the equalizer characteristics using the informa-tion from the eye diagram monitor
The ultimate goal of this work is to study how well a two dimensional eye opening monitor based adaptation system can perform in adapting a continuous time linear equalizer to a setting were inter symbol interference is minimal. Different equalizer architectures will be used for this purpose. The results discussed in this thesis focus on this goal.
1.3
Thesis Organization
The thesis is organized into the following chapters:
• Chapter 2 gives a background to the equalization techniques and further discusses the CTLE architectures that have been implemented in this work.
• Chapter 3 gives an overview of the various adaptation techniques that can be used with CTLE.
• In Chapter 4 the basic operation principle and architecture of the eye-opening mon-itor (EOM) built in this work is discussed. It also elaborates on the various design considerations for the EOM.
• Chapter 5 discusses the operation of the adaptation algorithm used for each equalizer designed.
• Chapter 6 deals with the layout and results of the equalizer and the EOM. Towards the end a comparison on the performance of the EOM with the adaptation algorithm on each equalizer is made.
• Finally, Chapter 7 concludes the thesis work and also gives proposals for future work. In the appendix section, cadence SKILL codes developed to extract some of the results have been provided.
Chapter 2
Continuous time linear Equalizers
Equalizers are used to combat the distortion in the signal caused by inter-symbol interfer-ence (ISI). Many variants of the equalizers exist based on the application. They can be at the transmitter and/or receiver, can be linear or non-linear, can be continuous time or discrete time. Our goal is to build a continuous time linear equalizer which can provide effective equalization over a wide range of mildly attenuated channels for which different architectures have be analyzed. This chapter introduces the concept of equalization and different types of equalizers. Further, few of the continuous time linear equalizer (CTLE) architectures selected in this work are discussed and compared.
2.1
Basics of Equalization
Equalizers try to undo the effect of ISI by providing the inverse frequency response of the channel in-order to compensate for the bandwidth limitation of the channel due to various losses. In reality, the exact characteristics of the channel are not known in advance and they are also susceptible to huge variations due to factors like temperature, material properties, length of channel and other effects like bends, connectors etc. It is desired to have an equalizer that can be used with a wide range of channels (e.g. copper, optical fiber) and channel lengths. Therefore, an adaptive equalizer is required to compensate for the variations in the channel characteristics. An adaptive equalizer is also necessary to avoid over-compensation or under-compensation of the system. Figure 2.1 shows the effect of over-compensation and under-compensation on the signal in time-domain. It can be noticed that both result in the reducing the effective symbol period or in other words
Figure 2.1: Effect of eye-closure due to over-compensation and under-compensation
reduce the eye width. This effect can be used to estimate the quality of the signal.
Channel equalizers can be implemented at the transmitter end and/or the receiver end. Transmitter equalizers (pre-emphasis) are relatively simpler when compared to receiver ones in terms of complexity of implementation. They amplify the high frequency compo-nents of the signal in advance to compensate for the losses in the channel. The attraction of using this technique is that it does not amplify any noise which will be added to the signal during transmission. But this technique also has some serious disadvantages such as, adaptation of such equalizers require back-channel (feedback from receiver to transmitter) mechanism which can be very complex and difficult to implement. Transmitter equalizers can also contribute to cross-talk with neighboring transmission lines in a parallel link due to the strength of the high frequency components. Hence, transmitter equalizers are often used in combination with receiver equalizers.
Receiver equalizers provide easier adaptability to channels especially when the re-sponse is unknown or varies with time. A problem with using receiver equalizers is that it amplifies in-band channel noise, but in cases where the SNR of the received signal is not bad, ISI imposes a greater threat to the quality of the signal than the noise.
Receiver equalization approaches can be classified into linear and non-linear equaliza-tion. Linear equalizers have finite impulse response and non-linear equalizers have infinite impulse response. Linear equalizers have a feed forward structure, where the equalized data is not fed-back to adapt the equalizer. Whereas in non-linear equalization, the equalized
Chapter2 2.1. BASICS OF EQUALIZATION
data is fed-back to change the subsequent outputs of the equalizer. Non-linear equalizers are mainly used in cases where the channel distortion is too severe where they are often combined with linear equalizers so as to zero out the residual ISI at the output of the linear equalizer.
Linear equalizers can be further classified into: • Discrete time equalizer
• Continuous time equalizer
Discrete time equalizers which are based on FIR filter structures, require clocks recov-ered from the received data. This creates a cross dependency between the equalizer and the CDR (clock-data recovery) unit. These equalizers are normally power hungry and their power consumption increases drastically with increase in data rates due to the large number of taps in the FIR filters. Continuous time equalizers on the other hand consume less power and area, mainly due to their simple structure. They normally do not require sampling clocks but the re-timing of the signal for data recovery needs a sampling clock. The adaptation system might require a sampling clock based on the architecture used. In this work, we choose to build an adaptive continuous time linear equalizer (CTLE) whose response can be controlled by an adaptation loop such that effective equalization can be achieved for a channel whose response is unknown or time varying.
Many CTLEs are based on the conventional source degenerated differential pair struc-ture shown in figure 2.2 [3, 4, 5, 6]. The transfer function for this circuit is given by equation (2.1), where gm is the transconductance of the input transistors, RLand CL are
the load resistance and capacitance, RSand CS are the source degeneration resistance and
capacitance. This system has two poles and a zero. The zero provides a +20dB/decade slope and each pole provides -20dB/decade as shown in figure 2.3. The basic requirement of such an equalizer is to provide a high frequency boost whose peak can be controlled. This is done by tuning the zero of the system. By changing the degeneration capacitance (CS) the zero of the system can be moved thereby varying the high frequency boost. The
zero can also be tuned by varying the degeneration resistance (RS), but this also changes
the DC gain of the system.
A(s) = gmRL 1 + gmRS/2 ∗ 1 + sRSCS (1 + sRLCL) 1 + sRSCS 1 + gmRS/2 (2.1)
Vout Vin RL RS CS RL
Figure 2.2: Conventional source degenerated differential pair equalizer structure
ωZ ωP1 ωP2 A0 A0 * ωP1 ωZ Gain (dB) Frequency +20dB/Dec -20dB/Dec
Figure 2.3: Frequency response of first order CTLE
Many variants based on the above concept of the source degenerated differential pair equalizer exist. In this work, three equalizer architectures have been implement and their performance have been studied. This is discussed in detail in the following sections. Table 2.1 gives the target specifications of the CTLE to be built.
Chapter2 2.2. CTLE TARGET SPECIFICATION
2.2
CTLE Target specification
Parameter Value
Technology 65nm
Supply voltage 1.05 - 1.35 V
Sampling frequency 3 GHz
Min high frequency boost 0 dB
Max high frequency boost ~ 30dB (for given channel models) @ ~1.5GHz
DC gain 0 dB
Input common mode voltage 0.7875 - 1.012 V Output common mode voltage 0.7875 - 1.012 V
Table 2.1: CTLE target specification
2.3
Selected CTLE Architectures
Three CTLE architectures based on the source degenerated differential pair structure were selected for implementation in this work and their performance was compared. They are:
• Equalizer-I: With digitally tunable source degeneration capacitors
• Equalizer-II: With voltage controlled NMOS source degeneration resistance • Equalizer-III: Consists of two capacitively coupled parallel input stages
Equalizers I and II provide one degree of controllability over the high frequency boost whereas equalizer-III has two degrees of freedom for controlling the high frequency boost as well as the range of frequencies that are boosted. The design and operation of the equalizers are discussed in detail in the following sections.
2.3.1
Equalizer-I
In this architecture the degeneration capacitor (CS) is replaced by a digitally tunable
Vout Vin RL RS RL CS 2CS 4CS B0 B1 B2
Figure 2.4: Schematic of equalizer-I with digitally tunable source degeneration capacitor
the capacitor array consists of 3 parallel capacitors with each of them being digitally con-trolled by NMOS switches. Two switches have been placed on each side of the capacitor to ensure symmetry. The capacitance value is controlled by 3 binary bits <b2,b1,b0> which
are connected to the gates of the NMOS switches. Since we use binary coding for the control bits, the capacitor values should be in a geometric progression with common ratio 2. This results in 8 different possible linear settings for the degeneration capacitance.
The zero frequency of the system can be reduced by increasing the source degeneration capacitance thereby resulting in an increase in the high frequency boost. With 3 parallel stages of capacitors we can have 8 different settings for the high frequency boost. More parallel capacitor stages can be added to increase the granularity of the change in the capacitance value. The bias current for the equalizing filter is generated from an external biasing circuit which is not shown here.
Another feasible alternative that is commonly used to realize a variable capacitor is the MOS gate-bulk capacitor, where the source, drain and bulk of two transistors are shorted and the capacitance between the gates of the two transistors are controlled by a voltage connected to the bulk of the transistors. This technique was not an attractive option for this work as it was difficult to realize very low capacitance (~0 F) which was necessary to have zero or no high frequency boost. Hence digitally tunable capacitors have been used with
Chapter2 2.3. SELECTED CTLE ARCHITECTURES v (/outp /outn); ac dB20(V) v (/outp /outn); ac dB20(V) 0 v (/outp /outn); ac dB20(V) 1 v (/outp /outn); ac dB20(V) 2 v (/outp /outn); ac dB20(V) 3 v (/outp /outn); ac dB20(V) 4 v (/outp /outn); ac dB20(V) 5 v (/outp /outn); ac dB20(V) 6 v (/outp /outn); ac dB20(V) 7 -20.0 0.0 -30.0 10.0 -10.0 20.0 V ( dB ) Name Vis a 109 107 1011 freq (Hz) 10 10 105 106 108 104 AC Response
Figure 2.5: Frequency response of equalizer-I for different degeneration capacitance set-tings (Cs)
which zero peaking can be achieved by switching off all the NMOS switches.
The maximum high frequency gain that can be achieved with this circuit cannot exceed the DC gain of a non-degenerated differential pair. Hence multiple cascade stages of this equalizer have to be used to meet the maximum relative peaking requirements. Three cas-cade stages were used to get the necessary equalization for the channel models in this work. Figure 2.5 shows the frequency response of equalizer-I for different capacitor values. It can be noticed that increasing the capacitor values results in increased high frequency boost but the peaking frequency also gets shifted. This is because changing CS also results
in the shifting of one of the poles of the system, which is a drawback of this equalizer. The MOS switches have also been sized in a geometric progression as the capacitors, such that the effects due to parasitics and their ON resistance also get doubled for each parallel stage. This has been done to ensure a linear increase in the total capacitance and thereby the high frequency boost when sweeping the control bits.
V
outV
inR
LR
LCS Vctrl
Figure 2.6: Schematic of equalizer-II with source degeneration MOS resistor
2.3.2
Equalizer-II
The max high frequency boost that could be achieved with equalizer-I was not sufficient, so a modification to the architecture was made by controlling the source degeneration resistance (RS) instead of the capacitance (CS). A MOS resistor is used to realize the
variable resistor whose resistance is controlled by varying the gate voltage. Figure 2.6 shows the schematic of equalizer-II. The source degeneration capacitance is fixed.
It can be seen from equation 2.1 that varying RS moves the zero of the system. But
the gain and the zero are tightly coupled i.e., varying RS also changes the DC gain of the
system. This architecture takes advantage of this property in order to get more relative peaking. Increasing RS decreases the zero frequency as well as reduces the DC gain of
the filter. We are more interested in the high frequency boost relative to the DC gain, so decreasing the DC gain also increases the relative boost achieved. An issue with this technique is that the DC gain could drop below one (A0<1). But this loss could be
compen-sated using limiting amplifier stages after the equalizing filter to ensure A0>=1 over PVT
variations. The maximum attenuation of the signal at the input to the limiting amplifier is limited by the SNR of the equalized signal and offset of the limiting amplifier. Attenuation beyond these levels increases the BER of the system. So in-order to achieve a peaking beyond this limit, multiple stages of the equalizer could be used. In this work, we have
Chapter2 2.3. SELECTED CTLE ARCHITECTURES ...p /outn); ac dB20(V) ...p /outn); ac dB20(V) -0.18 ...p /outn); ac dB20(V) -0.17 ...p /outn); ac dB20(V) -0.16 ...p /outn); ac dB20(V) -0.15 ...p /outn); ac dB20(V) -0.14 ...p /outn); ac dB20(V) -0.13 ...p /outn); ac dB20(V) -0.12 ...p /outn); ac dB20(V) -0.11 ...p /outn); ac dB20(V) -0.1 ...p /outn); ac dB20(V) -0.09 ...p /outn); ac dB20(V) -0.08 ...p /outn); ac dB20(V) -0.07 ...p /outn); ac dB20(V) -0.06 ...p /outn); ac dB20(V) -0.05 ...p /outn); ac dB20(V) -0.04 ...p /outn); ac dB20(V) -0.03 ...p /outn); ac dB20(V) -0.02 ...p /outn); ac dB20(V) -0.01 10.0 20.0 -10.0 V ( dB ) -30.0 -20.0 0.0 30.0 Name Vis V_ctrl_R 106 104 105 109 freq (Hz) 10 10 1011 107 108 AC Response
Figure 2.7: Frequency response of equalizer-II for different degeneration resistance settings (Vctrl)
used 2 stages of the equalizer which creates a 40dB/decade slope.
The voltage controlling the resistance of the NMOS transistor is generated from a DAC. Each DAC setting corresponds to a different resistance value, so the peaking of the equalizer is adjusted by controlling the DAC input. Fine variations to the peaking can be made using smaller step size for the control voltage change which requires a fine resolution DAC. Figure 2.7 shows the frequency response of equalizer-II for different control voltage settings. A step size of 10mV is used here over a range of 200mV which needs a 5-bit DAC. The DAC has not been implemented as it is not the focus of this work and hence stays as behavioral model.
Equalizer-I and equalizer-II have similar structures but different control variables. Equalizer-II could be used achieve higher relative peaking when compared to equalizer-I. Also unlike equalizer-I, in equalizer-II changing the control variable (RS) resulted in
dif-ferent peaking at the same peak frequency. This is because changing RSdoes not move the
pole frequency too much due to the presence of the RS term in the numerator and
2.3.3
Equalizer-III
Equalizers-I and II have only one degree of freedom and the controllability was limited to the high frequency boost. There was no control over the shape/width of the peak. To better adapt to the different channel models which have different responses(roll-off slopes), it is desired to have more controllability on the equalizer response which controls the width of the peak without affecting the peak gain.
In this architecture, two stages of the source degenerated differential pair with parallel input stages and capacitively coupled output stages are used. The structure is similar to the first equalizing stage used in [7]. The equalizer architecture proposed in this work is shown in figure 2.8. Stage-2 has a variable MOS degeneration resistor to control the high frequency boost. Both stages of the equalizer have a 4 stage digitally tunable source degeneration capacitance with common control bits , <B0,B1,B2,B3>. In this way the high
frequency boost of the 2 stages can be increased evenly. Similar to equalizer-I, binary control bits bits are used and hence the capacitor values for each parallel stage is double that of the succeeding stage.
The output of the equalizer is taken from stage-1 and stage-2 is capacitively coupled the output. The transfer function for the circuit has been derived and is given by equa-tion 2.2, where gm1and gm2 are the transconductance of the input transistor of stages 1
and 2 respectively. The pole and zero positions can be moved by varying the degeneration capacitance CS1and CS2 of stages 1 and 2 and the degeneration resistance (RS2) of stage
2. We have gm2> gm1; RL1>RL2; with strong coupling so that stage-2 dominates stage-1 at
higher frequencies when coupling capacitor Cc couples together the outputs of the parallel
input stages. Additional poles and zeroes are added to the system. Since pole-zero analysis with this equation is extremely complex, a simpler approach to understand the behavior of the circuit is required, which is described as follows:
A(s) = gm1RL1 1 + gm1RS1/2 ∗ 1 + sRS1CS1 (1 + sRL1CL1) 1 + sRS1CS1 1 + gm1RS1/2 ∗ 1 + sRL2(CL2+CCX) 1 + s [RL2CL2+CC(RL1+ RL2)Y ] (2.2)
Chapter2 2.3. SELECTED CTLE ARCHITECTURES Vin RL Vctrl RL Vout Vin RL RS RL Cc Cc CS 2CS 4CS 8CS CS 2CS 4CS 8CS B0 B1 B2 B3 Stage1 Stage2
Figure 2.8: Schematic of equalizer-III with two parallel input source degenerated differen-tial pair stages
X = 1 + gm2(1 + gm1RS1) gm1(1 + gm2RS2) ∗ (1 + sRS2CS2) 1 + sRS1CS1 1 + gm1RS1/2 (1 + sRS1CS1) 1 + sRS2CS2 1 + gm2RS2/2 (2.3) Y = 1 + sRL1RL2(CL1+CL2) RL1+ RL2 1 + sRL1CL1 (2.4)
• At low frequencies stage-2 is completely isolated from the circuit due to the coupling capacitor CC; so the low frequency gain of the equalizer is set by stage-1 alone.
• At higher frequencies, coupling capacitor CC can be considered as a short, and the
extra transconductance of the stage-2 is added to that of stage-1.
• Varying the source degeneration capacitance of both stages equally results in differ-ent peak gain for the equalizer whilst not changing the low frequency gain.
Name Vis B ac ac 0 ac 1 ac 2 ac 3 ac 4 ac 5 ac 6 ac 7 ac 8 ac 9 ac 10 ac 11 ac 12 ac 13 ac 14 ac 15 40.0 V ( dB ) -10.0 0.0 10.0 20.0 30.0 freq (Hz) 10 10 105 106 107 108 109 ac
Figure 2.9: Equalizer-III frequency response for different degeneration capacitance settings (<Bi> sweep) of both stages
• Varying the degeneration resistance of stage-2 (RS2) moves the zero and also changes
the DC gain of stage-2. But the effect of these changes reflects only in the high frequency region of the equalizer response due to the coupling capacitor. This results in different peaking responses with different peak widths (in other words peaking over a wider frequency range) while the low frequency gain of the equalizer remains unchanged.
• The degeneration resistance of stage-1 is kept fixed so that the low frequency gain of the equalizer remains unchanged for all control settings unlike equalizer-II where the different control settings have different DC gains.
This equalizer inherits the main advantages of equalizer-I and equalizer-II by con-trolling the high frequency boost of the 2 stages using variable degeneration capacitance and resistance and combines it with the coupling of 2 stages. Equalizer-III provides two degrees of freedom for better adaptability to a wide range of channels. The high frequency boost can be controlled with the bits <B0,B1,B2,B3> connected to the digitally tunable
capacitors as shown in figure 2.9. Width of the peak can be controlled by varying the degeneration resistance of stage-2 using a control voltage generated from a DAC as shown in figure 2.10. Both these controls are independent of each other.
Chapter2 2.3. SELECTED CTLE ARCHITECTURES ac ac -0.24 ac -0.22 ac -0.2 ac -0.18 ac -0.16 ac -0.14 ac -0.12 ac -0.1 ac -0.08 ac -0.06 ac -0.04 V ( dB ) 0.0 10.0 20.0 30.0 40.0 Name Vis V_ctrl_R 1010 1011 freq (Hz) 104 105 106 107 108 109 ac
Figure 2.10: Equalizer-III frequency response for different degeneration resistance settings (Vctrl sweep) of stage2
The required high frequency boost for the given channel models is achieved by cascad-ing two stages of the equalizer followed by limitcascad-ing amplifiers such that the low frequency gain is greater than one (A0>=1) over corners.
Three different architectures of the continuous time linear equalizer have been analyzed and implemented in this work. Equalizer-I and II provide controllability over the high fre-quency boost whereas equalizer-III provides controllability over the high frefre-quency boost as well as the peak width. The extra degree of freedom in equalizer-III comes at the ex-pense of additional hardware. The simulation results for the equalizers are discussed in chapter 6.
Equalizer adaptation techniques
It is desired to have an adaptive equalizer for various reasons discussed in Chapter 2. In order to tune the equalizer to its best setting so as to get the right amount of equalization, an error signal related to the quality of the received data must be generated. The adapta-tion technique used tries to set the equalizer to a value which minimizes this error. Many different adaptation techniques exist, some of which work in the frequency domain by com-paring energies or in time domain by measuring the eye-opening. Some of the mainly used adaptation techniques for linear equalizers are discussed in this chapter.
3.1
Least mean square adaptation
Least mean square (LMS) adaptation is one of the many adaptation techniques used with discrete time equalizers to tune the equalizing filter taps. The aim is to minimize the mean square error J, where In is the transmitted symbol and zn is the sampled output of
the equalizer shown in equation 3.1. The error en represents a discrepancy between the
transmitted and the received symbol. The necessity of the transmitted symbol In to be
known at the receiver makes this technique to be used with known training sequences. Another alternative is to use the receivers estimate of the transmitted symbol, but this is often used after the training sequence. In this way any slight variations in the channel can be adapted.
en = In− zn (3.1)
Chapter3 3.2. NON DATA AIDED TECHNIQUES
The main drawback of this technique is that the error (en) is a function of the decision
made by the adaptation technique itself at the receiver. This cross dependency might cause convergence issues when the bit error rate (BER) is high.
LMS adaptation can also be used for certain complex continuous time structures, like the “complex graphic equalizer” consisting of a summation of several bandpass filters cov-ering different frequency bands whose outputs are weighted by a complex coefficient and summed, as demonstrated in [1]. But this technique cannot be used on continuous time equalizer structures chosen for implementation in this work. The other popular adaptation techniques for continuous time equalizers are discussed below.
3.2
Non data aided techniques
Some of the popular adaptation techniques for CTLEs are based on comparison of signal energies. The main attraction of using such a technique is that it does not require a sampling clock (with very accurate phase), as they use continuous time analog circuits to compare the signal in frequency domain. Some of the common architectures using this technique are discussed below.
3.2.1
Conventional continuous time adaptation technique
This approach compares the high frequency signal components (slope of the data tran-sitions) of the equalizer output and the slicer output [8]. When equalized correctly the waveforms at the input and output of the slicer should have the same transition energies which is the high frequency part of the spectrum. The error between the transition energies at the input and output of the slicer can be used to tune the equalizer high frequency boost. The block diagram for this technique is shown in figure 3.1.
A drawback of this technique is that when the amplitude of the signal at the input and the output of the slicer is different, the comparison of their high frequency energies will generate an error. But this is not desired as it would result in an incorrect equalizer setting. Advanced techniques to control the swing of the slicer by comparing the low frequency energies also exist as shown in [9].
Figure 3.1: Block diagram of conventional continuous time adaptation technique
3.2.2
Spectrum balancing technique
Consider a random binary sequence with NRZ code whose spectrum is shown in figure 3.2. A frequency can be chosen based on the data transmitted such that it divides the spectrum into two parts with equal powers. The spectrum balancing techniques works by comparing the powers of the low frequency and high frequency band (divided by a known frequency). The equalizer high frequency boost is set such that the error between the two powers is minimum. Figure 3.2 also shows the effect of having unequal powers in the two bands, which result in under equalization or over equalization.
Figure 3.3 shows the block diagram of the spectrum balancing technique. One issue to be addressed in this method is that the data transmitted need not be ideal random binary sequence. It may contain large amount of low frequency content which might result in under or over-compensation. To overcome this, advanced techniques to adaptively select the frequency that splits the spectrum into two parts need to be used [10]. Another possible alternative to this is the use of line codes.
All these non data aided techniques which compare the power in frequency domain have some drawbacks. The aim is to have the biggest possible eye opening after equalization which can be obtained by having a flat response until the Nyquist frequency. But, there could be multiple responses corresponding to different equalizer settings which have same
Chapter3 3.2. NON DATA AIDED TECHNIQUES
Figure 3.2: Effect of under-equalization and over-equalization on spectrum of NRZ coded ideal random binary sequence [1]
Name ... 15n 60n 1/VAR("fbaud") ) -400.0 -300.0 400.0 V ( m V ) 100.0 200.0 300.0 -200.0 -100.0 0.0 time (ps) 150.0 200.0 0.0 50.0 100.0 250.0 300.0 350.0 eyeDiagra...aud") )
(a) Unequalized eye
... 15n 60n 2/VAR("fbaud") ) V ( m V ) -750.0 -500.0 -250.0 0.0 250.0 500.0 750.0 Name 700.0 time (ps) 0.0 100.0 200.0 300.0 400.0 500.0 600.0 eyeDiagra...aud") ) (b) Equalized eye Figure 3.4: Difference in eye diagram of signal with and without ISI
powers in the high frequency part. In such cases, it is highly probable that the adaptation loop would set the equalizer to a value which need not be the best possible that can be achieved using the equalizer. The decision made by these techniques also involves the non ideal behaviors of the devices like rectifiers, integrators and band-pass or high-pass filters which have a small linear input range when working at GHz range. Thus the resulting equalizer adaptation using these techniques might not be optimal.
3.3
Eye opening monitor for adaptive equalization
The Eye Opening Monitor(EOM) gives a quantitative measure of the equalized signal eye diagram in time domain. Eye diagram or eye pattern is generated by dividing the signal into frames where each has a length of an integer multiple of the symbol period. Then all the frames are overlapped to create a single diagram with one/two frame length that contains several traces of the signal. The shape of the eye diagram and the received signal quality are highly correlated. This information regarding the signal quality can be extracted from the eye diagram using an EOM and used for adaptive equalization.
The distortion of the signal due to ISI causes closure of the eye diagram. Figure 3.4 shows the eye diagram of an unequalized signal and an equalized signal. EOM captures the information regarding signal quality by sampling the signal and analyzing its charac-teristics in time domain. For channels where ISI not very severe (e.g. Short channels), the
Chapter3 3.3. EYE OPENING MONITOR FOR ADAPTIVE EQUALIZATION
received signal will have open eyes. In these cases a comparison on the signal quality with different signals corresponding to different equalizer settings can be made by measuring the eye opening in vertical and horizontal dimensions.
The EOM generates an error signal related to the quality of the eye diagram. This error information is passed on to an adaptation algorithm which tunes the equalizer. The tuning of the equalizer is only based on the equalized signal eye opening. This is useful when there are no training sequences used and when BER is high.
EOMs can be classified into the following [11]:
• One dimensional EOM: They measure either the vertical or the horizontal opening of the eye. These are simple in configuration and low in power consumption but do not provide a good picture of the quality of eye.
• Two dimensional EOM: Quantifies the signal quality by measuring the vertical and horizontal eye opening. They consume moderate hardware and power. The signal is sampled at different points within a single sample period and any mismatch in the sampled data is considered as a violation. They usually consist of latched compara-tors, DACs and phase interpolators [12].
• Data edge based EOM: Quantifies the signal quality by examining the edges of data using multiple samples. The edge information of the data eye is extracted by sam-pling the data transition using many samplers. XOR gates and counters are used to record the number of transitions at each sampling point. An histogram based on this is generated which gives an idea of the quality of the signal.
• Multi-Sampling EOM: Here the data eye is scanned using large number of samples per sample period at various points horizontally and vertically. This method requires multiple sampling clocks and high precision phase shifters and hence is very power hungry. The sampling point with maximum eye-opening margin is used for data recovery.
The various advantages of evaluating the actual signal quality in time domain makes eye-opening monitors a very attractive technique for equalizer adaptation. From the different types of EOMs discussed, two dimensional EOM provides a good balance between cost and efficiency. In this work we have implemented a two dimensional EOM for adaptive equalization which is discussed in chapter 4.
Eye Opening Monitor
A two dimensional Eye Opening Monitor (EOM) based adaptation technique has been implemented in this work. The EOM evaluates the signal quality by making periodic observations of the equalized signal in time domain. This is done by sampling the signal at different points within a symbol and compare theses data to measure the eye-opening. A two dimensional EOM measures the eye-opening in horizontal and vertical domain. This needs the signal to be sampled at at-least 4 points within a symbol. Also these sampling points have to be movable in both the dimensions.
In this chapter we discuss the architecture and implementation of the EOM which acts as a ’sense unit’ in the adaptation system by extracting information regarding quality of the signal. The EOM is enabled by the adaptation controller which is discussed in chapter 5.
4.1
EOM principle of operation
Our implementation of the EOM samples the signal at 5 different points within a single symbol period. One at the center and four different points around the center. The data sampled at the center of the symbol period is also used by the clock data recovery unit (CDR) for phase aligning the base clock to the received data and for data recovery. The remaining four sampling points are used to measure the eye opening of the signal.
The four sampling points are set by two variable reference voltage levels and two sampling clocks whose phase can be varied. The four points form a rectangular mask as shown in figure 4.1. The mask size can be varied by varying the phase of the early and late
Chapter4 4.1. EOM PRINCIPLE OF OPERATION Mask Mask error Vhigh Vlow clkearly clklate SH,early SH,late SL,early SL,late SH,early SH,late SL,early SL,late
Figure 4.1: Mask error detection in a two dimensional EOM with rectangular mask
sampling clocks and the reference voltage levels. Early and late clocks are generated from the CDR base clock using phase interpolators. Reference voltage levels are generated from a DAC whose setting can be controlled. The design of the DAC and phase interpolators are not discussed in this work as they are not the focus of this thesis and stay as behavioral models.
Any transition within the mask can be easily detected using an XOR operation on the sampled data [12]. A difference in the sampled data at two points in mask (for the same bit) can be used to detect any transitions between the two points. Such transitions within the mask are considered as mask violations and are counted as mask errors. Mask errors are counted for a specific duration, for example we have used one period of the PRBS7 sequence (127 symbols) in this work mainly due to simulation time constraints. The total number of errors counted for a particular mask size is sent to the adaptation controller to tune the equalizer. The adaptation controller also sets the mask size of the EOM by controlling the phase input to the interpolator and the input to the DAC which generates the reference voltages. The working of the adaptation controller is discussed in chapter 5.
4.2
EOM architecture
Figure 4.2 shows the architecture of the EOM used. The basic building blocks of the EOM are the fully differential difference amplifiers (DDA) and the CML latches which together form the latched comparator. Two DDAs compare the differential input data with the dif-ferential reference voltage levels (Vhigh,Vlow). As the reference voltages are symmetric across common mode, the reference level for the 2nd DDA is generated by swapping the signals Vhigh and Vlow which are driven by a DAC.
The CDR block aligns the base clock to the received data using the sampled data at the edge (SM,~clk) and the center (SM,clk) of the symbol period. The early and late clocks are
generated using phase interpolators from the base clock. CML latches are used to build the differential flip-flops which are triggered at different sampling clocks. The ’Sync block’ synchronizes the data sampled at different clocks to the base clock (φclk).
4.2.1
Differential difference amplifier
DDAs are used to subtract the reference voltage levels from the input signal. Figure 4.3 shows the schematic of a DDA. It consists of two differential input stages of amplifiers which convert the input voltage into current. The currents of the two stages are subtracted and the difference is converted into voltage over the load resistors. Equation 4.1 gives the formula for the output of the DDA, where A0represents the DC gain of the DDA and the
output is effectively A0 times the difference between the input and reference levels. The
equation has been rearranged because, as Vrefp and Vrefn are DC signals (change is very
slow when compared to the input data), they are connected to different input stages as shown in the schematic.
Vout p−Voutn = A0(Vinp−Vinn) − Vre f p−Vre f n
Vout p−Voutn = A0 Vinp−Vre f p − Vinn−Vre f n
(4.1)
The output of the DDA is thus the amplified difference between the input data and the reference levels. This output is fed to a flip-flop for sampling the equalized signal at different points of the eye diagram. The reference inputs are driven by a DAC which is set
Chapter4 4.2. EOM ARCHITECTURE
Figure 4.3: Schematic of the fully differential difference amplifier used for reference sub-traction
by the adaptation controller. Two DDAs are used of which one has a positive reference level and the other has a symmetric negative reference level.
4.2.2
CML latch
The output of the difference amplifier is sampled by a CML D-flip-flop (DFF) using the sampling clocks generated from the CDR unit. A CML DFF is built using master and slave CML latches. A rising edge triggered DFF is built by enabling the 1st latch at the negative phase of the clock and the 2nd latch at the positive phase of the clock. CML latches can operate at much higher speeds than their CMOS counterparts. This is mainly due to the reason that the output swing is only a fraction of the supply voltage. The schematic of the CML latch is shown in figure 4.4[15].
The CML Latch operates in two phases: capture and hold. During the capture phase (clock is high) the input differential pair (M1 & M2) are ON and the input is transferred to the output. During the hold phase (clock is low), the input is detached from the output and the cross-coupled pair (M3 & M4) are ON and help retain the output value, forming a
Chapter4 4.2. EOM ARCHITECTURE
Figure 4.4: Schematic of CML latch
positive feedback.
4.2.3
DC offset
The latched comparator designed suffers from a DC offset due to the presence of device mismatches. The DC offset is measured as the value observed at output when the input is zero. A more common measure is the input referred offset which is defined as the input voltage that causes the output to go to zero. This input referred offset has to be reduced for the proper operation of the latched comparator.
For a differential pair, the input referred offset is given by equation 4.2 [16], where VGS
-Vthis the overdrive voltage and W/L is the width to length ratio of the input transistors and
RDis the load resistance. So in order to minimize the effect of variations in RD, W/L and
Vth due to device mismatches, the devices have to be sized such that the input transistor
pair has a lower overdrive voltage. This can be achieved by reducing the tail current or sizing up the W/L of the input pair. Such careful design considerations help minimizing the offset. But there are other limitations on such design like bandwidth/speed and output
common mode level. For e.g. decreasing tail current decreases the bandwidth and increases output common-mode level.
VOS,in= VGS−Vth 2 2" ∆RD RD 2 + ∆ (W /L) (W /L) 2# + ∆Vth2 (4.2) 4.2.3.1 Offset simulation
The input referred offset has been measured using the simulation technique mentioned in [17]. The offset of the latched comparator can be characterized as shown in figure 4.5(a). Figure 4.5(b) shows the offset simulation technique where the output of the comparator is fed back to the input through a differential amplifier and integrator. The output of the dif-ferential amplifier with unity gain is, VOD = Vp− Vn. This voltage is integrated and added
to common mode voltage VCMand fed to VB. Also, VA=VCM. Voltage at VB is increased
or decreased based on the polarity of VOD in-order to reach level VA. At equilibrium the
comparator output should have equal number of ones and zeroes over time. The average value of VA-VB is calculated as the input referred offset. The transient waveforms are
shown in figure 4.5(c). The offset simulation blocks namely, the integrator and the differ-ential amplifier which form the feedback loop are modeled in verilog-A for the simulations.
4.2.3.2 Offset compensation
To further reduce the offset voltage, dynamic offset cancellation techniques are used. Conventionally, pre-amplifiers have been used preceding the CML latch stage to reduce the effect of offset. It amplifies the small input voltage difference to a large value in-order to overcome the offset voltage of the latch. But these amplifiers are very power consuming for large bandwidth and the delay due to these stages need to be taken into consideration.
The technique we have used handles the offset of the DDA and latch separately. The calibration of the DDA is done by changing the reference voltages by a value equal to the offset so as to cancel its effect. For the latch, current calibration is used where current is drawn from one of the output terminals to compensate for the offset. These two techniques are used because if only current calibration is used, there can be a huge shift in the output common level after offset compensation. To reduce this, separate calibration of the DDA is done first. Also, DDA calibration alone wont be sufficient since one DDA is connected
Chapter4 4.2. EOM ARCHITECTURE
Figure 4.5: Offset simulation technique used to measure the input referred offset voltage of the latched comparator
to two different latches which might have offsets with different polarity.
For the DDA, from the model shown in figure 4.5(a), Vout p − Voutn = A0(Vinp−Vinn) − Vre f p−Vre f n+VOS. It can been seen that a positive voltage
off-set at the input of DDA can be canceled by reducing the reference level by a voltage equivalent to the offset. This idea is used by an offset calibration control block which during the calibration phase (Vin=VCM & Vref=VCM) changes the reference voltage (Vref)
in small steps (2.34 mV in our case) using a DAC, until the output of the comparator toggles (as in figure 4.5(c)) and then changes the direction of varying Vref. In this way
the average value of Vref is stored and later added to the actual reference level during the
operation phase.
For the CML latch offset compensation, a current calibration technique is used. Here, the DC offset is canceled by drawing a specific amount of current from positive output (Voutp) or negative output (Voutn) node such that the outputs have the same common mode
level. The amount of current drawn is proportional to the current on the load resistors due to the output offset voltage (VOS_out/Rload). The current to be drawn from the output
Chapter4 4.2. EOM ARCHITECTURE 10/23/2013 Anand Narayanan 1 Out early Out late I_early (Ip1-In1) I_late (Ip2-In2) Vref’ 1 1 Up Up Up
0 0 Down Down Down
1 0 Up Down - 0 1 Down Up - DDA Latch early Latch late Vref’ Data Ip1 In1 Ip2 In2 Out_early Out_late Offset Calibration Vref I_early I_late
Figure 4.6: Module for combined offset compensation of latched comparator
the current drawn can be incremented/decremented in small steps (3.75uA in our case) by changing the DAC input. The current drawn from a particular output (say positive) is incremented until the output voltage of the latch toggles. Then, the current at positive node is decrease in steps until it is 0 and then the current on the negative output is increased until the output voltage toggles again. Finally the average is taken over a period of time and settles to a particular value which ideally results in zero offset.
In our EOM architecture, a DDA is connected to two latches triggered at different clocks. An algorithm has been used to calibrate the Vrefof DDA and the offset currents of
two latches separately. This is required because the two latches can have different offsets and the DDA calibration need to be done by monitoring the flip-flop outputs working on the early and late clocks. Figure 4.6 shows the block diagram of the offset calibration module and a table describing the operation of the offset control algorithm. Ip1, In1, Ip2,
In2 are the calibration currents drawn from the positive and negative terminals of the two
latches respectively. Vref is the actual reference level and V’ref is the calibrated reference
level. Initially only Vref calibration is done by monitoring the out_early and out_late
signals. This is done until the two signals move in opposite directions, such that the offset common to the both data paths are compensated. Next, current calibration is done at the outputs of the two latches in-order to cancel the offset of the latches. For the Monte-carlo simulations, an offset of 18.65 mV was measured before compensation which reduced to 1.81 mV at 1σ after calibration using this technique.
Chapter4 4.2. EOM ARCHITECTURE 0 2 4 6 8 10 12 14 0 25 50 75 100 125 Of fset volt ag e (mV ) at 1 σ Temperature (°C) Without BGR With BGR
Figure 4.7: Offset voltage deviation with temperature drift after calibration at 25oC
4.2.3.3 Offset deviation
A deviation in the offset was noticed with drift in temperature after calibration at 25oC. This occurs due to the variation in threshold voltages of the transistors with temperature. These Vth variations cause the offset calibration currents to vary with temperature change.
To overcome this effect, a band-gap reference based reference current was used for offset calibration. This limited the variations to the offset with change in temperature. Figure 4.7 shows the graph for change in offset measured at 85oC and 125oC after calibration at 25oC, with and without use of band-gap reference.
4.2.4
CML latch kickback noise
The CML latch suffers from a kickback noise issue which affects the performance of the latched comparator. Consider the configuration shown in figure 4.8, if the clk_early and clk_late have a 180o phase shift, then latch_early would be in hold phase when latch_late is in capture phase and vice-versa. Due to the parasitic capacitance CGD, when latch_early
is in hold phase, the large voltage variations at its output (Ve) are coupled to its input(Vd)
through CGD. At this time latch_late is in capture phase and it captures the distorted signal
DDA Latch early Latch late Vref Data Out_early Out_late clk_early clk_late
Figure 4.8: Neutralization technique for CML latch kickback noise reduction
A neutralization technique has been used to eliminate the effect of kick-back noise[18]. In this technique, two nulling capacitors (CN) are added between the input and output nodes
of the CML latch which can cancel the effect of CGD as shown in figure 4.8. The capacitor
CNcan be realized using the CGDof a NMOS transistor with source and drain shorted. The
transistor should be sized with half the width of the input differential pair since CGD and
CGSof the transistor are added (in parallel) as its source and drain are shorted.
4.2.5
Synchronization Unit
This block synchronizes the sampled data at different sampling points using different clocks to the base clock (φclk). It consists of a series of flip-flops triggered at positive edge of the
base clock. The block diagram and timing diagram of this unit is as shown in figure 4.9. The sampled data at the early and late clocks are aligned to the base clock (φclk). For the proper functioning of this unit, the time difference between the early and late clock edges (te+tl) should not be too small, which might cause setup/hold time violations. This
introduces a lower limit on the minimum horizontal mask opening that the sense unit can be operated on.
4.2.6
Clock Data Recovery
The data recovery from the received signal requires a synchronous clock which is used to sample the received signal. The clock used at the transmitter can be transmitted with the data, using separate channels, but due to different delays of the channels the phase alignment between the data and clock is lost. Hence in many high speed systems the receiver generates the clock from a frequency reference and phase aligns it to the received
Chapter4 4.2. EOM ARCHITECTURE
Figure 4.9: Synchronization unit block diagram and timing
Figure 4.10: CDR block diagram
data.
A commonly used CDR architecture is shown in figure 4.10 [19]. It consists of a phase detector, loop filter and a voltage controlled oscillator (VCO). The phase detector detects the phase difference between the data and the clock by sampling the received signal at the rising and falling edge of the clock and comparing them. The clock phase is shifted in small steps according to the phase difference. Data recovery is done by sampling the received signal at the center of the eye-diagram using the base clock.
The early and late clocks for the EOM are generated using phase interpolators from the CDR base clock. The phase interpolator input is also tunable in-order to generate early and late clocks with different phases resulting in different mask sizes. The CDR block and
the phase interpolators have been kept as a behavioral models in this work.
So far, the architecture of the two dimensional EOM and the various design challenges involved have been discussed. For every given mask setting the EOM counts the number of mask errors over a specific duration of time. This mask error information is then passed on to the adaptation controller which then makes a decision on changing the equalizer setting. The function of the adaptation controller is discussed in detail in chapter 5.
Chapter 5
Adaptation Controller
The mask error information extracted by the EOM from the signal eye diagram is passed on to the adaptation controller. The controller works on an algorithm and tries to set the equalizer based on the information from the EOM. The controller also sets the EOM horizontal mask size by tuning the sampling phase for the early and late clocks and the vertical opening by varying the reference voltage levels. In this chapter we discuss how this algorithm works for each of the equalizers designed. The controller is optimized for each of the equalizers and is discussed separately.
The adaptation controller basically consists of two blocks, one which acts as the ’ac-tuator unit’ to control the equalizer setting and another ’mask control unit’ which sets the mask size for the EOM. The block diagram on how the system works is shown in figure 5.1.
Equalizer CDR
EOM
Data Equalized Data
Clock Mask Control Adaptation controller Actuator Unit Mask Control Unit Boost Control
