Department of Electrical Engineering
Examensarbete
Development of test equipment for analysis of camera
vision systems used in car industry
Printed circuit board design and power distribution network
stability
Examensarbete utfört i Elektriska kretsar och system vid Tekniska högskolan vid Linköpings universitet
av
Jimmy Johansson and Martin Odén LiTH-ISY-EX-ET--15/0445--SE
Linköping 2015
Department of Electrical Engineering Linköpings tekniska högskola
Linköpings universitet Linköpings universitet
vision systems used in car industry
Printed circuit board design and power distribution network
stability
Examensarbete utfört i Elektriska kretsar och system
vid Tekniska högskolan vid Linköpings universitet
av
Jimmy Johansson and Martin Odén LiTH-ISY-EX-ET--15/0445--SE
Handledare: Peter Johansson
isy, Linköpings universitet
Magnus Dannebro
Autoliv Electronics AB
Mattias Forsberg
Autoliv Electronics AB
Examinator: Dr. J Jacob Wikner
isy, Linköpings universitet
Institution av elektronik
Department of Electrical Engineering SE-581 83 Linköping 2015-08-25 Språk Language Svenska/Swedish Engelska/English Rapporttyp Report category Licentiatavhandling Examensarbete C-uppsats D-uppsats Övrig rapport
URL för elektronisk version
http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-XXXXX
ISBN — ISRN
LiTH-ISY-EX-ET--15/0445--SE Serietitel och serienummer Title of series, numbering
ISSN —
Titel Title
GSE, submodul
Development of test equipment for analysis of camera vision systems used in car industry
Författare Author
Jimmy Johansson and Martin Odén
Sammanfattning Abstract
The main purpose of this thesis was to develop a printed circuit board for Autoliv Electronics AB. This circuit board should be placed in their test equipment to support some of their camera vision systems used in cars. The main task was to combine the existing hardware into one module.
To be able to achieve this, the most important factors in designing a printed circuit board was considered. A satisfying power distribution network is the most crucial one. This was ac-complished by using decoupling capacitors to achieve low enough impedance for all circuits. Calculations and simulations were executed for all integrated circuits to find the correct size and numbers of capacitors.
The impedance of the circuit board was tested with a network analyzer to confirm that the impedance were low enough, which was the case. System functionality was never tested completely, due to delivery problems with some external equipment.
Nyckelord
The main purpose of this thesis was to develop a printed circuit board for Autoliv Electronics AB. This circuit board should be placed in their test equipment to support some of their camera vision systems used in cars. The main task was to combine the existing hardware into one module.
To be able to achieve this, the most important factors in designing a printed cir-cuit board was considered. A satisfying power distribution network is the most crucial one. This was accomplished by using decoupling capacitors to achieve low enough impedance for all circuits. Calculations and simulations were executed for all integrated circuits to find the correct size and numbers of capacitors. The impedance of the circuit board was tested with a network analyzer to confirm that the impedance were low enough, which was the case. System functionality was never tested completely, due to delivery problems with some external equip-ment.
Special thanks to Autoliv Electronics AB for giving us the opportunity to work on this thesis. It has been challenging and instructively. We would also like to thank Magnus Dannebro, Mattias Forsberg, Maria Christensen and Johan Molek-lint for being our supervisors at Autoliv. A big thanks to Peter Johansson and Jacob Wikner at ISY, Linköpings university for being our supervisor and exam-iner.
Linköping, August 2015 Jimmy Johansson & Martin Odén
List of Figures x
List of Tables xiii
Notation xv
1 Introduction 1
1.1 Motivation and purpose . . . 1
1.2 Problem formulation . . . 2
1.3 Thesis scope . . . 2
1.4 Thesis outline . . . 2
2 Background 5 2.1 Camera vision systems . . . 5
2.1.1 Electronic control unit . . . 6
2.1.2 KAFAS system . . . 7
2.1.2.1 KAFAS camera . . . 8
2.1.2.2 KAFAS electronic control unit . . . 8
2.1.2.3 Key components . . . 9
2.1.2.4 Controller area network communications . . . 10
2.1.3 INVP system . . . 11
2.1.3.1 INVP cameras . . . 12
2.1.3.2 INVP electronic control unit . . . 12
2.1.3.3 Key components . . . 13
2.1.3.4 Controller area network communications . . . 13
2.2 Test Equipment . . . 14
2.2.1 Break-out Box . . . 14
2.2.2 Generic surveillance equipment . . . 16
2.2.2.1 Gateway module . . . 17
2.2.2.2 Simulation module . . . 17
3 Theoretical background 19 3.1 Differential signals . . . 19
3.2 Electromagnetic interference suppression filters . . . 21
3.2.1 Ferrite bead . . . 22
3.2.2 Common mode choke . . . 23
3.3 Bus protocols . . . 24
3.3.1 Controller area network . . . 24
3.3.2 Low voltage differential signals . . . 26
3.4 Power distribution network . . . 26
3.4.1 Decoupling capacitors . . . 27
3.4.1.1 Capacitors in parallel . . . 30
3.4.1.2 Capacitors with different capacitor values . . . 31
3.4.1.3 Decoupling with equal capacitor value . . . 32
3.4.1.4 Printed circuit board capacitance . . . 33
3.4.2 Via inductance . . . 34 3.4.3 Impedance target . . . 35 3.4.4 Harmonics . . . 36 3.4.4.1 Odd symmetry . . . 36 3.4.4.2 Even symmetry . . . 37 3.4.4.3 Square wave . . . 37 4 Method 39 4.1 Submodule structure design . . . 39
4.1.1 KAFAS signal processing block . . . 40
4.1.2 INVP signal processing block . . . 42
4.1.3 Controller area network interface block . . . 43
4.2 Submodule power distribution . . . 45
4.3 Simulation module firmware changes . . . 45
4.4 Simulation setup . . . 46 4.5 Decoupling capacitor . . . 49 4.5.1 Calculations . . . 49 4.6 Schematics . . . 51 4.7 Front panel . . . 52 4.7.1 INVP connectors . . . 52 4.7.2 KAFAS connectors . . . 53
4.7.3 Controller area network connectors . . . 53
4.7.4 Connection layout . . . 53
4.8 CAD layout guidelines . . . 55
4.8.1 Low voltage differential signal mismatch . . . 55
4.8.2 Impedance match . . . 56
4.8.3 Connections and pin headers . . . 56
4.9 External cables . . . 56
5 Result 57 5.1 Final product . . . 57
5.2 Power distribution network . . . 58
5.3 Functionality and connection placement . . . 60
6 Discussion 63
6.1 Result . . . 63
6.1.1 Power distribution network . . . 63
6.1.2 System functionality . . . 65
6.2 Method . . . 65
A Appendix 69 A.1 Cables . . . 70
A.2 Front panel . . . 74
A.3 Capacitor calculations . . . 75
A.3.1 KAFAS serializer . . . 75
A.3.2 KAFAS I2C accelerator . . . 76
A.3.3 KAFAS clock . . . 77
A.3.4 INVP clock . . . 78
A.3.5 INVP and KAFAS clock multiplexer . . . 79
A.3.6 INVP deserializer . . . 81
A.3.7 INVP serializer . . . 82
2.1 General system block diagram for a camera vision system . . . 6
2.2 Placement of KAFAS electronic control unit in vehicle [5] . . . 6
2.3 KAFAS highlight function [5] . . . 7
2.4 Wide-VGA digital image sensor in casing [5] . . . 8
2.5 KAFAS electronic control unit from above [5] . . . 8
2.6 System overview of the KAFAS system [5] . . . 9
2.7 Overview of the KAFAS controller area network communication . 10 2.8 INVP animal and pedestrian night vision detection [4] . . . 11
2.9 The INVP near-infrared camera, to the left, and far-infrared cam-era, to the right. [4] . . . 12
2.10 Placement of cameras in vehicle [4] . . . 12
2.11 Front side of INVP electronic control unit with connectors [4] . . . 13
2.12 Test setup with break-out box equipment [6] . . . 14
2.13 INVP break-out box casing . . . 15
2.14 Break-out box interior, with the daughterboard on top of the moth-erboard . . . 15
2.15 Generic surveillance equipment system overview [7] . . . 17
2.16 Generic surveillance equipment test rack overview [7] . . . 18
3.1 Maximum length difference without jitter. [2] . . . 20
3.2 Electromagnetic interference transmission paths . . . 21
3.3 Electromagnetic interference suppression alternatives . . . 22
3.4 Ferrite bead circuit model [11] . . . 23
3.5 Example of impedance frequency characteristics of a ferrite bead . 23 3.6 Common mode choke structure . . . 24
3.7 Common mode choke equivalent circuit . . . 24
3.8 Controller area network overview . . . 25
3.9 Detailed controller area network . . . 26
3.10 Low voltage differential signal setup with one a single driver and 100Ωtermination. . . 26
3.11 Capacitor equivalent circuit.[3] . . . 28
3.12 Capacitor impedance for a 100 nF capacitor.[3] . . . 29
3.13 Capacitor impedance for different capacitor values and casings. [3] 30 3.14 Capacitor equivalent circuit, parallel connected. [3] . . . 31
3.15 Unwanted resonance peak.[3] . . . 31
3.16 Same value capacitors in parallel, 20 % tolerance.[3] . . . 33
3.17 Overview of a capacitor mounted on a 6 layer printed circuit board. 34 3.18 Square wave build of 6 sine waves with different frequencies. . . . 36
3.19 Harmonics of a 50 MHz square wave. . . 38
4.1 Submodule block diagram . . . 40
4.2 KAFAS signal processing block . . . 42
4.3 INVP signal processing block . . . 43
4.4 Controller area network interface block . . . 44
4.5 Power supply circuitry . . . 45
4.6 LTspice IV interface. . . 46
4.7 LTspice setup to simulate decoupling capacitors. . . 48
4.8 KAFAS deserializer simulation, two 10 nF decoupling capacitors . 50 4.9 Example circuit drawn in DxDesigner. . . 51
4.10 Simulation module and submodule mounted to the front panel. . 52
4.11 INVP connections. . . 52
4.12 KAFAS connection. . . 53
4.13 Controller area network connection. . . 53
4.14 Controller area network connections with three channels, sense and ground pins. . . 54
4.15 Location where connections can be placed. . . 54
4.16 Front panel with all connector cut-outs. . . 55
5.1 Final product . . . 57
5.2 Final product with measurement points. . . 58
5.3 Impedance at measurement point 1, top left corner. . . 59
5.4 Impedance at measurement point 2, top right corner. . . 59
5.5 Impedance at measurement point 3, bottom right corner. . . 59
5.6 Front view of the printed circuit board with connections including the D-sub 9 pin header . . . 60
5.7 Example of one old cable . . . 61
5.8 Example of one new cable . . . 61
6.1 Summary of all measurement points. . . 64
6.2 Worst case impedance target, which is 0.057Ω for the INVP dese-rializer. . . 65
A.1 Cable for connecting Kafas setup. . . 70
A.2 Cable for connecting BMW setup. . . 71
A.3 Cable for connecting AUDI setup. . . 72
A.4 Cable for connecting Daimler setup. . . 73
A.5 Blueprint of the new front panel. . . 74
A.6 KAFAS serializer simulation with two 10 nF decoupling capacitors. 75 A.7 KAFAS I2C accelerator simulation with one 10 nF decoupling ca-pacitor. . . 76
A.8 KAFAS clock simulation with one 10 nF decoupling capacitor . . . 77 A.9 INVP quarts crystal simulation with one 47 nF decoupling capacitor 78
A.10 INVP clock Multiplexer simulation with one 47 nF decoupling ca-pacitor. . . 79 A.11 KAFAS clock multiplexer simulation with one 10 nF decoupling
capacitor . . . 80 A.12 INVP deserializer simulation with two 47 nF decoupling capacitors. 81 A.13 INVP serializer simulation with two 47 nF decoupling capacitors. 82
3.1 Suitable decoupling capacitors [2] . . . 27 4.1 Controller area network pin setup for D-sub 9 connection. . . 54
Notation
Abbreviations
Abbreviations Description BoB Break-out Box
CAN Controller Area Network
CANH Controller Area Network High-signal CANL Controller Area Network Low-signal
CMOS Complementary Metal Oxide Semiconductor CPLD Complex Programmable Logic Device
CVS Camera Vision System DSP Digital Signal Processor DUT Device Under Test ECU Electronic Control Unit
EEPROM Electrically Erasable Programmable Read-Only Mem-ory
EMI Electomagnetic Interference ESL Equivalent Series Inductance ESR Equivalent Series Resistance EYEQ2 A Vision processor on KAFAS ECU
FIR Far-Infrared
FPGA Field-Programmable Gate Array
GTW Gateway module
GSE Generic Surveillance Equipment IC Integrated Circuit
INVP Intelligent NightView Plus
IO General purpose Input Output signal
I2C Standardised Inter Chip Communication protocol KAFAS Short form of camera based driver assistance system
LVDS Low Voltage Differential Signal MCU Micro Control Unit
NIR Near-Infrared
PCB Printed Circuit Board PDN Power Distribution Network RAM Random Access Memory
SIM Simulation module SRF Self Resonance Frequency
UART Universal Asynchronous Receiver/Transmitter VP Vision Processor
1
Introduction
This bachelor thesis is done at Autoliv Electronics AB, the world’s largest automo-tive safety supplier with sales to the leading car manufactures around the world. Autoliv develop, manufacture and market products. Autoliv has two major fields. Passive safety, such as airbags, seat belts, steering wheels etc. and active safety systems such as radar and camera vision systems (CVS).
This thesis will be performed at Autoliv’s Active safety department. The main purpose will be to improve the analysis equipment used today.
1.1
Motivation and purpose
Today Autoliv uses different types of fault analyzing equipment for different types of CVS. They have developed a new test equipment called generic surveil-lance equipment (GSE). The main goal with the GSE is to have a standardized test environment for all CVS products.
The GSE consist of one rack that contains several modules, one gateway module and eight simulation modules. Briefly explained, the gateway module can be loaded with a "test run" that executes on the simulation modules.
A submodule is attached to each simulation module. The submodule is product specific and the only non generic module on the GSE. This needs to be changed depending on the product.
The GSE will increase the efficiency in several ways. Two of the main reasons are that 8 units can work in parallel and the possibility to simulate different products at the same time.
The request from Autoliv and the purpose of this thesis was to develop a submod-ule compatible with their older systems. The submodsubmod-ule is a high speed printed circuit board (PCB) with a given size of 10x16 cm.
Beside the functionality of the PCB, this thesis will also consider the problems that can occur when designing a high speed PCB. The trend towards faster in-tegrated circuits with more connections and increasing edge rates of high-speed signals makes it more challenging for a designer to make a proper PCB-design. One of the major problems with the increasing edge rates is that the circuits will consume power more rapidly. This will cause disturbances in the power distribu-tion network (PDN) and if the PDN is not well designed it can cause the circuits to malfunction.
1.2
Problem formulation
This thesis will cover the following questions.
• How should the submodule be designed to support multiple CVS?
• Is there a way to design the PCB so that we can guarantee that the power distribution network will be stable enough not to cause the system to mal-function?
These questions will be discussed and answered through big parts of this thesis.
1.3
Thesis scope
When creating high speed digital design there are a lot of parameters to consider to make it work properly. One thing to take under consideration is that the high speed PCB connections/traces could behave as transmission lines when the signal frequency becomes too high. This will cause reflections and an unstable behavior. Another problem to be considered is trace crosstalk and vagabond currents. Due to the fact that this thesis does not cover the design of the PCB layout, we have chosen to delimit the scope of this thesis to PDN disturbances and the circuit functionality.
1.4
Thesis outline
Due to the complexity of Autoliv’s systems a background chapter is needed to give the reader a better understanding of the purpose of this thesis. This will also include a short description of all necessary equipment in chapter 2, background. The reader does not need knowledge about PCB design, basic knowledge about electronics is sufficient. All theoretical information needed is described in detail in chapter 3, theoretical background.
To simplify the understanding of our procedure we have chosen to divide the system functionality into three different blocks. All calculations made in chapter 4, method, is based on the facts and the equations from the previous chapter. The impedance for all important integrated circuits is also simulated in this chapter. In chapter 5, result, we measure the PCB impedance using a network analyzer. The final product got delayed a lot due to a series of unpredicted problems. Some of the external equipment also had a delayed delivery and therefor only a small part of the functionality could be tested.
The result where analysed and discussed in chapter 6, discussion. The impedance graphs showed that all previous calculations where sufficient enough to manage the PCB impedance target.
2
Background
To give the reader an overview of the system functionality and information of pe-ripheral equipments, this chapter will describe the basic functions of the camera vision systems and associated test equipment.
2.1
Camera vision systems
Autoliv has developed several camera vision systems (CVS) systems. Each of these systems has their own specification and functions. During the development of the systems, several subsystems have been created for different car manufac-turers. [1]
The submodule developed in this thesis will work on the KAFAS, INVP, NV3 Audi, NV3 BMW and NV3 FLIR systems. This thesis will only give an insight on two systems, INVP and KAFAS. These systems are chosen due to their complexity. The KAFAS and INVP systems consists of three major components, an electronic control unit (ECU), cameras and a display. A general system block diagram is seen in figure 2.1
Figure 2.1:General system block diagram for a camera vision system
2.1.1
Electronic control unit
The ECU is the central control unit in the system. It analysis the camera image and process it. The processed image is outputted on a display in the car. The ECU communicates with the rest of the vehicle through the controller area network (CAN), a standardized vehicle communication protocol. The CAN protocol will be described more in detail in section 3.3.1.
The ECU consists of a PCB inside a metal casing which is placed in a bracket below the steering wheel, passenger compartment or in the trunk. A mounted KAFAS ECU is illustrated in figure 2.2. All CVS contains of a unique ECU [5] [4].
2.1.2
KAFAS system
KAFAS is a mono-camera based system and stands for Kamerabasiertes Fahreras-sistenzystem. The KAFAS system consists of three different versions, KAFAS20, KAFAS21 and KAFAS22. The hardware is the same for all systems, but they have their own setup of applications. The KAFAS system applications are:
• Speed limit information • No passing information • Forward collision warning • Lane departure warning • High beam assistance • Glare free HBA
• Vision/Radar fusion ACC • Preventive pedestrian protection
• City collision mitigation by active braking • Vision only
• Queue assist
These applications will not be described in this thesis. As a summary the sys-tem detects pedestrians, vehicles and obstacles and highlight them on a display in front of the driver. The function of highlighting obstacles is visualized in fig-ure 2.3 [5].
2.1.2.1 KAFAS camera
The KAFAS camera is a wide-VGA digital image sensor and has a focus radius of 8 meters. The camera is an independent unit and is placed in the windshield of the car. The camera communicates with the ECU through a low voltage differential signal (LVDS) and an inter-integrated circuit bus (I2C). The I2C bus transfer pixel data and sync information [5]. The KAFAS camera can be seen in figure 2.4.
Figure 2.4:Wide-VGA digital image sensor in casing [5]
2.1.2.2 KAFAS electronic control unit
The KAFAS ECU consists of a PCB and will handle the communication with the camera through a special cable. The PCB is placed in a metal casing with two connectors, one for the vehicle and one for the camera, see figure 2.5.
2.1.2.3 Key components
The KAFAS system contains several key components. The components are: • Micro controller unit (MCU)
• Serializer/deserializer • EYEQ2
• Electrically erasable programmable read-only memory (EEPROM) • Complex programmable logic device (CPLD)
• Power circuit
A system overview of the key components in the KAFAS system is seen in fig-ure 2.6.
Figure 2.6:System overview of the KAFAS system [5]
The MCU is a small computer on a single integrated circuit. The MCU handle the system algorithms.
The serializer and deserializer transmits and receives data between the camera and the EYEQ2. These components convert data between serial data and parallel data interfaces in each direction.
The EYEQ2 is an image processing application-specific integrated circuit (ASIC). The processor receives picture data over the LVDS and I2C communication. The EYEQ2 identifies objects in the picture and tracks movement through algorithmic calculations. The I2C connection is set up directly between the camera and the EYEQ2 chip. The LVDS stream passes by the deserializer before it reaches the EYEQ2.
The CPLD extracts video sync signals from the LVDS stream that is needed by the EYEQ2. The CPLD also works as a transceiver for the CAN communication between the MCU and EYEQ2.
The camera EEPROM can be read through the I2C communication. The EEPROM is accessed when the system needs information about the camera.
2.1.2.4 Controller area network communications
The KAFAS system has three CAN communications: • FA-CAN, the vehicle CAN
• SF-CAN, the debug CAN • EQ-CAN, the internal CAN
The KAFAS ECU communicates with the vehicle through the FA-CAN. The mes-sages from the ECU originate from the MCU. The SF-CAN is an interface between the EYEQ2 and the vehicle and is used for debugging.
The EQ-CAN is the interface between the EYEQ2 and the MCU. The EQ-CAN can be referred as the internal-CAN and does not use any CAN transceivers. The CAN bus is routed through the CPLD instead. An overview of the CAN commu-nication in the KAFAS system can be seen in figure 2.7
2.1.3
INVP system
INVP is a dual-camera based night vision system and stands for intelligent night view plus. The INVP system features are:
• Animal detection • Pedestrian detection • Spotlight function • Scene analysis
The system is active when the driver has reduced visibility, e.g. in foggy or dark conditions. The system detects pedestrians and animals then highlights them on a display in front of the driver. The system can also be equipped with a spotlight that illuminate pedestrians and animals.
This is achieved by transmitting the detected object position to the vehicle through CAN. The INVP functionality is visualized in figure 2.8.
The scene analysis application makes an approximation of which functions that should be active, depending on the environment. The application uses the image context to calculate the probability for example, that the vehicle is in a city envi-ronment. If the probability is above a certain threshold the application sets the scene to be in a city. In that case, the animal detection is deactivated [4].
2.1.3.1 INVP cameras
The INVP system uses two infrared cameras for night vision detection. One near-infrared (NIR) camera and one far-near-infrared (FIR) camera. The two cameras are shown in figure 2.9.
Figure 2.9:The INVP near-infrared camera, to the left, and far-infrared cam-era, to the right. [4]
An infrared camera has a lot of similarities with a standard camera. The major difference is that an infrared camera uses radiation instead of visible light to form an image.
The FIR camera is used for detections and the NIR camera for the image, which is sent to the display. The FIR camera is placed in the front grille and the NIR camera is placed in the front windshield (see figure 2.10) [4].
The cameras communicate with the ECU through LVDS.
Figure 2.10:Placement of cameras in vehicle [4]
2.1.3.2 INVP electronic control unit
The INVP ECU consists of a PCB in a metal casing. The communication with the cameras are handled through special cables. There are two versions of the INVP ECU, one analog version and one digital version. The difference of the versions
is the video output. The only hardware difference is the way the video output is handled (see figure 2.11).
Figure 2.11:Front side of INVP electronic control unit with connectors [4]
2.1.3.3 Key components
The INVP system contains several key components. The components are: • Micro controller unit (MCU)
• Serializer/deserializer
• Field-programmable gate array (FPGA) • Random access memory (RAM)
• Flash memory
• Digital signal processor (DSP) • Power circuit
Apart from the key components there is a module called the vision Processor. The vision processor is integrated into the FPGA and the DSP. It handles the video processing, including animal and pedestrian detection. It also enhances the NIR background image to be shown in the vehicle display.
Except being a part of the vision processor, the FPGA interfaces with the cameras and the DSP performs the object tracking.
The MCU supervises the INVP system and communicates the status to the vehi-cle. It handles the FIR camera authentication, the power management, the CAN communication and storing of diagnostic trouble codes.
The serializer and deserializer transmits data between the camera and the FPGA. These components convert data between serial data and parallel interfaces in each direction, same as the KAFAS system.
2.1.3.4 Controller area network communications
The INVP system only has one CAN communication, the FA-CAN. The CAN sys-tem work in a similar way as the KAFAS FA-CAN (see section 2.1.2.4). The only difference is the car protocol, due to the different car manufacturers.
2.2
Test Equipment
This chapter will describe the current test equipment and its usage.
The test equipments used today are a combination of several external hardware solutions. One is a break-out box, referred to as a BoB. The goal of this thesis was to replace the current BoB solutions to a generic one that are compatible with the GSE.
2.2.1
Break-out Box
The BoB was developed to be a multipurpose data recorder and debug/verification tool for camera systems. As different cameras adhere to different standards in terms of electrical connections and protocols, as well as image size and frequency, the BoB was designed to be able to adapt to most foreseeable camera varieties [6]. A BoB is an electrical circuit that is an essential external help tool in the camera tests. The BoB has connections for the camera and ECU, it also communicates with a PC through a gigabit ethernet connection. The test setup is visualized in figure 2.12
Figure 2.12:Test setup with break-out box equipment [6]
The BoB consist of two separate PCBs, a motherboard (identical for all BoB types) and a daughterboard (different for each BoB type). Also the BoB firmware can be different for each BoB type. The BoB casing is shown in figure 2.13 and the BoB interior, the motherboard and daughterboard, are shown in figure 2.14.
Figure 2.13:INVP break-out box casing
Figure 2.14: Break-out box interior, with the daughterboard on top of the motherboard
The BoB can simulate either a camera or an ECU. It can also bridge between the two, so it can listen to the communication between the camera and the ECU in a running system [6].
The motherboard handles the ethernet and CAN interfaces. It hosts the FPGA and its memories as well as the power regulation.
The daughterboard connects to the motherboard. It handles serialization of out-going data and deserialization of incoming data. Some daughterboards hosts an extra control channel such as I2C, UART or CAN.
2.2.2
Generic surveillance equipment
The generic surveillance equipment (GSE) is developed by Autoliv and is a mul-tipurpose test equipment.
The equipment is satisfying a need for:
• Simulation of bus communication between vehicle and a device under test (DUT)
• Continous monitoring of bus communication from a DUT. • Simulation of sensors/actuators connected to a DUT in a vehicle.
• Continous measuring of analog signals to/from a DUT (current consump-tion, sensor supply).
• Continous monitoring of video output from DUT.
These are the key features when performing design verification and product ver-ification. It is also of high importance when performing robustness test during the normal system testing [7].
The purpose of the GSE is to have a standardized test equipment for all Autoliv products. It consists of one rack that contains two different modules:
• Gateway module, GTW • Simulation module, SIM
Figure 2.15:Generic surveillance equipment system overview [7]
2.2.2.1 Gateway module
The gateway module is the test engine PCB. It communicates with a test PC and the simulation modules through Ethernet. It can also communicate with the test PC through a USB connection. It can be loaded with a "test run" that executes on 1-8 simulation modules. The Gateway module makes it possible to run tests independent of the test PC.
2.2.2.2 Simulation module
The simulation modules consist of: • One generic main board
• One project specific adapter-board, called submodule • One project specific front panel
The submodule holds the project specific DUT interface physics and sensor inter-face physics. It can hold transceivers, serializers, deserializers, project specific signal conversion and project specific connectors, e.g camera connectors. Related to this thesis the submodule will be designed to represent a BoB daughterboard and a BoB CAN interface.
The main board executes parameter tests, measure contentiously on certain pa-rameters and provide vehicle simulation on project specific interfaces. Related to this thesis the main board can be modified to represent a BoB motherboard.
The simulation module has a front panel for LED indicators of system status and "cut-outs" for main board connectors and submodule connectors [7]. An overview of the test rack can be seen in figure 2.16.
3
Theoretical background
This chapter will give the reader the theoretical knowledge of important aspects when designing a printed circuit board (PCB). The chapter will also describe the controller area network functionality in more detail together with the theoretical background of the components that will be used on the PCB.
3.1
Differential signals
Differential signals consist of two signals sent from a source to a receiver. The receiver detects the voltage difference between the signals. If the voltage differ-ence is above or below a fixed point the receiver reads the signal as a logic "1" or "0". The advantage of these kind of signals is that it works even when there is a big ground offset between the source and the receiver. Opposed to single ended signals which are depended on the difference between a voltage and ground. To minimize the signal distortion the differential signals should be traced side by side on the printed circuit board (PCB). This will cause disturbances to affect both signals. It is also very important to have the same length of both signal traces, so that the signals arrive at the same time. If the signals arrive too far apart from each other jitter will occur (see figure 3.1). Jitter is a deviation from a periodic signal, the logic signals does not arrive in an accurate frequency. [2]
Figure 3.1:Maximum length difference without jitter. [2]
The maximum length difference allowed without jitter is calculated by:
M = min (Sr, Sf) · ν (3.1)
or
M = Jm· ν (3.2)
where
M = Maximum length difference [m]. Sr= Source rise time [s].
Sf= Source fall time [s].
ν = Signal speed in transmission lines [m/s]. Jm= Maximum allowed jitter [s].
Differential signals are a great method of transferring data with less disturbances than single ended signals. The downside is that it requires two pins, two traces, two drivers and two receivers. In circuits with a stable ground layer and low fre-quencies, signal noise is not a major problem. Therefor single ended signals have been used due to the less expensive hardware. But the ever increasing switching frequencies made it necessary to start using differential signals to cope with the noise. Ground offset was one of the first reasons to use differential signals and it is still a major one. [2]
3.2
Electromagnetic interference suppression filters
Electromagnetic interference (EMI) is a process by which disruptive electromag-netic energy is transmitted from one electronic device to another. When elec-tronic devices receive electromagnetic waves, unwanted currents can be induced in the circuit which could cause the circuit to malfunction. EMI can adversely affect the performance of an integrated circuit (IC) internally. Connected and nearby electrical components might also be affected. If the electromagnetic en-ergy applied to the circuit is too high the device can be damaged.
EMI can be transferred via radiated or conducted paths. Noise interference oc-curs when a noise source, exposed circuit and transmission path exist (see fig-ure 3.2). If one factor is avoided, noise interference can be eliminated [8] [9].
Figure 3.2:Electromagnetic interference transmission paths
Measures can be taken on the source origin or on the exposed circuit. The radi-ated EMI can be prevented by introducing shields and the conducted EMI can be reduced using filters (see figure 3.3).
A shield refers to an enclosing material, often a metal plate that protects either the source or exposed circuit. The shield efficiency depends on the thickness of the material and its magnetic permeability. Although the protected device can achieve sufficiently large protection with a thin metal plate such as aluminum foil. The noise suppression effects depends more on the design method and en-closure rather than material specifications.[8]
An EMI filter refers to a function or a part that suppress noise. The noise is diverted to ground, but can be alternatively absorbed inside the parts or be re-turned to the noise source. The noise suppression usually uses low-pass filter, since the noise tends to be distributed more in a higher frequency range. One can use parts such as inductors, capacitors and resistors together as a low-pass filter. To completely remove noise from an electronic circuit, an EMI suppression filter is used.[8]
These filters take advantage of uneven frequency distribution of noise. There are also filters that uses the voltage difference, such as a varistor. Some filters make use of conduction mode difference, such as common mode choke coil.[8]
Figure 3.3:Electromagnetic interference suppression alternatives
3.2.1
Ferrite bead
A ferrite bead is a passive component that removes noise energy from a circuit in the form of heat. It is a hollow cylinder or bead that is made of a ferrite material. It suppresses or filters the amount of high frequency EMI in the circuit. Ferrite is a semi-magnetic substance that consists of iron oxide along with a mixture of other metals. The bead is encased in a plastic material to protect and keep the component in place.
The bead creates an impedance over a frequency range that removes all or parts of unwanted noise energy.[10]
It is desirable to have a low DC resistance for DC voltage applications, to prevent large power losses within the desired signal. It is also desired to have a high impedance at unwanted frequencies. The ferrite beads impedance is related to its material, size, winding construction and number of windings. [10]
Bead manufacturers usually provide an equivalent circuit model for simulation. A ferrite bead can be simply modeled as a network of R, L and C components (see figure 3.4). [11]
Figure 3.4:Ferrite bead circuit model [11]
One important factor of using a ferrite bead is that the EMI noise must be in the resistive state. The resistive state is where the resistance of the ferrite beads is larger than the reactance of the ferrite bead, R > X. At frequencies where the reactance is larger than the resistance the ferrite bead behave as an inductor, X > R. For frequencies where the resistance is larger than the reactance the ferrite bead behaves as a resistor, which is desired for the ferrite bead. When the ferrite bead is in the resistive stage it will absorb the noise energy from the circuit in the form of heat. [10] [12]
An example of the impedance frequency characteristic is shown in figure 3.5.
Figure 3.5:Example of impedance frequency characteristics of a ferrite bead
3.2.2
Common mode choke
Common mode chokes are used in order to filter common mode EMI currents and suppress common mode noise. All this without causing a signal degradation of differential signals. The common mode choke work as an inductor against com-mon mode current since magnetic flux flows inside the ferrite core. Differential mode currents are not affected by the choke coil[9]. The component structure is shown in figure 3.6 and the equivalent circuit in figure 3.7.
Figure 3.6:Common mode choke structure
The common mode current flows in the same direction in the choke windings. This creates two equally large and in-phase magnetic fields, which adds together. The common mode signal passes through the choke heavily attenuated because of the high impedance caused by the magnetic field.
The differential mode current flows in the opposite direction of each other in the windings. This creates opposite and equally large magnetic fields, which cancels each other out. The differential mode signal passes through the choke unaffected.
Figure 3.7:Common mode choke equivalent circuit
3.3
Bus protocols
There are a lot of different bus protocols that are commonly used. Different pro-tocols have often or always standard settings defining how the buses work. The speed and performance can often be changed through different setups. Some buses operates synchronously, sends signals on rising or falling edge of the clock. Others operate asynchronous, the transmitter determines when to send signals.[2]
3.3.1
Controller area network
The controller area network (CAN) is a serial communication technology that was developed by Bosch in 1983. CAN was originally developed to be used in automotive vehicles, but has later on also being used in other areas. CAN is a multi-master serial bus standard for connecting different electronic control units (ECU) in vehicles, also known as CAN nodes [13].
The CAN nodes are linked physically by a two-wired network that allows com-munication between devices without a host computer or a master. All communi-cation signals in the network are differential signals. This eliminates the negative effects of interference voltages induced by other units in the vehicle, such as igni-tion contacts, motors and switch contacts. The two lines in the network is called can low line (CANL) and CAN high line (CANH) which is shown in figure 3.8. The lines are also terminated with termination resistors that prevents reflections in the high-speed network. The characteristic impedance of these electrical lines is 120 Ohm.[13].
Figure 3.8:Controller area network overview
An ECU connected to CAN communication needs a CAN interface, which in-cludes a CAN controller and a CAN transceiver (see figure 3.9). The CAN transceiver operates as the interface between the CAN controller and the physical bus connec-tion. The transceiver converts the digital signals generated by the CAN controller to a more suitable signal that is transmitted over the CAN bus, and vice versa. In most cases the transceiver also works as a buffer between the CAN controller and high-voltage spikes that can occur from outside sources. Despite the high-voltage buffer protection it is common to place a common mode choke near the output that can help to further reduce emission noise. The transceiver has two input pins, one for the CANL signal and one for the CANH signal [13].
The CAN controller receives serial bits from the transceiver and store them until the entire message is available. This can later on be fetched by the host processor. When transmitting messages the CAN controller transmits the bits serially onto the bus, this can only be done when the bus is free. The CAN controller is often an integral part of the host e.g. a microcontroller. [13].
Figure 3.9:Detailed controller area network
3.3.2
Low voltage differential signals
Low voltage differential signals (LVDS) were first created by National Semicon-ductor and a few laptop computer manufactures. They collaborated to solve the problem of getting graphic data with high bandwidth from the motherboard to the screen. This path was too narrow to create a stable ground layer which made the single ended signals not work properly. This type of signal method gives good rejection against noise and ground offset. LVDS can be clocked at extreme clock frequencies. Due to this, LVDS can be found in a wide variety of products. For example, ethernet links up to 9,6 GB/s and USB communication.[2]
Figure 3.10: Low voltage differential signal setup with one a single driver and 100Ωtermination.
3.4
Power distribution network
The ideal power distribution network (PDN) will deliver a constant voltage to all circuits independent of the load. That implies zero impedance for all frequencies, but this is not possible to achieve in practice.
Almost all circuits consist of CMOS transistors mounted on a PCB. As the tech-nical progress of transistors is moving forward this resulting in smaller circuits. Number of gates per chip and clock frequency tend to increase combined with a lower supply voltage. All these parameters make designing a stable PDN much harder.
In most electrical circuits the power consumption varies more or less rapidly over time. All components will perform better if the supply voltage is stable. Ohm’s law states that if a current varies over an impedance the voltage will also vary. If the impedance is low at the frequency that the circuit operates, the voltage will be more stable. Most digital circuits have a wide bandwidth which will increase the difficulty of reducing the impedance over the whole operation region. [3] By using voltage regulators the voltage can maintain a stable level, but only up to a few kHz. A lot of circuits operate above a few kHz and the regulators does not fill its purpose in this region. To be able to guarantee a stable supply voltage with good quality at these frequencies, decoupling capacitors can be used. Mod-ern processors and FPGAs consume power at very high frequencies, up to a few GHz [3]. At these frequencies the power and ground layers of the PCB works as a capacitor. The size of the PCB, thickness and placement of the layer determines the boards capacitive properties. [2]
3.4.1
Decoupling capacitors
There are a lot of different types of capacitors that can be used as decoupling capacitors.
Some examples of suitable capacitors:
Ceramic Large capacitance
Large physical size High voltage Low ESR
Tantalum 1 uF to 1000 uF
Medium physical size Low voltage
Low ESR
Aluminum electrolytic Large capacitance Large physical size High voltage Low ESR
Arrays Very low ESL
High cost
It is important to choose the right type of conductor, depending on the systems specifications. Not only to achieve the highest performance, but also consider the economic part.
Conductors are not ideal and do not only have conductive properties. In practice conductors also have resistive and inductive properties.
Figure 3.11:Capacitor equivalent circuit.[3]
All conductors have an inductive and a capacitive part. This means that at some frequency resonance will occur. The resonance will occur at the frequency where the capacitive reactance and the inductive reactance are equal. And can be calcu-lated by Xl= Xc (3.3) where Xl= 2πf L (Inductive reactance). Xc= 1 2πf C (Capacitive reactance).
At this frequency the impedance is equal to the series resistance of the capacitor. The lowest impedance value is equal to the capacitors ESR (see figure 3.12). For frequencies above the resonance frequency the capacitor behaves as an inductor.[3]
Figure 3.12:Capacitor impedance for a 100 nF capacitor.[3]
To determine a decoupling capacitors effective impedance the following equation is used:
Z =
q
Rs2+ (Xl−Xc)2. (3.4)
When choosing decoupling capacitors, there are a lot of aspects to consider. • ESL
All conductors are connected to the circuit through conductive leads and paths. Due to the non-ideal properties of connectors and casings, conduc-tors have an unwanted inductive behavior. A capacitor inductance is there-fore almost only dependent on its casing. The size of the conductor has none or small impact on the inductance. It is desirable to have low induc-tive properties.
• ESR
Small ESR decreases the impedance at the self-resonance frequency (SRF), which is desirable. The downside is that the resonance peak between two ca-pacitors increases. Too high resonance peaks can cause problems. Conduc-tor’s series resistance depends a lot on the size of the capacitor. Choosing a capacitor with the correct ESR value depends on the circuitry.
• Capacitor value
value capacitors decrease the impedance at lower frequencies and the oppo-site for small value capacitors (see figure 3.13). Decoupling capacitors with value between 1 nF to 100 nF are often suitable. [3]
The small impedance difference between same sized capacitors can be seen in figure 3.13. One can also see that the impedance between different cas-ings are quite small.
Figure 3.13:Capacitor impedance for different capacitor values and casings. [3]
3.4.1.1 Capacitors in parallel
Connecting capacitors in parallel causes a resonance peak between their SRF’s. Equation 3.5 can be used to calculate were the parallel resonance frequency will occur. ωp= 1 q C1·C2 C1+C2· (ESL · ESR) (3.5)
In the following equations, the ESL and ESR are set to the same value for both capacitors to simplify the equation. [3]
Figure 3.14:Capacitor equivalent circuit, parallel connected. [3]
3.4.1.2 Capacitors with different capacitor values
Decoupling capacitors with large value differences causes a big parallel resonance peak. This resonance peak can cause problems if being ignored.
Figure 3.15:Unwanted resonance peak.[3]
It is desirable to use decoupling capacitors of the same value if possible, due to the high impedance at the parallel resonance peak caused by different values of capacitors. If a resonance peak occurs, the impedance at this frequency has to be put into consideration. Equation 3.6 can be used to calculate the impedance for parallel capacitors resonance peak. [3]
Zp=
ESR
2 +
Xp2
2ESR (3.6)
A too small ESR value can cause a very high resonance peak. The optimum value of ESR is the same value as Xp, this can be shown by deriving equation 3.6. [3]
By expanding equation 3.6 we get
Zp = ESR
2 +
ESL(C1−C2)2
4C1C2(C1+ C2)ESR. (3.7)
From the equation 3.7 one can achieve ESR = Xp by tuning some parameters.
Normally ESR cannot be changed. Even if a series resistor can be used to increase ESR this would be anti-productive. The extra resistor would also add inductance which increases the impedance for higher frequencies. There are some methods to decrease Xp. One can either use capacitors with small ESL, use the same
capac-itor values (C1= C2) or use capacitors with large values
3.4.1.3 Decoupling with equal capacitor value
As with resistors, the capacitor also has a tolerance rating. The tolerance of a capacitor can vary from -20% to +80%. By using equation 3.7 with two capacitors with a tolerance level of 20% we get
Zp≈ ESR 2 + ESL · 4ε2C2 4C22C · ESR = ESR 2 + ESL · ε2 2C · ESR (3.8)
where ε indicates the tolerance level. A tolerance of 20% is equal to ε = 0.2 [3].If ε is small i.e. deviation between the capacitors is small the second term is almost negligible. The impedance at SRF when choosing same sized capacitors is equal to ESRN , where N = number of capacitors in parallel. A graph of parallel connected capacitors with the same value and a tolerance of 20% is shown in figure 3.16.
Figure 3.16:Same value capacitors in parallel, 20 % tolerance.[3]
3.4.1.4 Printed circuit board capacitance
Multilayer PCB’s often contains of separate layers for power supply and ground, these two layers work as a conductor. The capacitive value depends on the size, layout and material of the PCB [2].
To calculate the PCB capacitance one can use the following equation:
C = E · Er·L · W T (3.9) where E = 0.2249 [F/m] Er= PCB Permittivity L = Length [m] W = Width [m] T = Dielectric thickness [m].
3.4.2
Via inductance
Depending on the stack-up of the PCB and how the vias are connected to the decoupling capacitor there is an additional inductance.
To calculate the via inductance depending on the PCB properties one can use following equation: Lv= µ 2π· 2h · ln 2s d (3.10) where Lv= via inductance [H] µ = via permeability [H/m] h = via length [m] d = via diameter [m]
s = distance between vias [m].
The PCB properties is shown in figure 3.17 [3].
Figure 3.17: Overview of a capacitor mounted on a 6 layer printed circuit board.
3.4.3
Impedance target
As described in 3.4, an ideal PDN would have zero impedance for all frequencies. Since this is not possible in practice, a maximum allowed impedance a circuit can tolerate has to be calculated.
When calculating the maximum step change in supply current, one has to con-sider the worst case scenario. The worst case scenario occurs when all gates switch at the same time in an IC. How to calculate the maximum current peak is show by:
∆I = N CL·
∆V
∆t (3.11)
where
∆I = Maximum current peak [A] N = Number of output pins CL= Capacitive load [F]
∆V = Voltage difference between low and high output [V]
∆t = Smallest value of rise time or fall time [s]. [15]
The impedance of the PDN must be below an impedance target to guarantee that the power supply noise will not exceed the maximum noise the circuit can tolerate. How to calculate the target impedance i shown by:
Zmax=
V · RM
∆I (3.12)
where
Zmax= Maximum allowed impedance [Ω]
V = Supply voltage [V]
RM= Maximum allowed ripple in [%]
∆I = Maximum current peak [A]. [15]
At the frequency where the IC operates the impedance of its PDN has to be lower than the impedance target. It is also important to consider the frequency harmon-ics.
The amplitude of the harmonics is much lower than the fundamental frequency. Therefore the impedance target for the frequency harmonics can be much higher than for the fundamental frequency. The amplitude difference of a 50 MHz square-wave signal and its harmonics i shown in figure 3.19. [15]
3.4.4
Harmonics
All non-sinusoidal signals are built of harmonics, sinusoidal signals with differ-ent frequencies which is shown in figure 3.18. All harmonic frequencies are an integer multiple of the fundamental signal frequency. Fourier series is a mathe-matical method to describe waveform distortion.
Figure 3.18:Square wave build of 6 sine waves with different frequencies.
Fourier series can provide a deeper understanding on harmonics and when they occur. The mathematical expression of a signal can be defined as:
v(t) = a0 2 ∞ X k=1 akcos(kωt) + bksin(kωt). (3.13)
There are two different types of symmetry of a signal, odd and even. Depending on the symmetry the harmonics will occur in different ways.
3.4.4.1 Odd symmetry
For odd signals the variables, ak and bk, in equation 3.13 is defined as:
ak= 0 (3.14) and bk = 4 T T /2 Z 0 i(t) sin(kω1t)dt. (3.15)
The ak and bk is inserted in equation 3.13 to get the representation of a odd
3.4.4.2 Even symmetry
For even signals the variables, akand bk, in equation 3.13 is defined as:
ak = 4 T T /2 Z 0 i(t) cos(kω1t)dt (3.16) and bk = 0. (3.17)
The ak and bk is inserted in equation 3.13 to get the representation of a even
symmetry signal. [14]
3.4.4.3 Square wave
Almost all circuits operate with a clock signal, which is a type of a square wave signal. The harmonics of a square wave signal can be calculated by using equa-tion 3.13 with the variables 3.14 and 3.15. The variable 3.15 can be expanded by: bk = 4 T T /2 Z 0 V sin(kω1t) = −4V kω0T cos(kω1t)|t=T /2t=0 = −4V kω1T cos kω1T 2 ! −cos(0) ! (3.18) and since ω1= 2πT , it can be expanded further by:
bk =
−4V
2kπ(cos(kπ) − 1) = 2V
kπ(1 − cos(kπ)) (3.19)
which gives the result:
bk =
4V
2kπ, k odd. (3.20) By inserting this result into equation 3.13 the total square wave signal is repre-sented by: v(t) = 4V π ∞ X k=1 k odd 1 ksin(kω1t) = 4V π sin(1ω1t) + 1 3sin(3ω1t) + 1 5sin(5ω1t) + ... . (3.21)
which shows that the harmonics occur with an odd multiple of the fundamental signal and each harmonics amplitude decreases with 1/k. The amplitude of the harmonics is defined by:
Amplitude = k · ωf (3.22)
where
ωf = fundamental signal frequency
k = odd integer.[14]
One example of a 50 MHz square wave harmonics amplitude diagram is shown in figure 3.19.
4
Method
This chapter will give the reader the understanding of how we implemented the theoretical background into this thesis task. The chapter will describe how we chose to divide our PCB into different system blocks and which components we used. Beside the system functionality, the chapter will also show how we calcu-lated the impedance target of each integrated circuit and how the simulations and calculations were done.
4.1
Submodule structure design
In order to design the submodule we needed to study the schematics and func-tionality of the already existing test equipment, the break-out box (BoB) versions, the controller area network (CAN) interfaces and the generic surveillance equip-ment (GSE).
The BoB motherboard hardware solution is represented on the GSE simulation module. The submodule is connected to the simulation module through two 160 pin connectors. The connectors provide the submodule with power and required signals, the same way as the BoB motherboard provides the BoB daugtherboard with power and signals.
With that in mind, we wanted to find a way to combine the INVP BoB hardware solution with the KAFAS BoB hardware solution. We also needed to find a way to support the different CAN protocols, FA-CAN, SF-CAN and EQ-CAN.
To make it easier for us to design the submodule, we divided it into three parts. One KAFAS signal processing block, one INVP signal processing block and one CAN interface block. The submodule block diagram is shown in figure 4.1.
Figure 4.1:Submodule block diagram
4.1.1
KAFAS signal processing block
The KAFAS signal processing block was designed to support the KAFAS camera system. The design was based on the KAFAS BoB hardware solution. The key components we used were:
• KAFAS CAM connector • KAFAS ECU connector • I2C accelerator • 2 x EMI filters • Clock multiplexer • 27 MHz quartz crystal • 10-bit LVDS serializer • 10-bit LVDS deserializer
The KAFAS block structure is shown in figure 4.2.
The KAFAS CAM connector and the KAFAS electronic controller unit (ECU) con-nector are used to connect the KAFAS system to the submodule.
The I2C bus between the KAFAS ECU and the KAFAS camera is relatively long due to the cables connected to the submodule. In order to keep the I2C communi-cation stable, we connected an I2C accelerator to the I2C bus. The I2C accelerator enhances the data transmission speed and its reliability. It allows a longer, more
capacitive interconnection between devices without compromising the bus per-formance.
To provide the simulation module with the correct camera signals we used a 10-signal deserializer. It converts the camera serial data to a proper parallel data that the GSE simulation module can process.
In order to provide the KAFAS ECU with a proper signal we used a 10-signal Serializer.
The 27 MHz Quarts crystal is used to deserialize the camera signal in the correct frequency.
To be able to run a different kind of simulation tests, a clock multiplexer was needed. The clock multiplexer is a glitch free, phase-locked loop based multi-plexer with zero delay between input and output. It has two clock signal inputs, the 27 MHz crystal signal and the deserializer reference clock. The reference clock has the same frequency as the sample frequency of the incoming LVDS sig-nal. The multiplexer output one of the clock signals depending on a select-sigsig-nal. The select-signal is controlled from the simulation module.
The electromagnetic interference (EMI) filters we used were Common-mode chokes. The Common-mode chokes were connected to the low voltage differential signal (LVDS) paths in order to reduce EMI noise. How the Common-mode choke works are described in detail in section 3.2.2.
Figure 4.2:KAFAS signal processing block
4.1.2
INVP signal processing block
The INVP signal processing block was designed to support the INVP, NV3 Audi, NV3 BMW and NV3 FIR systems. The design is based on the INVP BoB hardware solution. The key components we used were:
• FIR CAM connector • NIR CAM connector • FIR ECU connector • NIR ECU connector • 4 x EMI filters • 10.519 MHz crystal • 18.5 MHz crystal • Clock multiplexer • 2 x 29-bit LVDS serializers • 2 x 29-bit LVDS deserializers
The system has a similar structure as the KAFAS processing block. The NV3 and INVP camera systems are connected to the submodule through the FIR and NIR connectors.
The differences compared to the KAFAS system block is that the INVP system block runs with other frequencies and uses different serializers and deserializers. To provide the ECU and the simulation module with the correct signals we used a 29-bit LVDS serializers and a deserializers. These serializers and deserializers also have an I2C communication that is connected to the simulation module.
Figure 4.3:INVP signal processing block
4.1.3
Controller area network interface block
The CAN interface block were created to support all three different CAN proto-cols, FA-CAN, SF-CAN and EQ-CAN. The key components we used were:
• D-sub 9 connector • 3 x EMI filter
• 4 x CAN transceivers
In order to support three CAN protocols we used a D-Sub 9 connector. The pin configuration of the connector is described in section 4.7.4.
To convert the CAN communication to suitable signals for the simulation mod-ule we used high speed CAN transceivers. The simulation modmod-ule provides two CAN-nodes for the FA-CAN and one CAN-node each for the SF-CAN and EQ-CAN. Therefore the FA-CAN is divided into two signal paths with a transceiver connected to each one. How a CAN communication work is described in detail in section 3.3.1.
To reduce high frequency noise we connected a common mode choke on each CAN signal path.
4.2
Submodule power distribution
The IC components on the submodule needs in total three different voltages to work properly, 1.8 V, 3 V and 5 V. The 3 V and 5 V power are provided from the simulation module. In order to get a 1.8 V power supply, we used a voltage regulator that converts 3 V to 1.8 V.
To keep the power supplies stable and to prevent high frequency noise we used a ferrite bead together with a 4.7 µF capacitor on the power supply lines. The circuitry was placed near the power supply pins. The circuitry can be seen in figure 4.5.
Figure 4.5:Power supply circuitry
4.3
Simulation module firmware changes
Autoliv’s wish was that the same FPGA firmware used in the BoB could be used in the simulation modules FPGA or that the changes would be minimal. During the time we were designing the submodule we noticed that the simulation mod-ule did not provide the submodmod-ule with enough signals. To make it work we tried to figure out which signal paths could be shared between the KAFAS signal processing block and the INVP signal processing block.
We discovered that some signals could be shared between the two signal process-ing blocks, but it was not enough to use the old firmware without some small changes. The changes that had to be made were to move some connections to other pins on the FPGA.
4.4
Simulation setup
All simulations were done in LTspice IV. LTspice is a free simulation software of electrical circuits, by Linear Technology. This program was chosen due to the performance and the fact that it is free of charge. A test setup in LTspice is shown in figure 4.6.
Figure 4.6:LTspice IV interface.
Before setting up the simulation circuit we had to calculate all things that would affect the decoupling properties.
The inductance of the vias can not be negligible and was therefore calculated. This was done by using equation 3.10. We were not sure on which side of the PCB the capacitors would be placed. Hence we calculated an average value of the via length between the two sides. The length of one via is from the capacitor to the power supply layer. The via length to the power layer is 0.49 mm from one side and 1.08 mm from the other, which gave us the average length of 0.775 mm. The permeability of a via in vacuum is 4π · 10−7[3].
The via diameter used on the PCB is 0.3 mm. The distance between vias was hard to determine before the layout of the PCB was done. We chose to calculate on a placement with one via on the opposite side of the capacitor and fairly close to the capacitor. The length between the vias was calculated to 2.1 mm.
A summary of all calculated values is listed below:
µ = 4π · 10−7 H/m, via permeability
h = 0.775 · 10−3 m, via length.
d = 0.3 · 10−3 m, via diameter.
s = 2.1 · 10−3 m, distance between vias.
By using the equation 3.10 we calculated the via inductance to be:
4π · 10−7
2π · 0.775 · 2 · ln(
2 · 2.1 · 10−3
0.3 · 10−3 ) = 82 nH
The PCB’s ground and power layer behave as a capacitor. Due to its capacitive effects, the PCB will affect the impedance for higher frequencies.
We calculated the plane capacitance by using the equation 3.9.
0.2249p · 4 · 10 · 16
0.0013 = 111 nF
For the simulation we chose a voltage source of 1 V with a 50Ω internal resis-tance.
After all the values had been calculated, we setup up the simulating circuit. The simulation setup is shown in figure 4.7.
Figure 4.7:LTspice setup to simulate decoupling capacitors.
Setup description referred to figure 4.7:
1. Frequency analysis from 100 kHz to 1 GHz with 100 measure points per decade.
2. Via inductance.
3. Decoupling capacitors with internal ESL and ESR. 4. Power source with internal series resistance. 5. PCB capacitance.
4.5
Decoupling capacitor
To be able to guarantee that the power distribution network (PDN) is working properly, we calculated the impedance target for all the circuits. All circuits have been simulated using the software LTSpice. The simulation graph shows how the impedance varies over frequencies from 100 kHz to 1 GHz. We chose the decou-pling capacitors so that the impedance was low enough in the circuits operation region. The harmonics were also put under consideration.
4.5.1
Calculations
This section will describe how we chose the number of decoupling capacitors and their value. We will only show the calculations for the KAFAS deserializer in this section. However the other circuits were calculated in the same manner. The calculations and simulations for all other circuits are shown in Appendix A.3. The KAFAS deserializer has 12 switching output signals with a 15 pF load each. The deserializer operates at 27 MHz and the harmonics we considered according to equation 3.21 was 3 · 27 MHz = 81 MHz and 5 · 27 MHz = 135 MHz. The amplitude above the fifth harmonics are almost negligible and was therefore not put under consideration.
To be able to calculate the impedance target for the KAFAS serializer, we needed to know its maximum peak current. To calculate the maximum peak current we used equation 3.11.
12 · 15 pF · 3.3 V
1.5 ns = 0.396 A
By using the equation 3.12 and the deserializers maximum peak current we cal-culated the impedance target to be:
3.3 V · 0.05
0.396 A = 0.42Ω
The circuit data sheet recommended that a 100 nF and a 1 nF capacitor should be placed at each supply voltage pin. Combining these two capacitors causes an unwanted resonance peak.
By using our simulation setup we achieved low enough impedance with two 10 nF capacitors in parallel instead. The simulation result is shown in figure 4.8.
Figure 4.8:KAFAS deserializer simulation, two 10 nF decoupling capacitors
The impedance for the fundamental frequency as well for the harmonics are lower than the impedance target. No resonance peak will occur.
4.6
Schematics
All schematics have been drawn in DxDesigner, which is an schematics editor from Mentor Graphic. The DxDesigner interface is shown in figure 4.9, contain-ing a simple test schematic.
Figure 4.9:Example circuit drawn in DxDesigner.
DxDesigner is used as one of the primary schematics software at Autoliv and was therefore requested. After figuring out how all blocks should be connected we started a new schematic. To fit all components we created 5 pages, one for KAFAS, two for INVP and 2 for connections. We started to place all key components for each block and connecting them together. All components that were chosen had to be in Autolivs component database. A few components that we wanted was not in the database and had to be requested. A request imply that the component gets an internal part number followed by a schematic symbol and layout footprint.
