Analysis of noise and offset in the comparator of ananalog-to-digital converter

Institutionen för systemteknik

Department of Electrical Engineering

Examensarbete

Analysis of noise and offset in the comparator of an

analog-to-digital converter

Examensarbete utfört i Elektroniksystem vid Tekniska högskolan i Linköping

av

Annie Rydholm LITH-ISY-EX-ET--08/0351--SE

Linköping 2008

Department of Electrical Engineering Linköpings tekniska högskola

Linköpings universitet Linköpings universitet

Analysis of noise and offset in the comparator of an

analog-to-digital converter

Examensarbete utfört i Elektroniksystem

vid Tekniska högskolan i Linköping

av

Annie Rydholm LITH-ISY-EX-ET--08/0351--SE

Handledare: Christer Jansson

Sicon semiconductor

Examinator: Mark Vesterbacka

isy, Linköpings universitet

Avdelning, Institution

Division, Department

Division of Electronics System Department of Electrical Engineering Linköpings universitet

SE-581 83 Linköping, Sweden

Datum Date 2008-08-26 Språk Language ¤ Svenska/Swedish ¤ Engelska/English ¤ £ Rapporttyp Report category ¤ Licentiatavhandling ¤ Examensarbete ¤ C-uppsats ¤ D-uppsats ¤ Övrig rapport ¤ £

URL för elektronisk version http://www.es.isy.liu.se http://adressadressadress ISBN — ISRN LITH-ISY-EX-ET--08/0351--SE

Serietitel och serienummer

Title of series, numbering

ISSN

—

Titel

Title Analysis of noise and offset in the comparator of an analog-to-digital converter

Författare

Author

Annie Rydholm

Sammanfattning

Abstract

Since digital system has become very common today it is important to have good interfaces in between the analog and digital domain. This puts high demands on the analog to digital converter. It is therefore important in the design of the analog to digital converter to reduce noise and offset as much as possible. That is also what this analysis is going to consider but in a comparator which is a crucial part of the analog to digital converter. The comparator consists of a preamplifier and a latch and it is the preamplifier that will be studied here. The analog to digital converter in consider is of PSAR structure. Some other structures will also be mentioned in the first part together with some noise theory.

Nyckelord

Abstract

Since digital system has become very common today it is important to have good interfaces in between the analog and digital domain. This puts high demands on the analog to digital converter. It is therefore important in the design of the analog to digital converter to reduce noise and offset as much as possible. That is also what this analysis is going to consider but in a comparator which is a crucial part of the analog to digital converter. The comparator consists of a preamplifier and a latch and it is the preamplifier that will be studied here. The analog to digital converter in consider is of PSAR structure. Some other structures will also be mentioned in the first part together with some noise theory.

Acknowledgments

I would like to thank my supervisor Christer Jansson and employees at Sicon semiconductor for sharing their knowledge and information. I would also like to thank my examiner Mark Vesterbacka and his colleague Kent Palmkvist. At last I would like to thank friends, family and everyone else who has helped and supported me during this project.

Contents

1 Introduction 1

2 Background 3

2.1 Introduction . . . 3

2.2 The tool MATLAB . . . 4

3 Theory 5 3.1 Analog front end . . . 5

3.1.1 Sicon A/Dvance and digital imaging . . . 5

3.2 General ADC theory . . . 6

3.2.1 Sample and hold . . . 7

3.2.2 A typical comparator structure . . . 8

3.2.3 Delta-sigma ADC . . . 9

3.2.4 Single- and multi-slope ADC . . . 9

3.3 Offset and noise in the ADC . . . 15

3.3.1 Noise from the MOSFET . . . 15

3.3.2 Amplifier noise model . . . 16

3.3.3 Offset cancellation in the comparator . . . 16

4 Specific theory according to study 19 4.1 Sicon A/Dvance . . . 19

4.2 The PSAR architecture A/DvanceII . . . 19

4.2.1 ADC-slice . . . 20

4.2.2 The comparator in one ADC-slice of A/DvanceII . . . 20

5 Practical Part 23 5.1 A model of the AFE . . . 23

5.1.1 Time propagation model . . . 25

5.1.2 Time model calculations . . . 25

5.1.3 Correction term model . . . 28

5.2 Gain stage . . . 29

5.2.1 Charge analysis . . . 29

5.3 Gain stage . . . 30

5.3.1 MATLAB modeling . . . 31 ix

x Contents

6 Summary 33

Bibliography 35

A Correction term 37

Chapter 1

Introduction

This report is a bachelor thesis project report with the purpose to describe the 10p/15hp, or 10 week, bachelor thesis project mandatory for the educational pro-gram ”Bachelor of Science in Engineering Electronics” at the Institute of Tech-nology, Linköping University. The project has been performed at the company Sicon Semiconductor with Christer Jansson as supervisor. Examiner is Professor Mark Vesterbacka at Electronics Systems, Linköping University. This report is a description of the project and will include some background theory about analog to digital converters in general followed by a description of the project.

The purpose with this project is to study noise and offset in the gain stages of the comparator of an Analog to Digital Converter (ADC) within the Analog Front End (AFE) A/DvanceII by Sicon Semiconductor. The aim is to understand how the correction circuit is affecting the design. The correction is applied in each of the gain stages to suppress noise and offset and is investigated and modeled with respect to offset and noise in the gain stage. To achieve this, understanding of basic theory is needed. Therefore this report will consider some basic ADC theory at first. The next phase is to design models of the gain stages and find expression for those models. Implementation in MATLAB will also be considered. In the following text, abbreviations will be marked by capital letters in the considered word followed by the abbreviation of the word surrounded by parenthesis. Logical one and logical zero will be written as ’1’ and ’0’ respectively.

Chapter 2

Background

2.1

Introduction

Many systems of today that previously operated in analog domain has been re-placed by digital systems. There are several reasons for that. Some of the ad-vantages with a digital system, compared to an analog with the same basic func-tionality, is that the power consumption and the size of the system often can be held much lower in a digital system. Along with this there is other possibilities for error correction in a digital system than in an analog. Since digital systems has been more and more common, good interfaces in between analog and digital domains needs to be implemented.

Data conversion interfaces between analog and digital domains are found in dig-ital applications with analog input signals. examples of products using digdig-ital interfaces are equipment for medical imaging, instrumentation, industrial control, speech processing and radar. The demands on the ADC interfaces must meet up to the specific requirements needed for each application. Other examples of digital interface products are consumer product such as telephones, camcorders, modems and high-definition televisions (HDTV). There is a large, and growing market for home theater equipment and other products with analog to digital in-terfaces. Along with the growing market, demands on the product performance has increased and techniques for improving the products evolved with that. For digital imaging it is desired to increase the pixel resolution and color dynamics. Factors to keep in mind when designing interfaces is to meet the requirements of speed for the application, to lower the power consumption, to decrease the area and still be able to offer a good price. Depending of the product requirements, a trade off between these design parameters will be needed. [1] and [10].

4 Background

2.2

The tool MATLAB

For the part of the project where the offset is modeled, MATLAB has been used. MATLAB is a tool used in many universities and industries, commercially available since 1984. MATLAB can be run from several platforms, for example Windows, Linux, Macintosh and Sun workstations. MATLAB is an acronym for MATrix LABoratory. As the name indicates, MATLAB is used for matrix computations. The core of the program consists of C-coded routines for matrix computations, providing an interactive environment for technical computations. Running MAT-LAB by typing commands in the command window is possible, but the users are also able to define their own functions in m-files. The m-files are plain text files with the extension .m and can be opened in a text editor. Predefined functions built in the kernel are also provided. The built in functions and m-files are gath-ered in several toolboxes, both commercial and free, for different fields of use in applied science and engineering. There is for example toolboxes for signal pro-cessing, simulation and control theory. A toolbox is a collection of standard or specific application oriented m-files. Predefined functions in MATLAB provides a help text, defining how to use the function when typing ’help’ followed by the name of the function in the command window. The help text defines how to use the function [5].

Chapter 3

Theory

3.1

Analog front end

Transferring analog data to a digital representation requires a good interface be-tween the analog and digital domains. Keeping noise and offset in this interface low is very important since errors added by the interface may be able to effect the whole system in a negative way. Since the ADC is the crucial part in the interface, the largest part of this chapter will be dedicated to ADC theory.

The AFE, or the interface between the analog and digital domains of the system, contains one or several ADC’s. The ADC is a crucial part of the interface since it is in the ADC where the analog to digital conversion takes place. For different types of digital systems there are different demands regarding the functionality of the ADC. It is therefore important to choose an ADC architecture that is able to fulfill the most important requirements of the design. Cost, area, power consumption and speed are exemles of parameters to design for and such parameters will vary with different ADC architectures. Since the analog signal is processed through this interface, errors added in or before the interface will follow the digital signal and therefore affect the whole digital system. Reducing errors in the interface is therefore important and that is also why it is interesting to develop the design with error correction and suppression of offset and noise.

3.1.1

Sicon A/Dvance and digital imaging

Human color perception can be represented by the sum of a weighted value of each of the three basic colors red, green and blue (RGB). In digital imaging, a color is coded into sets of bits representing each RGB color intensity value. With the

6 Theory

depth of 8 bits, each color can be represented by 28_{= 256 levels. The more bits per}

pixel in an image, the larger is the amount of information that can be transferred. The demand for higher resolution and color dynamics is constantly increasing and the growing market for home theater equipment is one factor responsible for that. Sicon Semiconductor A/Dvance is a product family of ADC’s and AFE’s. A/Dvance is suitable for image applications, for example computer graphics and interface for flat panel projection, this due to the fact that the A/Dvance has good performence in color, graphics resolution and power consumption.

In this project an ADC will be considered. The stand alone ADC in the A/Dvance family has a low power consumption and high bandwidth input buffer. Today, the Sicon A/Dvance AFEs provides up to 10-bit graphics interfaces with very low power consumption. The conversion method used is time interleaved Succes-sive Approximation Register (SAR), also called Parallel SuccesSucces-sive Approximation Register (PSAR) and a key advantage of this solution is that it can be implemented with CMOS technology. [1]

3.2

General ADC theory

A digital system uses discrete values for the signal representation while analog systems uses time continuous signals. Measured signals in our environment can represented by voltages continuous in time and it is in the analog-to-digital con-verter these signals are translated from analog to digital. In this section different conversion methods and ADC architectures be briefly described.

First of all the input signal must be bandwidth limited, that is removing undesired frequencies with a low-pass filter so that subsequent sampling does not alias any unwanted signals into the actual signal band. Then the signal is quantized in the time domain, using a sampling circuit. The signal is also limited in amplitude by a quantizer so that the signal can be represented by fixed amplitude references. A decoder is used to convert the amplitude references as a function of the discrete time to binary representation [10].

According to the Nyqvist theorem the input signal must be sampled at a rate of at least twice the maximum frequency component in the signal in order to preserve all the information of the input signal so that the sampled signal can be fully recovered. If the input signal is not limited, folding will occur [4]. Sampling according to the Nyquist theorem. ADC’s fulfilling this criteria is referred to as Nyquist-rate ADC’s. When oversampling, undesired noise and distortion will occur and it can be removed by filtering. The demands on the ADC differs with the applications, therefore characteristics of the analog signal and requirements of the digital signal must be considered when deciding what type of ADC to use in a design. Further design aspects next to higher speed, smaller sizes and lower power consumption are to achieve high accuracy, low circuit complexity and high

3.2 General ADC theory 7

resolution. The resolution is dependent of the number of bits in the ADC [9]. In Figure 3.1 a coutinious-time signal, illustrates an analog signal. That signal is

sampled with the period Tsand quantized in amplitude. After that the signal in

the figure can for exemle be represented with the 2-bit binary sequence "00 01 10 11 10 01 00". Other schemes for the digital encoding than in this exemple can also be used for representation of the digital signal.

A m p l i t u d e t i m e T s 0 0 0 1 1 0 1 1 b 0 b 1 B i t e n c o d i n g

Figure 3.1. The continuous-time signal is illustrating an analog signal. The

discrete-time, amplitude quantized samples are representing that signal digitally.

3.2.1

Sample and hold

When converting the analog signal to a digital, the first step is to make the signal step-wise constant in the time domain before quantization. To achieve that a

Sample And Hold (S&H) circuit is used. The open loop sample and hold circuit

might look like in Figure 3.2. When the switch controlled by the sample clock is

closed, the buffered input value is going to charge the capacitor CHOLD. When

the switch is opened again, the charged value at CHOLD will give the level of the

buffered output value.

The signals from a S&H circuit can be described as first letting the analog signal

be sampled with the period time Ts. After the quantization in time, the signal is

also quantized in amplitude which is illustrated with the discrete values in Figure 3.1. The time and amplitude quantized samples can then be represented with, in this example, a two bit binary code for the four levels of the digital signal in

Figure 3.1. An ideal ADC with N-bit resolution can represent 2N _{analog levels}

8 Theory

A sampling scheme that can be used are track-and-hold, where the output sig-nal from the sample-and-hold circuit follows the asig-nalog input sigsig-nal when not in the hold mode. Another sampling scheme is sample-and-hold where the signal is constant in amplitude instead of tracking the analog signal [10][7].

S a m p l e c l o c k

V V

I N O U T

C

H O L D

Figure 3.2. A simple open loop sample-and-hold architecture

3.2.2

A typical comparator structure

Comparators are characterized by their voltage gain and their slew rate. The comparison is producing a ’1’ or ’0’ depending on the polarity of the given input. A typical ADC comparator structure consist of a preamplifier and latch as shown in Figure 3.3 . The characteristics of a non-ideal comparator can be approximated to the characteristics of a high-gain amplifier [4].

P r e -a m p L a t c h C l k V i n 1 V i n 2 V o u t C l k

3.2 General ADC theory 9

3.2.3

Delta-sigma ADC

Delta-sigma ADC’s are oversampled (i.e sampled faster than the Nyquist-rate) and noise-shaping converters. The basic structure is illustrated in Figure 3.4 and consist of a comparator with a feedback loop to the negative input of the input amplifier. The feedback signal will be subtracted from the input signal and the resulting signal is amplified and integrated before the comparator. After that, the signal is fed to the negative input of the comparator. The digital output data is taken after filtering the output of the comparator with a digital filter. An advantage of this architecture is high precision, but at a quite low sampling rate. Mobile phones and HIFI-products are two examples of where this modulation method often is used [8] [9] [7].

A M P + -D i g i t a l F i l t e r 1 - b i t D A C + -1 - b i t s e r i a l d a t a V i n D i g i t a l o u t p u t d a t a

Figure 3.4. Delta-sigma ADC

3.2.4

Single- and multi-slope ADC

The dual-slope ADC works by performing an integration of an unknown input signal followed by an integration of a known reference signal of opposite polarity. The unknown signal level is then determined by using the time difference between the two ramp signals. The dual-slope ADC operates during two phases. A counter can be used to determine a fixed time interval for each of the two phases. Running

the counter for 2N _{clock cycles yields T}

1 = 2NTclk, the first time period. The

signal −Vinis assumed to be constant during conversion.

During the first period, the switch S1 is connected to −Vin and the switch S2 is

open. The node Vx, assumed to initially be zero, will ramp up to a magnitude

proportional to the magnitude of Vin. At the end of the first phase, the signal at

the node Vx will be equal to VinT1/R1C1. In the beginning of the second phase

10 Theory - V_{i n} V_{r e f} -+ -+ V_x b 1 b 2 b n C o n t r o l l o g i c C o u n t e r S₁ S₂ S₁ S₂ C l k B_{o u t} C o m p a r a t o r I n t e g r a t o r R₁ C₁

Figure 3.5. A dual-slope ADC [8]

interval T2will be determined by

T2= 2NTclkBout (3.1)

where Bout = b12−1+ b22−2+ . . . + bN2−N. The two phases are related as

T2= T1

Vin

Vref (3.2)

Combining 3.1 with 3.2 Bout = Vin/Vref. The conversion speed for this type of

converter is slow, but with high resolution. This type of ADC’s is typically used for instrumentation [8] [4].

The single-slope ADC is constructed and used similarly to the dual-slope but the single-slope ADC operates with a single, fixed slope for a complete measurement. This ADC is faster and less expensive than the dual-phase, but not as accurate

[4]. To make the structure in Figure 3.5 a single slope converter, the switch S1

is connected to Vref and the input signal is moved to the comparator. The reset

switch S2 is closed until the start of a conversion when the reset switch opens

and the signal at the node Vxis a constant slope voltage ramp. A binary counter

counts until the voltage at Vx is equal to the input signal. The counter value at

that point will give the digital representation of the analog input signal value.

Flash converters (parallel ADC)

Flash converter is the standard approach for realizing high speed converters. The reference signal is fed to the converters through a resistance ladder and the input

3.2 General ADC theory 11

signal is connected directly to the comparators as shown in Figure 3.6 [8]. The

m-bit flash ADC structure requires at minimum 2m_{− 1 comparators [4]. The}

resistance ladder provides a set of voltage reference levels.

D e -c o d e r D i g i t a l O u t p u t A₂ A₁ A_j A_{j + 1} V_j V_{j + 1} V_{R E F} V_{i n} m 2 C o m p a r a t o r s

Figure 3.6. An m-bit flash ADC [10].

Each comparator can be illustrated as a clocked system consisting of a preamplifier and a latch. The clock signal responsible for enabling the amplifier is inverted to the latch. When the amplifier tracks the input signal the latch is disabled. During the next clock phase the preamplifier is disabled and the latch is enabled and generates the logic output signal to the decoder. Because of that, the flash ADC do not need a S&H circuit at the input, at least for converters with low resolution. The comparisons are performed in parallel and the conversion speed will therefore be high. However, designing a 10-bit ADC requires at least 1023 comparators. It is possible to fit that number of comparators on single silicon chip, but this high number of comparators will take a large amount of area and also make the power consumption high. An issue is that the large number of comparators connected to the input node generates a large parasitic load. This decreases the speed. To solve that problem in the flash ADC, a buffer can be added to drive the input signal. Adding a buffer will help the speed increase but at a cost of even higher power consumption. Flash ADC’s can be constructed with a very high conversion rate since each comparison is completed during one clock cycle. The input amplifiers can be reduced using an interpolating structure. The number of comparators can be reduced by using a folding structure. [8] [10] [6].

12 Theory

Successive approximation register

With the Successive approximation register (SAR) structure it is possible to realize ADC’s with a medium conversion rate as the same time as the complexity of the circuit is kept low. An advantage is low power consumption. The comparator can be designed for high-speed operation, and high resolution.

V_{r e f} S & H + -C o n t r o l L o g i c S u c c e s i v e -a p p r o x i m -a t i o n r e g i s t e r b1 b2 b N D A C V i n Bo u t V D A C V_H

Figure 3.7. A SAR block diagram.

2 V ref t A m p l i t u d e V H V D A C

Figure 3.8. An n-bit example of the output signal from the DAC in a SAR converter

where n = 10.

The functionality of the SAR can be described with the algorithm ”binary search”. In Figure 3.7 a n-bit SAR is illustrated. The comparator compares the digital signal from the SAR register with the analog input signal. In the start of the conversion, the Most Significant Bit (MSB) is set to ’1’ in the register and all the

3.2 General ADC theory 13

For a 10-bit SAR example, using Vref = 11111111112(204710) comparison starts

with Vref/2 = 10000000002 (102410). If the analog input is smaller than the

output of the DAC, the current bit (the MSB) is set to ’0’ otherwise the ’1’ is kept. This procedure is repeated for the rest of the bits, continuing with the next most significant bit until all the bit has been set to ’0’ or kept as ’1’. For Figure 3.8

together with a 10-bit structure like in Figure 3.7 the Boutwould be ’0010110010’

when the conversion is finished with the MSB at the leftmost position [8] [10] [9].

Two-step (subranging) ADC

The operation of a two-step, or subranging, ADC is divided into a course and a fine phase. As illustrated in Figure 3.9 , first a course digital value of the analog input is obtained generating the MSB’s. This value is converted back to analog

and subtracted from the input signal. The residue signal, Vres is then eventually

amplified before it is applied to a fine ADC with a resolution of N −K bits. This is often used for high speed converters with medium accuracy. For the flash converter power and area can be saved, using this architecture. The reason of that is the need of fewer comparators. For a 10-bit flash ADC in parallel structure previously described, the number of comparators needed would at least be 1023 but for a 10-bit subranging flash ADC the number of comparators needed in the structure

is 2 · 25_{= 64 with a 5-bit course ADC and a 5-bit fine ADC [8] [10] [9].}

C o u r s e A D C D A C V i n b 1b2 bK + V D A C A m p F i n e A D C b K + 1 b K + 2 b N V r e s

-Figure 3.9. A two-step (or subranging) ADC

Pipelined ADC

Pipelining is used in order to achieve higher speed where several operations must be performed serially. A two-step architecture can be generalized to multiple stages where each stage has only one or a few bits precision. A general pipelined structure is shown in Figure 3.10. The analog input signal is processed through the first stage, first through the S&H circuit before the k-bit ADC in the stage. The input signal is thereby kept constant until the MSB(s) are determined. The value of the most significant bits after the ADC is converted back to analog by the DAC and subtracted from the analog input value. The the analog result after the subtraction is then amplified before the next stage and fed to the S&H of the

14 Theory

next stage where the same procedure is repeated. The procedure is repeated for the remaining stages until the last stage where the LSB(s) are given directly from the ADC in the last stage. Through this method a new sample can be processed each clock cycle so that the total speed will increase. [8] [10] [9].

S t a g e 1 S t a g e j S t a g e N -+ k - b i t A D C k - b i t D A C A S & H I n p u t M S B ( s ) L S B ( s ) b i t ( s ) f r o m s t a g e j

Figure 3.10. A general pipelined ADC structure. [9][10]

Interleaved ADC

Another way to achieve higher speed at a relatively low complexity is to use time

interleaving. In Figure 3.11 the clock rate of φ0is running M times the rate of φ1

to φM. When realizing an interleaved structure, more N-bit ADC’s are added. [8]

The A/DvanceII PSAR is an interleaved architecture.

S & H S & H S & H S & H N - b i t A D C N - b i t A D C N - b i t A D C D I G -I T A L M U X V i n D i g i t a l_{o u t p u t} O 0 O 1 O 2 O M

3.3 Offset and noise in the ADC 15

3.3

Offset and noise in the ADC

Noise is often defined as a random signal. Pseudo random noise is considered to be switching noise, clock leakage, or other systematic noise from the circuit. In an integrated circuit the flicker noise (1/f) is a major noise source along with the thermal noise [9].

Since noise and offset will affect the ADC, it is important to find methods to correct for it in order to get rid of as much of the unwanted disturbances as possible. An error model can be helpful when finding the major noise sources and to see how they affect the system to be able to remove noise at crucial parts.

3.3.1

Noise from the MOSFET

The MOSFET transistor will contribute with noise to the circuit. The comparator within the ADC in A/DvanceII is designed with MOSFET transistors. The noise added by the MOSFET can be divided into three principal sources. The three principal sources are shot noise, thermal noise and flicker noise [3]. The shot noise

appears because of leaking currents through the SiO2 gate to the source. More

significant for the MOSFET noise model are the flicker noise and thermal noise sources. The flicker noise, also called 1/f noise, can be modeled with a voltage source in series with the gate of the MOSFET or a current source from the drain to the source [8]. The flicker noise current can be expressed as

If l=

Kf lIDQAF

f CoxW Lef f

(3.3)

where Kf l is a coefficient for the flicker noise, IDQAF is the quiescent drain current

to the power of the constant AF. W is the channel width and Lef f is the effective

channel length. Coxthe gate oxide capacitance[3] and f the frequency.

The thermal noise drain current can for the active region be expressed as

Ith2(f ) = 4kT

2

3gm (3.4)

The total noise power at the output of the drain-source channel can be expressed as

I2

no= Ith2 + If l2 (3.5)

16 Theory

3.3.2

Amplifier noise model

An amplifier with a voltage gain Av qnd with internal and external noise sources

can be modeled with the noise sources referred to the input of a noise-free amplifier.

The total noise at the output port can be expressed as E2

no= A2vEi2where Ei can

be considered to consist of the thermal noise source and amplifier noise source. This expression can be used to represent the noise voltage source at the input node of the amplifier, i.e. like following

Ei2= E2 no A2 v (3.6) With uncorrelated sources, that is when noise voltage are produced independently,

the equivalent input noise, E2

nican be expressed as

E2

ni= Eth2 + En_amp2 + In_amp2 Rs2 (3.7)

Where Eth is the thermal noise source, En_amp the amplifier noise source, Rs is

the input resistance. For correlated noise sources a correlation term can be added to (3.7) . For modeling purposes it can be advantageous to express all the noise that an amplifier produces into two noise sources. In figure in Figure 3.12 , with

the voltage source En and current source In at the input of the amplifier.[3]

+ -N o i s e l e s s A m p l i f i e r * * + -i n V + -o u t V E I n n

Figure 3.12. Amplifier model with voltage and current noise sources[3].

3.3.3

Offset cancellation in the comparator

Mismatches of MOS devices in CMOS circuits will generate offset. There are several offset cancellation techniques for CMOS and BiCMOS circuits. Consider an ADC comparator structure consisting of a preamplifier stage and a latch. With a low offset in the latch, the preamplifier does not have to have a high gain. Thereby the amplifier can be optimized for speed and power dissipation. To use offset-canceled latches is one technique for reducing the offset in the latch and thereby in the comparator. Techniques where the basic idea is to store and subtract

3.3 Offset and noise in the ADC 17

the errors from the input signal can be used to reduce offset in the preamplifier. Some of the techniques are Input Offset Storage (IOS), Output Offset Storage (OOS) and multistage offset storage. Another technique is cancellation of offset using an auxiliary amplifier and this technique will be further described. There is also several methods for correction of nonlinearities as well as methods for digital correction [10].

Offset cancellation with an auxiliary amplifier

Consider an ADC structure consisting of a preamplifier stage and a latch. Let us start with the preamplifier. The offset in an operational amplifier referred to the input will cause different nonlinearities. Adding an auxiliary amplifier, the signal path from the offset storage capacitors will be isolated while canceling the offset from the main amplifier. The basic idea is to let the error be stored and removed from the input signal that is overlayed by the error signal.

The circuit in Figure 3.13 operates in two phases. In the first phase, the switches

S1−4 are on while the switches S5 and S6 are off. In this phase, phase one, the

gm2R loop is closed. The output value at a zero input is during phase one stored

over the capacitors. During amplification of the input signal in phase two, only

S5 and S6 are on while the rest of the switches are open. During phase two, the

offset value stored at the capacitors is added to the input signal through gm2. The

input signal is inverted through gm1. gm2adds a dc component at the output so

as to cancel the offset [10] .

+ + -g_{m 1} + + -R + + -g_{m 2} S 1 S 2 S 5 S 6 S 3 S 4 V i n V o u t

Figure 3.13. Offset cancellation with an auxiliary amplifier [10].

A method to calculate the residual offset of the circuit is to consider the gm2R

as open, as during phase two, and the inputs of both gm1and gm2 connected to

ground, corresponding to a zero input signal. The offset here denoted as VOS1

and VOS2 will be amplified by their gain factor gm1 and gm2 respectively. Then

18 Theory

negative feedback reduces gout by a factor approximately equal to gm2R. The

overall offset at the output is expressed by (3.8 ) and can be referred to the input, as for the noise model in Figure 3.12 by division of the gain of the forward amplifier,

gm1R. The equivalent input offset is expressed by 3.9 [10].

Vout =gm1RVOS1+ gm2RVOS2

gm2R (3.8) VOS_EQIN = VOS1 gm2R+ VOS2 gm1R (3.9)

Chapter 4

Specific theory according to

study

4.1

Sicon A/Dvance

Designing ADC’s with high resolution and speed as well as low power and cost, Sicon provides an AFE for computer graphics interfaces at present with 10 bits per color. Sicon A/Dvance ADC and AFE product family provides stand alone ADC’s and also monolithic application specific analog interfaces for capturing analog graphics signals from DVDs, cameras, set top boxes, personal computers and workstations. The resolution has increased from 8 bit to 10 bit and the architecture is based on time interleaved successive approximation. [1]

4.2

The PSAR architecture A/DvanceII

The A/DvanceII is time interleaved. In Figure 4.1 an M-channel PSAR architec-ture is illustrated. The block OEC is for Offset Error Correction. The number of channels is equal to 14 and the channels are referred to as ADC-slices. This design has been implemented in 150, 130, 90 and 80 nm CMOS processes [9]. The max-imum sample frequency is 270 MHz. The resolution is 10 bit. The conversion is divided into a course and a fine period where the five MSB are determined during the coarse period and the five LSB during the fine period. Since the architecture is clocked with 14 clock cycles this leaves four clock cycles for each ADC-slice where no conversion is made. In the start of each clock period a reset is made during the first clock cycle, then about two clock cycles are dedicated to calibration, with one clock period for sampling the input signal, and will from now on be referred

20 Specific theory according to study

to as the correction phase.

It is essential for the comparator within each channel to be matched. Different offset in different channels because of unmatched channels will cause problems. A dc offset in only one channel will every M’th time be responsible of producing a digital word that differs from the desired output signal, assuming a constant input

signal. A tone at fs/M where fsis the sampling frequency will be caused. With

a different offset added by each channel a repetitive pattern would appear. Tran-sistor matching and offset suppression in each channel is therefore very important when interleaving [1]. S A R A D C s l i c e M - 1 B U F F E R S A R A D C s l i c e 1 D I G -I T A L M U X V i n D i g i t a l o u t p u t C l k R e f S A R A D C s l i c e 2 S A R A D C s l i c e M O E C D E -M U X

Figure 4.1. The A/Dvance PSAR architecture [9]

4.2.1

ADC-slice

In the time interleaved PSAR structure, each ADC-slice will compute a sample but the slices will not operate parallel in time. After calibration, the first ADC-slice is starting to compute the first sample value while the next ADC slice is finishing its calibration and so on that there is one ADC-slice taking a sample each clock period. The signals are multiplexed at the output to a single digital output [9].

4.2.2

The comparator in one ADC-slice of A/DvanceII

In the comparator, the decisions how to represent the output from information of the input and reference signal are made. It is therefore important that the comparator interprets the signals correct. The comparator in the A/DvanceII is a four stage comparator consisting of three gain stages followed by a latch.

4.2 The PSAR architecture A/DvanceII 21

Since the gain stages are designed in CMOS technology the MOSFET transistors will contribute with thermal noise and flicker. Perfect matching is theoretically possible, but in practice a mismatch will lead to undesired offset voltage. Noise and offset within the preamplifier can be suppressed by adding correction. The comparator is clocked with a period of 14 clock cycles for each sample, but since the structure is a PSAR (Figure 4.1) the first sample will be processed in the first ADC-slice and then the next sample in the following ADC-slice and so on. Each sample period starts with a reset of the comparator, after that a correction phase follows. During the correction phase, the resulting offset with zero input signal will appear at the output. After the correction phase the signal is sampled and five coarse comparisons followed by five fine comparisons are made before the output is available to the latch. The latch will interpret the signal and a voltage level will be available at the output.

Each gain stage in the preamplifier is designed with an internal correction circuit which will sense the offset during the correction phase. The transistor implemen-tation of the first stage differs from stage two and three. The first stage need thick oxide transistors at the input. The reason for this is because the input signal is stored at sampling capacitors that the first stage must connect to. During the first clock cycle a reset will be made, after that about two clock cycles is given for the correction to settle, then another reset is made during the sampling of the signal. Actually this reset is delayed in time for each of the three stages but this has been ignored in this project. The input is then switched from zero to the actual input value through an array of capacitors. The ten following clock cycles are dedicated to the successive approximation. In the actual circuit the first gain stage of the preamp is designed with larger transistor width to increase the accuracy. In this project the same simplified circuit, but with different transconductances for each of the stages will be used to represent the gain stages. Information in this section has been provided by Christer Jansson and [2].

It is common to design a high speed comparator with a preamplifier stage fol-lowed by a track-and-latch stage, as shown in Figure 3.3 . Thechnology used for this implementation is often CMOS [1]. Figure 4.2 shows a simple model of the A/DvanceII latch. The gain stages before the latch are further described in the next chapter. The gain stages are added in order to amplify the signal so that for example offset in the latch will have less effect on the decision made by the latch. After a reset is made the latch couples the signal to Vdd or Ground depending on the voltage level of the input signal. The latch is clocked in contra-phase to the preamplifier before.

22 Specific theory according to study r s t v n B i a s v i n P v i n M r g P r g N

Chapter 5

Practical Part

5.1

A model of the AFE

The purpose with the practical part in this project is to make a model that includes the noise and offset sources in the preamplifier before the latch in a comparator in the AFE A/DvanceII. The comparator is a part of one ADC slice in the A/Dvance PSAR architecture and consists of a preamplifier followed by a latch. The pream-plifier consists of three ampream-plifier stages in cascade. The three cascaded stages with added offset sources is mathematically modeled in order to find out how the correction within each gain stage is suppressing the offset. The calculations were limited to consider only offset sources in this project. To do similar calculations like for the offset, but also with noise sources added could be considered, but will be left out here. The equivalent input offset has been found and a suggestion is instead to overlay the offset terms by the noise sources such as thermal noise and flicker noise. The input signal to the preamplifier is a time discrete signal consisting of several samples. In each stage of the preamplifier, the offset is sensed during the correction phase and then cancelled from the input signal.

The first part of the modeling is to find a general expression for the correction

term for one of the three gain stages that the preamplifier consists of. The transfer

function is also needed. After that, that calculation model is evolved to consider more stages. The next correction term dependent of the previous term and the output value is also expressed.

Since the three stages can be different internally, the time it takes for a signal to propagate through one stage can differ from the other. Therefore it is also needed to express the propagation time through one stage as well as several. Since the propagation time of the signal value from the input to the output of each of the gain stages is time dependent hence a time dependent model will also be useful. Note

24 Practical Part

that it is the offset stored from the previous value that will be used to cancel the offset from the next input sample. This will have the effect that the compensation need a certain time to settle before this operates with greater perfection. Since the frequency is in the range of hundreds of megahertz, running a couple of samples before calibration has settle would not really affect the functionality too much and only during a very short time initially.

The expressions will then be modeled in MATLAB. An attempt to modify a matlab model of the AFE by Bengt E Jonsson, ADMS Design AB, has been made. Figure 5.1 shows the hierarchal tree of the functions in that ZAFE2 MATLAB model. The modified functions are marked with a dotted line and a new function with a dashed line. Not only the gain stage, has been modified. The ADC slice function has been modified to call the new function, ”Corr”. The function ”Corr” is supposed to calculate the correction values. The correction values are after calculation stored and used in the ”Comparator” function, slightly modified to suit the new ”Gain stage” function. The ”Gain stage” function has been modified to include terms of offset. These parameters could additionally be modified to also include terms of flicker and thermal noise but from this point only the offset is considered. Since the calculation is made on an architecture with tree gain stages, the restriction in the MATLAB model to only use three gain stages in the ”Gain stage” function is used. Previously the ”Gain stage” function were called one time for each stage. This change will have the effect that the number of gain stages is not able to be overridden as in the original version.

I n p u t A F E f u n c t i o n A D C f u n c t i o n A D C S l i c e f u n c t i o n C o m p a r a t o r f u n c t i o n G a i n s t a g e f u n c t i o n L a t c h f u n c t i o n C o r r e c t i o n f u n c t i o n

5.1 A model of the AFE 25

5.1.1

Time propagation model

The gain terms Agx and Acx in the expression for the correction term will be

dependent of time for the amplification which in turn is dependent of the sample time, Ts. For the correction phase this time will be longer than for the evaluation phase. In ”Appendix B - Propagation time” the propagation behavior through a series of stages is calculated. To get a time dependent model, each stage is considered as an output capacitance in parallel with the output resistance and an input dependent current source.

During the correction phase and active phase the gain stages has for each of the phases different amount of times to amplify the values since the system is clocked fast and the amplified value need time to settle. During the correction phase, a longer gain time is available and during the comparisons the gain time is shorter. This is illustrated in Figure 5.2.

T s t i m e A m p l i t u d e T_{a Tc} P r o p a g a t i o n t h r o u g h : O n e s t a g e T w o s t a g e s T h r e e s t a g e s

Figure 5.2. Illustration of different gain time during different phases.

5.1.2

Time model calculations

Using extracted parameters for the resistance, capacitance and transconductance a mathematical model which illustrates the gain as a function of time in each of the stages, and also the stages together. This is calculated and plotted in MATLAB

26 Practical Part

to illustrate the model output which later is used in the MATLAB model because of the different propagation times of the stages.

I ( t ) = g m V i n

R C

.

Figure 5.3. A model of one time dependent stage.

Time dependent model calculations to express each of the stages, and also the stages together are found in ”Appendix B - Propagation time”. For the correction phase, the t in the expression is replaced with the variable correction time, in this case the correction time is assumed to be two clock cycles running with a global sampling clock frequency of 100 M Hz. For the active phase, the t in the expression is replaced with the available correction time, assumed to be 0.45 clock cycles of the global sampling clock frequency.

The derived expressions in are normed. Here with gain normed to one, showing only the propagation in time for each stage. The gain in previous expression will be replaced with the gain for the first model, together with expression for the propagation value for the corresponding time. The gain time constant, τ is

dependent of the output resistance and capacitance of each stage. τ1 = R1C1,

τ2= R2C2, τ3= R3C3

For propagation through one stage like in Figure 5.3 following expressions were found. The gain is normed to one.

prop1= (1 − e −t τ1) prop₂= (1 − e −t τ2) prop₃= (1 − e −t τ3)

This is illustrated in a MATLAB plot in Figure 5.5,with extracted values for the resistance and capacitance. Propagation through all the three stages with the gain normed to one gives following expression. This is when the stages are assumed to be connected like in Figure 5.4.

5.1 A model of the AFE 27 prop123(t) = 1 − τ1τ1 (τ1− τ2)(τ1− τ3)e −t τ1 + ( τ1 τ1− τ2 − 1) τ2 τ2− τ3e −t τ2+ ( τ1τ1 (τ1− τ2)(τ1− τ3)− τ1τ2 (τ1− τ2)(τ2− τ3)+ τ2 τ2− τ3 − 1)e −t τ3 I ( t ) = g m V i n R C 1 1 1 1 I ( t ) = g m V i n R C 2 2 2 2 1 2 I ( t ) = g m V i n R C 3 3 3 3 3

Figure 5.4. A model of all three time dependent stages.

Propagation through only two stages with gain normed to one has also been derived and will look like this.

prop12(t) = 1 − _τ1τ_−τ1₂e −t τ1 _{+ (} τ1 τ1−τ2 − 1)e −t τ2 _{prop23(t) = 1 −} τ2 τ2−τ3e −t τ2 _{+ (} τ2 τ2−τ3 − 1)e −t τ3

During the correction phase, the current correction value is calculated from the output and stored to be used during the next correction phase for the next con-version cycle with the next sampled input value. An expression for the next correction value as a function of previous is found. This propagation time model is used together with the correction term model in the MATLAB models.

28 Practical Part 0 0.2 0.4 0.6 0.8 1 x 10−8 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Re: prop1, Bl: prop2, Gr: prop3

Normed gain

Propagation through one stage

0 0.2 0.4 0.6 0.8 1 x 10−8 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Cy: prop12, Ma: prop23, Bl: prop123

Normed gain

Propagation through more than one stage

Figure 5.5. Time dependent stages. Propagation through one stage with normed gain

to the left. Propagation through more than one stage with normed gain to the right.

5.1.3

Correction term model

The three cascaded gain stages with correction, the preamplifier before the latch, is illustrated in Figure 5.6. An offset source has been added to the input of each gainstage and also to the input of the correction term. The aim is to collect and move all the offset terms to the input og the preamplifier in order to have a model of the preamplifier with an equivalent offset term at the input.

The technique for offset cancellation is similar to the previously described offset cancellation technique with an auxiliary amplifier in the chapter Theory. A general and simplified gain stage like in Figure 5.7 will be modeled. A common mode correction is implemented in the actual model but in this model the common mode will be considered already to be cancelled by the circuit. Consider each of the stages to be constructed like the stage in 5.7, but with different transconductances. Two offset sources has been added to the amplifier models in the gain stage, one to the input of the forward gain stage and the other to the input of the auxiliary amplifier. A third error source could be added for the amplifier model where the correction term is amplified before addition to the amplified input signal but the error source Vosg1 can instead be considered to represent both those sources to make the calculations less complicated.

The output value from each of the stages is dependent of the correction term and the input to the stage, that is either the input to the current stage or the output from the previous stage. The correction term includes the previous output value since a sample-and-hold of the output value is made and stored and used in order to compensate for the offset when subtracted from the input signal.

The structure of the preamplifier as in Figure 5.6. Modeling the gain stages, the first thing to is to find terms of correction and to express the output signal as a function of the terms of correction and the input together with terms of

5.2 Gain stage 29 V o s g 1 -V i n 1 V o 1 V c o r 1 H C O R R 1 A g 1 A c 1 V o s i n t 1 + -+ V o s g 2+ -V i n 2 V o 2 V c o r 2 H C O R R 2 A g 2 A c 2 V o s i n t 2 + -+ V o s g 3+ -V i n 3 V o 3 V c o r 3 H C O R R 3 A g 3 A c 3 V o s i n t 3 + -+ +

Figure 5.6. The three gain stages before the latch

offset. During the correction phase and active phase respectively the gain stages has different amount of times to amplify the values. A longer time is available during the correction phase. The technique for offset cancellation is similar to the previously described offset cancellation technique with an auxiliary amilifier. A general and simplified gain stage like in Figure 5.7 will be modeled, that circuit is simplified from the original design. A common mode correction is implemented in the origial model but in this model the common mode will be considered already to be cancelled by the circuit.

5.2

Gain stage

One simplified stage is represented in Figure 5.7. Two offset sources are added for the amplifier models in the gain stage, one to the input of the forward gain stage and the other to the input or the correction. A third error source could be added for the amplifier model where the correction term is amplified before addition to the amplified input signal but the error source Vosg1 can instead be considered to represent both those stages for example.

5.2.1

Charge analysis

An expression of the correction term can be found through charge analysis. Figure 5.7 is further simplified in Figure 5.8. For each sample a new correction value is calculated and stored. This correction value will be used during the next correction phase. Calculacorrections according to Figure 5.8 can be found in ”Appendix A -Correction term” with each of the stages in Figure 5.6 , denoting the index 1,2 or 3 with x. The table below illustrates the switching states of the switches in Figure 5.8. A ’0’ denotes open switch and a ’1’ denotes closed switch.

30 Practical Part V o s g x + -V i x + V i x -V o s i n t x + -C i n t C i n t C r C r V o x + V o x -S 2 + S 1 + S 1 S 2 -V c o r x + V c o r

-Figure 5.7. One of the three gain stages in the comparator preamplifier stage before

the latch, simplified circuit model.

5.3

Gain stage

C i n t A i n c t x + + -C i n t V o s i n t x + V c o r x p V c o r x m C r S 2 -S 1 + S 1 -S 2 + C r V o x p V o x m q i n t m + q i n t m -q r m + q r p + q r p q r m -q i n t p + q i n t p -+ + -V x p + -V x m + -+ + -A c x + + -A g x V o s g x + -V i x p + -V i x m + -V i n x + -V o x p + -V o x m + V o x +

-Figure 5.8. One comparator preamplifier stage, simplified calculation model

The calculations in ”Appendix A - Correction term” yields 5.1 through charge analysis. Table 5.3 illustrates the different states of the switches in Figure 5.8.

5.3 Gain stage 31 S2 S1 state 0 0 0 1 nT − T 0 0 1 0 nT − T /2 0 0 0 1 nT

Table 5.1. Switching states of S1 and S2in Figure 5.8

Vcor(nT ) = Vcor(nT − T ) − Vox(nT − T ) Cr

Cint − Vosint

Cr

Cint (5.1)

Vox(nT − T ) and Vcor(nT − T ) are the output and correction term respectively

from the previous state that will yield the new correction value. From Figure 5.8 the expression 5.2 is found.

Vox= Vcorx· Acx+ (Vinx+ Vosgx) · Agx (5.2)

where the index x is denoting the number of stage.

5.3.1

MATLAB modeling

Extracted values for transconductances, resistances and capacitances are used in MATLAB models in the time dependent model will be used together with the expressions for the correction term. The MATLAB model of the AFE by Bengt E Jonsson, ADMS Design AB is quite complex since it is describing an AFE. Hence a quite large amount of time was spent on understanding the model. The first attempt to change the code was to figure out how to locate and overwrite a textstring. When that succeded the correction model together with the time model was inserted along with changes in the code. The changes in the code consists of parameters inserted and redirecting call of functions. The demo code provided with the model were run with the new code but no obvious differences in the output from the demos were observed.

Expressions in previous sections can now be used together in matlab models. In this exemple, a short loop for how to calculate the output and the next correction value for the first stage. The parameter it is increased to the value of M , it < M initially. The correction value vcor1 must initially be set to a value as well as all the other terms must.

32 Practical Part

Exemple: for (it = 1 : M ) % output signal

vout1(it) = vcor1(it) ∗ gm1 ∗ R1 ∗ prop1 + (V in1 + vosg1) ∗ gm1 ∗ R1 ∗ prop1;

% next correction value

vcor1(it + 1) = vcor1(it) − vout1(it) ∗ Cr/Cint − vosint1 ∗ Cr/Cint;

end

The following table is a result using an own demo for calling the new ”Correction” function that were inserted in the MATLAB model of the AFE. In this model, for each stage there is two offset sorces referred to the input of forward gain and the correction respectively. The index ”g” referres to the gain and the index ”int” referres to the integrating correction cicruit. The indexed number referres to the stage, index 1 refers to stage one offset sources for exemple. Parameters for the stages according to size differs, and the cascaded stages effets onenaother. The equivalent input offset after settling is here listed. Without correction, only the forward gain. In the first table, for correction phase only. In the second table in the active phase, after settling.

Other offset Correction Correction No correction No correction

sources but 100 M Hz 270 M Hz 100 M Hz 270 M Hz here is zero. vosg1 = 10 mV ±1.7488 · 10−18 _{V ±4.2189 · 10}−18 _{V 10 mV 10 mV} vosg2 = 10 mV ±1.0930 · 10−19 _{V 2.6368 · 10}−19 _{V 0.65220 mV 0.97617 mV} vosg3 = 10 mV 0 V 0 V 40.471 µV 86.026 µV vosint1 = 10 mV 23.664 µV 0.34484 mV 0 V 0 V vosint2 = 10 mV 0.94390 µV 26.774 µV 0 V 0 V vosint3 = 10 mV -2.4528 µV -5.2141 µV 0 V 0 V

Conclusions of this is that it seems like the correction is correcting the equivalent input offset to zero. Without correction the equivalent input offset is higher for the higher frequency, but with the correction approximately zero input offset with offset injected in the forward gain. However, the correction circuit will add noise to the circuit but that noise referred to the input will be much smaller than noise sources of same sizes injected in the forward path.

Chapter 6

Summary

This analyse has considered modeling the offset in the comparator in an ADC slice in the PSAR arcitecture A/DvanceII. The PSAR structure that has been studied has a 10 bit resolution. High resolution is important in digital imaging for exemple. In the models only one channel consisting one ADC has been studied. MATLAB code can be efficiently written like in the original model of the AFE that has been modified. The modification could have been made better. The structure of the original model has a good way of creating parameters and cleaning up. Main focus in this report has though been on explaining functionality and behaviour of the preamplifier within the comparator and its correction. The derivation of the mathematical models has been listed in the Appendix. These are connected to the images in the chapter ”Practical Part”.

The analysis of noise and offset in the comparator of an analog-to-digital converter has been limited to only concern the offset. To include noise in this model, a suggestion is to overlay the offset terms with noise in the current model. Of course a calculation model with added noise terms could be considered as a continuing of this study.

Bibliography

[1] Sicon semiconductor. www page, 2008. http://www.siconsemi.com.

[2] ADMS Design AB B.E Jonsson and Sicon Semiconductor AB R. Sundblad.

Adc’s for sub-micron technologies. EE Times Europe, 2008.

[3] J.A Connelly C.D Motchenbacker. Low noise electronic system design. John

Wiley & Sons, 1993. ISBN 0-471-57742-1.

[4] K.M Daugherty. Analog-to-digital conversion. McGraw-Hill, Inc, 1994.

ISBN 0-07-015675-1.

[5] N. Bergman F. Gustafsson. MATLAB for Engineers Explained.

Springer-Verlag, 2003. ISBN 1-85233-697-8.

[6] D.F Hoeshele. Analog-to-digital and digital-to-analog conversion techniques.

John Wiley & Sons, Inc, 1994. ISBN 0-471-57147-4.

[7] Elbornsson J. White Paper on Parallel Successive Approximation ADC.

MathCore Engineering AB, 2005.

[8] D.A Johns and K. Martin. Analog Integrated Circuit Design. John Wiley &

Sons, Inc, 1997. ISBN 0-471-14448-7.

[9] P. Löwenborg. Mixed-signal processing system. UniTryck, 2004.

[10] B Razavi. Principles of data conversion system design. IEEE Press, 1995.

ISBN 0-7803-1093-4.

Appendix A

Correction term

Regarding the charges for Figure 5.8 at qrm−, qrp+, qm− and qp− during the

different states of transition regarding the switches S1 and S2 as in table 5.3 ,

following can be derived from Figure 5.8:

nT − T

qintm−(nT − T ) = (V xm(nT − T ) − V corxm(nT − T ))Cint (A.1)

qintp−(nT − T ) = (V xp(nT − T ) − V corxp(nT − T ))Cint (A.2)

qrm+(nT − T ) = (V oxp(nT − T ))Cr (A.3)

qrp+(nT − T ) = (V oxm(nT − T ))Cr (A.4)

nT − T /2

qintm−(nT − T /2) = (V xm(nT − T /2) − V corxm(nT − T /2))Cint (A.5)

qintp−(nT − T /2) = (V xp(nT − T /2) − V corxp(nT − T /2))Cint (A.6)

38 Correction term

qrm+(nT − T /2) = (V xp(nT − T /2))Cr (A.7)

qrp+(nT − T /2) = (V xm(nT − T /2))Cr (A.8)

Assuming the charge is transferred from previous state to this state from the previous, then:

qrp+(nT − T ) + qintm−(nT − T ) = qrp+(nT − T /2) + qintm−(nT − T /2) (A.9)

qrm+(nT − T ) + qintp−(nT − T ) = qrm+(nT − T /2) + qintp−(nT − T /2) (A.10)

nT

qintm−(nT ) = (V xm(nT ) − V corxm(nT ))Cint (A.11)

qintp−(nT ) = (V xp(nT ) − V corxp(nT ))Cint (A.12)

Assume that the charge stays at the Cint capacitors from previous state to this state, then

qintm−(nT ) = qintm−(nT − T /2) (A.13)

qintp−(nT ) = qintp−(nT − T /2) (A.14)

Hence

V corxp(nT ) = V corxp(nT − T /2) (A.15)

V corxm(nT ) = V corxm(nT − T /2) (A.16)

39

V xm(nT ) = V xm(nT − T /2) (A.18) For the differential amplifier:

V oxp(nT ) = V cmo + 1 2V ox(nT ) (A.19) V oxm(nT ) = V cmo −1 2V ox(nT ) (A.20) V xp(nT ) = V cmx +1 2V x(nT ) (A.21) V xm(nT ) = V cmx −1 2V x(nT ) (A.22) V corxp(nT ) = V cmcor +1 2V cor(nT ) (A.23) V corxm(nT ) = V cmcor −1 2V cor(nT ) (A.24) Looking at Figure 5.8 assuming Aintcx to be ideal then

V x = −V osint (A.25) Where Vcmo, Vcmx, Vcmcor are common mode voltages. Expressions above for the differential amplifier are the same for nT − T if nT replaced.

The output value, Voutx can also be calculated from Figure 5.8 with Voutx =

Voxm− Voxp

Voutx= Acx(Vcorxm− Vcorxp) + Agx(Vixm− Vixp− Vosg) (A.26)

Now insert expressions for differential voltages in A.1 and so on

qintm−(nT − T ) = (V cmx − 1

2V x((nT − T ) − V cmcor + 1

2V cor(nT − T ))Cint (A.27)

40 Correction term

qintp−(nT −T ) = (V cmx+1

2V x(nT −T )−V cmcor− 1

2V cor(nT −T ))Cint (A.28)

qrp+(nT − T ) = (V cmo −1 2V ox(nT − T ))Cr (A.29) qrm+(nT − T ) = (V cmo + 1 2V ox(nT − T ))Cr (A.30) qintm−(nT −T /2) = (V cmx−1 2V x(nT −T /2)−V cmcor + 1 2V cor(nT −T /2))Cint (A.31) qintp−(nT − T /2) = (V cmx +1 2V x(nT − T /2) − V cmcor − 1 2V cor(nT − T /2))Cint (A.32) qrp+(nT − T /2) = (V cmx −1 2V x(nT − T /2)))Cr (A.33) qrm+(nT − T /2) = (V cmx +1 2V x(nT − T /2)))Cr (A.34) qintm−(nT ) = (V cmx − 1 2V x((nT ) − V cmcor + 1

2V cor(nT ))Cint (A.35)

qintp−(nT ) = (V cmx +1

2V x(nT ) − V cmcor − 1

2V cor(nT ))Cint (A.36) Use A.9 and A.10 together with A.13 and A.14 .

qrp+(nT − T ) + qintm−(nT − T ) = qrp+(nT − T /2) + qintm−(nT ) (A.37)

qrm+(nT − T ) + qintp−(nT − T ) = qrm+(nT − T /2) + qintp−(nT ) (A.38)

41 (V cmo −1 2V ox(nT − T ))Cr + (V cmx − 1 2V x(nT − T ) − V cmcor + 1 2V cor(nT − T ))Cint = (V xm(nT − T /2))Cr + (V cmx − 1 2V x((nT ) − V cmcor + 1 2V cor(nT ))Cint (A.39) (V cmo +1 2V ox(nT − T ))Cr + (V cmx + 1 2V x(nT − T ) − V cmcor − 1 2V cor(nT − T ))Cint = (V xp(nT − T /2))Cr + (V cmx +1 2V x(nT ) − V cmcor − 1 2V cor(nT ))Cint (A.40)

Eliminate Vcmo in A.39 A.40 . Use A.17 and A.18.

1 2V ox(nT − T )Cr − (V cmx − 1 2V x(nT − T ) − V cmcor + 1 2V cor(nT − T ))Cint+ (V xm(nT ))Cr + (V cmx −1 2V x(nT ) − V cmcor + 1 2V cor(nT ))Cint +1 2V ox(nT − T )Cr + (V cmx + 1 2V x(nT − T ) − V cmcor − 1 2V cor(nT − T ))Cint = (V xp(nT ))Cr + (V cmx +1 2V x(nT ) − V cmcor − 1 2V cor(nT ))Cint Simplify

V cor(nT ) = V cor(nT − T ) − V ox(nT − T ) Cr

Cint − V x(nT − T ) + V x(nT ) Cr

Cint+ V x(nT )

Use that A.25

V cor(nT ) = V cor(nT − T ) − V ox(nT − T ) Cr

Cint− V osint Cr

Appendix B

Propagation time

Propagation time calculation is derived.

General expression

From the 5.3 , some general expressions are derived:

C · V0_{(t) = i(t) −} V (t) R ⇒ i(t) C = V 0_{(t) +}V (t) RC

Multiply this by the integrating factor eRCt :

eRCt ·i(t) C = e t RC · V0(t) +V (t) RC ⇔ d dt(e t RC) ·i(t) C = e t RC · V (t) ⇔ Z (eRCt ·i(t) C )dt = e t RC · V (t)

Using this general expression for a stage following can be derived for three cascaded stages:

43

Propagation through one stage

For stage 1, assume Vinto be constant. For the correction phase it will be equal to

zero and during the comparisons equal to an input voltage assumed to be constant.

τ1= R1C1, τ2= R2C2, τ3= R3C3 i1(t) = gm1Vin V1(t) = e −t R1C1 Z (eR1C1t _·i1(t) C1 )dt ⇔ V1(t) = e −t R1C1 Z (eR1C1t _·gm1Vin C1 )dt ⇔ V1(t) = e −t R1C1gm1Vin C1 (R1C1e t R1C1 _{· +k1)} ⇔ V1(t) = e −t τ1_gm1R1Vin(eτ1t _{· +}k1 τ1)

Starting with a reset V1(0) = 0 k1= −τ1and the expression for the output voltage

of a single stage can under these assumptions be written as following. Index 1 illustrates the first stage alone. Replacing index 1 with 2 or 3 representation of

the output of the stage with constant input Vin.

V1(t) = gm1R1Vin(1 − e −t τ1) (B.1) V2(t) = gm2R2Vin2(1 − e −t τ2) (B.2) V3(t) = gm3R3Vin3(1 − e −t τ3_{) (B.3)}