Low-power 8-bit Pipelined ADC with current mode Multiplying Digital-to-Analog Converter (MDAC)

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Institutionen för systemteknik

Department of Electrical Engineering

Examensarbete

Low-power 8-bit Pipelined ADC with current mode

Multiplying Digital-to-Analog Converter (MDAC)

Examensarbete utfört i Elektroniska komponenter vid Tekniska högskolan i Linköping

av

Khurram Shahzad

LiTH-ISY-EX--09/4320--SE

Linköping 2009

Department of Electrical Engineering Linköpings tekniska högskola Linköpings universitet Linköpings universitet SE-581 83 Linköping, Sweden 581 83 Linköping

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Low-power 8-bit Pipelined ADC with current mode

Multiplying Digital-to-Analog Converter (MDAC)

Examensarbete utfört i Elektroniska komponenter

vid Tekniska högskolan i Linköping

av

Khurram Shahzad

Handledare: Christer Svensson

isy, Linköpings universitet

Examinator: Christer Svensson

isy, Linköpings universitet

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Avdelning, Institution

Division, Department

Division of Electronics Devices Department of Electrical Engineering Linköpings universitet

SE-581 83 Linköping, Sweden

Datum Date 2009-08-17 Språk Language Svenska/Swedish Engelska/English Rapporttyp Report category Licentiatavhandling Examensarbete C-uppsats D-uppsats Övrig rapport

URL för elektronisk version

ISBN

—

ISRN

Serietitel och serienummer

Title of series, numbering

ISSN

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Titel

Title

Lågeffekt 8-bit pipelined ADC med strömmod MDAC

Low-power 8-bit Pipelined ADC with current mode Multiplying Digital-to-Analog Converter (MDAC) Författare Author Khurram Shahzad Sammanfattning Abstract

In order to convert the analog information in the digital domain, pipelined analog-to-digital converter (ADC) offers an optimum balance of resolution, speed, power consumption, size and design effort.

In this thesis work we design and optimize a 8-bit pipelined ADC for low-power. The ADC has stage resolution of 1.5-bit and employ current mode multiplying analog-to-digital converter (MDAC). The main focus is to design and optimize the MDAC. Based on the analysis of "On current mode circuits" discussed in chapter 2, we design and optimize the MDAC circuit for the best possible effective number of bits (ENOB), speed and power consumption. Each of the first six stages consisting of Sample-and-Hold, 1.5-bit flash ADC and MDAC is realized at the circuit level. The last stage consisting of 2-bit flash ADC is also realized at circuit level. The delay logic for synchronization is implemented in Verilog-A and MATLAB. A first order digital error-correction algorithm is implemented in MATLAB.

The design is simulated in UMC 0.18µm technology in Cadence environment. The choice of technology is made as the target application for the ADC, ’X-ray Detector System’ is designed in the same technology. The simulation results ob-tained in-term of ENOB and power consumption are satisfactory for the target application.

Nyckelord

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Abstract

In order to convert the analog information in the digital domain, pipelined analog-to-digital converter (ADC) offers an optimum balance of resolution, speed, power consumption, size and design effort.

In this thesis work we design and optimize a 8-bit pipelined ADC for low-power. The ADC has stage resolution of 1.5-bit and employ current mode multiplying analog-to-digital converter (MDAC). The main focus is to design and optimize the MDAC. Based on the analysis of "On current mode circuits" discussed in chapter 2, we design and optimize the MDAC circuit for the best possible effective number of bits (ENOB), speed and power consumption. Each of the first six stages con-sisting of Sample-and-Hold, 1.5-bit flash ADC and MDAC is realized at the circuit level. The last stage consisting of 2-bit flash ADC is also realized at circuit level. The delay logic for synchronization is implemented in Verilog-A and MATLAB. A first order digital error-correction algorithm is implemented in MATLAB.

The design is simulated in UMC 0.18µm technology in Cadence environment. The choice of technology is made as the target application for the ADC, ’X-ray Detector System’ is designed in the same technology. The simulation results ob-tained in-term of ENOB and power consumption are satisfactory for the target application.

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Acknowledgments

First of all I thank to Almighty Allah Who has given me the power and courage to complete this work.

I would like to thank my supervisor Christer Svensson for giving me the op-portunity to do this work. During the thesis work I learned a lot from his great problem solving approach and dedication.

I am thankful to Prof. Atila Alvandpour for introducing me to Christer Svens-son for the thesis. I would like to thank Timmy Sundström for long discussions and solving the tool related problems. I am thankful to Abdul Mateen Malik for being opponent for thesis.

Finally I would like to thank all my friends in the ISY for their support.

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7.3 Plot of the power consumption vs input frequency for VF S=0.5V . 39 7.4 Plot of the power consumption vs input frequency for VF S=0.2V . 39 7.5 Plot of the power consumption vs sampling frequency for VF S=0.5V 40 7.6 Plot of the power consumption vs sampling frequency for VF S=0.2V 40 A.1 Design at top level . . . 45

A.2 A pipeline stage . . . 45

A.3 Schematic of Sample-and-Hold . . . 46

A.4 A 1.5-bit Flash ADC . . . 46

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2 Contents

A.6 (a) SR latch (b) Static CMOS NOR . . . 47

A.7 Schematic of MDAC . . . 48

A.8 2-to-1 multiplexer used in MDAC . . . 49

A.9 2-bit Flash ADC . . . 49

A.10 Gate level implementation of a full-adder . . . 50

List of Tables

2.1 DAC voltages . . . 15

4.1 Reference voltages for sub-ADC . . . 25

4.2 Reference voltages for sub-ADC . . . 26

A.1 Optimized transistors’ width for comparator . . . 46

A.2 Reference voltages for sub-ADC . . . 46

A.3 Transistors’ width (in µm) for comparator . . . . 47

A.4 Optimized transistors’ width (in µm) for the MDAC circuit . . . . 48

A.5 Bias voltages used in MDAC circuit . . . 48

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Chapter 1

Introduction

1.1 The task

The aim of the thesis is to design and optimize a low-power, high-speed 8-bit pipelined ADC for ’X-ray Detector System’. Since most of the power in a pipelined ADC is consumed by multiplying analog-to-digital converter (MDAC), the primary goal of the thesis is to design and optimize a simple current-mode MDAC to acheive a reasonable speed, ENOB and power consumption.

This requires the design and implementation of a Sample-and-Hold (S/H), MDAC, 1.5-bit and 2-bit flash ADCs, a delay logic and a digital error-correction algorithm to test the design.

1.2 Analog-to-Digital Converter

An analog-to-digital converter (ADC) converts an analog signal into a digital code, more specifically it converts a continuous-time, continuous-amplitude signal into a discrete-time, discrete-amplitude signal [6]. This can be considered as two step process, i.e., sampling the analog signal and quantizing the sampled value. An ADC is characterized by the number of bits it can produce over the range of input signal called resolution. An ADC with N-bit resolution can encode an input signal to 2N _{codes. The higher the resolution the better the conversion is. Figure 1.1(a)}

depicts the block diagram of an ADC. Vin and Vref is analog input and reference voltage respectively. Dout (B0, B1, . . . , BN −1) is an N-bit digital output word

where B0 is the least significant bit (LSB) and BN −1 is the most significant bit

(MSB).

In Figure 1.1(b) analog signal is first band-limited to avoid the aliasing. Then band-limited signal is sampled and held constant by Sample-and-Hold (S/H) cir-cuit. Then the sampled analog value is quantized. And finally quantized output is decoded to form a digital output. The transformation of Vin into Dout can be

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4 Introduction

Figure 1.1. (a) General block diagram of an ADC (b) Analog to digital conversion

process

shown mathematically as,

V in V ref = Dout + eq = N −1 X i=0 Bi2i+ eq (1.1)

Quantization error, eq is the difference between the original input and the

quantized output (i.e, difference of Vin divided by Vref and Dout). Quantization error is decreased by increasing the resolution, and its effect can be viewed as additive noise ("quantization noise") at the output [6].

There exits several ADC architectures, each having its own merits and demer-its. For example flash ADC is extremely fast but on the other hands has highest power consumption for a given resolution. One of the popular architecture called pipelined ADC, which is the focus of this thesis study is explained below.

1.3 Pipelined ADC

Pipelined ADCs offer an attractive combination of speed, resolution , low power consumption and small die size [2].

1.3.1 Architecture

As its name suggests pipelined ADC employs several pipelined stages to achieve high speed and high resolution. Figure 1.2 shows a general block diagram of pipelined ADC. It consists of k low-resolution ADCs, a delay logic for synchronizing the output and a digital correction logic to remove the redundancy.

Each stage has B+r bit resolution, where B represents effective stage resolution and r represents redundancy for the comparator offset correction algorithm. First k-1 stages employ similar architecture and usually have same resolution. The last stage does not have redundancy, so it is B-bit(s) flash ADC. The total resolution N of a pipelined ADC with k stages can be expressed as,

N =

k

X

i=1

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1.3 Pipelined ADC 5

Figure 1.2. General block diagram of a pipelined ADC

Where Bi is effective resolution of corresponding stage for first k-1 stages and

Bk is resolution of last stage. Two successive stages operate on non-overlapping

clock phases. Digital outputs from each stage is delayed according to position of stage in the pipelined ADC for synchronization. Then synchronized output is fed to the correction logic.

Figure 1.3 depicts a single stage of pipelined ADC, consisting a sample-and-hold, a sub-ADC, a DAC (digital-to-analog converter), a subtracter and an am-plifier.

Figure 1.3. A stage of Pipelined ADC

Analog input to stage is held constant by sample-and-hold module and at the same time it is also converted into digital form by sub-ADC. The digital encoded number is converted back to analog value by DAC. Then output of DAC is subtracted from output of sample-and-hold resulting the stage residue. Then the residue is amplified by gain given in equation 1.3 [8] for the next stage.

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6 Introduction

Gi= 2Bi+1−r (1.3)

Each stage operates concurrently, i.e., first stage works on most recent sample and second stage works on a sample delayed by one time unit and so on.

In principle each stage can be as low as 1-bit. But to comparator offset errors 1-bit stage is not used in practical implementations. This problem and its solution is discussed in next section. Output residue for 1-bit is obtained according to equation 1.4

V out =

2(V in + V ref ) (V in < V mid)

2(V in − V ref ) (V in > V mid) (1.4)

Where Vref is a reference voltage and Vmid is midpoint in the input range. Residue plot for 1-bit stage is shown in Figure 1.4.

Figure 1.4. Residue plot of an ideal 1-bit stage of pipelined ADC

1.3.2 1.5-bit stage

In 1-bit stage implementation offset error in a comparator can lead to completely wrong decision for a stage. And from that stage onwards the output gets saturated. This effect is shown in Figure 1.5. Here we see that offset error in stage 2 produces saturated output which is the input for stage 3. So stage3 gets saturated input and produces saturated output. All following stages produce the saturated output. For this reason 1-bit stage is not used in practical Pipelined ADCs.

In this thesis study Pipelined ADC is designed with 1.5-bit stage resolution. A 1.5-bit stage is actually a 2-bit stage (i.e., 2 comparators) with three output regions rather than four. And 0.5-bit is a redundant value which is removed by correction logic.

Figure 1.6 shows the residue plot of 1.5-bit stage. As seems from the figure only three combinations of comparators output (00, 01 and 11) are considered. Here offset errors from comparators are mitigated due to third level as compare to 1-bit stage. Equation 1.5 relates the input and output for 1.5-bit stage,

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1.3 Pipelined ADC 7

Figure 1.5. Effect of offset error in 1-bit stage

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8 Introduction V out =    2(V in + V ref +) (V in < V comp−)

2(V in) (V comp− < V in > V comp+) 2(V in − V ref −) (V in > V comp+)

(1.5)

where Vref+ and Vref- is midpoint in positive and negative input range respec-tively. Vcomp+ and Vcomp- are V inmax₄ and V inmin₄ .

1.3.3 Latency

The pipelined mechanisim of the ADC latency as each sample has to propogate through the all pipeline stages before all bits can be combined to be corrected by the digital error-correction. For a 8-bit pipelined ADC with 1.5-bit stage resolu-tion, latency is 7 clock cycles.

1.3.4 Correction Algorithm

Most pipelined ADCs include a digital error-correction circuitry to reduce the effects of offset errors nonlinearity in S/H and sub-ADC respectively. Digital error-correction help to improve the linearity of the ADC. A simple error-error-correction algrothim used in this thesis corrects the digital output by summing appropriate bits from the last stage to the first stage. A detail description can be found in chapter 5.

1.4 ADC Performance metrics

Performance metric for ADC is divided into two groups, static and dynamic.

1.4.1 Static specifications

Circuit realization with non-ideal component is the main cause of the static er-rors. Important static specification includes differential non-linearity (DNL) and integral non-linearity (INL). The deviation of step size in the non-ideal ADC from the ideal size (∆) is termed as DNL. INL is defined as the deviation of output value from the ideal value. Other static specifications are offset errors, gain error etc [4].

1.4.2 Dynamic specifications

Dynamic specifications are important in high speed applications such as communi-cation, ultrasound imaging, instrumentation and IF digitization [2]. Some of most commonly known are as follows,

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1.4 ADC Performance metrics 9

Signal-to-Noise Ratio (SNR)

As its name suggests it is the ratio of the signal power to the noise power. SNR is given by equation 1.9,

SN RdB = 10log(P s

P n) = 6.02N + 1.76dB (1.6)

SNR is increased by 6dB for every additional bit in the ADC.

Spurious Free Dynamic Range (SFDR)

It is the ratio of signal power and the power of the largest spurious in the band of interest.

Signal-to-Noise-and-Distortion Ratio (SNDR)

It is the ratio of the signal power to the total noise power including all spurs and harmonics.

SN DR = 10log( Signal P ower

N oise and Distortion P ower) (1.7)

Effective Number of Bits (ENOB)

The effective resolution obtained for an ADC is determined by equation 1.8,

EN OB = (SN DR − 1.76dB

6.02dB ) (1.8)

In this thesis ENOB is mainly used a performance measurement parameter.

Dynamic range

It is the input power range for which the SNR is greater than 0dB.

DR = 10log( max signal power

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Chapter 2

Multiplying

Digital-to-Analog Converter

(MDAC)

The most important and challenging part of a pipelined stage is the multiplying digital-to-analog converter (MDAC). It consists of sample-and-hold (S/H), sub-digital-to-analog converter (sub-DAC), a subtracter and a residue amplifier. Gen-eral block diagram of Figure 1.3 is redrawn as Figure 2.1 where modules included in dashed-box represent MDAC.

Figure 2.1. Block diagram of pipelined ADC stage

MDAC performs the digital-to-analog conversion of the sub-ADC’s output, subtraction of the sampled analog signal from sample-and-hold (S/H) circuit’s output and amplification of the resulting signal called residue. Traditionally an MDAC is implemented using the switched capacitor technique, forming a SC in-tegrator around an operational amplifier [8]. In this thesis we implemented the MDAC operation with a current mode circuit explained in the next section. Since the S/H circuit is not integrated in MDAC implementation in this thesis study, we refer the term MDAC to a unit performing D/A conversion, subtraction of D/A

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12 Multiplying Digital-to-Analog Converter (MDAC)

output from signal held by S/H and residue amplification.

Our design of MDAC is based on current mode circuit. So it is worthwhile to analyze the current mode circuit in detail.

2.1 On current mode circuits

Current mirrors have a limited accuracy in a nm process due to relatively low output impedance. Because of very low voltage headroom, this cannot be improved by cascodes. However, if we understand the source of errors (and if the errors are systematic) we may correct them by adjusting transistor sizes. We do analysis of the circuit shown in Figure 2.2 with the first order model of drain current including the output conductance, g0 as,

id = gmVg+ g0Vd (2.1)

Figure 2.2. A current mode circuit

In the Figure 2.2 we assume that i1 is input current, i2 is output current from

first mirror, i3is DAC output to be subtracted from i2and i4is the output current

to be mirrored by T4. So we would like to see

i4= i1− i3 (2.2)

using the equation 2.1 we have

i1= gm1V1+ g01V1 (2.3)

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2.1 On current mode circuits 13 i2= gm2V1+ g02V2 (2.4) which yields id = gm2 gm1+ g01 i1+ g02V2= 1 1 + g01 gm1 gm2 gm1 + g02V2 (2.5)

The first term in the above equation indicates the gain error caused by first mirror. The reason for this error is that V2 is different from V1. In Figure 2.3 V2

is controlled by T4which in fact increases the error. We also need to check if there

is an error in the subtraction of i3 from T3. Let us therefore make a complete

calculation of i4.

i4= i2− i3 (2.6)

i4= (gm4+ g04)(Vdd− V2) (2.7)

from this we get V2,

V2= Vdd− i2− i3 gm4+ g04 (2.8) putting 2.8 into 2.4, i2= gm2 gm1+ g01 i1+ g02Vdd− g02 gm4+ g04 i2+ g02 gm4+ g04 i3 (2.9)

solving for i2 gives

i2= gm4+ g04 g02+ gm4+ g04 gm2 gm1+ g01 i1+ (gm4+ g04)g02 g02+ gm4+ g04 Vdd+ g02 g02+ gm4+ g04 i3 (2.10) finally calculating i4 yields

i4= i2−i3= gm4+ g04 g02+ gm4+ g04 gm2 gm1+ g01 i1+ (gm4+ g04)g02 g02+ gm4+ g04 Vdd+ gm4+ g04 g02+ gm4+ g04 i3 (2.11) First we note that if all g0 are zero we have ideal solution. So all errors

are related to g0

gm in some combination. We can also observe that all errors are

predictable here, so they can be corrected by an appropriate choice of gm’s. So by

finding transistors with low g0 and correcting the remaining errors by adjusting

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2.1.1 Adjusting transistor sizes

Since the equation 2.11 describe the transfer function from i1 to i4, so most

im-portant is the first term. As there are too many parameters here, so we need a strategy. Let us consider the controlling transistors (first stage in the current mirror), T1, and to T4as fixed (nominal values). So we adjust T2or gm2. And we

adjust gm2in a such a way that i_i4₁ is 2. From the first term in the 2.11 we then

get gm2= 2(gm1+ g01)(g02+ gm4+ g04) gm4+ g04 = 2gm1(1 + g02 gm1 )(1 + g02 gm4+ g04 ) (2.12)

So we need to increase the nominal value gm2 from the nominal value 2gm1.

And this requires some iterations as g02

gm4+g04 depends on the size of T2.

Choosing T1 smaller than T4 will lead to a smaller _g_m4g02_+g₀₄ term and less

adjustment of T2.

Term 2 in equation 2.11 is an offset term which is adjusted by the control of bias level.

Regarding the third term, it should not be adjusted from this equation, we need to include the controlling transistor for T3 gate voltage. Then we adjust

gm3. As the gm3 is not included in equation 2.11 so the proposed adjustment of

gm2is independent of gm3’s adjustment.

2.1.2 Effect of V

T

spread

Introducing a spread in VT, we can describe this as:

id = gm(Vg− VT) + g0Vd (2.13)

Defining a VT error for each transistor, VT i and inserting the equation above,

yield, i4= gm4+ g04 g02+ gm4+ g04 gm2 gm1+ g01 i1+ (gm4+ g04) g02+ gm4+ g04 (gm2Vdd+ gm2VT 2 − gm2gm1 gm1+ g01 VT 1) − g02gm4 gm4+ g04+ g02 − gm4+ g04 g02+ gm4+ g04 i3 (2.14)

So we see that VT values only show up as an offset. That means VT spread

will only give rise to offset which is manged by the 1.5-bit redundancy per stage which we use in the thesis.

2.1.3 Voltage swing

In the current mirror circuit shown above we need to keep the gate voltage of each transistor large enough so we do not loose speed. This leads to a minimum

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2.2 Current mode differential MDAC 15

gate voltage of Vmin (say 0.3V). Maximum gate voltage (corresponding to

max-imum current) is Vmax. For the maximum current case V1=Vmax and V2=Vdd

-Vmax(also T4 gate voltage is Vmax). Furthermore, the gate drain voltage of T2 ,

Vmax-V2 must be smaller than VT, to keep T2 in saturation. Thus

Vmax− V2= 2Vmax− Vdd < VT (2.15)

which gives

Vmax=

Vdd− VT

2 (2.16)

Assuming Vdd = 1.8V and VT = 0.4V gives Vmax = 1.1V. With Vmin=0.4V

we arrive to maximum voltage swing of 0.7V. In this thesis work, simulation were performed at two different voltage swings, mainly on 0.5V and later at 0.2V.

2.2 Current mode differential MDAC

We do the basic design of MDAC by adjusting the parameters in the current mode circuit. Then by varying the parameters manually we tried to maximize the ENOB. In order to implement the function defined in equation 1.5, a current mode circuit shown in Figure 2.3 is designed. The design is carried out by adjusting the parameters analyzed in the current mode circuit. Differential mode circuit is realized for the MDAC. It consists of an input stage, current mirror stage, amplification stage, a DAC stage and an output stage. The current mirror stage (of lower differential part) mirrors the current from the input stage causing a change δ at point A, whereas input from upper differential circuit (through PMOS in amplification stage) also cause a change of δ at point A, with the net effect of 2δ. In this way 2Vin is achieved. Based on the sub-ADC output DAC voltages

are added through DAC stage.

The transistors in the MDAC are sized to achieve a gain of 2.2. Bias controls the DC level and the DAC voltage shown in Table 2.1 adds and subtracts the correct level through DAC stage depending on the output of the sub-ADC.

sub-ADC(B1 B0) Vdac,p,pmos Vdac,p,nmos Vdac,n,pmos Vdac,n,nmos

00 Bias1 Gnd Vdd Bias4

01 Vdd Gnd Vdd Gnd

11 Vdd Bias2 Bias3 Gnd

Table 2.1. DAC voltages

As we see there are two different input voltages (Bias and Vdd/Gnd) to be

selected for each transitor in the DAC stage of the MDAC. To do this multiplexer selects the proper input based on the sub-ADC’s output. For example, input voltage for the Vdac,p,pmos is selected by using B0bit at the selection input of the

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Figure 2.3. Differential MDAC

2.2.1 Power consumption

The MDAC consists of three stages (current mirror, amplification and output stage) with 6 active transistors. Each has a noise current of

i2_n= 4kT γgmB (2.17)

where k is Boltzmann constant, T is absolute temperature in Kelvins, γ is a complex function of basic transistor parameters and bias voltages and B is the noise bandwidth. Current gain is about 1 from each transistor to the output, so the output noise current is Mi2n, where M is the number of transistors. We get a

noise voltage at output of M i2n

gm2, where

1

gm is the load resistance of the output

stage (an MOS diode). Noise bandwidth can be estimated to gm

4CL, where CL is

the load capacitance at output (which is also the sampling capacitance into next stage). We then have the output noise voltage

v_n2= M kT γ

CL

(2.18)

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2.2 Current mode differential MDAC 17 vq2= V2 F S 12 2 −2n _(2.19)

Setting the input thermal noise (Vn2

4 , as the MDAC has a gain of 2) equal to 1 4

of the quantization noise (allowing also other noise sources) gives

CL=

12M γkT

V2

F S

22n (2.20)

Settling of the sampling capacitor can be described as

τ = 1 − e−2fsCLgm _(2.21)

where we allow time _f2

s (time constant

gm

CL). Full settling (to within 1-2

−n_{) gives}

the gmrequirement,

gm= 2fsCLnln2 (2.22)

From the above derivations we calculate the power for the given frequency and voltage swing used in the thesis in chapter 7.

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Chapter 3

Sample-and-Hold

3.1 Basic Principle

Sample-and-Hold (S/H) circuit samples the analog input and then holds the input stable for certain time so that it can be used. A clock signal turns on and off the switch so that input signal is sampled and held. During one phase of the clock the analog input is tracked while in the other phase the tracked input is held constant for the further operation, that is why it is also called Track-and-Hold (T/H). A simple sampling circuit is shown in Figure 3.1(a). When switch is closed capacitor CH is charged to the level of input signal and when switch is opened the tracked

input is present at Vout. Sampling process is shown in Figure 3.1(b), where during

the positive half cycle of the clock input signal is tracked and during the negative half cycle tracked input is held stable.

Figure 3.1. (a) A simple S/H (b) Sampling process

A simple S/H can be implemented by replacing the switch with a MOS tran-sistor in the Figure 2.1(a). Since it is not possible to charge the capacitor CH

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20 Sample-and-Hold

completely to the input level within a finite time, output is considered to be set-tled when it is within a certain error bound around the final value. In a switch capacitor based sampling circuit sampling speed is determined by the on-resistance of the switch and the value of the sampling capacitor. So in order to achieve high speed, a large aspect ratio and a small capacitor is used.

3.2 Complementary Switch

Since the on-resistance of a NMOS is increased with increase in input voltage and on-resistance of PMOS is decreased with the increase in input voltage, it is better to use complementary switch as shown in Figure 3.2(a). The equivalent on-resistance of complementary switch is shown in Figure 3.2(b).

Figure 3.2. (a) Complementary switch (b) on-resistance of the complementary switch

The complementary switch shown in Figure 3.2 can lead to the distortion in the sampled value if the NMOS and PMOS are not turned off simultaneously. Since in the thesis two ideal non-overlapping clock are used there is no such problem. But when clocks are not ideal, care is required to design the non-overlapping clock to avoid this problem.

3.3 Error sources in S/H

There are three types of phenomenon causing the error in the operation of a MOS transistor when it is switched off [5].

3.3.1 Channel Charge Injection

When the switch is ON there exists a channel under the gate. But when switch is closed the charge under the gate exits through source and drain terminals. This phenomenon is called channel charge injection. This is shown in Figure 3.3. This leads to a deviation of the ideal sampled value at the output. Mathematical modeling shows that this error is directly proportional to the product of width, length and oxide capacitance of the transistor and is inversely proportional to the value of the capacitor.

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3.3 Error sources in S/H 21

Figure 3.3. Effect of charge injection

Charge injection is supposed to contribute a gain error, dc offset and nonlin-earity in the MOS sampling circuits. Gain error and dc offset can be corrected in many applications but not the nonlinearity [5].

3.3.2 Clock Feedthrough

As shown in Figure 3.4, a transition at the clock is coupled to the sampling capac-itor through gate-drain or gate-source overlap capacitance. Due to this an error voltage is generated on the sampling capacitor when the switch is turned off. Cou-pling towards the input can be neglected but couCou-pling to samCou-pling capacitor needs to handled.

Figure 3.4. Clock feedthrough in S/H

The error introduced by the clock feedthrough is independent of the input level. So its effect is equivalent to a constant offset in the input and output. With slower gate voltage transition a MOSFET finds an additional time to compensate the coupling error, yielding in smaller clock feedthrough error [11]. So it leads to a trade-off between speed and precision.

3.3.3 Thermal Noise

Thermal noise (also called kT/C noise) is introduced at the output of the S/H due to the on-resistance of the switch. And this noise is stored at the sampling capac-itor with the instantaneous value of the input voltage. Solution to this problem is that one should use large capacitor, but that can lead to the degradation in speed.

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22 Sample-and-Hold

3.3.4 S/H with dummy switches

In order to minimize the effects of charge injection and clock feedthough we used a S/H with complementary switches and dummy transistor as shown in Figure 3.5. The width of the dummy transistors are kept half of the one used in complementary switches to suppress the clock feedthrough.

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Chapter 4

Sub-ADC

In 8-bit pipelined ADC each of the first six stages employ a 1.5-bit (three decision levels) differential mode flash analog-to-digital converter (ADC). The last stage is a 2-bit differential mode flash ADC without any MDAC stage. The ADC used in each stage is usually termed as low-resolution ADC or sub-ADC. A 2-bit single ended flash ADC is shown in Figure 4.1.

Figure 4.1. A 2-bit flash ADC

For N-bit resolution flash ADC employs 2N− 1 comparators. High-speed com-parators are cascaded to form a flash architecture where all comcom-parators produce the output simultaneously. The resistive divider network with 2N _resistors

pro-vides the reference voltages to the comparators. The reference voltage for each comparator is one least significant bit (LSB) greater than the reference voltage for the comparator immediately below it [3]. Each comparator produces the output "1" when the input voltage is more than its reference voltage. When the output of a comparator is "1", than the output from all comparators below that is also "1".

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24 Sub-ADC

So the output from the comparators is in thermometric fashion. A thermometer to binary encoder is used to produce the binary output.

A differential mode flash sub-ADC is designed in the thesis which employs the differential comparators. In the next section we briefly discuss the comparator used in the sub-ADC.

4.1 Differential pair comparator

A differential pair sense-amplifier-based comparator used in sub-ADC is given in Figure 4.2. At any given time it is either in equalization mode or in regenerative mode. When the clock is low the comparator is in equalization mode, where two output nodes Vout,+ and Vout,− are equalized around Vdd − Vth. When clock is

switched to high state, the pull-down network connects the cross-coupled inverter with the ground, causing the current flow. A voltage difference on the input is then translated to current imbalance which leads to faster discharge of one node than the other. When the output nodes approach to switching point of the two cross-coupled inverters, the voltage difference is amplified to full swing [9].

Figure 4.2. Sense-amplifier-based comparator

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4.2 1.5-bit sub-ADC 25

4.2 1.5-bit sub-ADC

A differential mode 1.5-bit sub-ADC is realized with two comparators as shown in Figure 4.3. The output of the sub-ADC can only be in one of the three possible states namely, 00, 01 and 11. More specifically when the input signal is in the range Vin,min− Vin,min 4 , Vin,min 4 − Vin,max 4 and Vin,max 4 − Vin,max output is 00, 01

and 11 respectively. The thermometric output is converted to decimal equivalent in the File-writer module which is implemented as high-level model in Verilog-A. In order to generate a stable digital output signal latches are used.

Figure 4.3. Sub-ADC used in pipeline stage

4.2.1 Bias voltages

Bias voltages required are generated with ideal voltage sources in Cadence. Table 4.1 shows the reference voltages used in the sub-ADC. As the design is simulated for two different input voltage swings i.e., 500mV peak-to-peak at dc offset of 900mV and 200mV peak-to-peak at dc offset of 650mV, two different set of bias voltages is given in the table.

Input voltage swing(Vpp) Vref,+ Vref,−

500mV 962.5mV 837.5mV 200mV 675mV 625mV

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26 Sub-ADC

4.3 2-bit ADC

The last stage of the pipelined ADC is a 2-bit flash ADC, without any MDAC stage. It is implemented by cascading three comparators and thermometric to binary encoder as shown in Figure 4.4. Thermometric to binary encoding is implemented with a full-adder.

Figure 4.4. 2-bit flash ADC used in last stage

Reference voltages used are generated with ideal voltage sources. These are given in Table 4.2.

Input voltage swing(Vpp) Vref,h Vref,m Vref,l

500mV 1025mV 900mV 775mV 200mV 700mV 650mV 600mV

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Chapter 5

Delay and Correction Logic

5.1 Delay Logic

In a pipelined ADC each stage process a different input sample (time delayed) at any given time. For example, first stage operates on the most recent input sample, second stage process the result of the input sample delayed by 1 time unit and so on. Which means that the digital output of a input sample is partially generated by each stage at a different time unit. The most significant part of the digital output is generated by the first stage and the least significant part by the last stage. So there is a k time units latency for an input sample, where k is the number of stages. In order to synchronize the output delay elements are used.

A simple solution is to use a flip-flop at each output bit until the result from the last stage is generated. In other words the output of a stage m must be delayed by w clock cycles, where w is the number of pipelined stages after stage m. For example, for a 8-bit pipelined ADC with 1.5-bit stage resolution, the output from the first stage is delayed 6 clock cycles and the output from the second stage is delayed 5 clock cycles.

5.1.1 Delay logic used in thesis

The delay logic is mainly implemented in MATLAB. The data from the each stage is written into a file for further processing. Since the bits are generated at a positive and negative clock phases, it was observed that with a single file-writing block writing data at positive and negative edge of the clock introduces timing errors. Bits from the odd stages are delayed one clock cycle so that output bits from all stages are written into the file at the same time. This is shown in Figure 5.1.

Timing diagram for the delay logic used is shown in Figure 5.2. A valid output from each odd stage is available just after the positive edge of the clock φ, and the output from the even stages are available after the positive edge of the clock

¯

φ. As all flip-flop are clocked with ¯φ, so the output of odd (output from flip-flop)

and even stages are available for the writing to the file at the positive edge of the

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28 Delay and Correction Logic

Figure 5.1. Delay logic used in the project

clock φ.

Figure 5.2. Timing diagram for delay logic of Figure 5.1

5.2 Correction Logic

In order to eliminate the errors introduced by non-linearity in the sub-ADC, a scheme known as Digital Correction Logic is used in the pipelined ADC.

5.2.1 Basic Principle

As discussed in section 1.2.2, a true 1-bit sub-ADC with single comparator is not suitable in a pipelined ADC. So by adding an extra comparator in the sub-ADC stage resolution is increased to 1.5-bit (three levels). Here 0.5 bit is the overlap bit due to the extra comparator and is removed by the digital correction logic.

An error correction range for two stages of 1.5-bit resolution each is shown in Figure 5.3. Here we assume that A1 and A2 are the threshold levels for the sub-ADC in stage 1 and the threshold levels for sub-ADC in second stage are marked B1 and B2. The corrected codes for first stage are obtained by adding the (corrected) codes of the second stage with the output code of the first stage. Then for the final bit decision for the first stage, code 00, 01 and 10 is considered as ’0’ and code 11 is considered as ’1’. Errors are up to ±1₂ LSB in the first stage

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5.2 Correction Logic 29

are corrected [1]. Note that the correction is done from the last stage to the first stage.

"Digital correction improves the linearity by allowing the converter to post-pone decisions on inputs that are near the first-stage A/D subconverter decision levels until residues from these inputs are amplified to the point where similar nonlinearity in later-stage A/D subconverters is insignificant" [7].

Figure 5.3. Error correction range for 1.5-bit stage

5.2.2 Correction logic used in thesis

Each of the first six stages generate an output code 00, 01 or 11 where as the 2-bit last stage generates an output 00, 01, 10 an 11. As discussed in above section, output codes from each stage are added to generate the final output. The process for 8-bit ADC with 1.5-bit stage resolution is shown in Figure 5.4.

Figure 5.4. Digital correction for 8-bit pipelined ADC with 1.5 bit sub-ADC

While writing the output bit to the file, thermometric to decimal conversion is also done in the module File-writer, which is implemented in Verilog-A. So output from the first 6 stages are in the range 0-2 and output from the last stage is in the range 0-3. Digital error correction is implemented in MATLAB as shown in 5.1. And before digital correction delay balancing is done by reading the proper indices.

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30 Delay and Correction Logic

Output(i) = 64 ∗ x(i, 1) + 32 ∗ x(i, 2) + 16 ∗ x(i + 1, 3) + 8 ∗ x(i + 1, 4)

+4 ∗ x(i + 2, 5) + 2 ∗ x(i + 2, 6) + x(i + 3, 7) (5.1) where x is the vector where output of Figure 5.1 are stored and i runs from 1 to the number of samples.

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Chapter 6

Design and Design

Verification

A differential mode 8-bit pipelined ADC is designed and implemented in 0.18µm technology with 1.8V power supply. Top level design is shown in Figure A.1, where each of the first 6 stages is of 1.5-bit resolution. The last stage is of 2-bit resolution. As 0.5 bit is an overlap bit to compensate the offset error of the sub-ADC in the 1.5 bit stage, the actual resolution of 1.5-bit stage is 1-bit. 6 bits from the first six stages plus the 2-bits from the last stage together implements the 8-bit ADC. A top level diagram of the 1.5-bit stage is shown in Figure A.2. Sampe-and-Hold (S/H) is realized with a transmission gate and a capacitor at circuit level. 1.5-bit ADC is implemented as a flash ADC, where comparators are realized at transistor level. Bias voltages for the ADC are provided with ideal voltage sources. Transistor level realization of the MDAC is used in the design. Bias voltages for the MDAC are also generated from ideal voltage sources. The last 2-bit ADC is realized as a flash ADC at transistor level. The bias voltages for this are also generated from ideal voltage sources in Cadence. Block diagram at high level to the transistor level schematics of each module used in the design are given in Appendix A. D flip-flops and file-writer are implemented in Verilog-A and are given in Appendix B. The MATLAB code for the error-correction and ENOB calculation is given in Appendix C.

6.1 Design Flow

After the abstract level modeling in MATLAB of the 8-bit pipelined ADC we implemented the design in Cadence. The implementation process can be divided into three phases.

In phase 1 a single stage MDAC was realized at transistor level and simulated. This was done to see the effects of parameters (transistors size and bias voltages) variation on the output transfer function and to achieve an output function which is close to the ideal one. Simulation of the MDAC required a S/H to hold the

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32 Design and Design Verification

input voltage until ADC’s output is generated. A 1.5-bit ADC is used to gener-ate the digital output and multiplexers to select the proper bias voltage for the MDAC based on the ADC’s output. The S/H, 1.5-bit ADC and multiplexers were implemented at high level in Verilog-A. Transient simulations were performed.

In the second phase, a complete test bench shown in Figure A.1 was setup to measure the ENOB based on phase 1 optimization. Here in each stage only the MDAC was realized at transistor level. S/H, 1.5-bit ADCs and multiplexer were in Verilog-A. To calculate the ENOB digital output from each stage was synchronized and stored in a file on the computer. Delay elements, D flip-flop, used to synchronize the digital code were implemented in Verilog-A. The reason for using delay with odd stages is that digital output from each stage is synchronized in the way so the file-writer can write the data on a single clock edge. The Verilog-A implementation of the DFF is shown in Verilog-Appendix B. Before writing the output bits, thermometric code from each stage is converted to decimal equivalent in file-writer block. The Verilog-A implementation of the file-writer module is given in Appendix B. The MDAC realized at transistor level and all other modules implemented at high-level gave an indication of how good ENOB and speed could be achieved. The maximum ENOB and sampling frequency acheived in this phase was 6.15 and 220MHz respectively. Estimation of maximum sampling frequency is based on the delay of the MDAC. The maximum delay of MDAC measured was around 2.3ns, and the output of the MDAC has to settle within the half clock cycle.

In last phase each stage was completely realized at transistor level and simu-lation were performed. Schematics of the MDAC, S/H, 1.5-bit ADC, 2-bit ADC are shown in Appendix A. Final optimization was performed to achieve the results close to one obtained in phase 2. In this phase the Verilog-A implementation of the DFF was used and error-correction was performed in MATLAB before the ENOB calculation. The design was simulated in Cadence environment, UMC 0.18µm technology with 1.8V power supply.

6.2 Input voltage

We decided to design the ADC with the maximum voltage swing VF S, as power

consumption is inversely proportional to the square of the VF S. This is derived

in Equations 2.20 and 2.22. Note that power consumption is directly proportional to gm.

By putting Vdd=1.8V and VT=0.5V in Equation 2.16 we get Vmax=1.15V.

With Vmin=VT, the maximum voltage swing is 0.65V. So VF S=0.5V at dc offset

of 0.9V was chosen for the design. After the optimization of the design with VF S=0.5V, we decided to optimize the design for lower voltage swing. This was

done to see how much ENOB can be improved with lower VF S. VF S=0.2V was

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6.3 Sampling frequency 33

6.3 Sampling frequency

Each stage of the pipeline ADC shown in Figure A.2 is clocked with time period Tclk. In one half of the clock period, S/H and sub-ADC are in evaluation mode

where in other half the MDAC performs its operation. As the MDAC has max-imum delay which limits the minmax-imum value of Tclk. With transient simulation

by providing DC voltage at input of the MDAC and observing the time it takes to settle the MDAC’s output, delay is calculated. The DC voltages are chosen such in a way that they correspond to worst case for the MDAC. The maximum delay measured for VF S = 0.5V with this approach is 2.3ns, corresponding to

sampling frequency fs of 217MHz. The maximum sampling frequency estimated

for VF S= 0.2V is 208MHz.

In Figure 6.1, ENOB is plotted against sampling frequency. From transient noise analysis, ENOB is calculated by taking 1024 points for the corresponding sampling frequency. The input signal is a sine wave with VF S=0.5V and input

frequency, calculated according to Equation 6.1 with k=3 and N=1024. Here we see that for fs=200MHz the ENOB is around 6 and for above 200MHz it is droped

significantly. So we chose fs=200MHz for VF S= 0.5V.

Figure 6.1. Plot of ENOB vs sampling frequency for the VF S=0.5V

In Figure 6.2 ENOB for VF S=0.2V is shown with respect to sampling

fre-quency. Here we see that for fs less than 100MHz ENOB is greater than 6. And

for fs greater than 100MHz ENOB is reduced rapidly. We choose fs=100MHz for

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Figure 6.2. Plot of ENOB vs sampling frequency for the VF S=0.2V

6.4 Optimization process

In general optimization is done by varying the parameters (transistor sizes, bias voltages) and observing the effect of those variation on the output function and ENOB, the parameters were varied in the same direction or in opposite direction. To explain this the ideal transfer of a pipeline stage is shown in Figure 6.3. Vout is the difference of Vout,p and Vout,n. Vin is the difference of Vin,p and

Vin,n. This output function can be divided into three regions, the left most region,

middle region and the right most each separated by the a vertical line in the output function. In each region the slope of the output function is 2. In first phase of the design, keeping the ideal output function in mind transistor sizes and bias voltages of the MDAC were varied until we achieved the output function close to the ideal one. To do this systematically the effect of variation of each transistor size on the slope and the DC level of the output function was recorded. In second and third phase this process was carried out until further adjustment had a negative effect on the results. The optimized transistor sizes and bias voltages for the MDAC are shown in Table A.4 and A.5 respectively.

From Equation 2.20 with M=6, VF S=0.5V, γ =1.5 and n=8 we get CL=118fF.

For a differential case this means 2 capacitors of 59fF each. With VF S=0.2V we

get CL=366fF. For VF S=0.2V and CL=366fF the maximum ENOB obtained is 5.5

at sampling frequency of 100MHz, which is not a very good value. An optimum value is found for the capacitor to obtain ENOB greater than or equal to 6 at 100MHz. The optimum value of CL=100fF is used in the design.

Block diagram and/or schematic with transistor sizes and bias voltages of each module implemented is given in Appendix A. All gates (NOT, AND, NAND, NOR, XOR) used to implement the SR latch, multiplexer and full adder are designed as static CMOS logic with the minimum transistor sizes (width of the PMOS is kept 3× that of the NMOS).

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6.5 Simulation method 35

Figure 6.3. Plot of the ideal output function for VF S=0.5V

6.5 Simulation method

During the optimization process the transient simulation with accuracy setting of

moderate is used mainly. To see the effect of noise on the design, transient noise

simulation is done. Noiseseed=1 and noisefmax=1G are used in the transient noise simulation. All results shown in this thesis are obtained from the transient noise analysis.

6.6 ENOB calculation

Output stored with the file-writer module are read in MATLAB. As the output (bits) of each odd stage is delayed so that the file-writer can write the results at single edge of the clock. Each line of the output file contains 7 decimal values, one for each stage. The first two values in each line of the output file corresponds to input sample m, third and fourth corresponds to sample m-1, fifth and sixth to m-2 and last value corresponds to input sample m-3. So synchronization is done to align the output corresponding to a input sample. Then error-correction is performed and finally calcENOB function is called to calculate the ENOB. The MATLAB code is given in Appendix C.

The calcENOB function given in Appendix C, takes output data, angular fre-quency, ω, of the input signal and a time vector t to calculate the ENOB. It estimates the error from the data. Then root mean square (rms) value of the input signal and error are calculated. Then it calculates the SINAD from the rms value of input signal and error. Finally ENOB is calculated from SINAD.

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as shown in Equation 6.1.

fin=

k

Nfs (6.1)

Where fin is input signal’s frequency, k is an odd integer, N is number of

samples and fs is sampling frequency. The number of points, N=1024 is chosen

for the results shown in this report.

6.7 Power calculation

Except the DFF and file-write block all other modules (MDAC, S/H, 1.5-bit ADC and 2-bit ADC) are realized at transistor level. In the test bench a single voltage source is used to provide Vdd to each transistor. Current drawn from that single

voltage source is averaged and used for the power calculation. As the bias voltages for MDAC and sub-ADCs are generated with the ideal voltage sources, so the power reported in the thesis does not include the power consumption of the bias circuit.

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Chapter 7

Results and Future work

7.1 Results

7.1.1 ENOB of the optimized design

For VF S=0.5V ENOB is plotted against the input frequency, finin the Figure 7.1.

Up to 3MHz of input frequency ENOB is around 6. The ENOB is dropped to 5.5 around input frequency of 5MHz, so the effective bandwidth of the optimized ADC is 5MHz.

Figure 7.1. Plot of the ENOB vs input frequency for VF S=0.5V

The ENOB measured from the optimized design for VF S=0.2V is given in

Figure 7.2. Up to 4MHz ENOB is greater than 5.5. The effective bandwidth

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38 Results and Future work

(where ENOB is reduced by 0.5 bit) is 4MHz.

Figure 7.2. Plot of the ENOB vs input frequency for VF S=0.2V

7.1.2 Power consumption

In this section we first calculate the theoretical power consumption then we present the measured power consumption. From Equation 2.22 with fS=200MHz, CL=60fF

and n=8 we get gm=130µA/V. The required DC current is gmVef f, where Vef f

must be equal to the voltage swing, VF S. With VF S=0.5V we arrive to a

cur-rent of 65µA per transistor stage, or 195µA for the full MDAC. 12 MDACs (2×6 MDACs totally) then consume 2.34mA. We have a power consumption of 2.34mA*1.8V=4.21mW for the MDACs. As the effective resolution is 6, putting n=6 in Equation 2.22 the power consumption is 3.24mW.

We can compare power to the "ideal sampling power" [10], 24kTfs22n=0.8µW.

Here we are 4000× over this value, which is not too bad. We can understand some "losses". 1.8/0.5=3.6× from small voltage swing. 6× from using 6 transistors instead of one in the MDAC, together 20×.

For VF S=0.2V, with fS=100MHz, CL=100fF and n=6 we get gm=83µA/V.

With Vef f=0.2V current per transistor is 16.5µA. The total power consumption

is 595µW.

Power measured for VF S=0.5V from simulation is plotted in Figure 7.3. We

see that maximum power consumption is 3.4mW. We also note that the power consumption is almost constant with respect to input signal’s frequency. The power consumption for effective bandwidth is 3.4mW.

Figure 7.4 shows the measured power consumption of the ADC for VF S=0.2V.

The relationship of the power consumption and sampling frequency is shown in Figure 7.5 and 7.6 for the optimized design with VF S=0.5V and VF S=0.2V.

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7.1 Results 39

Figure 7.3. Plot of the power consumption vs input frequency for VF S=0.5V

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40 Results and Future work

Figure 7.5. Plot of the power consumption vs sampling frequency for VF S=0.5V

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7.2 Future Work 41

7.2 Future Work

The most important task after this would be to proceed with the layout imple-mentation so that the design can be verified by measuring the results from the fabricated chip.

This may include the circuit realization of the following modules.

• Biasing for the MDAC circuit and comparators used in sub-ADCs and in the last stage’s 2-bit Flash ADC

• Thermometric to binary encoding for sub-ADCs • Flip-flops for the delay logic

• Correction algorithm • Clock generator

• Differential input generator

One may choose to use the external bias voltages and clock signals while pro-cessing the thermometric to binary encoding, output synchronization and correc-tion algorithm off the chip to save the chip area and design time at cost of too many input/output pins on the chip.

Another future aspect of the design can be to use some advanced correction algorithm to improve the ENOB.

As discussed in chapter 3, the design of MDAC is carried on the analysis of the circuit given in "On current mode circuits", where we used a simple first order current equation to model the system. In future design more parameters may be considered for the better optimization.

7.3 Conclusion

As the main goal was to investigate that how many effective number of bits is possible with this simple and straightforward design, where the simplicity gives good speed, low area and low power consumption. Our results indicate that we can achieve ENOB of 6, which we think would have been sufficient for the original target application, the X-ray detector system, although we decided not to use an ADC in this system.

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Bibliography

[1] O. A. Horna. "A 150 Mbps A/D and D/A conversion system", Comsat Tech. Tev., vol. 2, no 1, pp. 3.73, 1972.

[2] Maxim. "Defining and Testing Dynamic Parameters in High-speed ADCs, Part1", http://pdfserv.maxim-ic.com/en/an/AN728.pdf, Application Note 728, 2001.

[3] Maxim. "Understanding Flash ADCs", http://pdfserv.maxim-ic.com/en/an/AN810.pdf, Application Note 810, 2001.

[4] Nianxiong Nick Tan Mikael Gustavsson, J. Jacob Wikner. "CMOS DATA CONVERTERS FOR COMMUNICATIONS", Publisher: Kluwer Academic Publishers, 2000, ISBN 0-7923-7780-X.

[5] Behzad Razavi. "Design of Analog CMOS Integerated Circuits", Publisher: McGraw-Hill Science Engineering, 2000, ISBN 9780072380323.

[6] Behzad Razavi. "Priciples of Data Convertion System Design", Publisher: IEEE Press, 1995, ISBN 0-7803-1093-4.

[7] PAUL R. GRAY STEPHEN H. LEWIS. "A Pipelined 5-Msample/s 9-bit Analog-to-Digital converter", IEEE Journal of Solid State Circuits, vol. SC-22, No. 6, December 1987.

[8] Lauri Sumanen. "Pipeline Analog-to-Digital Converters for Wide-Band Wire-less Communications", Publisher: Helsinki University of Technology, 2002, ISBN 951-22-6222-3.

[9] A. Alvandpour T. Sundström. "A KICK-BACK REDUCED COMPARA-TOR FOR A 4-6BIT 3-GS/S FLASH ADC IN A 90NM CMOS PROCESS", Mixed Design of Integrated Circuits and Systems, 2007. MIXDES ’07. 14th International Conference.

[10] Christer Svensson Timmy Sundström, Boris Mormann. "Power Dissipation Bound for High-Speed Nyquist Analog-to-Digital Converters", IEEE Trans-action on Circuits and Systems, pp. 509-518 Vol. 56, No. 3, March 2009. [11] Eby G. Friedman Weize Xu. "CLOCK FEEDTHROUH IN CMOS ANALOG

TRANSMISSION GATE SWITCHES", Publisher: IEEE, 2002.

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Appendix A

Design Schematics and

Parameters

Figure A.1. Design at top level

Figure A.2. A pipeline stage

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46 Design Schematics and Parameters

Figure A.3. Schematic of Sample-and-Hold

(VF S) M0 M1 M2 M3 CL

0.5V 500nm 1.5µm 250nm 750nm 60pF 0.2V 3µm 9µm 1.5µm 4.5µm 100pF

Table A.1. Optimized transistors’ width for comparator

Figure A.4. A 1.5-bit Flash ADC

(VF S) Vref,+ Vref,−

0.5V 962.5mV 837.5mV 0.2V 675mV 625mV

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47

Figure A.5. Schematic of comparator used in ADC

(VF S) M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10

0.5V 1 1 1 1 1 1 1 1 3 3 3 0.2V 1 1 1 1 1 1 0.5 0.5 0.5 0.5 1.5

Table A.3. Transistors’ width (in µm) for comparator

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Figure A.7. Schematic of MDAC

(VF S) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 Length

0.5V 3.2 0.61 3.2 0.61 4.18 0.44 2.2 0.48 0.79 0.49 360nm 0.2V 1.2 0.5 1.2 0.5 2.15 0.85 2.3 0.9 1.6 0.85 360nm

Table A.4. Optimized transistors’ width (in µm) for the MDAC circuit

(VF S) Vdac,p,pmos Vdac,p,nmos Vdac,n,pmos Vdac,n,nmos Bias

0.5V 860mV 980mV 860mV 980mV 900mV 0.2V 1040mV 635mV 1040mV 635mV 1020mV

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49

Figure A.8. 2-to-1 multiplexer used in MDAC

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Input voltage swing(Vpp) Vref,h Vref,m Vref,l

0.5V 1025mV 900mV 775mV 0.2V 700mV 650mV 600mV

Table A.6. Reference voltages for 2-bit ADC

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Appendix B

Verilog-A code of DFF and

file-writer

B.1 DFF implemenation

Given below is the Verilog-A for DFF.

// INSTANCE parameters

// vlogic_high = output voltage for high [V] // vlogic_low = output voltage for high [V]

// vtrans = voltages above this at input are considered high [V] // vtrans_clk = transition voltage of clock [V]

// tdel, trise, tfall = {usual} [s] //

module d_ff(vin_d, vclk, vout_q); input vclk, vin_d;

output vout_q;electrical vout_q, vclk, vin_d; parameter real vlogic_high = 1.8;

parameter real vlogic_low = 0; parameter real vtrans_clk = 0.9; parameter real vtrans = 0.9;

parameter real tdel = 20p from [0:inf); parameter real trise = 20p from (0:inf); parameter real tfall = 20p from (0:inf);

integer x; analog begin

@ (cross( V(vclk) - vtrans_clk, +1 )) x = (V(vin_d) > vtrans);

V(vout_q) <+ transition( vlogic_high*x + vlogic_low*!x, tdel, trise, tfall ); end

endmodule

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52 Verilog-A code of DFF and file-writer

B.2 File-writer implementaion

Given below is the Verilog-A code for file-writer module. ‘include "constants.vams" ‘include "disciplines.vams" module File_writer(clk, b1_0, b1_1, b2_0, b2_1, b3_0, b3_1, b4_0, b4_1, b5_0, b5_1, b6_0, b6_1, b7_0, b7_1); electrical clk, b1_0, b1_1, b2_0, b2_1, b3_0, b3_1, b4_0, b4_1, b5_0, b5_1, b6_0, b6_1, b7_0, b7_1; parameter real vthres=0.9;

parameter string filename="/tmp/adc_out.txt"; //Local variables integer x1, x2 ,x3 ,x4 ,x5, x6, x7; integer outdata; integer outfile; analog begin @ ( initial_step ) begin outfile = $fopen(filename,"w"); end

@ (cross(V(clk) - vthres, +1)) begin outdata=0;

//stage1 - 1.5 bit stage

if (V(b1_1)<vthres && V(b1_0)<vthres) x1 = 0;

else if (V(b1_1)<vthres && V(b1_0)>vthres) x1 = 1;

else if (V(b1_1)>vthres && V(b1_0)>vthres) x1 = 2;

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B.2 File-writer implementaion 53

//stage7 - 2 bit stage

else if (V(b7_1)>vthres && V(b7_0)<vthres) x7 = 2;

//Write data to file

$fstrobe(outfile, "%d %d %d %d %d %d %d", x1, x2, x3, x4, x5, x6, x7); end // Close file @(final_step) $fclose(outfile); end endmodule

Low-power 8-bit Pipelined ADC with current mode Multiplying Digital-to-Analog Converter (MDAC)

Institutionen för systemteknik

Department of Electrical Engineering

Examensarbete

Low-power 8-bit Pipelined ADC with current mode

Multiplying Digital-to-Analog Converter (MDAC)

Low-power 8-bit Pipelined ADC with current mode

Multiplying Digital-to-Analog Converter (MDAC)

Examensarbete utfört i Elektroniska komponenter

vid Tekniska högskolan i Linköping

av

Abstract

Acknowledgments

Contents

List of Figures

List of Tables

Chapter 1

Introduction

1.1

The task

1.2

Analog-to-Digital Converter

1.3

Pipelined ADC

1.3.1

Architecture

1.3.2

1.5-bit stage

1.3.3

Latency

1.3.4

Correction Algorithm

1.4

ADC Performance metrics

1.4.1

Static specifications

1.4.2

Dynamic specifications

Chapter 2

Multiplying

Digital-to-Analog Converter

(MDAC)

2.1

On current mode circuits

2.1.1

Adjusting transistor sizes

2.1.2

Effect of V

spread

2.1.3

Voltage swing

2.2

Current mode differential MDAC

2.2.1

Power consumption

Chapter 3

Sample-and-Hold

3.1

Basic Principle

3.2

Complementary Switch

3.3

Error sources in S/H

3.3.1

Channel Charge Injection

3.3.2

Clock Feedthrough

3.3.3

Thermal Noise

3.3.4

S/H with dummy switches

Chapter 4

Sub-ADC

4.1

Differential pair comparator

4.2

1.5-bit sub-ADC

4.2.1

Bias voltages

4.3