Histogram Based Correction of Matching
Errors in Subranged ADC
Jonas Elbornsson
Jan-Erik Eklund
Division of Communication Systems
Department of Electrical Engineering
Link¨
opings universitet
, SE-581 83 Link¨
oping, Sweden
WWW:
http://www.comsys.isy.liu.se
Email:
jonas@isy.liu.se
5th November 2001
REGLERTEKNIK
AUTOMATIC CONTROL LINKÖPING
Report No.:
LiTH-ISY-R-2400
Submitted to ESSCIRC’01
Technical reports from the Communication Systems group in Link¨oping are available by anonymous ftp at the address ftp.control.isy.liu.se. This report is contained in the file 2400.pdf.
Abstract
A method for correcting matching errors in an ADC is presented. The method uses the unknown input data from the application and does not require any test signal. Two algorithms for implementing the method are compared. One algorithm is general and works on any type of ADC. The other algorithm utilizes the subranged architecture of a specific ADC and is very simple to implement in hardware. The signal quality is similar for both algorithms.
Histogram Based Correction of Matching Errors in Subranged ADC
J. Elbornsson
Link¨opings universitet
Department of Electrical Engineering
SE-581 83 Link¨oping,SWEDEN
jonas@isy.liu.se
J.-E. Eklund
Ericsson Microelectronics AB
SE-581 17 Link¨oping, SWEDEN
jan-erik.eklund@mic.ericsson.se
Abstract
A method for correcting matching errors in an ADC is presented. The method uses the unknown input data from the application and does not require any test signal. Two al-gorithms for implementing the method are compared. One algorithm is general and works on any type of ADC. The other algorithm utilizes the subranged architecture of a spe-cific ADC and is very simple to implement in hardware. The signal quality is similar for both algorithms.
1.
Introduction
In modern communication systems, such as xDSL modems and radio base stations, a greater part of the signal process-ing is done in the digital domain. This increases the de-mands on high performance of the analog to digital con-verter, ADC. Calibration of an ADC is time-consuming and expensive. Therefore a lot of costs can be saved if the errors in the ADC can be automatically estimated and removed under drift.
Several methods for compensating for these errors have been presented, [1, 2]. These methods are based on equal-ization of the histogram of the output signal. But all of them assume either a training signal with known probability den-sity or an additional ADC with higher accuracy than the ADC-under-test to estimate the probability density.
In this paper, we will present a method for estimating matching errors in subranging AD converters, that does not assume any knowledge of the input signal, except that its amplitude distribution function should be smooth. We will also compare two algorithms for implementing the method. The first algorithm does not assume any knowledge of the subranging structure of the ADC. In the second algorithm,
the subranging structure of the test ADC is explicitly used for simplifying realization in hardware.
2.
ADC Description
The algorithms are tested on an ADC of the type subranged Successive Approximation-ADC. The reference level gen-eration is implemented as a combination of voltage shar-ing in resistor ladders and charge redistribution in capac-itors. Each resistor ladder together with a capacitor form one subranging stage, Fig. 1, [3, 4]. The analog signal,v
a,
is sampled in the capacitorC
1 by bottom plate sampling.
The binary search algorithm is then implemented as: select
a,b,cso that min(v a C 1 (V 1 aC 1 +V 2 bC 2 +V 3 cC 3 ))>0 (1)
The digital output code from the ADC, D, is then formed
from a,b, cwhich are represented by4,4,5bits
respec-tively. The subranging stages are overlapping [5] and a redundant code is formed as
D=(a12+b)24+c (2)
where the bits in a are the most significant. (A
non-redundant code would be formed asD=(a2 4
+b)2 5
+c.)
In [5] the redundancy is used for dynamic error correction. Here, we will use it for matching error correction.
The test ADC is implemented in a 0.6m CMOS 2M2P
process, where the resistors are made of poly-silicon. The clock frequency during the test was 10MHz (sampling fre-quency 10/16MHz) and the circuit consumed 2mW from a 3.3V supply. + _ V1⋅a C1 C2 C3 va Sampling Comparator Binary search Switch
Test chip MATLAB
algorithm Calculate parameters , HˆE Θ Accumulate histogram HM Equation (2) D Calculate Address A C Look-up table LUT(A) Generate corrected data a=0 a=15 Stage 1 V2⋅b b=0 b=15 Stage 2 V3⋅c c=0 c=31 Stage 3 control
110 101 100 011 010 001 111 000 011 010 Stage 1 Stage 2 y z z z 110 101 100 011 010 001 111 000 110 111 010 001 000 Code density, HM Decimal Code D 3⋅6+1=19: y=011, z=001 3⋅6+2=20: y=011, z=010 2⋅6+6=18: y=010, z=110 2⋅6+5=17: y=010, z=101 2⋅6+4=16: y=010, z=100 2⋅6+3=15: y=010, z=011 2⋅6+2=14: y=010, z=010 2⋅6+1=13: y=010, z=001 1⋅6+6=12: y=010, z=110 011 010 Stage 1 Stage 2 y z z z 110 101 100 011 010 001 111 000 110 111 010 001 000 Error Code density, HM Decimal Code D 2⋅6+7=19: y=010, z=111 3⋅6+1=19: y=011, z=001 2⋅6+6=18: y=010, z=110 2⋅6+5=17: y=010, z=101 2⋅6+4=16: y=010, z=100 2⋅6+3=15: y=010, z=011 2⋅6+2=14: y=010, z=010 2⋅6+1=13: y=010, z=001 1⋅6+7=13: y=010, z=111 3⋅6+2=20: y=011, z=010 1⋅6+6=12: y=010, z=110 011 010 Stage 1 Stage 2 y z z z 110 101 100 011 010 001 111 000 011 010 001 000 E rror Code density, HM Decimal Code D 3⋅6+2=20: y=011, z=010 3⋅6+3=21: y=011, z=011 2⋅6+6=18: y=010, z=110 2⋅6+5=17: y=010, z=101 2⋅6+4=16: y=010, z=100 2⋅6+3=15: y=010, z=011 2⋅6+2=14: y=010, z=010 2⋅6+1=13: y=010, z=001 1⋅6+6=12: y=010, z=110 110 101 111 3⋅6+1=19: y=011, z=001 1⋅6+5=11: y=010, z=101 (c) (d) (f) (e) (g) (h) Single stage D (binary code) Code density, HM Decimal Code D (a) (b) 6 5 4 3 2 1 7 0
Fig. 2. Left column: references with various matching
er-rors. Right column: corresponding histograms.
3.
Theory
In this section, a method for estimation and correction of mismatch errors in ADCs is described. Two algorithms for implementing the method, one general and one subrange specific, are also described.
3.1. Common properties and definitions
The basic ADC operation is summarized as: Sample an ana-log signal, compare the sample with a set of anaana-log refer-ence levels and assign the output to a digital code which corresponds to a selected reference level.
The matching error origin in that we cannot produce ref-erence levels with enough accuracy. Thus, we do not know exactly what a digital output code from the ADC means. The correction methods use a look-up table with the content
LUT for adjusting the digital output codes from the ADC, D(2), to corrected values,C, in such a way that the transfer
function from the analog input signal,v
a, to the value Cis
linear (except for quantization).
The information we use to calculateLUTis a histogram, H
M, of the ADC output,
D. Fig. 2(a) shows an analog
ref-erence with matching errors. The height of each step in the reference corresponds to the probability that the analog sig-nal is within this range and thus the number of occurrences of the corresponding code at the analog output, Fig. 2(b). The problem is that the density of a specific code is also dependent of the amplitude distribution of the analog in-put signal,v
a, which is unknown. With the assumption that
two neighboring codes should have approximately the same code density, an estimate of the expected histogram, ^
H E,
can be calculated from,H
M, by a filtering operation. The
relation between ^ H
E and H
M then give a correction
pa-rameter vector. The address to the look-up table,A, is
calculated fromDand the vectorLUT is calculated as
LUT(A)= A X
i=1
(i)+A (3)
Most of the codes will occur in the middle of the range, Fig. 4. The estimate will be best in the middle. If we have a repetitive structure, the errors in the ends can be extrapo-lated, but the result is not perfect. This can be seen in Fig. 5, where the performance is less ideal for large amplitudes.
3.2. General estimation algorithm
This general algorithm is based on the data word D (2),
which will have a behavior as in Fig. 2(a)(b). The algorithm does not take any information about the subranging into ac-count. The algorithm is described in more detail, and in a more general form in [6]. In this paper, we have modified this algorithm to handle only large errors. This modifica-tion greatly reduces the calculamodifica-tion burden. The algorithm is divided into two parts:
^ H
E is calculated as a low pass filtered version of H
M.
Here a zero-phase filter should be used to avoid drift to-wards higher levels. This is achieved by forward-backward filtering of a second order butterworth filter.
The next step is to find a mapping,D!C, that
elimi-nates the matching errors inC. First the codes
correspond-ing to the largest errors are found by comparcorrespond-ingH M with ^ H E. l=fDj jH M (D) ^ H E (D)j ^ H E (D) >g (4)
Herelis a vector that contains the codes where the relative
deviation between the measured and estimated histograms is larger than. A vector=[
1 :::
N
]is used to
parame-terize the errors in the ADC. The parameters corresponding to levels with large errors, f
i
(In the general formulation all the parameters are free). The other parameters are fixed to the relative mean deviation be-tween the measured and the estimated histogram. The his-togram of the corrected output, ^
H E
(D;), is
parameter-ized with the error vector by interpolation between adjacent histogram values. The error estimate,^
, is calculated as the
minimizing argument of the loss function
V()= N X D=1 (H M (D) ^ H E (D;)) 2 (5) where N is the number of levels in the ADC. The loss
function is minimized numerically with the steepest descent method.
The address to the look-up table in Fig. 1 isA=Dand
the corrected value isC=LUT(A). 3.3. Implementation specific algorithm
The implementation specific algorithm is directly based on the separation into subranging stages, and is intended to be simple to implement in hardware.
The algorithm is illustrated by an example of how a matching error is found in a 2-stage subranging SA-ADC with 3 bits in both the first and second stage and a redun-dant code, Fig. 2(c-h). Fig. 2(c) shows how the stages map to each other. The output (in this example) is formed as
D=y6+z (6)
The codes marked with bold face in Fig. 2(c-h)
fy2f000 111g;z2f001 011ggare unique, and
ide-ally, the result should be a combination of these codes. The other combinations of codes occur when there are match-ing errors. In this example we assume that, if there are no matching errors,H
M is a constant function, Fig. 2(d).
If the physical reference level, which is corresponding to the codey = 011, is a bit too high, Fig. 2(e), the code fy =010;z = 111gwill start to appear. The mapping of fy = 010;z = 111gto an output code (6) will, however,
giveD=19, which is the same as forfy=011;z=001g.
The number of occurrences of the codeD=19is then too
high, Fig. 2(f). If the physical reference level, which is cor-responding to the codey=011, is a bit too low, Fig. 2(g),
the codefy=010;z=110gwill almost not appear at all.
The number of occurrences of the codeD=18is then too
low, Fig. 2(h).
As seen in Fig. 2(f)(h), the positions of the matching errors in the histogram is known. This information is used to simplify the algorithm:
26250 2630 2635 2640 2645 2650 2655 2660 500 1000 1500 2000 2500 3000
Histogram for code segment with matching error
Code number Code count Measured 1st Estimate Selected 2nd Estimate
Fig. 3. Measured and estimated histogram segment
Divide H
M into fractions around the positions of the
errors,H Mi
=fH M
(D),D=32i;:::;32(i+1) 1g
(+ in Fig. 3). (The value 32 comes from 5 bits in the fine reference in the implemented ADC.) For each segment,i,
calculate ^ H
Eias an LMS curve fit of a straight line to H
Mi,
(dashed in Fig. 3). (This can be compared to the filtering operation in 3 3.2). Since ^
H
Eiis heavily dependent of the
error, this first estimate is not very good. Therefore, select the values close to ^
H
Ei (o in Fig. 3) and calculate a new
estimate ^ H
Ei(solid line in Fig. 3). The size of the matching
error is then given as the relative error as:
(i)= 32 X k =1 H Mi (k) ^ H Ei (k) ^ H Ei (k) (7)
From (2), we get the address to the look-up table in Fig. 1 asA=(a12+b)and the corrected data asC=LUT(A) 24+c.
4.
Implementation
The algorithms was tested as post processing in MATLAB of measured data. The cost of implementing them in hard-ware is of great importance for the usefulness and is there-fore investigated. Table 1 shows the number of operations and an estimate of required area and power, which is needed to do an implementation in a 0.25m CMOS process. Only
the collection of the histograms and the look-up table access are done at the sampling frequency. The correction algo-rithms are calculated batch wise and thus several millions of clock periods are available. This part can be implemented as a very small processor, which also can handle the control.
Table 1. Implementation cost
Algorithm
Operation GeneralSpecific Units Histogram 64 K 64K bits of RAM
0.3 0.3 mW/(MSamples/s) 1 1 mm2 Additions 1 M 71 k Multiplications 1 M 51 k Divisions 13 k HW including 20 k 20 k Gates control 0.5 0.5 mm2 0.1 0.1 mW/(MSamples/s) Memory for 1 M 8 K bits of RAM calculations 15.6 0.13 mm2
0.3 0.3 mW/(MSamples/s) Look-up table 182 K 8 K bits of RAM
2.9 0.13 mm2
0.3 0.3 mW/(MSamples/s) Total area 20 1.8 mm2
Total power 1 1 mW/(MSamples/s)
5.
Measurements
In this section we show results from measurements on the ADC described in section 2. Both estimation algorithms described in section 3 are evaluated here.
5.1. Data acquisition
A sequence of Discrete Multi Tone (DMT) symbols was used as input signal to the ADC when calculating the his-togram. In Fig. 4, an example with510
6
20000 2200 2400 2600 2800 3000 2000 4000 6000 8000 10000 12000 code number code density
Histogram of output signal
Fig. 4. Measured histogram,H M
5.2. Evaluation
The correction algorithms have been evaluated with sinu-soidal signals. The signal power has been varied and the Signal to Noise and Distortion Ratio (SNDR) and Spuri-ous Free Dynamic Range (SFDR) has been measured before and after correction for each signal, Fig. 5. Both methods show similar results and the peak improvement is about 8dB for SNDR and 14dB for SFDR.
6.
Discussion
6.1. Reference signals
The assumption was that two neighboring codes would have similar densities. For the large data sets in this test, this is true enough. The results in this paper are based on a his-togram from a DMT signal, which has a nice distribution. A more nasty set of signals, with sequences of one strong and one weak (<32 LSBs) sine wave was also tested. The
correction works as good as for DMT, but the data set has to be increased about 5 times.
6.2. Validation of the algorithms
The results show that matching errors in an ADC can be cor-rected on the fly. There are mainly two differences between the algorithms that was tested.
First, the general algorithm requires a large memory for storing the Jacobian of the histogram, and will thus require a large area. The subrange specific algorithm requires only 1.8mm2
and 1 mW/(MSamples/s) which makes it feasible. The second difference considers overflow in the his-togram accumulators. The filtering operation in the gen-eral algorithm rely on the entire histogram. Handling of overflow (reset or scaling) must thus be done on the entire histogram simultaneously. The ratio between high and low density will thus be preserved, which limits the precision in the ends of the histogram. In the subrange specific al-gorithm, the filtering is done on each segment separately, Fig. 3. Overflow within one segment can be handled as di-vide by 2 or 4 (shift operation) within the segment only. The histogram will thus be compressed. In principle, this means that data is acquired for a longer time in the low density regions and precision is increased for these codes.
7.
Acknowledgment
The authors would like to thank Dr. Dake Liu at Link¨oping University for help with estimating the implementation cost.
−800 −70 −60 −50 −40 −30 −20 −10 0 10 20 30 40 50 60 70 80
Signal Power [dBFullScale]
SNDR(+), SFDR(o) [dB] Signal quality compensated not compensated (a) −800 −70 −60 −50 −40 −30 −20 −10 0 10 20 30 40 50 60 70 80
Signal power [dBFullScale]
SNDR(+), SFDR(o) [dB]
Signal quality corrected
not corrected
(b)
Fig. 5. Signal quality for (a) General (b) Subrange specific
algorithm. + marks SNDR and o marks SFDR. Solid line indicates corrected and dashed line indicates not corrected. The theoretical limit for SNDR (quantization) is drawn as a solid line.
8.
References
[1] F. Maloberti S. Mazzoleni U. Gatti, G. Gazzoli, “A calibration technique for high-speed high-resolution A/D converters,” in
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[2] C.F.N. Cowan A.C. Dent, “Linearization of analog-to-digital converters,” IEEE Transactions on Circuits and Systems, vol. 37, no. 6, pp. 729–737, June 1990.
[3] J.-E. Eklund, “A 200MHz cell for a parallel-successive-approximation ADC in 0.8m cmos, using a reference pre-select scheme,” in Proceedings of the 23rd European
Solid-State Circuits Conference, Southampton, UK, September
1997, pp. 388–391.
[4] C. Svensson J. Yuan, “A 10-bit 5ms/s successive approxi-mation adc cell used in a 70ms/s adc array in1:2mcmos,” IEEE Journal of Solid-State Circuits, vol. 29, no. 8, pp. 866–
872, August 1994.
[5] M. P. V. Kolluri, “A 12-bit 500-ns subranging ADC,” IEEE
Journal of Solid-State Circuits, vol. 24, no. 6, pp. 1498–1506,
December 1989.
[6] J. Elbornsson, “Blind estimation and error correction in a CMOS ADC,” in Proc. of the Thirteenth Annual IEEE
In-ternational ASIC/SOC Conference, Arlington, Virginia, USA,
