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Master of Science Thesis in Electrical Engineering

Department of Electrical Engineering, Linköping University, 2017

Synchronization of

distributed units without

access to GPS

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isy, Linköpings universitet

Division of Automatic Control Department of Electrical Engineering

Linköping University SE-581 83 Linköping, Sweden Copyright © 2017 Erik Carlsson

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iii

Abstract

Time synchronization between systems having no external reference can be an is-sue in small wireless node-based systems. In this thesis a transceiver is designed and implemented in two separate systems. Then the timing algorithm of "Two Way Time Transfer" is then chosen to correct any timing error between the two free running clocks of the systems. In conclusion the results are compared to-wards having both systems get their timing based on GPS timing.

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v

Acknowledgements

I would like to give a special thanks to a couple of people for giving me some extra help to complete this journey.

• Ulrika Uppman, for being my supervisor and giving me a helping hand when I got stuck.

• Kent Palmqvist, for being my examiner and making it possible for this the-sis to reach the finish line.

• Milton Johansson, for being my opponent and giving me excellent feedback on things that could be improved.

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1.2 Purpose . . . 1 1.3 Questions . . . 2 1.4 Limits . . . 2 1.5 Outline . . . 2 1.6 Related Work . . . 3 1.6.1 PISync . . . 3 1.6.2 GraDeS . . . 3

1.6.3 Two way time transfer . . . 3

1.6.4 Blink Protocol . . . 3 2 Theory 5 2.1 Distortions . . . 5 2.1.1 Frequency offset . . . 5 2.1.2 Phase offset . . . 6 2.1.3 Intersymbol Interference . . . 6 2.1.4 Noise . . . 6

2.1.5 Signal to noise ratio . . . 7

2.2 The general receiver . . . 7

2.2.1 Correlation Receiver . . . 7

2.2.2 Matched Filter . . . 8

2.2.3 Root Raised Cosine Filter . . . 8

2.2.4 Timing Recovery . . . 9

2.2.5 Phase Locked Loop . . . 10

2.3 The channel model . . . 11

2.4 Modulation . . . 11 2.4.1 BPSK . . . 12 2.4.2 QAM . . . 13 2.4.3 DPSK . . . 14 2.4.4 OFDM . . . 14 2.5 Synchronization Protocols . . . 15

2.5.1 Reference Broadcast Synchronization . . . 15

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Contents vii

2.5.2 Time-Sync Protocol for Sensor Networks . . . 15

2.5.3 Flooding Time Synchronization Protocol . . . 15

2.5.4 Two Way Time Transfer . . . 16

2.6 CORDIC . . . 17 2.7 LMS algorithm . . . 18 2.8 PI(D) Regulator . . . 19 2.8.1 Proportional . . . 19 2.8.2 Integrator . . . 19 2.8.3 Derivative . . . 20 3 Matlab results 21 3.1 Matlab simulation . . . 21 3.1.1 PID-regulator . . . 21

3.1.2 Two way time transfer . . . 23

3.1.3 Frequency canceler as time tracker . . . 23

4 Implementation 25 4.1 Hardware . . . 25 4.1.1 FPGA . . . 25 4.2 System Overview . . . 26 4.3 Demodulation . . . 26 4.4 Matched filter . . . 27 4.5 Receiver . . . 27 4.5.1 FIR filters . . . 27 4.5.2 Timing recovery . . . 27

4.5.3 Phase locked loop . . . 28

4.5.4 Detector . . . 30

4.5.5 Bit error detection . . . 31

4.6 Synchronization algorithm . . . 31

4.7 QPSK . . . 32

4.7.1 Modulation . . . 33

4.8 RX and TX part . . . 33

4.8.1 FPGA - Xilinx Zynq 7Z020 . . . 33

4.8.2 AD - AD9361 Transceiver . . . 33

5 MikTran results 35 5.1 MikTran Octave Analysis . . . 35

5.1.1 Frequency offset of a QPSK . . . 35

5.1.2 DPSK . . . 37

5.1.3 Half QPSK . . . 37

5.2 MikTran Hardware Simulation . . . 40

5.2.1 First TWTT simulation . . . 40

5.2.2 Second TWTT simulation . . . 41

5.2.3 One QPSK message . . . 42

5.3 Hardware implementation . . . 42

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6.1 General . . . 49 6.2 Time measurement . . . 50 6.3 Different solutions . . . 50 6.4 Questions . . . 51 7 Conclusion 53 7.1 Summary . . . 53 7.2 Lesson learned . . . 53 8 Future Work 55 8.1 Timing algorithms . . . 55

8.2 Higher bit rates . . . 55

8.3 Wireless transmissions . . . 56

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Notation

The next list describes several abbreviations that will be later used within the body of the document:

BBP Baseband processor BPSK Binary Phase Shift Keying

CORDIC COordinate Rotation DIgital Computer DPSK Differential Phase Shift Keying

DSP Digital signal processor FIFO First in, first out FSM Finite-state machine GPS Global positioning system LSB Least significant bit

Matlab Mathematical software suit from Mathworks MikTran Software defined radio platform from FOI MSB Most significant bit

Octave Open source mathematical software suit PLL Phase Locked Loop

PPS Pulse Per Second

QAM Quadrature Amplitude Modulation

QPSK Quadrature Phase Shift Keying (same as 4-QAM) SNR Signal to Noise Ratio

TWTT Two Way Time Transfer

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1

Introduction

1.1

Motivation

In today’s military conflicts there is an immense reliance on radio communica-tions and GPS. In a modern conflict, one of the first things to be targeted are hostile communications [5], so it stands to reason that a small distributed radio systems will still have to work together in a self contained group, without rely-ing on easily distorted signals, such as GPS. Therefor the goal of this thesis is to create a small distributed system. That is able to keep a common time consensus without the use of external timing (like GPS) among at least two nodes.

The constant reference to GPS in this thesis is for simple reason that it gives both timing and position reference. In a real world conflict both of these pieces of in-formation can suddenly disappear and the goal here is to replace timing aspect of it.

1.2

Purpose

This thesis was suggested by the "Swedish Defence Research Agency" and con-cerns the synchronization of wireless units without common timing, like GPS. The goal of the thesis is to find and implement a synchronization algorithm that will place at least two units within a reasonable timing reference from each other. The comparison will of course be against a pair of systems being synchronized by GPS.

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• Is it possible to achieve time synchronization on par with GPS in small distributed systems without using GPS?

• How should a visualization of the result look?

1.4

Limits

The thesis was an ongoing project between the February and August of 2017. It foremost concerned theoretical comparisons of different synchronization algo-rithms were one of them was implemented into hardware, in an FPGA.

The Miktran chip used for this thesis is a newly developed hardware platform that some extent lack exact documentation. This means that some errors or specifics might be skimmed over since it is either unknown or there was not enough time to calculate the exact nature of the issue.

1.5

Outline

Short information on what each chapter of this thesis contains. Introduction:

The purpose of the thesis is explained and general information given. Theory:

Contains the explanation of different concepts and equations for them. Such as timing, distortions and transmitting/receiving data.

Matlab results:

Contains simulation results of different timing algorithms. Implementation:

Explains how the chosen algorithm as well as the transceiver parts were implemented in the FPGA.

Miktran results:

Contains results from both hardware simulations of VHDL code as well as the results from the actual hardware.

Discussion:

What happened, why and answers to the questions asked in the introduc-tion.

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1.6 Related Work 3

Conclusion:

Sums up the result and lessons learned. Future work:

Outlines possible improvements and ways forward for the system.

1.6

Related Work

There is a lot of research being done in the world of timing synchronization right now. The technologies outlined here are but a few. There are also Ethernet/Wifi protocols, like White Rabbit, that aims to have sub nanosecond synchronization.

1.6.1

PISync

The so called PIsync algorithm was created and coined in 2015 [21]. It consists of the idea that each node in a WSN (wireless sensor network) system runs a PI regulator to average the time in the entire system. Basically each node in the system averages all the external times it receives during a time Tc. It then uses

this value as input to a PI-controller and calculates a new clock for itself which is then transmitted to the rest of the network. More on the PI(D) regulator can be found in Section 2.8

All this means that the entire network can synchronize without a reference node. It simply converges to a normal time. Drawbacks of this system: An excessive converge time for this work and setting the gains for system such that it can’t go out of bounds, which means it would become unstable.

1.6.2

GraDeS

This gradient descent synchronization algorithm was developed and released in 2016 [20]. It consists of every node of the WSN running a gradient descent algo-rithm that averages the times from the other systems and tries to minimize the ’error’ of the local time compared to the average.

1.6.3

Two way time transfer

The TWTT algorithm is based on a simple fact. If two systems are in principle stationary to each other, the delay from S1to S2should be as long in reverse. That

means that the error of the system can negated by transferring them between each other, accounting for them at each new calculation [7]. More about the function is in Section 2.5.4.

1.6.4

Blink Protocol

This system is based upon Ultra Wide Band technology and was published in 2015. It was proved possible to create a sub 10 nano-second rms in system

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con-2

Theory

2.1

Distortions

General distortions or noise exists in all systems. In communication systems were two or more units need to talk to each other many common problems are magni-fied. With the introduction of a channel as a as offsets between the systems, there are a host of issues, with some of them described below.

2.1.1

Frequency offset

When two system are in communication, they need to (in most cases) communi-cate with the same speed, or clock frequency. This means that they need a road between each other (carry frequency, fc) where the cars (the data) can get from

point A to point B. A common issue here is that the roads don’t completely meet, even though you thought they should. For example, you set the fcto 100 MHz in

both systems and everything should work. Though it might not because all oscil-lators have drift, due to temperature, process variations and many more factors. These can range from parts per million (ppm) to parts per billion (ppb). If an oscillator has a drift of 50 ppm that means that the fcof 100 MHz is really in an

area of 100 MHz ± 5 kHz. This is a problem that increases with clock speed, so if there is a fcof 1 GHz and a 40 ppm oscillator, there is suddenly of a span of ± 40

KHz where the signal can be.

Solutions for this problem is either a frequency locked loop, or just a phase locked loop if the offset is small [17]. There is also modulation schemes like DPSK [1], which are designed to ignore frequency offset as a part of its fundamental design.

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A phase error can occur because of a time delay in start time between two units, because of an non ideal channel or mismatches in hardware, like the ADC or DAC. The first error is because of the fact that a time delay in the time domain equals a phase shift in the frequency domain [9]. When an PLL tries to drive the error to zero, it does this by being an LMS algorithm, Section 2.7, essentially the old error is the new error with a correction until the error is driven to zero.

2.1.3

Intersymbol Interference

Intersymbol Interference or ISI occurs when the energy of one symbol spills into it’s neighbours spectrum. This can happen because of many reasons, like multi-path propagation, synchronization error, filtering as well as a band limited chan-nel. This means that for any point of sampling, there can be the desired signal as well as some residue from neighbours in the spectrum.

2.1.4

Noise

Noise exists in all transfer channels and comes in two variants. White and coloured noise. For this part the focus will be on white noise of the Gaussian kind, or as more commonly referred to as AWGN, Average White Gaussian Noise.

White Gaussian noise is special case of Gaussian noise. Gaussian noise is a sta-tistical noise where PDF (Probability Density Function) is equal to the normal distribution. The special case for white Gaussian noise is that the values at any pair of times are identically distributed and statistically independent (and hence uncorrelated).

In telecommunication and communication channels in general, the use white Gaussian noise is prevalent to create additive white Gaussian noise (AWGN) on a channel. This is used to mimic the random process and noise that can occur in nature while still having a uniform power over a frequency band and a normal distribution, making it rather easy to create a mathematical model. The stochas-tic variable for the Gaussian PDF, can said to be X and that is given by:

fx(x) = √1

2πσ · e

(x−m)2

2σ 2 (2.1)

where V(x) = σ is the variance of the PDF, E(x) = m is the mean. For an ideal receiver there will be white noise that is equal for any and every frequency. This

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2.2 The general receiver 7

not possible in the real world since such a signal would have infinite energy, so it starts to fall off in the [THz] region but for the purpose of this thesis it is treated as:

N0= kT0 (2.2)

where k = 1.38 · 10−23 joule/kelvin (Boltzmann’s constant) and T0 is the system

temperature in kelvin. This gives a noise level of Sn(f) =N0∗BW

2 for any frequency

since the noise power is measured over the bandwidth [1].

2.1.5

Signal to noise ratio

Signal to noise ratio or SNR is what decides the quality of a communications link [1]. That is the received signal power over the noise power as

SN R = S N =

Pr

N. (2.3)

Where S is the incoming signal with a received power of Pr and N is the noise

power into the receiver.

2.2

The general receiver

The goal of a systems receiver is to maximize the signal power into the system, correct any phase, frequency and timing offsets and finally it should demodu-lated the received signal to the correct values. It’s other goal is to remove any errors that has occurred in the data.

The receiver of a system is usually modeled after 3 different models, outlined in [8] on the last page. Modeled as either fully analog adjustment, mixed adjust-ment or fully digital adjustadjust-ment. The general difference is if the filtering, time adjustment and phase adjustment are done in the digital or analog realm.

2.2.1

Correlation Receiver

The correlation receiver [12] is an optimal receiver in the sense that it maximizes SNR at the sampling instant. For a signal existing between time 0 and T, the signal will multiply the signal with a known template and then integrate this value over T time. The sampled output at the time T is the maximum correlation between the input signal and the template. This value is then sampled and the integration is reset, and starts to integrate over the next signal.

(n+1)T Z nT r(t) · so(t − nT )dt = A2· T (2.4) (n+1)T Z nT r(t) · s1(t − nT )dt = −A2· T (2.5)

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Figure 2.1:Example of BPSK correlation receiver

is the ideal example where r(t) is the input signal seen in Figure 2.1. soand s1are

the known signal templates (+1 and -1 for BPSK) and A is the known amplitude of the signal.

2.2.2

Matched Filter

The goal of the matched filter is to maximize SNR of the received signal, much like the correlation receiver. Imagine a channel with the transfer function HC(f )

and a transmitter with the HT(f ). Combining them into

HT C(f ) = HT(f )HC(f ) (2.6)

where HTC(f ) is transfer function and the Fourier transform of hT C(t). To create

a match filter that maximizes SNR, the receiver’s impulse response is hr(t) = h∗T C

(−t). This gives the the transfer function HR(f ) = H ∗T C (f ) is needed for the

receiver [11].

2.2.3

Root Raised Cosine Filter

A root raised cosine filter is a filter designed to cancel out ISI of the channel. Assuming that the transmitter, channel and receiver can be modelled as [11]

HT(f )C(f )HR(f ) = HRC(f ) (2.7)

where HT(f ) is the transmitter filter, C(f ) is the channel response, HR(f ) is the

received filter and HRC(f ) is the raised cosine frequency response given by

         T , 0 ≤ |f | ≤1−α2T T 2(1 − sin[πTα (|f | − 2T1 )]), 1−α2T ≤ |f | ≤1+α2T 0, otherwise         

where α is the roll-off factors, between 0 ≤ α ≤ 1, and 1/T is the symbol rate of the system. When the roll-off factor of α is increased above 0, the excess band-width of the filter increases. So when the Nyqvist Frequency is 1/2T and the roll-off factor is 0.5, the response HRCis 50%.

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2.2 The general receiver 9

Figure 2.2:Function of late-early algorithm

2.2.4

Timing Recovery

There are a multitude of timing recovery algorithms. Some examples are Muller-Muller, Gardner, Polyphase filter bank and Late-Early symbol recovery [11]. In this section the focus is on the Late-Early algorithm and the Gardner algorithm. The purpose of a timing algorithm is to find the peak amplitude of an incoming signal. To achieve this, the signal is almost always run through a filter that re-shapes it from a square form into a triangle shape. This shape can be seen in Figure 2.2 and 2.3.

Late-early algorithm

The advantage of this timing recovery scheme is that it only requires one symbol for each adjustment. It uses the output of the shaping filter to find the peak value of each symbol. According to

e = [x(n + 1/2) − x(n − 1/2)] · x(n) (2.8) where e is the error that is feed to the loop filter and x(n+k) are the samples on each symbol. The symbol timing is moved according to

e = 0, the timing is not changed.

e > 0, the timing is advanced for the next symbol. e < 0, the timing is delayed for the next symbol.

which makes it very easy to implement and run on almost any wireless and con-figurable system. A drawback of the algorithm is that is dependant on the signal being equal on both sides of the peak. If it isn’t the signal will start to skew in one direction and create a constant error.

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Figure 2.3:Function of Gardner Algorithm

Gardner Algorithm

The Gardner algorithm was introduced by Floyd Gardner in 1986 [6]. It is depen-dant on having 2 samples per symbol, as can be seen in Figure 2.3. The equation for the algorithm is derived as

e = [x(n) − x(x + 1)] · x(n + 1/2) (2.9) and in the ideal case, each peak has the same magnitude as the next and the sample in between them, x(n+1/2), has a magnitude of zero. The error correction is handled with e in comparison to zero as described in Section 2.2.4: Late-early algorithm.

2.2.5

Phase Locked Loop

Phase looked loops comes in many variants but the principles are the same. It is an adaptive algorithm that based on the phase of an input signal outputs a signal with the same phase. A schematic outline can be seen in 2.4. Consisting of a Phase comparator, loop or low-pass filter and a VCO, voltage controlled oscilla-tor.

Figure 2.4:Basic outline of a PLL

Phase comparator/detector:

As the name implies, this circuit compares the phase of two signals and generates a voltage depending on the phase difference between them.

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2.3 The channel model 11

Loop filter:

This filter is filtering the output from the comparator in the PLL. It is used to delete any unwanted components of the signals of which the phase is being compared from the VCO. It also governs many of the characteristics of the loop and its stability.

Voltage controlled oscillator (VCO):

The voltage controlled oscillator is the circuit block that generates the out-put signal. Its frequency can be controlled and moved across the opera-tional frequency band for the loop.

The above description covers the basic function of an phase locked loop but it is mostly based in the analog world. A digital phase locked loop of the type ’Costas loop’ was used for this thesis, where the both the phase detection and loop filter were created in digital domain, after the DAC.

A detailed description of a digital phase locked loop can be found in [17], where all calculations are made. Here the focus is the end values and implementation of a digital phase locked loop:

kp = 2ζwnTs

KN CO· KP D

(2.10) where kpis the proportional gain of the loop filter, ζ is the dampening factor, wn

the natural frequency, Tsis the period time of the sampling frequency and KN CO,

KP D are the gains of respective components.

ki =

(wnT s)2

KN CO· KP D

(2.11) where kiis the gain of the integral part of the loop filter. The rest of the variables

are the same as for calculating kp. More on kpand ki in Section 2.8.

2.3

The channel model

A model of a wireless system is generally divided into 3 parts. The transmitter, the channel and the receiver. Noise is modelled as being only added into the channel but this is not true in the real world. For a general understanding we are modelling the noise and frequency offsets in both the transmitter and receiver as being part of the general channel, see Figure 2.5.

2.4

Modulation

The principle of modulation is to redefine a set of bits that needs to be transmit-ted over a channel. This can be done to both increase the bits/sample of each transmission, Section 2.4.2, or to increase its resilience to noise and distortions of the channel [12]. A general rule of thumb is as the number of bits per sample

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Figure 2.5:Basic overview of a transmitter and receiver model

increases the resilience to noise and distortions go down. This can be seen by comparing 4-QAM and 16-QAM in Figure 2.6. If the energy between two points in 4-QAM is E then the energy between two points in 16-QAM is E4. This means that if a phase or amplitude shift occurs, there is less tolerance in the system for it. Since the margin for error has shrunk from E2 toE8 since the decision edges lies on half the euclidean distance.

Figure 2.6:Comparison of QAM modulation

2.4.1

BPSK

Binary Shift Keying is simpler modulation method then QPSK 2.4.2. It simply phase shifts the signal 180 degrees or π. It’s major advantage is that it can tolerate a large phase shift and still come out as the correct bits, the major disadvantage of this modulation is that it only transfers 1 bit/symbol. Mathematically the definition is [12]:

Sn(t) =

r 2Eb

T · cos(2πf t + π(1 − n)), n = 0, 1. (2.12)

where Eb is the maximum energy of each bit, or in this case the constellation

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2.4 Modulation 13

Figure 2.7:BPSK modulation

2.4.2

QAM

Quadrature amplitude modulation is used in a host of communication systems and is based on a combination between phase and amplitude manipulation. QAM is often denoted by the number of constellation points beforehand, like 4-QAM, 16-QAM and such. Since it mostly comes as a square form, the numbers go up by increments of 4, like 4, 16, 64, 256 and so on. 4-QAM is the same as QPSK since the amplitude is a static of ±1 and only the phase is changed.

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time as their euclidean distance is shrinking as the constellation grows. These two factors increases the chance that one constellation point is mistaken for it’s neighbour and it leads to a bit error.

QPSK might be an interesting choice for this thesis as it is widely used, rather easy to implement and can be scalable depending on the situation. You can have a system to jumps between QPSK to 16-QAM to 64-QAM and then back down depending on the amount of errors that are being caused by noise. The definition of QPSK [12] is close to Equation 2.4.1 and is

sn(t) =

r 2Es

Ts

· cos(2πf t + (2n − 1) ·π

4), n = 0, 1, 2, 3. (2.13) Where Esis the energy of the symbol, Tsis symbol duration and each n is

equiva-lent to a constellation point on the unit circle.

2.4.3

DPSK

Differential phase shift keying [1] builds upon the modulation of BPSK but with a twist. Instead of measuring the incoming phase of the signal, the difference between the current sample’s phase and the last sample’s phase is measured. If the phase is unchanged or at least less then a threshold value, like 90◦, it is in-terpreted as a zero. If the phase difference is more then the threshold value, it’s counted as a one. This means that any constant phase shift of the signal can be disregarded as long as all symbols have the same amount of shift. If a frequency error is small enough, a slowly rotating constellation can also be disregarded. As long as the constellation doesn’t rotate more than 90◦ between two symbol instances.

2.4.4

OFDM

Orthogonal Frequency Division Multiplexing has become a common to use in modern communication systems. It offers resistance to multipathing, easy equal-ization and the use of a guard interval handles inter symbol interference (ISI). It works by dividing up a wide bandwidth in narrow channels. For example, 30 MHz of bandwidth could become a 1000 channels with 30kHz bandwidth each. The orthogonality is achieved by placing a new channel at every Ts on the zero

point of the last channel. This causes all channels to be orthogonal but very sen-sitive to shifts in frequency since that will move a channel of the zero and cause it correlate with its neighbours.

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2.5 Synchronization Protocols 15

OFDM could possibly be implemented into the system since requires almost no equalization, uses FFT which could be implemented in the hardware and it is easy to synchronize but sensitive to frequency errors.

2.5

Synchronization Protocols

Synchronization means that two or more things are working in tandem. For this thesis the requirement on the units are on the nanosecond scale since a difference between 10 ns and 20 ns is the distance of

Dist = C ∗ T = 299792458 · 10−8= 2.998m (2.14) This implies that all the units in the system need to have the same understanding of time and if their clocks start drifting it needs to be immediately corrected. There are a multitude of ways to synchronize time in wireless systems. Some use a reference broadcast node that pushes a time to everyone else, Section 2.5.1, or are in constant contact with each other to compare both time and error for correction, see Section 2.5.4. Here the focus will be on overview on each protocol so that the reader can gain a basic understanding on each of them.

2.5.1

Reference Broadcast Synchronization

RBS uses a Master - Slave dynamic where the master unit transfers a reference message to all slave units. They in turn record when they received the reference message (Mref) and then exchange their local time with each other making it

possible to find a least square solution that fits the errors of each unit [4].

2.5.2

Time-Sync Protocol for Sensor Networks

Is a protocol where the entire system is based out of the root node in a tree struc-ture. It starts from the center and works outwards, which each pair of nodes synchronizing in a semi-duplex way. Following Figure 2.9, the change in the clock becomes

d = ((T2−T1) + (T4−T3)) (2.15)

accounting for both the clock skew and propagation delay of the system. TSPN is a rather basic structure that doesn’t handle topology changes very well, since it has to recompute the entire tree when the change occurs. That means TSPN or variants of it are mostly used for stationary sensor networks [14]. Because of these reasons, TSP was excluded as a choice for implementation.

2.5.3

Flooding Time Synchronization Protocol

The flooding protocol is based on all nodes pushing synchronization messages into the net consisting of RootI D, SequenceN R, SendingT ime. The system with

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Figure 2.9:TSPN - 2 nodes

the lowest ID in the system is considered root. What then happens are two com-parisons, if the root ID is less or equal then the current stored ID, keep that message. If the sequence number is higher then the last received message, keep it. The node then updates it’s current clock to the received time and then transmits a global synchronization message. The receiving nodes calculates their clock-scew based on linear regression

The root of the network is always based on the the ID number of the nodes. The node with the lowest ID will always be declared root after the setup time. So if a node should not get a sequential message in a finite amount of time, it will declare itself root and start broadcasting until it receives a messages with a lower

RootI D [13].

2.5.4

Two Way Time Transfer

Two Way Time Transfer is used in the Two-Way Satellite Time and Frequency Transfer (TWSTFT). It is based on the idea that if the two transmission paths are reciprocal the delays will essentially cancel out at both receivers. At a certain time zero, two systems sends their respective (local) time into the channel, to-wards one another. For this example, lets call them A and B, as seen in Figure 2.10.

Figure 2.10:Basic two way time transfer system

At time zero and at continuous interval, both system A and B will send their cur-rent time to the counter-part. Since the information will be delayed about the same amount by the channel, that part will cancel out. The largest factor of skew will instead be the hardware dependant delays [7] of the systems: like ADC,

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fil-2.6 CORDIC 17

ters and components in the analog realm.

Denoting the time difference between the two units as dAB and dBA, while the

calculated difference or error at each node is E(A) and E(B). This gives equation 2.16, where A and B denotes the local time in respective system.

A − (B − E(B) − dBA) = B − (A − E(A) − dAB) (2.16)

is the general equation for the systems communication and if the paths between the systems are reciprocal then (dAB, dBA) becomes are equal, the time difference

is only a function of the offset calculation, which becomes more clear as

A − B = E(A) − E(B)

2 +

dABdBA

2 (2.17)

meaning if that the transfer between the systems is reciprocal and there is no time delay, the time difference becomes zero. Otherwise the clock difference will unknown but (hopefully) converging towards zero.

2.6

CORDIC

A CORDIC algorithm is used to do vector translations and computations in hard-ware [18]. It is either feed the I and Q values of a signal to rotate them, or translate them into phase and amplitude. It can also do the reverse. Other functions are Sin, Cos, Atan and square root conversions.

The algorithm was first suggested by Jack E. Voldner 1959 [16] and stands for COordinate Rotation DIgital Computer. It is an iterative way to find a certain angle of φ by taking multiple steps instead of directly finding it through complex multiplication which can be very difficult to do in hardware. An easy example of a CORDIC in rotation mode is this:

1. The desired angle φ is 34

2. The algorithm starts with vector V at 45◦

3. Since φ < V. Take V - 45◦/2 for the first iteration. 4. V is 22.5◦so φ > V which gives V - 45◦/4. 5. V is now 33.75◦which is close to the 34◦needed.

The algorithm has rotated to the desired angle of the signal without using any multiplications. Only adding, subtracting and division by 2, that in hardware is implemented as shift registers. The resolution of the output phase is depen-dant on the bit-length of the incoming vectors and length of the implemented CORDIC.

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For vector translation, the input of I and Q, or X and Y if preferred, is converted from rectangular to polar coordinates. Which means a conversion to values of phase and amplitude. The output phase can also have a coarse rotation, which means that it can represent any point from π to −π.

2.7

LMS algorithm

The least mean square algorithm that attempts to find a set of weights that will drive a defined error to zero. The weights are loosely defined and updated as "the new weight is the old weight, times a correction". So in general it would look like figure 2.11.

Figure 2.11:Block Diagram of LMS algorithm

The weights for controlling the system is inside of the ’Adaptive Algorithm’ block. And y(n) is a function of an N amount of scaled inputs multiplied with an N amount of weights ~ u(n) = [x(n), x(n − 1), x(n − 2), ..., x(n − N + 1)]T (2.18) ~ w(n) = [w0(n), w1(n), ..., wN −1]T (2.19) y(n) = ~u(n)T · ~w(n) (2.20) ~ w(n + 1) = (1 − µ) · ~w(n) + µ · e(n) · ~u(n) (2.21)

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2.8 PI(D) Regulator 19

where µ is the step size variable which is a value less then one (µ < 1). The weight is updated each iteration and will chase the error, attempting to drive it to zero.

2.8

PI(D) Regulator

A regulator of the PID type is often used in the field of automatic control, to drive an error towards zero. It can up to three different parts that are called: Pro-portional, Integral and Derivative. The proportional component is the difference between the first and second input scaled with a gain often called kp, this part

is memory less and will only look at the two current inputs to the system. The integrator is the component responsible for looking into the past and figuring out if the system needs an extra push or not, to catch up with the current error. The derivative part can be used to look into the future and estimate what the next value should be.

Figure 2.12:Block Diagram of PID Regulator

2.8.1

Proportional

The proportional gain is simply the error between the two inputs times a gain factor of less then 1. One way of setting kp is to find the maximum gain of the

system before it becomes unstable. Where the output is at a steady and constant oscillation. A common practice is to move the kpgain to the right of the second

addition, Figure 2.12.

2.8.2

Integrator

Together with the proportional part, the integrator forms a PI regulator. This this will decrease the stationary error caused by the proportional gain but shouldn’t sufficient care be taken with the scaling factors, the whole system could become

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unstable. Since the integrator is a constant summation of received values, the gain ki has to be sufficiently small, as to not allow the system to become unstable.

Figure 2.14:Integrator part of the system

2.8.3

Derivative

The derivative part of the regulator is trying to estimate what the next value in the series will be and regulate for that. This means that in present of noise it can cause a system to become very jittery/unstable. Because the derivative part is going to try and estimate a value that will be offset by a random noise coefficient

N1. Next time it will then try to estimate with added N1but then the coefficient

will have changed to N2 so it will be off again. As system runs this error can

build up and cause the derivative to send the entire system out of stable operation limits .

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3

Matlab results

3.1

Matlab simulation

As the first step of the process 3 algorithms were tested and compared. TWTT, PI-Sync and a remade frequency canceller. These were generally varied and po-tentially easy to implement. The simulation was used to see the convergence rate and steady state error of the different algorithms.

3.1.1

PID-regulator

According to the work done in [21] and explained in Section 2.8 there is a case for using a PI(D) regulator to correct for time in a cluster of systems. This was implemented in Matlab with 2 simulated systems running with different clock drifts and a large starting offset between them. In this simulation the systems takes turn to update every other sample, when they receive new data.

The blue line in Figure 3.1 is the transmitting system and the red line is the sys-tem adjusting with the PID algorithm. The green line of in the figure is what the clock of the second system would look like without time adjustment. The values of P, I and D was set to arbitrary values just to see the function of the system. What can be seen is that system converges in 40 values but there is a steady state error.

A second implementation was then done with only PI present as the derivative part risked being to noise sensitive in the final system. In this implementation both systems are running a PI algorithm and the results can be seen in Figure 3.2. The other difference between this simulation and the first is that the systems are only updated every 10:th sample. This is to more closely simulate reality where

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Figure 3.1:PID regulator used to correct for time

thousands of clock cycles can be run before the next message arrives. The differ-ence between this results and those in Figure 3.3 is that one converges to zero with while the other is constantly updating to correct for the time drift.

Figure 3.2:PI regulator used to correct for time in 2 systems

This second implementation had the a proportional coefficient of 0.2 and a inte-gral coefficient of 0.5−5

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3.1 Matlab simulation 23

3.1.2

Two way time transfer

The simulation of the two way time transfer (TWTT), Section 2.5.4, is the simu-lation that came the furthest. It was deemed unnecessary to have a offset in the middle so that was scraped. The largest difference between this and the other algorithms is that it only updates each 20 sample and still converges towards as final value. In Figure 3.3 a blue, red and green line can be seen. The green line is system 1 without the algorithm working. The red and blue lines are system 1 and 2 respectively, with the TWTT algorithm doing its work. The algorithm converges towards zero in simulation and does so rapidly, in under 20 samples for each system.

Figure 3.3:Simulation of TWTT algorithm

The advantage of the TWTT algorithm is that is unbound on how large error it can handles since it will always converge towards an average value. A drawback to this is that system can suddenly have its timing position reversed by a large margin if introduced to a new system that for example starts at zero. Since it then will have to recalculate with a large error that propagates through the system.

3.1.3

Frequency canceler as time tracker

For this test a frequency canceler was used, that was redesigned as a time tracker and implemented in Matlab. As can be seen in Figure 3.4, the system converges in about 100 samples but for this test no offset is occurring in the middle. The problem that was quickly found with this system that it never converges. It con-tinuous to have a ripple instead of instead settling down. This was the reason that it was not expanded upon for a hardware implementation.

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4

Implementation

4.1

Hardware

The chip used for this thesis is called MikTran, an in-house developed transceiver by FOI. It consists of a two main parts: A AD9361 chip [3] and the base band pro-cessor (BPP) called Zynq-7020 [19]. These two are connected on a common board to form the MikTran chip. The system takes it’s clock from the AD9361, which generates both the carry and bandwidth frequency for itself and also the system clock for the FPGA. This reference clock has a an offset of up to 40 ppm, meaning that if the BBP frequency is set to a 100 MHz it can in reality be somewhere in between 100 MHz ± 4 kHz. This hardware was chosen as the implementation platform by FOI.

4.1.1

FPGA

FPGA stands for "field-programmable gate array" [10] and is technically pro-grammable hardware. When using this and a hardware description language (HDL), the programmer is essentially creating a hardware configuration to be implemented. Unlike in software development, where the hardware is already predefined and each cycle runs commands input by the software language. The advantage of a hardware implementation is lower power consumption, higher efficiency with dedicated hardware for all functions and the possibility to still have a software layer on top of finished design [19].

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functions to run the system was implemented in software on the ARM processor but all the timing algorithms and the whole signal chain was implemented in VHDL.

The system is by design built with a modular approach so that it can support dif-ferent modulations and algorithms by swapping out blocks for the synthesized design. Data comes in from the ADC at the left, then travels through the system until it is output at the right, through the DAC into the transmission medium, see Figure 4.1.

So if a different project would have an interest in testing out a new algorithm for the current hardware. It could simply change the middle block as long as all bit length are kept in order which shouldn’t be a problem. This is since a new designer will have access to the documentation of the implementation in practise.

Figure 4.1:Basic Overview of the system

4.3

Demodulation

In the signal chain, seen in Figure 4.1 the demodulation is the first thing that occurs, when not accounting for the receiver that locks onto the signal (in the Rx block, Figure 4.1). For the every received sample two bits are set and then passed on to a load register. If that register finds a set preamble signal the system knows that the next 128 bits will be the intended message, containing both the local time and error of the other system. When these two messages have been sam-pled, the information is passed on in the chain to the TWTT block. A colourful representation of this function can be seen in Figure 4.4.

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4.4 Matched filter 27

4.4

Matched filter

A root raised cosine filter with 7 taps and a roll-off (α) of 0.22 was used to shape the signal in both the the transmitter and receiver, Section 2.2.2.

4.5

Receiver

For this system with the AD9361 chip, Section 4.8.2, the carrier recovery is done in the digital domain of the system, in the Zynq chip’s FPGA, see Section 4.8.1. For the correct bits to be sampled a receiver had to be created. This unit contains matched filtering, basic low-pass FIR filters, timing recovery as a well as a PLL for phase/carrier recovery. The incoming data is a burst message containing a string of random numbers, followed by 4 preambles to give the system time to find if it locked to the wrong phase and finally make a decision if a real message was received and not just noise.

4.5.1

FIR filters

The FIR low-pass filters are extremely basic for this thesis, containing just 4 taps, and existing to reshape the signal into a triangular shape, so that timing recovery can be performed. The incoming data to the taps are in 12-bits and the outgoing is 18-bits. Making it impossible for a overflow to occur as the bits are added up and then divided to create an average.

4.5.2

Timing recovery

The timing recovery was performed by using a modified version of the Gardner algorithm, Section 2.2.4. If the sign of the two following symbols are different the "zero" sample is added to an integrator to move where the data is sampled in the incoming bit stream. For the first implementation of this function a 10 symbol long register was used, where the pointer can move the middle sample from +1 to -2 on the basis that the incoming signal is 4 times over-sampled. So if the middle point starts at 6, the correlating peaks should be at 4 and 8. The issue with this implementation was that there was a bit error when it went from -2 to 1 or vice versa. This caused the algorithm to sample on the next symbol, creating a bit error since one symbol was lost in the sampling.

The second implementation of the timing algorithm was instead the same reg-ister but instead an integrate and dump function was used. When the integra-tion reached max value and sampling time was either retracted or forwarded one point. So that the same sample point in the register is always used, only the timing is changed which has the advantage of never creating a wrap around error. To create an efficient function that wasn’t dependant on phase error, data from both the I and Q path is used. This means that if the error of the I-channel

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Section 2.6, as well as a phase comparator and loop-filter. The first CORDIC is used to rotate the incoming signal based on the input from the loop filter. From this output data the bits are sampled to the detector as well as being sent into the second CORDIC. This second CORDIC is used to translate the data from the I and Q representation into phase and amplitude. The amplitude is used to dis-cern if their is an input signal above noise level and then the phase is used to correct for any offset, be it phase or frequency. The phase error is then feed into a summation that feeds into the error block. This function can be seen working as intended in Figure 5.11.

A drawback with this dual CORDIC implementation is that it creates long delay lines in the system, since it takes approximately 18 clock cycles for each CORDIC to produce an output based on the input. So using two CORDICs, it takes 36 cy-cles for the system to start compensating for an offset. That is the reason that the lock-in bits exists before the preamble, Section 4.5, to give the PLL time to lock on to the phase/frequency error. Another alternative would have been to use a FIFO register to pipeline the signal.

An advantage is that a summation is in use. This means that even when no signal is present, all bits will still be rotated as much as the latest ones. That means that any phase error will be compensated and there will be a head start on most frequency errors, as long as they haven’t rotated close to a decision edge. What happens then is that the comparator becomes unsure where the signal belongs. Since in one moment it is in quadrant "3" and the next in quadrant "4", Figure 4.2. To the comparator is looks like first has a large positive error but then a large negative error, creating a ripple effect that can make it take some time to settle, in one of the four quadrants.

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4.5 Receiver 29

Figure 4.3:Implementation of Phase Locked Loop

The loop filter of the PLL consists of a proportional and integral part as specified in Section 2.8. Since there is the addition of the ’phase step’ component in the system, the calculations for proportional and integration part are slightly of from the ideal. The output of the phase comparator is called phasedif f and the factors

are

K_p = phasedif f

32 (4.1)

K_i = K_i +phasedif f

4096 (4.2)

Kf q=

phasedif f

64 (4.3)

which adds up to the summation after the filters. The Kpis the proportional part

which can differ each sample, Ki is the integration which adds up over time and

Kf qis the difference between the last sample and current sample. Going into the

integration block called "SUM" in Figure 4.3 and give the equation

P hasesum= P hasesum+ (K_p + K_i + Kf q) (4.4)

which as feed as the input to the CORDIC rotation block in Figure 4.3. The rota-tion CORDIC takes in I and Q, outputting Irotand Qrotdepending on the value

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1. A 180 degree phase shifted preamble is detected 2. If a bit-pair is "00", it will then be flipped to "11" 3. A correct preamble can be found. Look for a second.

4. Another preamble found. The next 128 bits are the message. 5. Wait for a new preamble, or phase-shifted version.

A quick version of the preamble detector can be seen in Figure 4.4. Preambles are found, then the first 64 bits are sent as one message and then the second message are the other 64 bits.

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4.6 Synchronization algorithm 31

4.5.5

Bit error detection

To remove bit error from the project a solution of dual sent messages was intro-duced. Each message is sent two time in each transmission. The receiver then compares them, if they aren’t the same, the entire message is considered faulty and rejected. This increased the size of the payload from 256 bits to 384, which is an increase by 50% but considered necessary for the system to have a proper func-tion. A more advanced implementation would be sending 3 messages through the channel and keeping the "majority bit" on the receiving side. A third alternative would be to implement error correcting code, like cyclic redundancy check.

4.6

Synchronization algorithm

The two way time transfer algorithm was implemented in hardware and was to proven to work in simulation after week 8. For this thesis it was implemented using a state machine to run each part of the algorithm in steps as can be seen in Figure 4.5. The exact equation of the algorithm can be found in Section 2.5.4. First it compares the received and local time, then it compares this difference with the received difference. Dividing this second difference by two and then subtracting it from the local clock value. In the last step it outputs it’s local clock and calculated difference to other receivers in the system.

The entire FSM takes 5 clock cycles to execute and that is compensated for in the system by subtracting those cycles. The division is done by a arithmetic shift to save time and this is a general advantage of the TWTT algorithm, it contains no large multiplications or divisions.

A full implementation of the algorithm looks like this:

Elocal = TLocalTExternal (4.5)

Edif f =

ElocalEExternal

2 (4.6)

TLocal= TLocalEdif f (4.7)

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Figure 4.5:Finite State Machine of the TWTT algorithm

4.7

QPSK

The communication technique chosen for the implementation was 4-QAM/QPSK which generates a data-rate of 2 bits per sample. The reason for not going with a modulation scheme that has a higher bit rate is simply that would require a higher SNR and the actual value was not known at implementation. The second reason to stay at QPSK was because of easy implementation and as follows, less use of hardware. Since the values comes in 2’s-complement there stands to reason that only the sign-bit needs to be evaluated to see where the sample belongs, see Figure 4.6 and think about it.

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4.8 RX and TX part 33

4.7.1

Modulation

The demodulation process is done to the right of the TWTT in Figure 4.1. It receives the local time and error from the TWTT, then attaches the preamble and lock sequence ahead of message. These symbols in the message are the modulated to 2’s-complement I and Q values, being sent to the TX together with a preamble for each sample.

4.8

RX and TX part

The receiver and transmitter part of the system was predefined and built to han-dle data, in and out of the AD9361 chip. For information on this data-flow, look into the reference document of AD9361 [2].

4.8.1

FPGA - Xilinx Zynq 7Z020

The Xilinx Zynq-7020 is the base band processor (BPP) used from this thesis and consists of an Artix-7 FPGA and a dual core ARM processor, the Cortex-A9 [19]. The Artix-7 FPGA consists of 85 thousand logic cells, 53200 look up tables and 220 DSP slices. For this thesis the FPGA is clocked at a 100 MHz clock speed and is connected to the AD9361, Section 4.8.2, using a LVDS configuration. The ARM processor and the Artix FPGA is communicating via an AXI interface, that makes it possible for the ARM processor to read and write to certain registers in the FPGA as well as take interrupts from it.

For this thesis the Zynq is run at a nominal frequency of a 100 MHz and will be responsible for timing, phase and bit recovery of the signal. As well as running the timing algorithm and then creating the message for the AD9361 to transmit.

4.8.2

AD - AD9361 Transceiver

The AD9361 chip is an RF (Radio Frequency) Agile Transceiver. It was mainly designed for 3G and 4G mobile communications and therefor covers a frequency band from 70 to 6 GHz for both the transmitter (Tx) and receiver (Rx) [3]. It has a tunable channel bandwidth ranging from 200 kHz all the way up to 56 MHz. The chip takes in and outputs 12-bit signed data, creating a resolution of plus minus 2048 in the signal amplitude that can be sent and received by the base band processor (BBP). The connection to the BBP and the overlay of the chip can be seen in Figure 4.7. As can be seen from the overview, the AD9361 has two Rx and two Tx paths, which each has it’s own individual I (in-phase) and Q (quadrature) path.

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5

MikTran results

5.1

MikTran Octave Analysis

The first results from MikTran came from sending a predefined sequence from a ROM-memory, transmitting over a cable and into another MikTran which sam-ples the result. This file of raw data was then input into Octave to be analyzed.

What is Octave?

Octave is an open source program that is similar to MatLab. It is developed as an open source project but shares much of the MatLab syntax. Octave was used to analyze data collected from the MikTran system.

5.1.1

Frequency offset of a QPSK

A QPSK with a random sequence of numbers was loaded into the memory of the transmitter. When it was sampled at the receiver it had received shaping of the channel through noise and it was rotating around, or spinning as seen in Figure 5.1. This implies that there was a frequency offset between the two units. Since both the carry frequency and the ADC sample frequency is taken from the same reference clock with 40 ppm offset, there was a large chance that this would hap-pen.

What then happened was that an soft-fix was implemented into Octave. The sequence was both phase and frequency rotated with fixed values and the result can be seen in Figure 5.2. Where the real QPSK signal can be seen. There are some small sampling issues which creates the errors in between the constellation points as well as distortion, creating these "signal clouds" at each point. 4

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Figure 5.1:A QPSK modulated signal with frequency offset

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5.1 MikTran Octave Analysis 37

5.1.2

DPSK

Differential phase shift keying 2.4.3 was implemented as a way to combat the frequency spin without having to remove it. The received constellation of this can be seen in 5.3.

Figure 5.3:Received DPSK

5.1.3

Half QPSK

For more testing of the error, a half QPSK signal was created and transmitted. Which only had constellation points in two of the original four corners 5.4. This was to get a greater understanding of how the signal rotates and how much. First in Figure 5.5 the signal has a constant spin. This is then removed, creating the constellation that can be seen in Figure 5.6. The angles of both the spinning and fixed signal can then be seen in Figure 5.7. The error signal had a large negative deviation, which has been removed when looking at the fixed signal.

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Figure 5.4:Half QPSK

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5.1 MikTran Octave Analysis 39

Figure 5.6:Half QPSK after spin and phase shift has been taken out

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ferent "clock domains" that were set 5.9. Only one algorithm was tested in hard-ware. More were planned but with the limited time that was left after being able to transmit in the real world, all focus was placed on implementation.

Figure 5.8:Largest and average error

The TWTT algorithm achieved a maximum error of 12 clock cycles and an aver-age of 4 clock cycles when simulated, with results in Figure 5.8. This implies that the largest error of the algorithm is 120 ns and the average is 40 ns. The simula-tion was done with both systems sending sync messages to one another, in turn triggering the other system to send a sync message and so on. See Table 5.1 for a large amount of test setups as well as results. The results are written with the prefix milli, micro and nano seconds. The errors are defined as number of clock cycles.

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5.2 MikTran Hardware Simulation 41 Table 5.1:Results for Vivado simulation of TWTT

System clock 1 System clock 2 Simulation time Largest difference Average Stable

9.99996 ns 10.00004 ns — 2 ms 12 clk 4 clk 580 us 10 ns 10.1 ns 0.1 1 ms 13 clk 4 clk 157 us 9.1 ns 9.2 ns 0.1 2 ms 20 clk 6 clk 860 us 9.2 ns 9 ns 0.2 1 ms 20 clk 2 clk 173.9 us 10 ns 10.5 ns 0.5 1 ms 19 ns 5 clk 138 us 10 ns 11 ns 1 1 ms 23 ns 10 clk 320 us 10 ns 12 ns 2 1 ms 67 ns 24 clk 434 us 10 ns 12.1 ns 2.1 4 ms 5127 clk —– Unstable

There is a slight leap in time here and these are the results of the hardware simu-lation of the system. Where the FIR low-pass filters, timing recovery and PLL has been implemented. These results were down over cable with a 4 times oversam-pled signal was transmitted each 40000 clock cycle, or each 400 µs. The signal was then captured at the receiver, feed through Octave to create a simulation file and then used as input for a VHDL testbench.

5.2.2

Second TWTT simulation

The setup was for this algorithm was done with a random system clock feeding both systems, having a nominal cycle of 10 ns and having a drift up to 1 ns. For this simulation the FIFOs had been removed as system now would have the re-ceiver mounted in front of it that handle that part. The results can be seen in Figure 5.10. The system starts with a an time difference of 106 between the

sys-tems. What then can be seen is that both systems starts to adjust their time as the delta time starts to decrease, which can be seen at the bottom of Figure 5.10. The settling time of the simulated system is 61 messages and the final time dif-ference between the two systems is ±3 clock cycles. The time taken for the sim-ulation was about 16 ms and with an average of 10 ns clock cycles. The reason for only 61 messages being sent is that an artificial delay was introduced between the system, mimicking the time for the sender and receiver to do it’s work. The artificial delay introduced between the systems was 13000. A final result is that the algorithm is completely settled when the error in both units is the same (13007) in this case. This can be seen to the far right in Figure 5.10.

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Figure 5.10:Second simulation of the TWTT algorithm

5.2.3

One QPSK message

These results are from the VHDL test bench. At first the amplitude goes high, representing that a signal has passed the first CORDIC and that bits are incoming, represented by the yellow line. Then the timing algorithm finds the peak of the incoming transmission bits and the amplitude increases, represented by the red bar. Finally, the preamble detector find that the phase is locked in the wrong quadrant and then starts transforming the incoming bits to represent that. After these stages are done, the 2 preambles needed are detected and after that, each trial message, represented as 2D 16 times on hexadecimal form.

5.3

Hardware implementation

The hardware was implemented on two separate MikTran unit, running with a carry around 400 MHz and a signal sampling rate of 25 MHz. It was not possible to measure the frequency drift on the two units during the trials. Based on earlier tests this tends to be around 100-200Hz as a delta between the two units. This is well with in the margins of the receiver to compensate for.

The signals were sent inside of cables with connectors in the middle, creating some reflection as well as distortion in the cable but on the whole it should be a rather ideal transmission line.

5.3.1

First TWTT run

In Figure 5.12 and Figure 5.13 the start up of the system can be seen. At first it’s only doing incremental counting without any external inputs. In figure 5.13 the second system is booted and receives input from System 1 which is far ahead of it. In the first message received, a huge external time but small error is detected

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5.3 Hardware implementation 43

Figure 5.11:One captured QPSK message with annotation

by System 2. In the second messages received a compensated time from System 1 is received but this time the error is larger. This can be seen as the system time increase a second time. After these two first messages the system starts settling as can be seen in Figure 5.13. The jumps in time is from the sampling points, which occurred when a new message arrived, which means that the graph was not time continuous.

For this first trial run the exact settling time is unknown since no time stamp-ing or reference ID was implemented. What is on display is that the systems are communicating with each other, sending messages and correcting their time accordingly.

5.3.2

Secondary TWTT run

For this trial the system had the same carry and sampling frequency but the time samples were collected using the PPS signal from the on-board GPS receiver. That means that the time in each of the two units should be collected at the exact same second.

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Figure 5.12:Solo run of a TWTT algorithm

Figure 5.13:Settle of TWTT algorithm

The final timing difference the results can be see in Figure 5.14. Excluding some extreme values due to larger bit errors in the transmission, the time error was between 0-2000 clock cycles. With system clock running on at 100 MHz the error becomes

T imeerr= 2000 ∗

1

100 ∗ 106 = 20µs (5.1)

which is in the neighborhood of time synchronization of moving a GPS. One is-sue with this type of measurement is that the PPS timing was stationary. When measured with an oscilloscope the PPS time difference varied from 40 ns up to 5

µs. Comparing this result to Section 5.2.2 there was improvements to be done.

5.3.3

Third TWTT run

For the third iteration of the TWTT algorithm, bit error detection was introduced, described in Section 4.5.5. The algorithm was run for 800 seconds, sampling each

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5.4 Fourth TWTT run 45

Figure 5.14:Time error between two Miktran without error compensation

pulse of the PPS. The results can be seen in Figure 5.15. The absolute value of time difference was taken and as can be seen, the results are a median of 3 and an average of 12. Since these are clock cycles in difference, the average error can be said to be 120 ns since each is running on a 100 MHz clock.

5.4

Fourth TWTT run

As can be seen in Figure 5.16 the error between the two units is steadily below an absolute error of 20 clock cycles. This means that the error between the two unit is sub 200 ns with a median value of 4 and an average value of 4.436 clock cycles. This can be directly compared to the error in Figure 5.17 where no timing algorithm is active. The error between the two units grow on average with 62.5 clock cycles per second. Creating a discrepancy of 25000 clock cycles or 25 ms over a period of 400 seconds.

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Figure 5.15:Time error of two MikTran with error detection

Figure 5.17:Time error of two MikTran without time compensation

5.5

GPS test

The on board PPS and GPS time was tested on both Miktran units used and was found to have a slight drift. The PPS edges was about normally in the 100 ns range of each other but sometimes one of the units lost some satellite connection and it could drift up to 5 µs. The PPS measurement was done on an oscilloscope,

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5.5 GPS test 47

Figure 5.16:Time error of two MikTran on the fourth iteration

see Figure 5.18

Figure 5.18:Snapshot of PPS measurement

To reduce the error rate an antenna splitter was used, such as both systems would have the same input signal. This worked to eliminate the larger errors but since both GPS chips have a specified drift of up to 30 ns, some of the error remained. As can be seen in Figure 5.19, the error could sometimes move up to a 400 ns seconds offset before returning back the ±30ns jitter that was specified.

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Figure 5.19:Error between the systems as the PPS moves

5.6

Bit Error

In the early system design, sometimes a bit error would occur and the system would go out of bounds and have to settle again. An example of this is when the error is steady, it is around 2457 which can be represented by 12 bits. Since each error is represented by 64 bits there are 52 bits left which all have a higher value. So if any of these high bits are faulty it completely dominates the error. An examples of this is

Err1= ...000000000000000000000000000000000100110011001 = 2457

Err2= ...001100000000000000000000000000000100110011001 = 6597069769113

and can be seen in Figure 5.20, where the algorithm suddenly have a large errors that ripples through the system until it once again settles. This was solved using the bit error correction described in Section 5.6, sending dual messages.

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6

Discussion

6.1

General

To quote Donald Rumsfled "Because as we know, there are known knowns; there are things we know we know. We also know there are known unknowns; that is to say we know there are some things we do not know. But there are also unknown unknowns - the ones we don’t know we don’t know.".

For this thesis there have been a lot of interesting results but also a lot of things that were implemented that were not known when starting out. Such is the prob-lem when working with new a piece hardware, see Section 4.1. The entire receiver has been developed in a novel way both as an interesting approach and as an ad-hoc solution for an unknown problem.

The results that can be seen in Figure 5.10 tells the story that the algorithm works for being implemented in hardware and will drive the error between two units to zero given enough time. In the followup Figure 5.11 the observation is that the receiver is working for simulation purposes. First the timing locks, followed by the phase and then the preamble is detected. What should be noted is that neither the time- or the phase lock is perfect. They both ripple and especially for the PLL this can be real nuisance. If it at the starting point ends up with a large ripple because of the decision edge, Figure 4.2, it can be unstable so long that it misses the message. This is because of the feedback delay in both CORDICs, that adds up to 36 cycles, Section 4.5.3, creating slow repsone in the system.

Since the timing algorithm is implemented as a integrator with overflow, and the channels aren’t balanced there is always a risk that timing algorithm will get stuck jumping between two positions since it detects that the real value should

References

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