Institutionen för systemteknik
Department of Electrical Engineering
Examensarbete
Design and Implementation of an SDR receiver for
the VHF band
Examensarbete utfört i Elektroniksystem vid Tekniska högskolan i Linköping
av
Emad Athari & Petter Lerenius
LITH-ISY-EX--07/3946--SE
Linköping 2007
Department of Electrical Engineering Linköpings tekniska högskola
Linköpings universitet Linköpings universitet
Design and Implementation of an SDR receiver for
the VHF band
Examensarbete utfört i Elektroniksystem
vid Tekniska högskolan i Linköping
av
Emad Athari & Petter Lerenius
LITH-ISY-EX--07/3946--SE
Handledare: Per Löwenborg
ISY, Linköpings universitet
Jonas Nilsson
Signal Processing Devices Sweden AB
Examinator: Per Löwenborg
ISY, Linköpings universitet
Avdelning, Institution
Division, Department Elektroniksystem
Department of Electrical Engineering Linköpings universitet
SE-581 83 Linköping, Sweden
Datum Date 2007-01-31 Språk Language Svenska/Swedish Engelska/English Rapporttyp Report category Licentiatavhandling Examensarbete C-uppsats D-uppsats Övrig rapport
URL för elektronisk version
http://www.es.isy.liu.se http://www.ep.liu.se/2007/3946 ISBN — ISRN LITH-ISY-EX--07/3946--SE
Serietitel och serienummer
Title of series, numbering
ISSN
—
Titel
Title
Design och implementation av en SDR-mottagare för VHF-bandet Design and Implementation of an SDR receiver for the VHF band
Författare
Author
Emad Athari & Petter Lerenius
Sammanfattning
Abstract
The purpose of this thesis work is to examine the possibility of building a software-defined radio (SDR) for the VHF-band. The goal is to accomplish this with as few components as possible, thus cutting down the size and the production cost.
An SDR solution means that the sampling of the signal is done as close to the antenna as possible. The wide bandwidth needed in such a product is achieved by using SP Devices algorithm for time-interleaved ADCs. Two hardware proto-types and two versions of the software were designed and implemented using this technology.
They were also analyzed within this thesis work. The results proved to be good, and the possibilities to produce a commercial software-defined radio receiver for the VHF-band are good.
Nyckelord
Abstract
The purpose of this thesis work is to examine the possibility of building a software-defined radio (SDR) for the VHF-band. The goal is to accomplish this with as few components as possible, thus cutting down the size and the production cost.
An SDR solution means that the sampling of the signal is done as close to the antenna as possible. The wide bandwidth needed in such a product is achieved by using SP Devices algorithm for time-interleaved ADCs. Two hardware proto-types and two versions of the software were designed and implemented using this technology.
They were also analyzed within this thesis work. The results proved to be good, and the possibilities to produce a commercial software-defined radio receiver for the VHF-band are good.
Sammanfattning
Syftet med det här examensarbetet är att utreda möjligheten att bygga en mjuk-varudefinierad radiomottagare (SDR) för VHF-bandet. Målet är att göra detta genom att använda så få komponenter som möjligt, och därigenom minska stor-leken och produktionskostnaden.
En SDR lösning ger att samplingen kommer att ske så nära antennen som möjligt. Den stora bandbredd som behövs för en sådan produkt uppnås genom att använda SP Devices algoritm för att ”tidsinterleava” höghastighets ADC:er. Två hårdvaruprototyper och två versioner av mjukvaran har designats och imple-menterats.
Analyserna har visat bra resultat, och möjligheterna att bygga en komersiell mjukvarudefinierade radiomottagare för VHF-bandet ses som goda.
Acknowledgments
The completion of this thesis had not been possible without the help and support that we have received throughout this work. Therefore we would like to thank the people the persons that has made this possible.
Firstly we would like to thank our supervisors Per Löwenborg, at the Division of Electronics Systems at Linköping University, and Jonas Nilsson, at SP Devices, for their enormous support and for believing in us.
We would also like to thank all of the personnel at SP Devices and Peter, Christian, Marcus and Anders for great help and support.
Last but not least we would like to thank our families and friends for their endless love and support.
Abbreviations
ACK Acknowledgement
AD Analog-to-Digital
ADC Analog-to-Digital Converter AGC Automatic Gain Control
BB Baseband
BER Bit Error Rate
BPF Bandpass Filter
BW Bandwidth
BWch Channel Bandwidth
DAC Digital-to-Analog Converter
dB Decibel
dBc Decibel relative to the carrier dBFS Decibel relative to Full Scale Range dBm Decibel relative to 1 mW
DC Direct Current
DDS Direct Digital Sythesis DSP Digital Signal Processing
DR Dynamic Range
EMC Electromagnetic Compatibility ENOB Effective Number of Bits FFT Fast Fourier Transform
FIR Finite length Impulse Response FPGA Field-Programmable Gate Array
FSR Full Scale Range
GMSK Gaussian Minimum Shift Keying HDLC High Level Data Link Control
IF Intermediate Frequency
IP3 Third-Order Intercept Point IIP3 Third-Order Input Intercept Point IMD Intermodulation Distortion
IMD3 Third-Order Intermodulation Distortion
IQ In phase and Quadrature
IR Image Rejection
LNA Low Noise Amplifier
LO Local Oscillator
LPF Lowpass Filter LSB Least Significant Bit MAC Multiply and Accumulate
NF Noise Figure
NRZ Non Return to Zero
NRZI Non Return to Zero Inverted OIP3 Third-Order Output Intercept Point
PER Packet Error Rate
PG Process Gain
RF Radio Frequency
SAW Surface Acustic Wave
SDR Software Defined Radio
SFDR Spurious-Free Dynamic Range SNDR Signal-to-Noise and Distortion Ratio SNR Signal-to-Noise Ration
SNRreq SNR required
v4 Xilinx virtex 4
v5 Xilinx virtex 5
VGA Variable Gain Amplifier
Contents
1 Introduction 1
1.1 Background . . . 1
1.2 Purpose and Method . . . 1
1.3 Prerequisites . . . 2
1.4 Tools . . . 2
1.4.1 Protel . . . 2
1.4.2 Matlab and Simulink . . . 2
1.4.3 Xilinx ISE . . . 2
1.4.4 Microsoft Visual Studio . . . 2
1.5 Restrictions . . . 3
1.6 Report Disposition . . . 3
1.7 Reading Instructions . . . 3
2 Linearizer 5 2.1 Problems with Interleaved ADCs . . . 5
2.1.1 Gain Mismatch . . . 6 2.1.2 Offset Error . . . 7 2.1.3 Time-Skew . . . 7 2.2 The Solution . . . 8 3 Superheterodyne vs. SDR 11 3.1 Introduction . . . 11
3.2 Traditional Superheterodyne RF Receiver . . . 11
3.2.1 Advantages . . . 12
3.2.2 Disadvantages . . . 12
3.3 Software-Defined Radio Receiver . . . 13
3.3.1 Advantages . . . 13
3.3.2 Disadvantages . . . 13
4 Basic RF Receiver Concepts 15 4.1 Signal-to-Noise Ratio . . . 15
4.2 Receiver Noise . . . 15
4.3 Intermodulation Distortion & Intercept Point . . . 16
4.4 Dynamic Range . . . 18
4.5 Spurious-Free Dynamic Range . . . 18 xi
4.6 Effective Number of Bits . . . 18 4.7 Oversampling in Analog-to-Digital Converters . . . 18 5 Requirements 21 5.1 Bandwidth . . . 21 5.2 Sensitivity . . . 21
5.3 Intermodulation Response Rejection and Blocking . . . 22
5.4 Adjacent Channel Selectivity . . . 22
5.5 Signal-to-Noise Ratio . . . 22
6 Analog Front-End 25 6.1 Front-End Architecture . . . 25
6.2 Choise of Components . . . 26
6.2.1 ADC . . . 26
6.2.2 LNA and VGA . . . 27
6.2.3 Analog Filters . . . 28
6.2.4 FPGA . . . 31
6.2.5 USB-to-UART Interface . . . 31
6.2.6 DAC . . . 31
6.2.7 Crystal Oscillator and Clock Buffer . . . 32
6.2.8 Linear Voltage Regulators . . . 32
6.3 Theoretical Calculations . . . 34 6.3.1 SNR . . . 34 6.3.2 IMD3 . . . 36 6.4 PCB and EMC[13] . . . 37 7 Data Packets 39 7.1 The Packet . . . 39 7.1.1 Training Sequence . . . 40 7.1.2 Start Flag . . . 40 7.1.3 Data . . . 40
7.1.4 Frame Check Sequence . . . 41
7.2 Bit Stuffing . . . 41 7.3 NRZI . . . 41 7.4 GMSK . . . 42 7.4.1 Gaussian filter . . . 42 8 FPGA 43 8.1 Hardware Prerequisites . . . 43 8.1.1 DSP-slices . . . 44 8.2 First Attempt . . . 44 8.2.1 Linearizer . . . 44 8.2.2 First Decimation . . . 46 8.2.3 I - Q Modulation . . . 46 8.2.4 Second Decimation . . . 47
Contents xiii 8.2.5 Third Decimation . . . 47 8.2.6 Phase Differentiator . . . 48 8.2.7 FIFO . . . 48 8.2.8 Data Transfer . . . 49 8.2.9 DAC Controller . . . 49 8.3 Second attempt . . . 49 8.3.1 Linearizer . . . 49 8.3.2 IQ-modulation . . . 49 8.3.3 Decimation . . . 51 8.3.4 Phase Differentiator . . . 57 8.3.5 FIFO . . . 57 8.3.6 Serial Interface . . . 57 8.3.7 DAC Controller . . . 57 8.4 Calculations . . . 57 8.4.1 Scaling . . . 57 8.4.2 Word Length . . . 58 9 PC 61 9.1 Communication . . . 61 9.2 Matlab . . . 61 9.2.1 Symbol Syncronization . . . 61 9.2.2 Decode NRZI . . . 63
9.2.3 Extraction of the Data . . . 63
10 Tests and Results 65 10.1 Filter Bandwidths . . . 65
10.1.1 Board 1 . . . 65
10.1.2 Board 2 . . . 65
10.2 External LNA . . . 66
10.3 SNR . . . 67
10.3.1 Variable Gain - Fixed Signal Level . . . 67
10.3.2 Fixed Gain - Variable Signal Level . . . 68
10.4 Sensitivity Test . . . 69
10.4.1 Board 1 . . . 70
10.4.2 Board 2 . . . 72
10.5 Blocking Test . . . 72
10.6 Intermodulation Test . . . 74
10.7 Adjacent Channel Selectivity . . . 75
10.8 Power Consumption . . . 75
11 Conclusions and Future Work 77 11.1 Conclusions . . . 77
11.1.1 Test Results . . . 77
11.1.2 Hardware . . . 78
11.1.3 FPGA . . . 78
Contents xv
List of Figures
2.1 Effect of problems that occur when interleaving ADCs. . . 5
2.2 Result of a gain error in an ADC. . . 7
2.3 Result of an offset error in an ADC. . . 7
2.4 Result of time-skew in an ADC. . . 8
2.5 The block diagram of the linearizer . . . 8
2.6 Interleaved sequencies with missmatch, before and after linearization. 9 3.1 Superheterodyne receiver architecture . . . 11
4.1 Intercept Points/1-dB Compression Points . . . 17
6.1 The architecture of the analog front-end. . . 25
6.2 BPF1 - 1st order bandpass filter. . . 29
6.3 BPF2 - 2nd order bandpass filter. . . 29
6.4 BPF1 - 1st order bandpass filter. . . 30
6.5 The configuration for IMD measurements. . . 36
7.1 Block schematic for the modulation. . . 39
7.2 A packet’s different components. . . 39
7.3 The training sequence before and after NRZI encoding. . . 40
7.4 An example bit stream which has been bit stuffed. . . 41
7.5 An example bit stream encoded with NRZI . . . 41
8.1 DSP48-slice in virtex 4. . . 44
8.2 DSP48E-slice in virtex 5. . . 45
8.3 System overview for the first attempt. . . 45
8.4 The frequency response for the first decimation filter. . . 46
8.5 Impulse response for the second decimation filter. . . 47
8.6 Impulse response for the third decimation filter. . . 48
8.7 System overview for the second attempt. . . 50
8.8 The difference between the two DDS blocks. . . 51
8.9 The frequency response for the complete decimation filter. . . 52
8.10 A zoomed in portion of the frequency response in Figure 8.9. . . . 52
8.11 Impulse response for the first decimation filter. . . 53
8.12 Impulse response for the filter h2 . . . 53
8.13 Impulse response for the filter h3. . . 54
8.14 Impulse response for the filter h4 . . . 54
8.15 Impulse response for the filter h5. . . 55
8.16 Impulse response for the filter h6. . . 55
8.17 Impulse response for the filter h7. . . 56
8.18 Impulse response for the filter h8. . . 56
9.1 The impulse response for the correlation filter. . . 62
9.2 An example output from the correlation filter. . . 62
9.4 An example bit stream decoded from NRZI. . . 63
10.1 Frequency response for board 1. . . 66
10.2 Frequency response for board 2. . . 66
10.3 Setup for SNR test, without and with external LNA. . . 67
10.4 The setup for the sensitivity test for board 1. . . 70
10.5 The setup for the sensitivity test for board 1 with LNA. . . 71
10.6 The setup for the sensitivity test for board 2. . . 72
10.7 The setup for the sensitivity test for board 2 with LNA. . . 72
10.8 The setup for the blocking test. . . 73
List of Tables
2.1 Time-interleaved ADC matching requirements at 180 MHz clock
frequency. . . 6
6.1 SNR requirement at different sampling frequencies. . . 27
6.2 Properties for the VGA. . . 28
6.3 Component values for the analog bandpass filters. . . 31
6.4 Current consumption of the first PCB . . . 32
6.5 Current consumption of the second PCB . . . 33
7.1 Packet components and their sizes. . . 40
8.1 L2-norm scaling of the decimation filters. . . 58
8.2 SNR for different word lengths. . . 59
10.1 Properties for the external LNA. . . 67
10.2 SNR for a -70dBm signal without and with external LNA on board 1. 68 10.3 SNR for a -70dBm signal without and with external LNA on board 2. 68 10.4 SNR for various signal levels without and with external LNA on board 1. . . 69
10.5 SNR for various signal levels without and with external LNA on board 2. . . 69
10.6 Sensitivity test using PCB 1. . . 70
10.7 Sensitivity test using PCB 1 with external LNA. . . 71
10.8 Sensitivity test using PCB 2. . . 72
10.9 Sensitivity test using PCB 2 with external LNA. . . 73
10.10IMD test performed on board 2. . . 74
Chapter 1
Introduction
1.1
Background
Signal Processing Devices Sweden AB (SP Devices) was started in 2003, with an algorithm that solves the problems that occur when time-interleaving high precision ADCs. The algorithm was a result of research done by Håkan Johansson and Per Löwenborg at Linköping University.
The possibility of time-interleaving ADCs opens up many new fields for digi-talization. For example, with two 14-bit time-interleaved ADCs, sampling speeds of above 400 MSps can be achieved. This means that the Nyquist criterion can be met for a 200 MHz bandwidth.
The field of software-defined radios (SDR) is a big research area. The SDR can revolutionize the market of radio receivers. They are much more flexible and in some cases cheaper to produce than todays receivers.
The goal with this thesis is to show that SP Devices’ algorithm applied on two ADCs can be used to build a software-defined radio receiver for the VHF-band (112-174 MHz) with as few components as possible. This thesis work was conducted at SP Devices in Linköping.
1.2
Purpose and Method
The purpose of this thesis is to design, implement and analyze a prototype of a software-defined radio for the VHF frequencies 112-174 MHz from idea all the way to a working prototype. The SDR architechture will be compared with the superheterodyne receiver architechture, which is commonly used today.
During this work an incremental method of development will be used. By improving the design in small steps, the work will advance in steps that are easily controlled. This will be achieved by first building a model of the SDR in Matlab and then implement it as a prototype in two steps.
Two versions of both the hardware and the software will be completed during the thesis. This will make it possible to make an attempt and then refine it
and correct possible errors. The two versions are analyzed and their performance measured and compared.
1.3
Prerequisites
To grasp this thesis the reader should have some previous knowledge of electronics and concepts like field-programmable gate arrays (FPGAs). Also some under-standing of digital signal processing and radio technology could be useful.
1.4
Tools
During the work of this thesis some software tools have been used to complete the tasks of building a prototype. Here follows a description of the programs used and a description of their purpose.
1.4.1
Protel
Protel is a CAD program for designing printed circuit boards (PCB) and it also provides the possibility to do simulations on schematic level.
The schematic of the front-end architechture was drawn and simulated before the PCB was designed. The PCB was then routed by hand before it was sent for manufacturing at Elprint1.
1.4.2
Matlab and Simulink
Matlab and Simulink was used to make a model of the system and to predict its behavior. Matlab is convenient to use when dealing with simulations of digital processing. For simulations of the analog parts it is better to use Protel.
Matlab was also used for the decoding process and to present the results during the performance tests.
1.4.3
Xilinx ISE
Xilinx ISE is an integrated development environment (IDE) for Xilinx FPGAs. It translates, synthesizes and routes the Verilog or VHDL code onto the designated FPGA. In this project only Verilog was used. ISE is easy to work with and allows code modules to be in different files, which makes the development process much easier. It is free if developing for Xilinx Virtex 4 FPGAs, but needs a license when using a Xilinx Virtex 5.
1.4.4
Microsoft Visual Studio
C code was written to produce a dynamically linked library (dll) file used by matlab to fetch data from the usb port. It was written and compiled in the
1.5 Restrictions 3
Microsoft Visual Studio environment. Visual Studio is Microsoft’s IDE for C, C++ and many more languages.
1.5
Restrictions
This thesis work will produce a prototype for decoding a specific kind of digital messages that are modulated with GMSK. No other modulations will be treated or discussed. This report analyzes the prototypes designed and it will not cover any other solutions.
1.6
Report Disposition
This report will present the work performed during this thesis and its results. The first chapters cover the more theoretical parts while the later chapters describe the work and the results.
Chapter 2 explains the problems that come up when time-interleaving ADCs, and the solution that SP Devices has developed. Chapter 3 will explain more about how SDR works and what the advantages are compared to the common superheterodyne receivers that are commonly used today. It is followed by Chapter 4 that discusses the parameters of a receiver performance, while Chapter 5 presents the requirements for this project.
The work performed in this thesis will then be presented. It starts with the PCB and its analog front-end in Chapter 6. The data packages that are used for testing the receivers’ performance is explained in Chapter 7. It is followed by the description of the digital signal processing performed in the FPGA in Chapter 8 and the PC in Chapter 9.
The tests and their results are described in Chapter 10. Finally the conclusions made in this thesis are presented in Chapter 11 together with some ideas of how to continue with this work.
1.7
Reading Instructions
Those who have good knowledge in electronics and radio technologies could skip the first theoretical chapters, except for Chapter 5 which could be good to have read to understand the decisions made in Chapter 6.
The most interesting chapter is probably Chapter 10 where the results are presented.
Chapter 2
Linearizer
To achieve high speed analog-to-digital conversion, time-interleaving multiple ADCs seems to be a good solution. This has been used for low resolution ADCs since 1980, but higher resolutions matching problems deteriorate the quality of the sig-nal.
An 8-bit system that provides a dynamic range of 50 dB can tolerate a gain mismatch of 0.25% and a clock-skew error of 5 ps. This accuracy can be met by traditional methods like, matching the physical channel layouts, using common ADC reference voltages, prescreening devices, and active analog trimming, but this is not enough for higher resolutions[10].
The problems that need to be considered when ADCs are interleaved are shown in figure 2.1 were four ADCs have been time interleaved.
In this chapter the problems caused by interleaving will be discussed and then SP Devices’ algorithm for solving these problems will be presented.
Resulting digital signal Desired digital signal
Figure 2.1. Effect of problems that occur when interleaving ADCs.
2.1
Problems with Interleaved ADCs
There are three main categories of problems that arise when ADCs are interleaved. They all come from the fact that it is impossible to manufacture two silicon chips
that are identical. The surrounding environment also affects how well the ADCs match, e.g., if they have different temperature. This results in differences in gain, offset and timing, which affects the output in a way depicted by the Figure 2.1. For narrowband signals, there will be unwanted spurious frequencies in the output signal, called spurs.
ISgain(dB) = 20 log(ISgain) = 20 log
Ge
2
(2.1)
Ge = gain error ratio =
1 − VF SA
VF SB
(2.2)
ISphase(dB) = 20 log(ISphase) = 20 log θep 2 (2.3) θep = ωa∆te(radians) (2.4)
ωa = analog input frequency (2.5)
∆te = clock skew error (2.6)
IStot(dB) = 20 log
(ISgain)2+ (ISphase)2
(2.7) From equations 2.1 - 2.7 it is possible deduce that even very small divergences between the ADCs will result in large spurs that will deteriorate the dynamic range. Table 2.1 shows the matching requirements for a time-interleaved system[10].
Number of bits SFDR Gain Matching Aperture Matching
(dBc) (%) (fs) 12 74 0.04 0 12 74 0 350 12 74 0.02 300 14 86 0.01 0 14 86 0 88 14 86 0.005 77
Table 2.1. Time-interleaved ADC matching requirements at 180 MHz clock frequency.
2.1.1
Gain Mismatch
The gain error cause the ADC to affect the output by changing the signal am-plitude. As seen in Figure 2.2, this would not affect the signal noticeably if only one ADC was used, but when two ADCs are interleaved it will result in aliasing distortion. The differences in gain between two ADCs affects the output even if it is as small as 0.01%, as shown in equations 2.1 and 2.2. The spurs deteriorate the signal quality, or destroy the wanted signal if they coincide.
2.1 Problems with Interleaved ADCs 7
Gain error
Figure 2.2. Result of a gain error in an ADC.
2.1.2
Offset Error
An ADC has a small DC offset in its output, and when using two ADCs they will have different offsets. When two ADCs are time-interleaved different offsets will result in a spur at π. The figure 2.3 shows an exaggerated offset error.
Offset error
Offset
Figure 2.3. Result of an offset error in an ADC.
2.1.3
Time-Skew
Time-skew errors, or phase errors, arise when the ADC’s samples are taken at the wrong instants in time. When more than one ADC samples the signal the time-skew will be experienced as a phase error. This will cause aliasing distortion that coincide with the gain error[10]. The time-skew is depicted in Figure 2.4, where the samples are taken with a delay in time.
Time skew
Figure 2.4. Result of time-skew in an ADC.
2.2
The Solution
SP Devices has developed a clever algorithm, called linearizer, that corrects these errors by filtering the digital result. Figure 2.5 shows a block diagram of the linearizer. ADC 1 ADC 2 Reconstructor Estimator Monitor & Control
Linearizer
Figure 2.5. The block diagram of the linearizer
The linearizer is purely digital and uses advanced signal processing algorithms to correct the errors mentioned in the previous section. Since the correction is done digitally it can function with any ADC. The linearizer could also be used to increase the resolution while maintaining the speed.
The estimator uses a batch of data to estimate the different errors. These estimates are used for calculating the filter coefficient values. The coefficients are then passed on to the reconstructor. The reconstructor block consists of a filter that corrects the errors from the differencies in the ADCs in real time.
By using the linearizer, as depicted in Figure 2.6 it is possible to construct very fast ADCs with high performance, that opens up many new possibilities in fields previously not conceivable. The software-defined radio developed in this thesis is
2.2 The Solution 9 ADC ADC ADC ADC ADC ADC ADC ADC L i n e a r i z e r
Figure 2.6. Interleaved sequencies with missmatch, before and after linearization.
Chapter 3
Superheterodyne vs. SDR
3.1
Introduction
This chapter will explain the pros and cons of the commonly used superheterodyne radio frequency (RF) receiver and a software-defined radio (SDR) receiver. It also covers the differences between the two types and why the SDR receiver together with SP Devices’ technology is preferred in a broadband RF receiver where small area, low power consumption and low cost are the main requirements.
3.2
Traditional Superheterodyne RF Receiver
One of the most common RF receiver architecture types used in radio applications for the last century and today is the superheterodyne receiver. This receiver type is often preferred because of its great performance regarding receiver character-istics such as sensitivity and selectivity. A simple description of the traditional superheterodyne architecture can be seen in the block diagram in Figure 3.1.
RF Filter LNA BPF LO IF Amp BPF AGC Amp IQ-demodulator Rx IQ
Figure 3.1. Superheterodyne receiver architecture
The first block after the antenna is an RF bandpass filter (BPF) which atten-uates the undesired out-of-band frequencies. The signal is then amplified in a low noise amplifier (LNA) which amplifies the signal with relatively low noise contri-bution. This device is the most crucial part of the receiver chain because of the many system requirements depending on it. After the amplification and bandpass filtering the signal is down-converted by a mixer. This process is the principle of
heterodyning which is the generation of an intermediate frequency by mixing (mul-tiplying) the incoming high frequency signal with another high frequency signal generated by a local oscillator (LO). The mixer circuit has significant requirements on linearity and noise and can cause severe DC-offset problems in the receiver.
The generated IF-signal is amplified in the IF-amplifier before selection of the desired channel in the last BPF. In the last stage the signal amplitude is adjusted by the automatic gain control (AGC) to fit the dynamic range of the analog-to-digital converter(s) (ADC).
3.2.1
Advantages
• A major advantage of the superheterodyne receiver is that by mixing down
the signal to lower frequencies the cost of the components reduces. Gener-ally for RF components, such as filters and mixers, cost is proportional to frequency[4]. This is due to the fact that low frequency components are less complex and easier to find/build.
• The down-conversion to IF gives the receiver high selectivity i.e. high ability
of sorting out the desired signal by supressing the undesired signals. This is because the requirements on the filters are relaxed when operating at lower frequencies (IF), which makes it easier to build more effective selective filters with much narrower passband.
3.2.2
Disadvantages
• One of the biggest cons of the superheterodyne receiver is the amount of
external components. The wider frequency spectrum the harder it is to find or build narrow-passband filters to a reasonable cost, if not impossible. More components means higher cost, higher power consumption, larger area and higher architecture complexity.
• The complexity mentioned above leads to another problem which is the low
achievable level of integration. This also depends on the fact that the high performance of discrete components is hard to achieve in an integrated so-lution.
• Another problem in this architecture is the mixer and local oscillator stages.
One problem that is associated with mixer circuits, besides the cost, is the so called LO-leakage. This leakage can get mixed with the oscillator itself and/or get picked up by the antenna and get amplified in the LNA producing a spur.
• The wanted channel is predefined by hardware. Each channel require a
separate receiver which increases the need of hardware if multiple channels are desired.
3.3 Software-Defined Radio Receiver 13
3.3
Software-Defined Radio Receiver
One of the newest and most interesting concepts in radio architecture development is software-defined radio (SDR). In this thesis project only the receiver part is discussed.
The basic idea of the SDR receiver is to digitalize the incoming analog RF signal as close to the antenna as possible and then do the signal processing digitally. In an ideal SDR receiver the ADC(s) would be attached directly to the antenna sending the samples to some kind of processor (FPGA, DSP etc.) where the data would be transformed/shaped as desired by software. The sampling frequency (fs) would have to be greater than twice the signal bandwidth to be able to reconstruct the signal from the digital samples (Nyquist theorem)[11]. In practice this is hard to achieve due to the fact that todays ADC:s with the required resolution, are yet too slow to receive radio signals at higher frequencies.
In current commercial software receivers the problem mentioned above is solved by mixing down the radio signal to a lower frequency using local oscillators, as mentioned above in Section 3.2. This will not be the case here hence the main goal is to significantly reduce the use of analog hardware. Instead the problem is ap-proached by taking advantage of time-interleaving. As it was described in Chapter 2, interleaving allows faster fsthan the specified fsof the ADC. By interleavingN ADCs the fscould beN times the fsof a single ADC. Also described in Chapter 2 was that SP Devices algorithm makes it possible to interleave high-speed ADC:s without degrading the resolution. This technology allows high enough sampling frequency for sampling the signal without requiring down-conversion, i.e. no mix-ers or local oscillators are needed.
The hardware architecture used in this project is further explained in Chapter 6.
3.3.1
Advantages
• The SDR receiver has the ability to receive different modulation types while
using the same hardware platform.
• Its funcionality can be changed by downloading and running new software
whenever desired, without any change of hardware.
• Reduction/elimination of the use of analog hardware which means lower
cost, lower power consumption, smaller area needed and lower architecture complexity.
• The channel is not predefined by hardware which means that any channel
within the bandwidth can be chosen by software. It is even possible to receive several channels in parallel.
3.3.2
Disadvantages
• Finding the right components, such as amplifiers, for a flexible front-end can
• Filters are expensive and hard to design for such broadband applications. • Writing software for different applications can be quite complex.
Chapter 4
Basic RF Receiver Concepts
4.1
Signal-to-Noise Ratio
Signal-to-noise ratio (SNR) is the ratio between the power of the desired signal and the average power of the noise in the system. In other words, the higher SNR the less noise in the system and the clearer signal. SNR is calculated using Equation 4.1[11]. SN R= 10 log Psignal Pnoise (4.1) In the process of choosing components for the receiver it must be considered how much a specific component affects the overall SNR, due to its noise contribu-tion. This means that in order to do an approximate calculation of the systems SNR for a specific signal level the total receiver noise must be calculated. The section below shows the equations used for noise calculation. The SNR calulations for this system are done in Section 6.3.1.
4.2
Receiver Noise
In order to do a calculation of the receiver noise the thermal noise at the antenna must be calculated by using Equation 4.3[21] is Boltzmann’s constant, T is ab-solute temperature in kelvins and B is the Nyquist bandwidth, fs/2. Usually in receiver noise calculations T is chosen to be 290K and gives 10logkT = -174 dBm. dBm is a representation of a power level in dB relative to 1 mW. This representa-tion gives a clue of how much stronger the measured signal is in comparison with 1 mW.
Nth = kT B (4.2)
Nth(dBm) = 10 log kT + 10 log B =
= −174dBm + 10 log B (4.3)
After the calculation of the thermal noise the noise and gain contribution of all parts in the receiver are added, as shown in Equations 4.4 - 4.5. Nin is the total noise power of the receiver before the A/D-conversion.
Fi = Ni−1+ Ni Ni−1 = 1 + Ni Ni−1 ⇒ ⇒ Ni Ni−1 = Fi− 1 (4.4) Nin = G1G2kTB + G1G2[F1 - 1]kTB + G2[F2- 1]kTB = = G1G2[F1+F2− 1 G1 ]kTB = = GsysFsyskTB[W] (4.5)
Equation 4.5 represents the noise in a system containing two gain and/or noise contributing devices. Fi is the noise factor of the i:th device after the antenna and Gi is the gain factor of ditto. As shown in Equation 4.5, the noise factor of a device is divided by the gain factor of all previous devices. This means that devices that are placed far from the antenna contributes less to the overall noise than the ones closer to the antenna.
Notice that all noise and gain factors for the cascaded parts are linear values not logarithmic. Usually in the devices’ data sheets the noise is represented as noise figure (NF). NF is the common logarithm of the noise factor.
4.3
Intermodulation Distortion & Intercept Point
Intermodulation distortion (IMD) occurs when two or more different input fre-quencies exist in a device, resulting in production of undesired output signals (intermodulation products) at other frequencies. This is a problem in all ampli-fiers and mixers but also in passive components. In this project only ampliampli-fiers and passives are taken into account because of the absence of mixers. These in-termodulation products (IMD products) are produced at the sum and difference of integer multiples of the existing frequencies. Equation 4.6 expresses the output frequency components when two different input frequencies exist in the device, which results in two-tone intermodulation distortion.
IM D= m · f1 ± n · f2 (4.6)
The sum of the integers m and n in Equation 4.6 defines the order of the IMD product. Most of these products are either too weak to be detected or too far away to interfere with the desired frequencies. Generally in RF systems, and in the case of this project, the third-order products (IMD3: 2f1+ f2, 2f1− f2, 2f2− f1, 2f2+ f1) are of great concern, since the probability of them falling inband and interfere with the desired frequency is high[21]. Intermodulation rejection raito is the ratio between the desired signal and the highest IMD3 product. It is an
4.3 Intermodulation Distortion & Intercept Point 17
imortant parameter which describes the receivers ability to handle strong IMD products.
Commonly IMD3 products are specified in terms of third-order intercept point (IP3). This is a measure of the devices tolerance against interfering signals outside the desired passband. In Figure 4.1[7] the output power is plotted versus the input power, both in logarithmic scale. It is shown that both the output signal and the IMD3 product increase linearly with increased input signal. For every 1-dB of signal increase the IMD3 product amplitude increases 3 dB because of increased distortion in the device. At a certain level of input signal strength the wanted signal and the IMD3 product will be equal. This point is called the IP3 which usually is referenced to either the input or the output of the device. IIP3 is the input power at the IP3and OIP3is the output power at the IP3. The relationship between the two is OIP3= IIP3+ system gain.
Figure 4.1. Definition of Intercept Points and 1-dB Compression Points for Amplifiers
Also seen in Figure 4.1 is the 1-dB compression point which shows the input signal level at which the receiver begins to get a non-linear amplitude response. This means that the device is linear up to a certain input signal level after which the output becomes saturerad and stop increasing with increased input signal. Both IP3 and 1-dB compression point are important parameters in the choice of amplifiers and most often one or both these values are given in the devices data sheet.
The power of an intermodulation product is calculated using Equation 4.7[5]. PIMout is the power of the IMD product at the output of the device and Pout is
the signal power at the output.
This equation will be used in Section 6.3.2 to calculate a theoretical value of the total PIM generated in the chosen system configuration.
4.4
Dynamic Range
Dynamic Range (DR) is the ratio between the maximum and the minimum signal that a receiver is designed to handle simultaneously. This measure is used for describing the limits of receivers. DR is of great concern in SDR solutions because of the wide frequency band of interest where signal levels can differ significantly.
4.5
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) measures the ratio between the root-mean-square (rms) level of the desired signal and the rms level of the highest spur in the spectrum. It is an important parameter in cases where harmonic distortion and spurious signals are undesirable. One example of these cases is analog-to-digital converters (ADCs) in which noise and harmonics limit the dynamic range.
4.6
Effective Number of Bits
The ADC resolution is defined as the number of bits at its output, i.e. the size of the binary word which represents the sampled analog signal. An alternative definition is the size of the least significant bit (LSB), Equation 4.10. It should be noted that it is not a measure of the conversion quality. There are different error sources in an ADC degrading its performance. When all sources are included, the resolution is usually lower than the specified number of bits of the converter[11]. That is why the effective number of bits (ENOB) of an ADC is such an important parameter and represents the noise-free bits. ENOB is a measure of the ADCs accuracy at a specific input frequency. It is calculated using Equation 4.9[11]. As seen in the equation the value of SNDR is needed for the calculation of ENOB. SNDR is signal-to-noise-and-distortion ratio and is defined similarly as SNR except it also includes distortion. See Equation 4.8[11]
SN DR = 10 log Psignal Pnoise+ Pdistortion (4.8) EN OB = SN DR− 1, 76 6.02 (4.9)
4.7
Oversampling in Analog-to-Digital
Converters
As mentioned earlier in Section 3.3, in order to reconstruct a signal from its digital samples it must be sampled at a frequency that is greater than twice the bandwidth
4.7 Oversampling in Analog-to-Digital
Converters 19
i.e. Nyquist’s criterion. If fs/2 is higher than the Nyquist frequency the ADC is considered to be oversampled. By oversampling the ADC(s) the overall SNR is increased. The reason of this is explained below.
Quantization noise is introduced in the ADC when the continuous analog signal is quantized to discrete values[11]. This quantization noise is a fixed power and is independent of the input signal, as shown in eq 4.11[21] This noise is spread out over the Nyquist bandwidth, which is dc up to fs/2. If the ADC is oversampled the noise is spread out over a wider range of frequencies. So the wider fsthe lower noise floor, i.e. higer SNR. This improvement of the SNR is called oversampling gain or process gain, see Equation 4.12.
Vlsb = Vp−p 2N (4.10) Pqn = Vlsb2 12R (4.11)
process gain = 10 log
fs/2
BW
Chapter 5
Requirements
Several requirements regarding the receiver’s performance are set up for this project. These requirements will be presented in this chapter. Also some ba-sic RF receiver concepts will be explained in order to make the understanding of the requirements easier.
5.1
Bandwidth
The bandwidth (BW) of the receiver in this project is desired to be between 112-174 MHz. This wide BW of 62 MHz sets major requirements on the analog filters in the receiver. The filter requirements and problems caused by the wide BW are explained in Section 6.2.3.
5.2
Sensitivity
Receiver sensitivity is the lowest signal level that is detectable by the receiver. The requirements regarding sensitivity in this project is that the receiver must be able to decode a modulated message at 162 MHz with a signal level of -107 dBm. A packet error rate (PER) of 20% is allowed. The modulation type of the signal is discussed in Chapter 7.
The highest detectable signal is required to be -7 dBm. The number of un-correctly received messages at this level should not differ by more than 10 from those received at -77 dBm. These boundary values of the signal level give a span of 100 dB. It should be kept under consideration that all the components used in the analog front-end must have proper performance at all levels of the 100 dB interval.
5.3
Intermodulation Response Rejection and
Blocking
Intermodulation response rejection is the receivers ability to supress IMD products caused by two or more undesired signals. The frequencies of these signals have a specific relationship to the desired signal frequency. A blocker on the other hand is a strong out-of-band interferer that sets requirement on the receivers DR. The blocker signal sets limitation on the maximum allowed receiver gain.
In this project the receiver must be able to decode messages with 20% PER at a level of -101 dBm in presence of two IMD products at -27 dBm and a blocker signal at -15 dBm. One of the IMD products is adjusted 500 kHz below or above the wanted frequency and the other is adjusted 1000 kHz below or above it. The blocker signal is adjusted 5MHz below the wanted frequency. The input desired signal is adjusted to the same frequency as the previous test. This test is considered to simulate the worst case scenario.
5.4
Adjacent Channel Selectivity
The adjacent channel selectivity is the receivers ability to receive desired signals in presence of an undesired interfering signal at the frequency of the channel directly above that of the desired signal. The requirment on the adjacent channel selectivity of the receiver is that it shall not be less than 70 dB.
5.5
Signal-to-Noise Ratio
As mentioned in Section 5.3 the receiver must be able to operate despite the existence of a blocker signal and two IMD products. In this worst case scenario it is possible that the mentioned signals interfere with each other, hence their amplitudes will be added together, creating an amplitude even higher than the amplitude of the blocker signal alone. This amplitude is calculated by using the equations below.
A = 50 · 10−3· 10PdBm/10, conversion of dBm to V (5.1)
P = A
2
R (5.2)
Atot = Asig+ Ablocker+ AIM D1+ AIM D2 (5.3) Ptot,dBm = 10 log A2tot R· 10−3 (5.4) DR = Ptot,dBm− Psignal (5.5)
The resistor value R in Equation 5.2 is 50 Ω and is the antennas load resistance. In this case the signal caused by the mentioned interference is at a level of -11.5 dBm. The difference between this level and the desired signal level at -101 dB
5.5 Signal-to-Noise Ratio 23
gives a DR of 89.5 dB. The decoder that is used for decoding the received messages requires an SNR of 12 dB. This means that the receiver need an overall SNR of at least 89.5 + 12 = 101.5 dBFS to be able to decode a received message. dBFS is a representaion of the ratio between a signal and the full-scale signal of a system.
For the sensitivity test the required SNR is different from above due to the receiver gain which is decided by the gain in the amplifiers and possibly the filters. Thus the SNR of this test will be presented after the components has been chosen, see Chapter 6.
Chapter 6
Analog Front-End
This chapter covers the chosen architecture of the analog front-end and motivates the choice of components for both PCB versions. Also both PCB designs are presented together with the measures taken to prevent EMC problems.
6.1
Front-End Architecture
As mentioned earlier the main goal of this project is to build an RF receiver for the required frequency band containing as few analog parts as possible. This achieve-ment is possible due to the concept of SDR together with SP Devices technology. As was mentioned in Section 3.3 this technology makes it possible to build a so called direct sampling receiver witout using mixer circuits and local oscillators for frequency down-conversion. Despite this fact the ADCs can not be directly at-tached to the antenna due to a couple of reasons. One reason is that without some attenuating bandpass filters strong undesired signals could saturate the ADCs. Another reason is that without amplification the weakest signals would never get strong enough to get sampled properly by the ADC. The closer a signal is to the ADC’s input voltage range the more bits of the ADC are used. Figure 6.1 shows the chosen architecture for the analog front-end.
BPF1 LNA BPF2 AGC ADC1 ADC2 DAC
F
P
G
A
Figure 6.1. The architecture of the analog front-end.The first bandpass filter (BPF1) is intended to attenuate undesired out-of-band frequencies. The signal is then differentiated passing through a 1:1 transformer.
The reason for differentiating the signal path is to reduce the sensitivity of distur-bance in the transmission lines. This is further explained in Section 6.4.
After the first filter the signal is amplified in a low noise amplifier (LNA), which is the most crucial part of this design due to the noise and IMD requirements depending on it, see Section 6.2.2. The second bandpass filter (BPF2) is meant to filter out the wanted signal further before its amplitude is adjusted by the variable gain amplifier (VGA). The VGA is controlled to either amplify the signal or attenuate it, depending on the signal level. This is called automatic gain control (AGC) and is intended to push the signal amplitude as close as possible to the ADC:s input voltage range.
The last stage of the front-end is the A/D-conversion. Here the two interleaved ADCs digitalize the received signal and feeds it through to a field-programmable gate array (FPGA) where the data is processed. The data processing in the FPGA is explained in Chapter 8.
This front-end architecture is used on both PCB:s. The only difference is that in the first case the FPGA is off-board and is placed on a development board. On the second PCB the FPGA is placed on-board.
6.2
Choise of Components
In this section the chosen components are presented together with the motivation of why they were chosen. Choosing and finding the right components for the analog front-end is very challenging. The choice of the different parts of the receiver must be done in parallel, because the properties of all parts depend on each other. In this project the ADC is chosen to be the starting point.
The components used in the front-end alone do not differ between the two boards. The major difference is that the FPGA is mounted on-board in the second attempt while in the first case an external development board handled the signal processing.
6.2.1
ADC
The analog-to-digital conversion is usually the part that limits the performance of the receiver. The most important parameters in choosing this component are resolution, sampling frequency, SNR and SFDR.
SNR and fs
Some calculations were done on the some of the ADC parameters, mentioned in Chapter 4, at different sampling frequencies, see Equations 6.1 - 6.3. As it is shown, the channel bandwidth is chosen to be 25 kHz which is usually the case in the VHF band[14]. The results of the calculations can be seen in table 6.1.
The ADC resolution is defined as the number of bits at its output, i.e. the size of the binary word which represents the sampled analog signal. An alternative definition is the size of the least significant bit (LSB), Equation 4.10. It should be noted that it is not a measure of the conversion quality. There are different error
6.2 Choise of Components 27
sources in an ADC degrading its performance. When all sources are included, the resolution is usually lower than the specified number of bits of the converter[11]. That is why the effective number of bits (ENOB) of an ADC is such an important parameter and represents the noise-free bits.
Some calculations were done on the mentioned ADC parameters at different sampling frequencies, see Equations 6.1 - 6.3. As it is shown, the channel band-width is chosen to be 25 kHz which is usually the case in the VHF band[14]. The results of the calculations can be seen in table 6.1.
SNRreq = 101.5dB (6.1)
BWch = 25kHz (6.2)
SNRideal = SNRreq− 10 log fs/2 BWch (6.3) fs SNR 340 63.2105 380 62.7274 420 62.2928 460 61.8977 500 61.5356
Table 6.1. SNR requirement at different sampling frequencies.
The table above shows that the required values of SNR lessens with increasing
fs, which is a good reason to choose a high fs. Besides, considering the advantages of oversampling that were mentioned in Section 4.7, choosing fs high would help relaxing the requirements on the analog filters and improve the overall SNR.
The chosen architecture includes two interleaved ADC:s, as mentioned earlier. After spending relatively short time searching among the leading manufaturers, it was noted that the 14-bit ADC called ADS5546 from Texas Instruments was best suited for this applicaion. The maximum fsis 190 MHz which means a total
fs of 380 MHz after interleaving. The ideal SNR of this converter is 72.2 dB which is almost 10 dB higher than the required SNR for this fs, also shown in the same table. Some calculations are done in Section 6.3 to show that this ADC, theoretically, fulfills the system requirements mentioned in the previous chapter.
6.2.2
LNA and VGA
When choosing amplifiers for this project the most important parameters are the NF and the OIP3. Due to the inefficient analog filtering in this project it is prefer-able to have as linear components as possible to avoid intermodulation products in the system. Because of this the OIP3 and the 1-dB compression point of the amplifiers must be as high as possible.
As mentioned in Section 4.2 it is extra important that the components nearest to the antenna have low NF because the noise contribution affects the overall noise more in the early stages of the receiver chain. So it is of great importance that the LNA has low NF. As it was shown in Equation 4.5, it is also preferable to have high gain in the LNA or the other parts in the begining of the receiver chain. This makes the noise contribution of the following parts less important due to the division with the gain factor of the previous parts. Because of the differential signaling used in the design, the LNA should have differential input and output.
Finding an LNA with the mentioned characteristics is hard. After evaluating the data sheet of many LNA:s it was decided to use the ADL5330 from Analog Devices. This amplifier is a VGA which gain can be fixed by attaching the control pin to a fix voltage. The level of the fixed gain depends on the voltage level on the control pin. The amplifier has an acceptable NF and a high OIP3. Some properties of the circuit are presented in Table 6.2.
The same amplifier circuit is used for the AGC in this project. As it is presented in Table 6.2 the gain can be adjusted between -34-22 dB. The control signal range is between 0-1.4V which means that if the control signal is 0V the gain of the VGA is -34 dB, and if the control signal is 1.4 V the gain is 22 dB.
Calculations in Section 6.3 shows that this amplifier fulfills the requirements theoretically.
Gain -34 - 22 dB
NF 7.8 dB
OIP3 38 dBm
1dB Compression point 22 dBm Table 6.2. Properties for the VGA.
6.2.3
Analog Filters
BPF1 and BPF2 in Figure 6.1 are two analog BP-filters that are intended to select out the desired band and attenuate the neighbouring undesired bands. The frequency range of interest in this project is required to be 112-174 MHz, which belongs to the VHF-band. This means that the filters should have a passband of 62 MHz with a center frequency of 143 MHz. This passband should not attenuate the test signal at 162 MHz mentined in the test sections. The absence of mixer circuits, i.e. frequency down-conversion, in the receiver makes it very hard to find highly selective filters with such wide passband at such high frequencies with low insertion loss. Insertion loss in a filter is the ratio between the input power and the output power. It is a measure of the power loss in the device. In other words the passband attenuation in the filter.
However, a filter type commonly used in RF applications is surface acoustic wave filter (SAW). Their main properties are that they can be designed physically small providing good out-of-band rejection, broad pass-band and steep transition edges. With these filter characteristics the SAW filter appears to be the right
6.2 Choise of Components 29
choice for this application. But after spending hours and hours searching among manufacturers’ standard products, it was noted that finding a suitable SAW fil-ter is an impossible task due to their extremely high insertion loss. The chosen architecture can not afford this high level of insertion loss, hence with even zero insertion loss in the filters it still is a challenge achieving the required sensitivity of -107 dBm. Some manufaturers have the possibility of building customized filters but for a cost that is over budget in this thesis project.
After considering the facts and the given options it was decided to build the filters as passive bandpass filters with discrete components. A filter with the mentioned characteristics require high filter order. The higher the filter order the more discrete components are required. So a decision was made to loosen the requirements to be able to build low-order filters with a few components. It should be noted that with more time and higher budget the filters could be built much better, but for now passive low-order filters will do.
The first bandpass filter is a second order LC-filter with only one inductor and one capacitor, see Figure 6.2. The second filter is a fourth order LC-filter, as shown in Figure 6.3. An advantage of the implemented filters are that they have no insertion loss.
Zi=50 Ohm C L Ro=50 Ohm
Figure 6.2. BPF1 - 1st order bandpass filter.
Zi=50 Ohm Ro=50 Ohm
C2 L2
C1 L1
Figure 6.3. BPF2 - 2nd order bandpass filter.
As it is shown in the figures above both analog filters have 50 Ω impedance on both input and output. This depends on the output and input impedances of the components attached before and after the filters. In order to get the impedances matched it is necessary to choose the component values so that the resonance frequency of the filter circuits is equal to the desired signal frequency. Impedance matching between components is very important in order to avoid reflections in
the signal path. The resonance frequncy is easily calculated in both these cases, see equations 6.4[16].
Zi= Ro+ 1
jωC+ jωL (6.4)
The impedance is matched if Zi = Ro. In order to make this happen the component values must be chosen so that jωC1 + jωL = 0. This leads to equation 6.6 which is used for calculating the resonance frequency of the filter, which in this case means the least filtered frequency.
The chosen component values, see table 6.3 give an overall bandwidth of about 60 MHz with a center frequency around 160 MHz, which suits this project hence the required test signal is situated at 162 MHz. A frequency analysis was done in Protel on the two filters, which frequency responce can be seen in Figure 6.4.
75.00MHz 100.0MHz 125.0MHz 150.0MHz 175.0MHz 200.0MHz 225.0MHz 250.0MHz 275.0MHz 300.0MHz 0.000 dB -2.500 dB -5.00 dB -7.50 dB -10.00 dB -12.50 dB -15.00 dB Amplitude [dB] Frequency [MHz]
Figure 6.4. BPF1 - 1st order bandpass filter.
ω=√1
LC (6.5)
f = 1
6.2 Choise of Components 31
Filter Component Value
BPF1 C 100pF L 10nH BPF2 C1 100pF L1 10nH C2 100pF L2 10nH
Table 6.3. Component values for the analog bandpass filters.
6.2.4
FPGA
As shown in Figure 6.1 the digitalized signal from the ADC:s is fed through to an FPGA where the data is processed. The first PCB does not include the FPGA. Instead the front-end PCB is attached to a development board which includes a Virtex 4 FPGA from Xilinx. On the second board the front-end and the FPGA are placed on the same PCB. This time the Virtex 5 from Xilinx was used. These FPGAs can be programmed in two ways. One way is to directly program it via a JTAG-connection from the PC. This way the program is erased when the power is switched off and the FPGA must be reprogrammed at power on. The second way is to use the flash memory placed on-board. By programming the flash the FPGA can reprogram itself everytime the power is switched on.
After the FPGA the processed data is sent to a PC where the data is de-coded. For transmitting and receiving data to and from the PC a UART-interface was implemented in the FPGA. In the PC however the USB port was chosen as communication link. This means that a USB-to-UART converter is needed. The converter used is presented in the next section.
6.2.5
USB-to-UART Interface
For converting the FPGA:s UART-signals to the PC:s USB-signals and vice versa a converter from FTDI called FT232R was used. In the case of the first PCB this converter is built-in in a cable that is used for the communication between the development board and a PC. In the second case the converter is built-in in a chip which is placed directly on the PCB between the FPGA and a type B USB-port. According to the data sheet of FT232R it can handle up to 3 Mbits/s.
6.2.6
DAC
As mentioned above the chosen VGA has an analog control signal input. So the digital control signals from the FPGA must be converted to an analog signal with a digital-to-analog converter (DAC), as shown in figure 6.1. For this task a DAC called AD7302 from Analog Devices was chosen. It has a parallel 8-bit input and an output voltage range of 5V, which means that the output changes by steps of
settings. So only 7 bits of the DAC are needed, thus 26 = 64 is too few and 28= 256 is too much.
6.2.7
Crystal Oscillator and Clock Buffer
The ADCs need to have a clock signal that determines the sampling frequency. As mentioned in the ADC section the decided sampling frequency in this project is 380 MHz. This means that the interleaved ADCs have an fsof 190 MHz each. On the first board the clock signal is provided from an external signal generator. The generator provides a 380 MHz signal which gets divided into two 190 MHz clock signals by a clock buffer called CDCP1803 from Texas Instruments. The divided clock signal is then distributed to the ADC:s.
On the second board the signal is generated from a crystal oscillator which provides a 380 MHz signal. The oscillator is a Si530 from SiLab. In the same way as the first board the signal from the oscillator is divided into two 190 MHz signals in a clock buffer.
6.2.8
Linear Voltage Regulators
There are two different supply levels used on the first board and four different levels on the second. The first board contains 3.3V digital, 3.3V analog and 5V analog supply. The second board contains 1V digital, 2.5V digital, 3.3V digital, 3.3V analog and 5V analog supply.
The reason of why the digital and the analog supplys are split up will be explaind in Section 6.4. For the supply management some linear voltage regulators from Texas Instruments and Maxim are used. See Table 6.4 for the first board and Table 6.5 for the second. The TPS786xx is from Texas Instruments and has a maximum output current of 1.5A and the MAX8869 has a maximum output current of 1A. As it can be seen in the Tables 6.4 and 6.5 the amount of current that needs to be supplied is kept under the maximum limit on all regulators.
Regulator Component Quantity Supply Current(mA)
TPS78601 DAC 1 5 (Analog, 5V) VGA 2 215 Sum 435 TPS78633 ADC 2 300 (Analog, 3.3V) Sum 600 TPS78633 ADC 2 51 (Digital, 3.3V) Clk buffer 1 140 Sum 242 Sum(tot.) 1277
6.2 Choise of Components 33
Regulator Component Quantity Supply Current(mA)
TPS78601 DAC 1 5 (Analog, 5V) VGA 2 215 Sum 435 TPS78633 ADC 2 300 (Analog, 3.3V) Sum 600 TPS78633 ADC 2 51 (Digital, 3.3V) FPGA(I/O) 1 10 Crystal Osc. 1 100 Clk buffer 1 140 Flash 1 20 FTDI 1 100 Linear reg.(1A) 1 0.5 Sum 473 TPS78625 AFPGA(Aux) 1 73 (Digital, 2.5V) FPGA(I/O) 1 325 Sum 398 MAX8869 FPGA(Core) 1 500 (Digital, 1V) Sum 500 Sum(tot.) 2406
6.3
Theoretical Calculations
In this section some theoretical calculations are done to show that the chosen com-ponents fulfill the SNR and the third-order intermodulation requirements, hence these are the main requirements in this project.
6.3.1
SNR
In this section the two most crucial cases are studied, i.e. the sensitivity test and the intermodulation/blocking test.
Calculating the overall SNR of the receiver in dBFS can be done as follows:
Vnoisetotal = VnoiseADC 2+ V noisein 2 (6.7) SNRtot = 20 log VF SADC Vnoisetotal + Process Gain (6.8)
Vnoisetotal[21]is the total noise voltage of the system including the noise voltage at the ADC input and the noise voltage contributed by the ADC itself. the noise VF SADC in the equation above is the rms value of the full-scale (FS) signal of the
ADC, which is derived by using Equation 6.9. The noise in the ADC is independent of the input signal and will be the same value in both tests. The rms value of the ADC’s noise voltage is calculated as shown below[6]:
VF SADC = Vp−pADC 2√2 = 2 2√2 = 1 √ 2V (6.9) VnoiseADC2 = VF SADC· 10 −SNRADC 20 2 = 2 2√2 · 10 −72.2 20 2 ≈ 3.013 · 10−8V2
This value is used in the secitons below for calculating the overall noise in the receiver in both test environments.
Intermodulation and Blocking
As mentioned in the requirements, the receiver must be able to operate despite interference with unwanted signals. In section 5.5 it was explained that the level caused by the interference can get as high as -11.5 dBm. This level limits the maximum allowed amplification in the receiver. The ADCs have a specified input voltage range which sets the limit of the maximum allowed signal level. If the amplified signal passes this limit the ADC will be saturated. The chosen ADC has an input voltage range of 2V which gives a full-scale signal at 10 dBm. This gives a maximum allowed gain of 10− (−11.5) = 21.5 dB for this test. By using equation 4.5 together with the given maximum gain and the given amplifier NFs, the rms value of the total noise voltage at the ADCs input can be calculated. The total
6.3 Theoretical Calculations 35
NF of the system includes only the specified noise contribution of the amplifiers. Other, unspecified, noise sources are hard to estimate. The SNR calculations are done as follows: Nin,dBm = 10 log Nin= = −174 + 10 log(190MHz) + 20 log(107.820 +10 7.8 20 − 1 1021.520 ) + 21.5 = = −61.4898dBm Vnoisein2 = 10−61.4898/10· 10-3· 50 = 3.548 · 10−8V2 (6.10)
The calculations above give the total noise voltage for the system.
Vnoisetotal =
3.013 · 10−8+ 3.548 · 10−8≈ 2.5614 · 10−4V
Now the overall full-scale SNR of the system can be calculated using Equation 6.8: SNRtot= 20 log 0.7071 2.5614 · 10−4 + 10 log 190MHz 25kHz = 107.6282dBFS
This means that with the chosen components an SNR of 107.6 dBFS can be achieved theoretically, which is more than 6 dB greater than the required SNR of 101.5 dBFS in this test. Theoretically it would be possible to also fulfill the sensitivity requirement with the same amplification thus the required SNR would be 107.5 dBFS. This would mean that the VGA is not needed. But in reality this will not be the case thus the noise contribution of the analog filters and other noise sources are not included in this calculation. The 0.1dB margin is not enough to fulfill the requirement when all noise sources are included.
Sensitivity
In this test there are no other signals present but a weak signal of -107 dBm, thus maximum possible gain can be used. Theoretically, the full-scale SNR needs to be 10dBm - (-107dBm + 44dB) + 12dB = 85dBFS. This is the ratio between the ADC’s full-scale signal and the amplified test signal plus the 12dB required by the decoder. Here follows the SNR calculations that are done similairly as the calculations above:
