An FPGA implementation of a modulator for digital terrestrial television according to the DTMB standard

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Institutionen för systemteknik

Department of Electrical Engineering

Examensarbete

An FPGA implementation of a modulator for

digital terrestrial television according to the DTMB

standard

Examensarbete utfört i elektroniksystem vid Tekniska högskolan i Linköping

av Sebastian Abrahamsson and Markus Råbe LiTH-ISY-EX--10/4378--SE Linköping 2010

Department of Electrical Engineering Linköpings tekniska högskola

Linköpings universitet Linköpings universitet

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An FPGA implementation of a modulator for

digital terrestrial television according to the DTMB

standard

Examensarbete utfört i elektroniksystem

vid Tekniska högskolan i Linköping

av

Sebastian Abrahamsson and

Markus Råbe

LiTH-ISY-EX--10/4378--SE

Handledare: Oscar Gustafsson

ISY, Linköpings universitet

Patrik Sandström

A2B Electronics AB

Examinator: Oscar Gustafsson

ISY, Linköpings universitet

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Avdelning, Institution

Division, Department

Division of Electronic Systems Department of Electrical Engineering Linköpings universitet

SE-581 83 Linköping, Sweden

Datum Date 2010-04-22 Språk Language Svenska/Swedish Engelska/English Rapporttyp Report category Licentiatavhandling Examensarbete C-uppsats D-uppsats Övrig rapport

URL för elektronisk version

http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-55538

ISBN

—

ISRN

LiTH-ISY-EX--10/4378--SE

Serietitel och serienummer

Title of series, numbering

ISSN

—

Titel

Title

FPGA-implementation av en modulator för marksänd digital television enligt DTMB-standarden

An FPGA implementation of a modulator for digital terrestrial television according to the DTMB standard

Författare

Author

Sebastian Abrahamsson and Markus Råbe

Sammanfattning

Abstract

The increasing data rates in digital television networks increase the demands on data capacity of the current transmission channels. Through new standards, the capacity of exisiting channels is increased with new methods of error correction coding and modulation.

This thesis presents the design and implementation of a modulator for trans-mission of digital terrestrial television according to the Chinese DTMB standard. The system is written in VHDL and is intended for implementation on an FPGA.

Nyckelord

Keywords DTMB, DTTB, DMB-T, FPGA, VHDL, OFDM, signal processing, ECC, IDFT, LDPC, BCH, convolutional, frequency interleaving, raised cosine, filter

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Abstract

The increasing data rates in digital television networks increase the demands on data capacity of the current transmission channels. Through new standards, the capacity of exisiting channels is increased with new methods of error correction coding and modulation.

This thesis presents the design and implementation of a modulator for trans-mission of digital terrestrial television according to the Chinese DTMB standard. The system is written in VHDL and is intended for implementation on an FPGA.

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Acknowledgments

We would like to thank A2B Electronics AB for an interesting and challenging thesis work, everybody in Linköping and Motala for their valuable knowledge, inputs and discussion.

Further we would like to thank Oscar Gustafsson at ISY, Linköpings Universitet for being our examiner and Patrik Sandström at A2B Electronics for being our supervisor. Other thanks goes out to Kent Palmkvist and Anton Blad at ISY for help with various topics.

Finally we would to thank our opponents Fredrik Bengtsson and Rikard Berglund for their precise and thorough inspection of our final report and valuable input on our work.

Sebastian Abrahamsson and Markus Råbe, Linköping, March 31st 2010

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5 Results and performance 67 5.1 Scrambler . . . 67 5.2 BCH encoder . . . 68 5.3 LDPC encoder . . . 69 5.4 QAM mapper . . . 70 5.5 Convolutional interleaver . . . 70 5.6 Frequency interleaver . . . 71 5.7 IDFT . . . 72 5.8 Header generation . . . 72 5.9 SRRC filter . . . 73 5.10 Complete system . . . 74 5.10.1 Precision . . . 74

5.10.2 Resource utilization and performance . . . 74

5.11 Implementation of two DTMB modulators on one FPGA . . . 77

5.11.1 LDPC encoder . . . 78 5.11.2 Convolutional interleaver . . . 78 5.11.3 Frequency interleaver . . . 78 5.11.4 IDFT . . . 79 5.11.5 SRRC filter . . . 79 5.11.6 Conclusion . . . 79

6 Summary, conclusions and future work 81 6.1 Future work . . . 81

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List of Figures

1.1 One way communication situation . . . 5

1.2 The context in which the intended system implementation is situated 6 1.3 System design flow . . . 11

2.1 Digital QAM modulation . . . 16

2.2 A 16-QAM constellation . . . 18

2.3 A demodulated noisy QAM signal. . . 19

2.4 Example of a linear feedback shift register . . . 23

2.5 A typical system for transmitting digital information . . . 24

3.1 Overview of a DTMB transmitter . . . 26

3.2 Convolutional interleaver . . . 29

3.3 A 4-QAM constellation used in the DTMB standard . . . 30

3.4 Frequency interleaving scheme . . . 31

3.5 Ideal impulse response of the desired filter . . . 33

4.1 System overview . . . 40

4.2 Data transfer interface . . . 41

4.3 Overview of the implemented scrambler . . . 42

4.4 Overview of the implemented BCH encoder . . . 43

4.5 Overview of an LDPC submodule . . . 44

4.6 Overview of the implemented LDPC encoder . . . 46

4.7 Overview of the implemented QAM mapper . . . 47

4.8 Memory allocation for the convolutional interleaver . . . 50

4.9 Overview of the implemented convolutional interleaver . . . 51

4.10 Overview of the implemented frequency interleaver . . . 53

4.11 Overview of the implemented IDFT . . . 56

4.12 Overview of the implemented header generation unit . . . 57

4.13 Magnitude response of the 124th order SRRC1 _FIR2 _{filter . . . . .} ₆₁

4.14 Magnitude response of the 62nd order SRRC FIR filter . . . 61

4.15 Round off noise power spectrum of the 62nd order SRRC FIR filter 62 4.16 Second order section . . . 63

4.17 Magnitude response of the 12th order IIR filter . . . 63

4.18 Round off noise in the cascaded second order section filter . . . 64

4.19 Second order section with noiseshaping . . . 64

4.20 Group delay of the quantized IIR filter . . . 65

4.21 Overview of the filter implementation . . . 66

5.1 Resource usage per sub system . . . 76

5.2 Total resource usage . . . 77

1_{Square Root Raised Cosine} 2_{Finite Impulse Response}

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2 Contents

0.1 Abbreviations

ASIC Application Specific Integrated Circuit

BER Bit Error Rate

BCH Bose Chaudhuri Hocquenghem error correction code

BRAM Block RAM

DAC Digital to Analog Converter

DTMB Digital Television Terrestrial Broadcasting System

FEC Forward Error Correction

FIFO First In First Out

FIR Finite Impulse Response

FPGA Field Programmable Gate Array

FSM Finite State Machine

ICI Inter Channel Interference

IDFT Inverse Discrete Fourier Transform

IFFT Inverse Fast Fourier Transform

IIR Infinite Impulse Response

IP Intellectual Property

ISI Inter Symbol Interference

LFSR Linear Feedback Shift Register

LDPC Low Density Parity Check error correction code

LUT Lookup Table

MAC Multiply and Accumulate

MCB Memory Controller Block

QC-LDPC Quasi Cyclic Low Density Parity Check error correction code OFDM Orthogonal Frequency Division Multiplex

PRBS Pseudo Random Binary Sequence

N-QAM Nary Quadrature Amplitude Modulation

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0.1 Abbreviations 3

QAM Quadrature Amplitude Modulation

RAM Random Access Memory

ROM Read Only Memory

SER Symbol Error Rate

SRRC Square Root Raised Cosine

TDS Time Domain Synchronous

SNR Signal to Noise Ratio

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Chapter 1

Introduction

This chapter presents the purpose and method of the thesis. The concept of digital television along with some common standards are also presented.

1.1 Purpose

The purpose of this thesis is to test and evaluate implementation methods to a modulator for the DTMB standard in programming language VHDL. The role of the modulator is to digitally process the data stream before it is sent over the chan-nel, as illustrated in figure 1.1. Each subsystem in the standard is implemented individually and then put together to form a complete system.

Source

Modulator Channel Demodulator

Sink

Figure 1.1. One way communication situation

A more detailed sketch of the modulator is shown in figure 1.2. The VHDL module which will be implemented is the block named system.

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6 Introduction

Figure 1.2. The context in which the intended system implementation is situated

1.2 Background

The introduction of digital television allows for more data to be sent on the same bandwidth, this extra capacity can either be utilized for sending a higher definition picture, sending more standard definition channels and/or other services such as program information and other kinds of interactivity.

The digital signals are also more robust in terms of channel conditions since they contain error correction and channel compensation abilities compared to ana-log transmission. This results in a better image quality with less noise.

Also, since the modulation and channel coding part is all digitalized, this can be implemented in a single chip or FPGA1. The possibility also exist to include several modulators on one chip, thus reducing hardware costs.

There currently exist a number of standards for transmission of digital televi-sion. These differ by taking into account the properties of the channel type and requirements of the frequency band on which they are transmitted. They compen-sate for these by for example different methods of modulation, data composition and error correction.

The different standards within each channel type have common methods com-pensating for the channel properties. Essentially the only major difference between them is the data packaging, frame composition and pilot insertion.

Below is a set of different standards. [10, 7, 16]

• DVB-T/T2 • DVB-C/C2 • DVB-S/S2 • ATSC • ISDB-T/C/S • DTMB

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1.3 The DTMB standard 7

The different standards are used in different parts of the world, e.g ISDB is used in Japan and South America whilst ATSC is used in North and Central America. [1, 2, 3]

1.3 The DTMB standard

DTMB is a Chinese standard for transmission of digital television, it is also known by several other acronyms, such as DTTB and DMB-T. It was first published in 2006 and was executed in 2007.

1.4 Method

The first part of the work flow was to do a prestudy of the DTMB standard to find possible methods for implementing it’s subsystems. A comparison with different standards is also presented. Then, a model will be implemented for the purpose of complexity estimation, verification, performance and testing.

The second part will be to implement the subsystems. In the cases where complete IP2blocks exist, these will be evaluated with respect to resource demands and performance. Throughout the implementation process, the subsystems will be verified with respect to the MatLab model. The implementation will be considered correct when it matches the implemented system model.

The last part of the thesis is to measure the performance of the system imple-mented on the hardware platform and put together the conclusions we have drawn from the implementation of the modulator.

Figure 1.3 shows the work flow used in the implementation of the different subsystems. The dashed block entitled optimization was not performed for all subsystems. In this stage, one or more subsystems are examined and improved with respect to resource utilization. The three different recursive arrows depict different types of verification, they are performed as follows:

1. Simulation results are compared with the MatLab model. Not correct or unexpected results, go back to the implementation stage.

2. Data is extracted from ChipScope and compared with the MatLab model, if not correct or unexpected results, go back to the implementation stage.

3. After optimization, compare simulation and ChipScope results with the Mat-Lab model. Not correct or unexpected results, go back to the implementation stage.

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8 Introduction

1.5 Delimitations

The thesis will be restricted to discussing and implementing the subsystems used in a DTMB modulator that can implemented on the predetermined FPGA chip Xilinx XC6SLX45T.

The DTMB standard includes three different modes of error correction coding, two modes of time domain interleaving, three different frame header lengths, five different QAM modes and optional OFDM modulation. To reduce the complexity of the modulator, the implementation is therefore chosen to one set of modes, which is the following:

• LDPC code rate of 0.8

• Interleaving mode of B = 52, M = 240 • 64 QAM mode

• Frame header length of 420 bits • OFDM modulation

The possibility of parameterizing the subsystems for other modes will also be investigated.

In the thesis, architectures which have a balance of design time and resource cost will be prioritized over resource optimal solutions.

1.6 Report outline

Chapter 1 is an introduction to the thesis and presents purpose, background,

method, delimitations and also later added definitions and abbreviations used. This chapter also presents the tools and hardware used.

Chapter 2 gives an introduction to and explains various common concepts used

in digital communications. It also presents the related theory behind the dif-ferent digital modulation subsystems, to give an overview and basic knowl-edge of the function these systems.

Chapter 3 presents the DTMB standard and the specifics of the subsystems

which the modulator incorporates.

Chapter 4 presents the system model, implementation and presents the chosen

methods and architectures.

Chapter 5 summarizes the performance of the system, in terms of system

re-sources used, SNR3 _{and data rates. The chapter also contains a discussion}

how to be able to fit multiple modulators on the same FPGA chip.

Chapter 6 contains a summary and conclusions drawn of the implementation.

This chapter also presents possible future work.

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1.7 Tools and hardware 9

1.7 Tools and hardware

Presented in this section are the tools, hardware and concepts used in the imple-mentation of the modulator.

FPGAs

An FPGA4 _{is an integrated circuit, designed to be configured by the customer}

or designer after manufacturing. They are also reconfigurable, meaning that they can realize different systems by uploading a new configuration.

FPGAs consist of slices, or blocks, composed of hardware resources such as flip flops, LUTs, RAM5_{, multipliers, adders and other more complex blocks such as}

PLL6_s.

A LUT7 _{is basically a 2}N _{× 1 ROM}8 _{where N is the number of inputs, which}

is 6 in the targeted FPGA. These can, when interconnected form any type of combinational logic function by programming the ROMs in the LUTs with the proper values. Together with flip flops, they can form sequential logic nets.

To be able to program an FPGA, the logic is most often written in a hardware description language.

HDL - Hardware Description Languages

To realize the desired logic functions to be programmed to the FPGA, these are first captured in a hardware description language. These differ from normal pro-gramming languages by being parallel instead of sequential. They have a syntax which captures the nature of the hardware by enabling parallelism through various special commands and structures.

The purpose of these languages is to capture the hardware model of the desired system to be implemented. In a sense, HDL are not true programming languages, as they describe hardware structures instead of software.

When compiling an HDL design, it is said to be synthesized, as it is a more accurate description of the process.

Two common hardware description languages are Verilog and VHDL, of which the latter is used in this system implementation.

Hardware

The FPGA targeted for the implementation of the Xilinx XC6SLX45T.

The hardware used for verification and testing purposes were the Xilinx SP601 and SP605 evaluation boards. The latter has the XC6SLX45T chip and was used to test and verify larger blocks and system extents. The SP601 board contained

4_{Field Programmable Gate Array} 5_{Random Access Memory} 6_{Phase Locked Loop} 7_{Lookup Table} 8_{Read Only Memory}

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10 Introduction

the XC6SLX16 chip. This FPGA could not fit the entire system and was therefore only used to test the memory controller interface in the convolutional interleaver.

Xilinx ISE Webpack

ISE is a free development environment for FPGA implementations using HDL languages. It was used for generating and synthesizing VHDL code. The program is produced by Xilinx and is intended for use with their FPGAs. It also contains the Xilinx CORE generator which is used to generate common pre built blocks.

ModelSim

Modelsim is a program developed by Mentor Graphics for simulation and debug-ging of HDL code. Simulations of the hardware created in ISE Webpack were performed in Modelsim.

Xilinx ChipScope

ChipScope is a software tool from Xilinx used to debug and verify designs. Through a cable connected from the FPGA to a computer, it can be used to input and record signals in the design much like a logic analyzer scope. The communication to the FPGA requires modules to be inserted in the design.

This tool was used to test designs in hardware after they were simulated with ModelSim, to verify that the synthesized HDL code gave the desired result.

MatLab

MatLab is a mathematics processing tool created by the Mathworks Inc. This program was used to process data from Modelsim simulations and compare the data with the output from a model created in Simulink.

Simulink is an addon to MatLab and is also created by the Mathworks Inc. Simulink provides a graphical user interface and a set of preconfigured blocks for model based simulation for various kinds of systems. MatLab was used to create models of the various subsystems implemented. These models are then used to verify the hardware created in ISE Webpack and simulated using Modelsim. The implemented models were compared with the models to measure the performance in terms of SNR and errors.

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1.7 Tools and hardware 11

Prestudy

Modeling

Implementation

Simulation with ModelSim

Synthesis and verification with ChipScope

Performance measurement

Optimization

1.

2.

3. Iterated for each subsystem

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Chapter 2

Related theory

This chapter gives a brief introduction to digital communication and introduces various concepts used in this thesis. The concepts will mostly be viewed from the position of the transmitting side. The goal is not to give a complete understanding of the topics covered in section but is rather intended as a general introduction and orientation for the reader.

2.1 Digital communication

Digital communication refers to the transfer of digitally encoded information, this information is then modulated and transmitted over an arbitrary analog channel. These channels can for example be electric cables, wireless radio channels, or fiber optic cables.

2.2 Transmission channels

This section presents three different channel mediums and introduces some general telecommunication concepts.

2.2.1 Cable

Electrical cables are a common means of transmitting information over reasonably long distances. They often offer good transmission properties compared to other types of channels in terms of SNR1 _{and other signal degrading phenomenon.}

These cables typically attenuate the transmitted signal according to some fre-quency response derived from the cables properties. This response is however non-random and can be measured and compensated for by implementing filters on the receiving and transmitting end of the channel.

1_{Signal to Noise Ratio}

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14 Related theory

The major disadvantage with cable transmission is the lack of mobility. To be able to receive or transmit a signal via a cable, a user has to physically attach the transmitting or receiving device to a cable network of some kind.

2.2.2 Radio

There are basically two types of radio channels. There is the directed satellite uplink and there is the non-directed traditional radio transmission. The latter is in digital television referred to as terrestrial transmission. Satellite uplinks will be discussed in section 2.2.3.

Terrestrial (radio) transmission gives the advantage of mobility but has some drawbacks, of which one is the fading phenomenon. Please note that the fading phenomenon is not essentially the same as ISI discussed in section 2.3.5.

Fading is caused by multiple reflections of the signal which reach the receiver with different phase. If the phase of the different reflections are such that they cancel each other, the power of the received signal will drop. This is a random phenomenon and it is impossible or difficult to predict the exact properties of the fading of the current channel. [5]

Therefore, different compensation methods, such as OFDM2_and/or

interleav-ing are employed to reduce the effects of the fadinterleav-ing.

2.2.3 Satellite

Another type of radio transmission is the directed satellite uplink. The typical satellite transmission situation consist of a stationary satellite dish, directed at the location of the transmitting satellite. The dish focuses the received radio waves at a receiver to improve the received signal. The receiver is much less likely to pick up reflections of the transmitted signal, because both the transmission and the receiving are directional. This gives this type of channel a certain resistance to fading. [5]

Since the satellite channels operate at very long distances compared to terres-trial or cable transmission, the SNR of the signal will be low. Therefore, simpler modulation schemes and larger error correction codes are employed to facilitate good transmission. [9]

2.2.4 Noise

Since the digital information will be transmitted over some type of analog channel, there always exists some kind of noise.

The definition of noise in this context is any information which is not desired, that is anything other than the transmitted signal is regarded as noise. The most common type is thermal noise, generated by electronic circuits. This noise is additive, which means the noise’s amplitude is added to the transmitted signal. This noise is usually unavoidable, since wherever there is electronic circuits, there

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2.3 Digital modulation 15

is thermal noise. Any design of a transmission system must cope with this type of noise.

There also exist some other kinds of noise such as interferent noise. This is usually man made, i.e. it is generated by some adjacent frequency bands or by the current channel itself, by for example reflections. The noise is usually dealt with by filtering out the undesired frequency bands. [5]

2.2.5 Signal to noise ratio

SNR is the ratio between the signal power and the noise power, as defined in equation 2.1. SN R = 10 log10  Psignal Pnoise [dB] (2.1)

This quantity is perhaps the most important one in transmission of digital infor-mation. It determines, together with the bandwidth of the current channel, how much information that is possible to be sent (error free) over the channel. This is discussed in section 2.2.6.

Increasing the SNR means that it is less likely to be errors in the received signal. SNR determines the SER3_{and BER}4 _{as presented in section 2.3.3.}

2.2.6 The Shannon limit

The Shannon limit gives a theoretical upper limit of the capacity of a channel, given the SNR and the bandwidth of the channel.

This upper limit, C, is measured in bits_sec. B is the bandwidth in hertz, Psignal

and Pnoise is the power of the signal and the noise, respectively. C is calculated

as in equation 2.2. [15] C = B log2 1 + Psignal Pnoise (2.2)

2.3 Digital modulation

Digital modulation is the means to apply a digital modulation scheme to digi-tal information. This section describes some common techniques used in digidigi-tal modulation.

2.3.1 Quadrature amplitude modulation

Quadrature amplitude modulation (QAM) is a two dimensional modulation scheme, and can be formulated as sending the signal in equation 2.3.

s(t) = I(t) cos(ωct) + Q(t) sin(ωct) (2.3)

3_{Symbol Error Rate} 4_{Bit Error Rate}

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I(t) is referred to as the In phase component and Q(t) the Quadrature

com-ponent. As quadrature amplitude modulation is a two dimensional modulation scheme, it can then be illustrated in a two dimensional space.

If the quadrature modulated signal is described as the complex envelope in equation 2.4, the signal can be illustrated in the complex space where I(t) rep-resents the real axis and Q(t) reprep-resents the imaginary axis. This space will henceforth be referred to as the IQ space. [5]

eit= cos(t) + i sin(t) (2.4)

Quadrature amplitude modulation is the way of modulating the amplitude of the carrier waves, i.e, the real part and imaginary part of the complex envelope. Different amplitudes of the two carrier waves will generate different coordinates in the IQ space.

Figure 2.1 depicts a simple block diagram of a QAM modulator. m[k] is the message signal to be sent. It is then mapped into two different data streams which are the I and Q components. More about how the data stream is mapped is explained in section 2.3.2. H[z] are pulse shaping filters to reduce the ISI5. ISI is described in section 2.3.5.

The data is then passed to the DACs and upconverted by multiplying with the two carrier waves. The carrier waves are then added together to form the modulated RF signal. [5] QAM mapping H[z] H[z] DAC DAC × cos(ωct) × sin(ωct) + m[k] I[k] Q[k] s(t) Analog domain Digital domain

Figure 2.1. Digital QAM modulation

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2.3 Digital modulation 17

2.3.2 Symbol constellations

An information symbol denotes a coordinate in the IQ space. Due to the nature of digital information, the information to be sent will be divided into a finite set of binary information vectors.

To translate an input vector into a symbol, an input bit vector is mapped into a complex number represented by a real and an imaginary bit vector. In other words it performs the function fQAM specified in equation 2.5.

fQAM(vin) = vreal+ vimaginary (2.5)

vinis the input bit vector and vreal and vimaginary are the output bit vectors.

fQAM is specified by the application in which it is used.

A set of information symbols is said to be a symbol constellation . The symbols in the constellation are arranged in the IQ space according to the given modulation scheme. N-QAM6 refers to a set of N symbols with different coordinates in the IQ space corresponding to the QAM pattern to be used.

In digital modulation, when sending the modulated signal s(t) as in equation 2.3, binary information vectors are mapped to the different symbols in the constel-lation. The number of information bits b to be mapped to each symbol is limited by the number of symbols in the constellation, N , according to equation 2.6.

b = blog₂N c (2.6)

The number of symbols in a constellation is not always chosen to be a power of two.

Figure 2.2 displays an example of a 16-QAM constellation with information vector mapping.

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18 Related theory −8 −6 −4 −2 0 2 4 6 8 −8 −6 −4 −2 0 2 4 6 8 1000 1001 1011 1010 1000 1101 1111 1110 0100 0101 0111 0110 0000 0001 0011 0010 I Q

Figure 2.2. A 16-QAM constellation

2.3.3 Symbol error probability

As discussed in section 2.3.2, the information vectors are situated in the IQ space according to a scheme corresponding to the current type of modulation. As pre-sented in section 2.2.4 there is always some kind of noise present in the information channels. There will therefore be errors in the symbols on the receiver end of the channel.

As there are two carrier waves present, the additive thermal noise will super-impose on both carriers. This can be seen as a two dimensional additive noise which causes the received symbol to drift away from the presumed sent location in the IQ space. The lower the SNR, the farther away the received symbol will be from the sent one. The higher the SNR, the closer the received symbol will be to the sent one. Figure 2.3 gives an example of a nosiy received signal.

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2.3 Digital modulation 19 −8 −6 −4 −2 0 2 4 6 8 −5 0 5 I Q

Figure 2.3. A demodulated noisy QAM signal.

An error occurs in the receiver when a sent symbol drifts to close to another symbol point in the constellation. This causes the receiver to wrongly interpret that symbol as the adjacent one. The probability that this will happen is often hard to calculate exactly because of the relatively large number of points in a con-stellation. Several methods exist with which yield accurate approximations. The one which is used here is called the nearest neighbour method and is a pessimistic method, i.e,. it over estimates the symbol error probability. [5]

Symbol error probability for QAM modulation is estimated in equation 2.7. [13] Ps≈ 4 1 − √1 M Q s 3Es (M − 1)N0 ! (2.7)

Q is defined as in equation 2.8, in other words the tail of the Gaussian

distri-bution function. M is the number of symbols used in the constellation. Es the

energy per symbol transmitted, and N0is the noise power.

Q(t) = √1 2π ∞ Z t e−x22 dx (2.8)

The Q function is rapidly decaying, which means that for reasonably high SNR values, the probability that a symbol will drift longer than to the adjacent symbol will be very low. The information vectors corresponding to the symbols are also

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gray coded, which means that only one bit differ between adjacent symbols. This yields that the SER will essentially be the same as the BER, i.e, one symbol error only causes one bit error.

BER is calculated as in equation 2.9 where fs is the symbol rate measured in symbols

second, Pe is the symbol error probability.

There also exist larger QAM constellations. However, the larger the number of constellation points, the higher the error probability since the distance between two adjacent symbols decreases. The larger number of points allows for a greater number of bits to be transferred per symbol as stated in equation 2.6. The larger constellations are therefore generally only used in channel types with good prop-erties such as cable transmission. [5, 10]

BER = Pefs (2.9)

2.3.4 OFDM modulation

OFDM uses the principle of a large number of densely packed carriers. When used together with QAM, each carrier will have its own IQ space, effectively dividing the data stream onto all the carriers. Each symbol within a frame will then have its own carrier frequency. A frame is a set of symbols, equivalent to the length of the IDFT. [5]

To generate the carriers, i.e, transform the data from the frequency to the time domain, an IDFT7_{is applied to a frame of complex QAM}8_{symbols. The output of}

the IDFT is then sent serially to the DACs. The real part is then used to modulate the amplitude of the in phase component and the imaginary part the quadrature component.

Some of the advantages of OFDM are: [11, 5]

• High spectral efficiency

• Simple digital implementation by using the FFT algorithm

• Robustness against ISI and ICI9_{together with the use of guard intervals}

Some of the disadvantages are:

• High peak to average power ratio which require linear amplifiers • Loss in spectral efficiency due to the use of guard intervals • Frequency and time synchronization required

7_{Inverse Discrete Fourier Transform} 8_{Quadrature Amplitude Modulation} 9_{Inter Channel Interference}

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2.4 Forward error correcting codes 21

2.3.5 Intersymbol interference

ISI is a form of distortion where the current symbol is interfered by previous symbols sent over the channel, this is unwanted since the previous symbols act as noise on top of the desired one.

One cause of this is the band limitation of the channel which cuts of higher frequency components and causes the sent symbol to be "smoothed" and interfere with subsequent symbols.

Another cause of ISI is multi path propagation, which occurs when different versions of the signal arrive at different times, i.e. out of phase. This happens when the signal is reflected from for example buildings.

To reduce ISI, the rate at which the symbols are sent can be decreased. If the rate is decreased, the time intervals between the symbols are increased and there is less chance of the symbols interfering with one another. According to the Nyquist rate theorem in equation 2.10, the symbol frequency fsshould be less than twice

the bandwidth B of the channel as stated in equation 2.10.

fs=

1

Ts

< 2B (2.10)

Another solution to combat ISI is the use of pulse shaping filters which gives the symbols such a shape that they will interfere less with each other.

Practically, it is often ISI which causes the main difficulties for system design-ers. [5, 4]

2.4 Forward error correcting codes

A codeword is in this document defined as in equation 2.11.

¯

C = (c0c1 . . . cn−1) (2.11)

ci ∈ (0, 1)

The codeword contains k information bits and n−k parity bits. In other words, a codeword is a binary vector of length n.

The information most often used to define the properties of a certain type of error correction code is n and k. A code is said to be (n, k) or (n, k, d), where

d is the minimum distance between the codewords in the set of codewords

corre-sponding to the error correction code used. The notation in this document will be (n, k). [5]

The minimum distance is determined from the set of codewords used by the error correction code. This set is determined by the generator matrix as described in equation 2.14. The weight of a codeword is the number of ones it contains, the minimum distance can then be calculated by finding the minimum difference of weights between any two codewords.

The minimum distance d give the code the following properties according to equations 2.12 and 2.13. v is the number of errors that the code can detect and t is the number of errors that the code can correct in a received codeword. [5]

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22 Related theory v = d − 1 (2.12) t = d − 1 2 (2.13)

To generate codewords, a generator matrix G is used. A codeword is gener-ated according to equation 2.14 where G is the generator matrix and ¯m is the

information vector. [5]

¯

c = ¯m · G (2.14)

The output of the matrix multiplication will therefore be both the k information bits and the n − k parity bits. The output codeword will therefore be of length n. The generator matrix has k rows and n − k columns. [5]

2.5 Interleaving

Interleaving is used to combat frequency and time dependent channel errors. In-terleaving is divided into two categories, time and frequency based.

2.5.1 Frequency interleaving

Frequency interleaving is applied to a single frame before it is passed to the IDFT of an OFDM system. The interleaving process spreads the symbols across the frame to combat the frequency dependent channel errors. This can be done by different methods, commonly defined as in equation 2.15, where X is the input frame and Y the output frame. They contain the symbols to be sent via the channel.

Frequency interleaving is only applicable when OFDM modulation is used, since OFDM transforms the data from the frequency domain to the time domain. Before the IDFT, the data can be viewed as being in the frequency domain.

Y [f1(n)] = X[f2(n)] (2.15)

2.5.2 Time interleaving

Time interleaving may be used together with frequency interleaving and be per-formed before or after. In time interleaving, the symbols sent are spread among many different frames. This is done to reduce the effect of burst errors.

In other words, the interleaving process spreads the errors across different frames and inside frames and reduces the number of errors inside codewords due to channel errors. This benefits the error control coding. Because, as discussed in section 2.4, there is a limit to how many errors an error correction code can correct and detect, given certain code parameters. If the number of errors inside a received codeword is reduced below the threshold in 2.13, the decoded data will be error free. [5]

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2.6 Scrambling 23

2.6 Scrambling

Scramblers are widely used in digital communication systems. The function of the scrambler is to invert the data according to the ones in a PRBS10. The PRBS can be stored in a ROM, but it is more commonly generated by an LFSR11_{. The}

LFSR contains a set of flip flops interconnected with XOR12 _{gates. The sequence}

is then pre-determined by where the XOR gates are inserted and the number and initial state of the flip flops. [17]

The initial state is first loaded into the flip flops, the output of the scrambler is then generated by XORing the output of the LFSR with the input sequence. The result will be that the input sequence is inverted according to the sequence of ones in the PRBS as in equation 2.16 and 2.17. [5]

a ⊕ 1 = ¯a (2.16)

a ⊕ 0 = a (2.17)

Figure 2.4 shows an example of an LFSR with the generator polynomial G(x) = 1 + x3+ x5.

A generator polynomial defines the way the sequence is generated, which in this context is the interconnections between XOR gates and flip flops.

Figure 2.4. Example of a linear feedback shift register

The scrambler will in other words generate a more random sequence of zeros and ones from the input. This is done to eliminate long sequences of ones or zeros, making the frequency spectrum of the transmitted signal to have a more Gaussian distribution and independent of the data transmitted.

However, the scrambler does not guarantee that long sequences of ones or zeros will not occur, but it is much less likely.

2.7 A generic OFDM based transmitter

This section presents a general transmitter. Various standards contain more or less processing steps, but the ones presented here are common in most systems.

Figure 2.5 describes a simple generic digital modulator with OFDM modulated QAM.

10_{Pseudo Random Binary Sequence} 11_{Linear Feedback Shift Register} 12_{Exclusive Or}

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Data input Scrambling

Forward error correction QAM mapping Time- and/or frequency interleaving IDFT Digital filtering DACs and upconversion Transmission channel

Figure 2.5. A typical system for transmitting digital information

Note that the different blocks doesn’t necessarily come in this order and not all standards use the same blocks.

First the stream of data is passed through a scrambler. The data stream is then divided into message words and error correction codes are applied to the message words. Headers are then inserted to facilitate channel estimation and synchronization. The headers contain system information to give the receiver the modulation properties of the signal to ease demodulation.

The information sequence is then passed through a QAM mapper which divides the data in small segment and maps it onto complex QAM symbols. These symbols are then passed to the interleaving step.

After the interleaving, the frames now consisting of complex symbols are passed to the IDFT step which generates the large number of carriers used in OFDM. The output from the IDFT is then sent serially to the two DACs, one each for the real and imaginary part. The analog signal is then amplified and transmitted over the desired channel. [5, 10, 7, 16]

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Chapter 3

Brief analysis of the DTMB

standard

This chapter presents the characteristics of the transmitting side of the DTMB standard. All information in this chapter is taken directly from [16] unless other-wise stated.

All initial states, constellations and other constants which are referred to in the different sections are listed in the DTMB standard document and are therefore not displayed in this thesis.

3.1 Introduction

The DTMB standard is a standard for transmission of digital terrestrial television. It incorporates the properties of the data format and data rate, error coding, QAM1 _{modes and mapping, interleaving modes, header generation, IDFT}2 _size

and pulse shaping filter. It also specifies the combinations of different QAM modes, error correction codes and data rates which are valid.

3.2 Definitions

The following definitions are used in this chapter and represents different data composition stages.

Frame body: A vector consisting of 3744 QAM modulated symbols.

Frame: A vector of 3780 symbols consisting of 3744 data symbols and 36 system

information symbols.

Signal frame: A frame with a header added in front.

1_{Quadrature Amplitude Modulation} 2_{Inverse Discrete Fourier Transform}

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26 Brief analysis of the DTMB standard

3.3 Overview

Figure 3.1 presents an overview of the transmitter side of the DTMB standard.

Figure 3.1. Overview of a DTMB transmitter

The properties of the different processing steps will be presented and analyzed in the following sections. The block which is called "Frame Body Data Processing" is a 3780 point IDFT and is described in section 3.8. The block "Baseband Post Processing" contains a filter which will be presented in section 3.10.

Figure 3.1 is taken from the DTMB standard document.

3.4 Scrambler

The scrambler uses the generator polynomial in equation 3.1.

G(x) = 1 + x14+ x15 (3.1) This polynomial indicates that the outputs of the 14th and 15th stage in the shift register are XORed to form the feedback and output of the LFSR. The exact specified LFSR can be seen in the DTMB standard.

3.5 Forward error correction

The error correction in DTMB uses two types of error correction codes. The one applied first to the inner data packets is a BCH3_{code and the one applied to the}

outer packets (frames) is an LDPC4 _code.

3.5.1 BCH encoding

The BCH encoding uses a (1023, 1013) encoder to derive a (762, 752) code. 261 zeros are first sent to the encoder, then the 752 data bits. The first 261 zeros from the output are then discarded to obtain the 762 bit codeword.

However, simulations verify that this procedure doesn’t have to be performed. The output of the BCH encoder was the same without inserting and discarding

3_{Bose Chaudhuri Hocquenghem error correction code} 4_{Low Density Parity Check error correction code}

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3.5 Forward error correction 27

the 261 zeros, and instead resetting the flip flops, reducing the delay between computations.

The properties of the BCH code are such that it will yield a simple hardware implementation as will be discussed in chapter 4. [12]

3.5.2 LDPC encoding

The LDPC code used in the DTMB standard is a class of LDPC codes known as QC-LDPC5.

The generator matrix of this code is made up of submatrices called circulants. A circulant is a matrix whose rows is a rightward cyclic shift of the previous one. If the rows are cyclic shifts, then it follows that all columns also are cyclic shifts as shown in equation 3.4. These circulants are then defined by providing either the first row or the first column. In the DTMB standard, they are defined by providing the first row gi,j of the circulant Gi,jas in equations 3.3 and 3.4. [14, 16]

The generator matrix of the DTMB standard has the structure as presented in equation 3.2. G =      G0,0 G0,1 G0,c−1 I O . . . O G1,0 G1,1 G1,c−1 O I . . . O .. . ... Gi,j ... ... . .. O Gk−1,0 Gk−1,1 Gk−1,c−1 O O . . . I      (3.2)

Gi,j is a circulant matrix of size 127 × 127, I is an 127 × 127 identity matrix and O is a 127 × 127 zero matrix.

c and k in equation 3.2 are determined by the code rate used as shown below.

1. (7488, 3008) with a code rate of 0.4, takes four BCH codewords. k = 24,

c = 35

2. (7488, 4512) with a code rate of 0.6, takes six BCH codewords. k = 36,

c = 23

3. (7488, 6096) with a code rate of 0.8, takes eight BCH codewords. k = 48,

c = 11

The code rate is the ratio between the length of the codeword in and out of the encoder. For example, a code rate of 0.5 means that for one information bit there is one parity in the output codeword.

gi,j= ub−1 ub−2 . . . u1 u0 (3.3) Gi,j=      ub−1 ub−2 . . . u1 u0 u0 ub−1 . . . u2 u1 .. . ... . .. ... ... ub−2 ub−3 . . . u0 ub−1      (3.4)

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The first row ub−1 ub−2 . . . u1 u0 corresponds to the row gi,j.

After encoding, the first five parity bits in the codeword are removed to make a whole number of LDPC codewords fit inside a frame.

3.6 QAM mapping

For more information on how input data is mapped onto QAM symbols, see section 2.3.2.

The DTMB standard has five different QAM modes specified, these are:

• 64-QAM • 32-QAM • 16-QAM • 4-QAM • 4-QAM-NR

The DTMB standard refers to the 4-QAM-NR as "Quasi-orthogonal pre-mapping". More information on this subject was unavailable at the time when this thesis was written. Also, since this mode was not chosen for implementation, more informa-tion on this was not pursued.

All different QAM modes are gray coded, which means that only one bit differ between adjacent symbols in the IQ space.

The bit to symbol mappings are listed in the DTMB standard.

3.7 Interleaving

The interleaving in the DTMB standard consists of two parts, time and frequency interleaving. The time domain interleaving spreads symbols among many different frame bodies. Frequency interleaving spreads the symbols within a frame body. It is called frequency interleaving because each symbol within a frame will have its own carrier frequency after passing through the IDFT. The frequency interleaving then effectively swaps carrier frequencies between symbols.

The time domain interleaving is performed according to an algorithm known as convolutional interleaving, which is described in section 3.7.1.

The frequency interleaving is performed through the function described in sec-tion 3.7.3.

3.7.1 Convolutional interleaving

The time domain interleaving is performed by an algorithm called convolutional interleaving. Convolutional interleaving is performed as shown in figure 3.2.

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3.7 Interleaving 29

Figure 3.2. Convolutional interleaver

Each branch is a shift register with a delay of n · M where n = 0, 1, 2, ..., B − 1 which corresponds to the selected branch. B is the number of branches and M is the delay step length.

First, the value at the output of the shift register of the current branch is read, then one is written at the input. When the read and write are performed, the next branch is selected. This performed continuously for every symbol and the interleaver introduces a latency in the system, corresponding to the interleaving depth, D, of the interleaver. D can be calculated as in equation 3.5.

D = B(B − 1)M symbols (3.5)

In the DTMB standard, the parameter B is chosen to 52 and M can either be 240 or 720.

3.7.2 System information insertion

In a frame body consisting of 3744 symbols, 36 system information symbols are inserted.

The output of this insertion operation is a frame of 3780 symbols. These system information bits are modulated with 4-QAM with same I and Q components. 1 is mapped to the symbol with 11 and 0 is mapped to the symbol with 00 in figure 3.3. The 01 and 10 symbols are not used when modulating the system information or header bits.

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30 Brief analysis of the DTMB standard −6 −4 −2 0 2 4 6 −6 −4 −2 0 2 4 6 11 01 00 10 I Q

Figure 3.3. A 4-QAM constellation used in the DTMB standard

The system information bits are listed in the annex of the standard. They specify the QAM mode, interleaving mode, code rate and if the system uses OFDM or non OFDM modulation.

3.7.3 Frequency interleaving

The DTMB standard also supports non OFDM modulation in the so called C = 1 mode. If this mode is enabled, frequency interleaving is not applicable since the frequency interleaving becomes time interleaving.

In C = 3780 mode, i.e. OFDM modulated QAM, the frequency interleaving is done according to the pseudo code in figure 3.4.

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3.8 IDFT 31 f o r ( i = 0 ; i < 3 i ++) f o r ( j = 0 ; j < 3 ; j ++) f o r ( k = 0 ; k < 3 ; k++) f o r ( l = 0 ; l < 2 : l ++) f o r (m = 0 ; m < 2 ; m++) f o r ( n = 0 ; n < 5 ; n++) f o r ( o = 0 ; o < 7 ; o++) Y[ o ∗540 + n ∗108 + m∗54 + l ∗27 + k ∗9 + j ∗3 + i ] = Z [ i ∗1260 + j ∗420 + k ∗140 + l ∗70 + m∗35 n ∗7 + o ]

Figure 3.4. Frequency interleaving scheme

Y is the output frame and Z is the input frame.

3.8 IDFT

The block referred to as "Frame Body Data Processing" is an IDFT of 3780 points defined as equation 3.6. Y [k] = √1 C C X n=1 X(n)ej2πnCk (3.6) C = 3780

The IDFT is used to generate the OFDM signal when C = 3780 mode is enabled. This non-power-of-two IDFT gives a higher computational complexity com-pared to that if a power of two IFFT would have been used.

3.9 Frame header generation and insertion

After the IDFT has been performed, a frame header is inserted in front of the frame. There are three different lengths of the frame header, 420, 595 or 945 symbols.

The generator polyonomial for the three different header options are listed in equations 3.7, 3.8 and 3.9.

G420(x) = 1 + x + x5+ x6+ x8 (3.7)

G595(x) = 1 + x + x3+ x10 (3.8)

G945(x) = 1 + x + x2+ x7+ x8+ x9 (3.9)

It is here chosen to designate the generator polynomials according to the length of the frame header which they generate.

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To generate the header for the 420 symbol sequence, the initial state is loaded into the LFSR and then the calculation is iterated for 420 clock cycles. The 595 and 945 bit sequences are generated similarly. The initial state of the 595 bit mode is constant over all frames, while for the 420 and 945 bit modes the initial state is changed every frame. These initial states are listed in the standard.

The main purposes of the frame header is to act as a means of synchronization, channel estimation and guard interval. The guard interval prevents echoes from the previous frame of interfering with the current one. The 420 and 945 bit sequences are transmitted with twice the average power of the frame body. [18, 16]

The modulation of the headers is 4-QAM in the same way as with the system information bits, as in figure 3.3 and section 3.7.2.

3.10 Filtering

Before the data is passed to the DACs, it is passed through a pulse shaping filter to reduce the effects of ISI6_{. The filter also attenuates higher frequency components to}

prevent interference from the aliased components of the digital frequency spectrum. This filter is an SRRC7 _{filter with an ideal frequency response according to}

equation 3.10. H(f ) =          1 |f | ≤ fN(1 − α) r 1 2+ cos π αfN _{|f |−f} N(1−α) 2 fN(1 − α) < |f | ≤ fN(1 + α) 0 |f | > fN(1 + α) (3.10) fN =_2T1 s = fs 2 , α = 0.05, fs= 7.56 Msymbols/s.

The requirements of the filter will be discussed more in section 4.14.4. Because the transition band occurs around fs

2, the signal has to be upsampled,

before being passed to the filter. This upsampler only have to consist of zero insertion, as the SRRC filter will act as the interpolation filter which attenuate the mirror images.

The ideal impulse response of the filter is seen in figure 3.5.

6_{Inter Symbol Interference} 7_{Square Root Raised Cosine}

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3.11 Data rates 33

Figure 3.5. Ideal impulse response of the desired filter

The zero crossings lie at time intervals such that they occur at the main lobe of subsequent symbols, thus reducing the ISI of the transmitted signal.

3.11 Data rates

The symbol rate at the output of the modulator is 7.56 Msymbols/s, which is constant and below Nyquist sample rate in equation 2.10 in section 2.3.5. This means that one signal frame of 3780 symbols lasts 500 µs. The sample rate at the output will be 15.12 Msamples/s, coming from the up sampling and interpolation in the SRRC filter.

The effective data rate of the system will vary with different sets of QAM mode, LDPC code rate and header lengths.

The subset of system parameters that will be implemented in this thesis is the one that achieves the highest possible effective data rate. These parameters are listed below.

• LDPC code rate of 0.8

• Interleaving mode of B = 52, M = 240 • 64 QAM mode

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• Frame header length of 420

These parameters yield the highest effective data rate in the standard of 32.486 Mbit/s. The interleaving mode does not affect the data rate, but determines the memory demands and latency of the system. [16]

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3.12 Comparison with DVB-T and DVB-T2 35

3.12 Comparison with DVB-T and DVB-T2

Table 3.1 presents a short comparison of the DTMB, DVB-T and DVB-T2 stan-dards. The reason for the comparison is that these standards operate on the same channel type, which is terrestrial. All information is taken directly from [8], [7] and [16].

DTMB DVB-T DVB-T2

Error correction BCH, LDPC Convolutional,Reed-Solomon

BCH, LDPC

Interleaving Frequency, con-volutional

Bit, frequency, con-volutional

Bit, frequency, convolutional

IDFT size 37808 2k, 4k, 8k 1k, 2k, 4k, 8k,

16k, 32k

Pilot insertion Optional9 _{Continual, scattered} _Continual,

scat-tered, edge

QAM modes 4, 16, 32, 64 4, 16, 64 4, 16, 64, 256

Guard intervals Uses headers10 1/32, 1/16, 1/8, 1/4 1/128, 1/32, 1/16, 19/256, 1/8, 19/128, 1/4

Table 3.1. Comparison of DTMB, DVB-T and DVB-T2 standards

Pilot insertion is used for for example channel estimation and compensation. It is performed by inserting symbols with a constant power, which after the IDFT results in carriers at certain frequencies. These can either be continual, by having the symbols at the same input samples to the IDFT or by varying them, generating different carrier frequencies.

Guard intervals are intervals in which the frames are extended with a part itself, known as a cyclic prefix. They can have different lengths, as seen in table 3.1. These are inserted to reduce the interference from echoes of the same signal. The fractions in table 3.1 are the lengths of the guard intervals, relative to the frame size.

8_{The DTMB standard also features non OFDM modulation.} 9_{Pilots can optionally be inserted if non OFDM modulation is used.} 10_{DTMB uses its headers as a guard interval, see section 3.9.}

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Chapter 4

Subsystem modeling and

implementation

This chapter describes the implementation of each of the subsystems. The system model is also presented.

The purpose of the system model is to verify the function and measure the performance of the different subsystems. The modeling process also gives an esti-mation of the complexity of each subsystem.

Performance measurement results and methods are described more in depth in chapter 5.

4.1 Method and tools

The sub system models are made up of independent blocks. When implementing the sub systems, these models are used to verify the function, both independently and incrementally. These models are implemented either by Simulink models or a custom written MatLab script. The models can then be interconnected to verify different parts and extents of the system.

All simulation models have MatLab’s double floating point precision, which is as close as possible to an ideal implementation when using computer based simulations.

All blocks except the IDFT and the SRRC1 _{filter perform exact bit wise}

op-erations, and therefore it will only be needed to verify the functionality of these subsystems.

In the SRRC filter and the IDFT, there will be errors from the fixed point arith-metics used in the implementation. These errors will be measured by comparing the implemented system with the simulation models.

1_{Square Root Raised Cosine}

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38 Subsystem modeling and implementation

4.1.1 Simulation models

This section describes the simulation models and in which way they were used to verify the implementation of different subsystems.

Scrambler

The scrambler model is implemented using a custom written MatLab script which simulates the LFSR specified in section 3.4. The output vector can then be com-pared with the implemented system by either simulating it or using Xilinx Chip-Scope tool to record data from the system inserted on the FPGA.

BCH encoder

A model of the implementation was constructed by writing a custom script which simulates the intended implementation. Then, MatLab’s built in BCH encoder was used to verify the custom model to ensure that the suggested implementation method works correctly.

LDPC encoder

The model of the LDPC encoder was made by a custom script which constructs the entire generator matrix of the LDPC by taking in the first rows of all the circulant matrices as an argument. The output codeword is then generated by matrix vector multiplication.

This model can be used to verify the functionality of the LDPC encoder im-plemented in VHDL. The coefficients for the generator matrix was verified by constructing the generator and parity check matrix and using the property in equation 4.1. Through this, the parity check matrix is also verified.

HGT = 0 (4.1)

H is the parity check matrix and G is the generator matrix. [5]

QAM mapping

The QAM mapper performs translation of a bit vector into a complex number which is represented by two bit vectors.

The QAM mapper was modeled using a custom script which maps incoming bit vectors to two output bit vectors according to equation 2.5 in section 2.3.2.

Frequency interleaver

The frequency interleaver was simulated with a custom MatLab script with the function specified in figure 3.4.

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4.2 Hardware resources 39

Convolutional interleaver

The convolutional interleaver model uses the Simulink convolutional interleaver model to obtain the correct output sequence. This model was used in conjunction with ChipScope to debug and verify the implemented interleaver together with the memory controller. The same input sequence was input in both the VHDL implementation and the MatLab model. A section of the output sequence was then extracted from the model and inserted into the implementation. When this output sequence was detected, an LED on the SP601 evaluation board would light up to indicate that the correct sequence was obtained at the output.

A ModelSim simulation of the convolutional interleaver was not performed be-cause of three reasons. First, the simulation would take far too much time to complete since the interleaving depth is 170 frames of 3780 symbols each. Sec-ond, there did not exist any simulation models for the memory in VHDL, as the ModelSim version did not support mixed language simulations. At last, to fully verify the hardware memory controller, it was deemed best to test it in hardware to confirm its functionality.

IDFT

The suggested implementation of the IDFT block was modeled using MatLab with the help of the built in IFFT2function.

To measure the errors of the implemented IDFT, the MatLab model was used as reference.

SRRC filter

The SRRC filter was constructed in MatLab using the filter toolbox. By then ex-tracting the quantized filter object, binary output vectors can be obtained. These vectors was then used to verify that the filter implemented in VHDL outputs the correct data.

4.2 Hardware resources

The system is implemented on an XC6SLX45T chip from Xilinx. The relevant available resources on the chip are listed in table 4.2.

Slices Flip flops LUT3 DSP48A1 slices 18kb block RAMs MCBs

6,822 54,576 27,288 58 116 2

Table 4.1. Available hardware resources on the targeted FPGA

Slices Each slice contains four 6-input LUTs and eight flip flops.

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40 Subsystem modeling and implementation

DSP48A1 slices Each DSP48A1 slice contains one 18 x 18 multiplier, one adder

and one accumulator. These will be referred to as hardware multipliers.

Block RAMs Block RAMs are dedicated memory blocks and can either be used

as one 18 Kb block or two independent 9 Kb blocks.

MCBs Hard wired memory controller blocks.

The system is intended to run at 140 MHz, as this is the system clock for the eventual targeted system platform.

4.3 System overview

Figure 4.1 presents an overview of the system.

Figure 4.1. System overview

Figure 4.1 also shows the data widths and data rates throughout the system. These differ between systems because each system adds information to the input data. The output filter also performs up sampling by a factor of two.

4.4 Data transfer interface

To enable independent development of different subsystems, a data transfer inter-face was specified which is used between the different subsystems. The interinter-face consist of two status signals and one data transfer port. The data interface is illustrated in figure 4.2.