Design of an Input Multiplexer for Video Applications

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Institutionen för systemteknik

Department of Electrical Engineering

Examensarbete

Design of an Input Multiplexer for Video

Applications

Examensarbete utfört i Elektroniksystem vid Tekniska högskolan i Linköping

av

Pavel Angelov

LiTH-ISY-EX--10/4411--SE

Linköping 2010

Department of Electrical Engineering Linköpings tekniska högskola Linköpings universitet Linköpings universitet SE-581 83 Linköping, Sweden 581 83 Linköping

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Design of an Input Multiplexer for Video

Applications

Examensarbete utfört i Elektroniksystem

vid Tekniska högskolan i Linköping

av

Pavel Angelov

Handledare: J Jacob Wikner

isy, Linköpings universitet

Examinator: J Jacob Wikner

isy, Linköpings universitet

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Avdelning, Institution

Division, Department

Division of Electronics Systems Department of Electrical Engineering Linköpings universitet

SE-581 83 Linköping, Sweden

Datum Date 2010-06-11 Språk Language Svenska/Swedish Engelska/English Rapporttyp Report category Licentiatavhandling Examensarbete C-uppsats D-uppsats Övrig rapport

URL för elektronisk version

http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-65530

ISBN

—

ISRN

Serietitel och serienummer

Title of series, numbering

ISSN

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Titel

Title

Konstruktion av en Ingångsmultiplexer för Videotillämpningar Design of an Input Multiplexer for Video Applications

Författare

Author

Pavel Angelov

Sammanfattning

Abstract

In modern home entertainment video systems the digital interconnection between the different components is becoming increasingly common. However, analog sig-nal sources are still in widespread use and must be supported by new devices. In order to keep costs down, the digital and the analog receiver chains are imple-mented on a single die to form a system-on-chip (SoC). For such integrated circuits, it is beneficial to reduce the number of power supply domains to a minimum and preferably use the core voltage to power the analog circuits.

An eight-to-one input multiplexer, targeted for video digitizer applications, is presented. Together with the multiplexer, a simple current-mode DC restora-tion circuit is provided. The goal has been to design the circuits for a standard, single-well, 65 nm CMOS process, entirely using low-voltage core transistors and a single 1.1 V supply domain, while allowing the input signal voltages to extend beyond the supply rails.

To fulfill the requirements, a bootstrap technique has been proposed for the implementation of the multiplexer switches. Bootstrapping a CMOS switch allows high linearity, as well as wide bandwidth and dynamic range, to be achieved with a very low supply voltage. The simulated performance is: 3-dB bandwidth of 536 MHz with a 1.5 pF load at the output of the multiplexer and a SFDR of 65 dBc at 20 MHz and 1 Vp-pinput signal. It has been verified that no transistor

is stressed by high voltages, therefore, the circuit reliability is guaranteed. The DC restoration circuit utilizes the main video ADC, for measuring the DC level, and is capable of setting it with an accuracy of 60µV within the range of 100 mV to 500 mV.

Nyckelord

Keywords analog video, AFE, bootstrap, analog multiplexer, analog switch, leakage current, DC restoration, DC clamp, sub-micron CMOS

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Abstract

In modern home entertainment video systems the digital interconnection between the different components is becoming increasingly common. However, analog sig-nal sources are still in widespread use and must be supported by new devices. In order to keep costs down, the digital and the analog receiver chains are imple-mented on a single die to form a system-on-chip (SoC). For such integrated circuits, it is beneficial to reduce the number of power supply domains to a minimum and preferably use the core voltage to power the analog circuits.

An eight-to-one input multiplexer, targeted for video digitizer applications, is presented. Together with the multiplexer, a simple current-mode DC restora-tion circuit is provided. The goal has been to design the circuits for a standard, single-well, 65 nm CMOS process, entirely using low-voltage core transistors and a single 1.1 V supply domain, while allowing the input signal voltages to extend beyond the supply rails.

To fulfill the requirements, a bootstrap technique has been proposed for the implementation of the multiplexer switches. Bootstrapping a CMOS switch allows high linearity, as well as wide bandwidth and dynamic range, to be achieved with a very low supply voltage. The simulated performance is: 3-dB bandwidth of 536 MHz with a 1.5 pF load at the output of the multiplexer and a SFDR of 65 dBc at 20 MHz and 1 Vp-p input signal. It has been verified that no transistor

is stressed by high voltages, therefore, the circuit reliability is guaranteed. The DC restoration circuit utilizes the main video ADC, for measuring the DC level, and is capable of setting it with an accuracy of 60µV within the range of 100 mV to 500 mV.

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Acknowledgments

The person who deserves most gratitude for the completion of this thesis work is my supervisor and examiner Dr. J Jacob Wikner, he has provided me with the opportunity to prepare my thesis work in the division of Electronics Systems. Work and discussions with him have always been inspiring and highly motivat-ing. Dr. Wikner, you have guided me through the thesis work in a superb fash-ion. Thanks!

I am also thankful to Joakim Alvbrant for the help with the tools, and to every-body who worked in the mixed-signal thesis group, for the general discussions and support. Thanks also go to Yasir Ali Shah for opposing at the thesis presentation and providing valuable feedback for this report.

I am thankful to my friend Martin Tapankov for suggesting many corrections and improvements to the text and formating of this report, as well as for the numerous technical discussions.

I thank my girlfriend and life partner Valentina for the support and for the love, she also helped reviewing and proof-reading the final text of this report.

I owe never-ending gratitude to my parents who have always supported me unconditionally and for loving me. Without you none of this would have been possible. Thank you!

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Introduction

The objective of this thesis is to design an input analog multiplexer to be used in video digitizer applications and in a video analog-front-end integrated circuit (AFE IC) designed at the division of Electronics Systems, Linköping University. The design must be implemented in a low-voltage, “digital” CMOS process with as many components as possible brought down to layout level.

The multiplexer, designed in this thesis work, is an 8-to-1 multiplexer incor-porating a DC restoration circuit (clamp) for setting the DC level of the incom-ing video signal. The key performance measures are high linearity (more than 60 dB at 20 MHz), high bandwidth (more than 500 MHz) and low crosstalk (less than -70 dBc).

With the development of digital electronics, “digital” video formats, like DVI, HDMI and even video-over-USB, are becoming increasingly widespread. However, due to their historical usage, the analog video signaling formats are supproted by virtually all video devices in use today. Many digital devices, like personal computers, home entertainment video systems, TV sets, and even some photo cameras and MP3 players, support only analog video signaling. This means that in new devices analog video support must be availabe in parallel with the digital formats. In today’s highly integrated systems it is absolutely necessary to have the functionality for both analog and digital video formats on the same chip. Therefore, to take advantage of the modern CMOS processes, the analog parts must be designed using unconventional techniques, thus avoiding the problems introduced by the deep sub-micron CMOS technologies.

1.1 Purpose and goals

The following goals and tasks were set as guidelines for the project execution: • Design and verify a multiplexer together with a DC restoration circuit, as

well as an analog filter for limiting the bandwidth of the low-resolution video formats. Cover the performance requirements defined in the project design specifications.

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4 Introduction

• Aim the design towards applications with low supply voltage and low power consumption, possibly operated from a battery.

• Use digital circuit techniques as much as possible in order to facilitate scal-ability with future CMOS technologies and to make the realization in sub-micron CMOS processes feasible.

• Design the components such that as many as possible analog video formats are supported in the final digitizer integrated circuit.

1.2 Project scope

Even though the project is aimed at designing a fully functional video multiplexer it is not concerned with the implementation of the accompanying digital control blocks. The intention is to provide those parts of the multiplexer that directly interact with the analog signals, but leave the control strategy open for further development. However, some of the interfacing digital logic is provided, but it should not be considered optimal.

The project implementation is limited by the constraints that the video AFE has, in terms of IC manufacturing process, available power supply, supported video formats and design specifications and goals. The actual specifications will be discussed later in the appropriate chapters.

1.3 Target CMOS process description and

fea-tures

The semiconductor process, that the video AFE is designed in, is a state-of-the-art 65 nm, n-well process with seven metal and one poly layers.

The process provides a multitude of devices. There are two major transistor types—high-voltage, thick-oxide MOS transistors for a nominal supply voltage of 2.5 V, and low-voltage, thin oxide MOS transistors for a nominal supply voltage of 1.1 V. The two transistor types have two flavors each—general purpose (gp), and low power (lp). The low power transistors have thicker gate oxides to provide low gate leakage currents for non-speed critical circuit parts. The transistors have three threshold voltage options - high, standard and low Vt. The available

transistors with their main features are summarized in table 1.1.

As the design of the chip is targeted towards low power supply voltages and low power consumption only low voltage devices are used. This also lowers the cost since separate manufacturing steps are required for the high and low voltage devices.

1.4 Video digitizer overview

The designed multiplexer is a part of a large integrated circuit, a video digitiz-ing device, where it is used to select the active analog input. Since the digitizer

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1.5 Analog video signals 5

Transistor designation

Description Gate leakage Drain-Source leakage hvtlp high-Vt, low power low low svtlp standard-Vt, low power low medium lvtlp low-Vt, low power low high hvtgp high-Vt, general purpose high low svtgp standard-Vt, general purpose high medium lvtlgp low-Vt, general purpose high high

Table 1.1: Transistor types available from the target CMOS technology

stands at the boundary of the analog and digital domains it is also termed

analog-front-end (AFE). The architecture of the video AFE is shown in figure 1.1 and is

separated in two major blocks. The digitizing channel consists of an input mul-tiplexer together with a DC restoration circuit, a low-pass filter, a programable

gain amplifier (PGA) and an analog-to-digital converter (ADC) which digitizes

the video signal. This is followed by a digital post-processing block which per-forms gain and error correction. In order to cover all supported video formats five digitizing channels are used in parallel.

The timing block processes the synchronization information in the video signal (either embedded sync pulses or separate synchronization signal) and extracts the timing information needed to control the digitizing channel. The input signal is fed to a multiplexer, which selects the source of the synchronization signal, then to a phase-locked-loop (PLL) which aligns its output to the input synchronization signal, but at a higher frequency corresponding to the pixel rate. The

delay-locked-loop (DLL) is used to time-shift the rising edge of the clock produced by

the PLL so that the position at which the video signal is sampled can be precisely controlled and selected, thus allowing under-sampling to be utilized.

The AFE also incorporates a digital control block, which programs the op-eration of the different parts: video input and sync input selection, PGA gain, PLL multiplication factor and DLL phase. The video multiplexer, in particular, receives control signals for input selection, clamp activation and clamp voltage.

1.5 Analog video signals

Originally analog video was designed for the monochrome broadcast TV. The

cathode-ray-tube (CRT) was the only device available for video output in the

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6 Introduction

Clamp

Filter Designed blocks

PGA

Bias ADC Reference Generator Digital signal processing Gain correction Oﬀset correction Sag compensation/Clamp 5 x DIGITIZING CHANNEL Control DLL DLL PLL DLL Slicer Slicer _{27-MHz Oscillator} (RC type)

Power-on reset (POR) Digital signal processing Sync detection Clock dividers Registers Bandgap reference

Current and volatge reference

Mu ltipl e xer 2 x TIME/REF CHANNEL Main Video ADC Mu ltipl e xer

Figure 1.1: Block diagram of the video analog-front-end integrated circuit.

a CRT screen. This largely determines what “features” the analog video signal incorporates.

1.5.1 Monochrome video

The image on a CRT is formed by sweeping an electron beam over the back surface of the screen [1], starting from the top-left corner and continuing, line by line, to the botom end. After drawing a complete line, the electron beam is “swept” back to the left to start drawing the next line. After a whole frame has been drawn the beam is swept to the top-left corner and the display of the next frame begins. This process is shown in figure 1.2. The sweeping of the beam to the left and to the top is called horizontal and vertical retrace, respectively. Actually, to save bandwidth, in the TV formats the image is not displayed progressively, line-by-line, but is instead scanned odd lines first and then, on the next vertical retrace—even lines, this is called interlaced video.

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The tracing motion of the electron beam is controlled by the video signal. A portion of a signal representing one line of video is shown in figure 1.3. The hor-izontal scan starts slightly outside the visible area of the screen, this corresponds to the part of the video signal, called back porch, where the signal is kept at a level

Back Porch Front Porch

Active Video

Horizontal retrace path Vertical retrace path

Scan lines

A

ctive V

ideo

Figure 1.2: Electron beam scanning on a CRT screen.

Sync pulse

Back porch Front porch Blanking pulse 0% 25% 50% 100% Next line Time Amplitude 75% High detail region

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8 Introduction

corresponding to the color black. After that the actual image line is displayed, this portion of the signal is called active video. The voltage of the active video portion of the signal carries the color and brightness information of the pixel corresponding to the position of the beam at the particular instant of time. At the end of the line the signal is again blanked (brought to a level corresponding to black) and the beam is brought out of the visible screen area. This part of the video signal is called front porch. The horizontal retrace is controlled by a very important part of the video signal, following the front porch—the horizontal synchronization (hsync) pulse. During the hsync pulse the beam is brought back to its initial position, at the left of the screen and then released to display the next line. The length of the hsync pulse is long enough so as to allow the CRT control circuitry to settle. The voltage level of the sync pulse corresponds to a blacker-than-black color, so that the retrace period is not visible on the screen.

After the whole image is displayed, a pulse similar to the hsync pulse, called vertical synchronization, or vsync pulse occurs in the video signal and the beam is returned to the top left corner of the screen.

1.5.2 Color video

So far, we have only discussed the case where just a singel color is to be displayed. In order to represent color video three separate signals are required—one for red, one for green and one for blue, or RGB. These three base colors are combined on the screen to form the original colors of the image. Despite of that, the basic principle of drawing the image on the screen remains the same.

The need of three separate colors means that three times the number of cables, or three times the bandwidth, of the monochrome signal are required to transmit color video. To solve this problem several signaling (RGB, Y PbPr, composite) and

encoding (PAL, SECAM and NTSC) techniques were developed to represent the colors so that less cables/bandwidth are needed. However, any operation on the original RGB video signal deteriorates the image quality.

The first step in limiting the bandwidth is the color difference representation of the original RGB signal. This is merely a transformed color space called Y PbPr.

It is again formed by three signals, the luma Y carries the brightness (the mean value of the red, green, and blue), PB is the difference between the original blue

and luma, and PR is the difference between the original red and luma. The green

color can then be derived from the recovered blue and red and the original luma signals. The Y PbPr still requires three cables to send the video, but due to the

properties of the human eye, which is more sensitive to variations in brightness than to variations in color, the color signals can be filtered to half the bandwidth of the luma signal. The synchronization and blanking information is overlaid on top of the luma signal.

To limit the required number of wires, the color difference signals are used to modulate a color subcarrier, the resulting signal is called chrominance. This reduces the required number of wires to just two: one for luma and one for chromi-nance. This type of video signaling is called S-Video. The luma and chroma signals can be combined into just one signal to form a signal called composite video, which

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Video format Active video Sync Peak amplitude

RGB 700 mV – 700 mV RGBsync–on–green 700 mV -300 mV 1 V Y PbPr (PAL) luma 700 mV -300 mV 1 V chroma 700 mV – 700 mV Y PbPr (NTSC) luma 714 mV -286 mV 1 V chroma 1009 mV – 1.009 V S-video (PAL) luma 700 mV -300 mV 1 V chroma 885.1 mV – 885.1 V S-video (NTSC) luma 714 mV -286 mV 1 V chroma 835 mV – 0.835 V Composite video(PAL) 933.85 mV -300 mV 1.234 V Composite video(NTSC) 934.15 mV -286 mV 1.220 V

Table 1.2: Voltage levels for the different video formats. Blanking level is assumed to be 0 V in all cases.

is used in terrestrial television broadcast and in home video entertainment systems. The more the original RGB signal is processed the more quality and resolution is lost. This is the reason why different video systems stop processing the signal at different stages. Computer graphics and some high quality home entertainment systems directly use the RGB or Y PbPr (also called component) video signals.

S-video and component video are used in TV sets, DVD players, set-top boxes, etc.

1.5.3 Voltage levels

The information in the analog video is carried both in the value and in the time/-position of the signal. For PC graphics systems, using RGB signaling, the peak-to-peak voltage level is defined to be either 0.7 Vp-p, when the sync is a separate

signal, or 1 Vp-p when the sync is embedded in the green signal (termed

sync-on-green). Since the input multiplexer is only required to preserve the signal, the

details of the voltage levels of the different parts of the video signal for the other video formats and encoding techniques are not of a particular interest for the de-sign of the video multiplexer. What is important are the maximum peak-to-peak voltages that occur and the video blanking level. Table 1.2 lists these parameters for the different video signaling and encoding formats.

As the video AFE is targeted towards low-voltage design, the power supply voltage available for the input multiplexer is specified to be only 1.1 V, meaning that the signal levels that are to be switched are actually higher than the supply voltage. It is a major challenge to handle signals larger than the supply voltage in CMOS circuits and proved to be the main problem in designing the video multiplexer circuitry.

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10 Introduction

1.5.4 Signal coupling and termination

Video signals can be both DC or AC coupled between devices. DC coupling means that the input DC level of the receiving device is defined by the output of the previous device. This means that the two devices must be designed to operate with the same common-mode level and that the ground reference be kept at the same potential at both ends. The existence of DC path means that dangerous DC currents may flow between devices powered by different power supplies. This is the case, for example, in a home entertainment system where the TV set and the set-top box are powered separately. DC coupling is usually utilized within one and the same system where the common-mode levels are well defined.

Systems, designed to accept signals from different sources, must be AC coupled so that the common-mode level of the receiving end is well defined. To stop the DC component, a capacitor is placed in series with the signal path, as illustrated by figure 1.4. Thus, in order to achieve optimal performance, the two devices can set their own common-mode level at both sides of the input capacitor.

− + DC Clamp On-chip Receiving device Sending device

Figure 1.4: AC coupling of an analog video signal.

AC coupling introduces some problems as well. The receiving end must provide the means of setting the DC level at its input, leading to an increase of the required die area due to the additional circuitry. Since the video signal bandwidth extends to very low frequencies (the vsync frequency is at the order of 60 Hz), hence, in order to preserve the integrity of the signal, the coupling must not introduce significant attenuation. If the input resistance seen at the receiving device, after the input capacitor, is too low, the voltage on the capacitor will tend to track the mean level of the video signal. This effect (termed sag) causes variations of the brightness level at different parts of the picture. Circuits used for setting the DC level are called DC restoration, or DC clamp circuits. The clamp is, usually, activated only during the sync pulses or part of the back porch, so that the change in signal level is not visible on the screen.

Video signals are usually sent over 75–Ω cables, which are terminated at both ends to avoid reflections. To save board space, some low-cost manufacturers do not provide the termination at the receiving end, this causes the voltage levels,

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seen at the input, to double. A non-mandatory design requirement, to support double input levels, has been put for the input multiplexer, so this also has been investigated during the design process.

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Chapter 2

Analog Multiplexers and

Switches

2.1 Introduction

The main objective of this thesis is to design an analog multiplexer—a device used to select one-out-of-n inputs. Analog here refers to the continuous nature of the input signals that are to be switched/processed, not to the actual implementation of the internal schematics of the multiplexer.

V out Vin1 Vin2 Vin3 S1 S2 S3 VinN S n

Figure 2.1: Functional diagram of an analog multiplexer.

The functional diagram of an analog multiplexer is shown on figure 2.1. It is composed of n switches with one of their terminals connected together and serving as an output of the multiplexer, while the other terminal—serving as an input. At any instant of time only one of the switches Si is closed, while the rest are open.

The output voltage is, thus, equal to the voltage at the input corresponding to the closed switch, while the signals on the inputs with their switches open, ideally

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14 Analog Multiplexers and Switches

have no effect on the output signal.

Obviously, the main building block of an analog multiplexer is the analog

switch, thus its performance largely determines the performance of the

multi-plexer as a whole. Ideally, when closed (on-state), the switch should present a short-circuit and when open—infinite impedance. In practice, however, this is not the case and the switches present (small) resistance when on and a small current flows through the switches that are open (off-state). Furthermore, there exists capacitance present between the two terminals of the switch (shunt capacitance) and between each terminal and ground, this is shown on figure 2.2. The output capacitance, combined with the finite on-state resistance, limits the bandwidth of the switch, while the shunt capacitance deteriorates the off-state isolation at high frequencies. S1 V out Ron Cout Cin V in Cshunt Real Switch

Figure 2.2: Model of a real closed switch with parasitic elements.

Due to the analog nature of the video signals, it is of primary importance that the multiplexer does not introduce non-linear distortion. This is especially true for analog video where the color and brightness information are stored in the signal amplitude. In a practical CMOS implementation of a multiplexer, the main source of non-linearity is the dependence of the on-state resistance on the input voltage. Therefore; most of the multiplexer design time was devoted in achieving linear (enough) behavior of the switches.

It must also be noted that the switching speed between the different inputs does not need to be done with high speed, nor is the switching required to be glitch-free.

2.2 The MOS transistor as a switch

There are several approaches to implement analog switching behavior in a CMOS circuit. It is possible, for example, to turn off the bias current of an amplifier, effec-tively stopping the propagation of the input signal to the output. This approach is, however, considered too analog and was not investigated further.

The simplest electronic switch, that can be implemented in CMOS technology, is a single MOS transistor, with the drain and source terminals acting as the two

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2.2 The MOS transistor as a switch 15

terminals of the switch and the gate as the control input. This arrangement is shown on figure 2.3, where an NMOS transistor has been chosen. From basic

V in V out V in V co n tr ol V out

Figure 2.3: A single transistor analog switch.

device physics, it is known that the first order approximation of the drain current of a NMOS transistor, operating in linear region with VDS < (VGS− VT H), is:

ID≈ µnCox

W

L(VGS− VT H)VDS (2.1) That is, if the gate voltage is kept constant, the drain current varies linearly with the source (input) voltage. This represents a non-linear resistance seen in the signal path, and hence causes significant distortion. Furthermore, if the input voltage becomes higher than VG − VT H the transistor cuts off and the output

waveform is clipped. This limits the available input signal range and makes the circuit particularly unsuitable for low-voltage CMOS technology implementation. For our design case the gate can be kept at the supply voltage of 1.1 V and since the threshold voltage of the transistors is about 250 mV the usefull signal range is limited to about 750 mV. A rather small value, only suitable for the low voltage swing signals like RGB .

2.2.1 Transmission gate

A significant improvement over the single transistor switch can be achieved by con-necting two transistors with different conductivity (NMOS and PMOS) in parallel, this is shown on figure 2.4. The dependace of the on-state resistance of the two transistors on the input voltage is approximately the same, but with an opposite sign. That is, when the input voltage increases the NMOS resistance increases while the PMOS resistance decreases and vice versa. Also, when one of the tran-sistors enters the cut-off region the other one continues to conduct, significantly extending the useful signal range of the circuit. The variation of the resistance for both transistors as well as the combined resistance of the parallel connection as a function of the input voltage is illustrated in figure 2.5. It is seen that the total resistance of the switches remains approximately constant.

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16 Analog Multiplexers and Switches V in V out V in V out V co n tr ol

Figure 2.4: Transmission gate realization of an analog switch.

Signal Voltage RON NMOS PMOS Resistance of the parallel combination

-

+

Figure 2.5: Dependence of the on-resistance of MOS transistors and their parallel combination on the applied gate-source voltage.

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2.2 The MOS transistor as a switch 17

The smallest resistance variation is achieved when the PMOS transistor is sized such that the electrical size of the two transistors is approximately the same. Such matching, however, is difficult to achieve in sub-micron CMOS technologies, which are characterized with significant device variations, hence large non-linear distor-tions would occur across process corners. Furthermore device matching techniques are considered to be too “analog” and therefore do not fit well within the “digital” design philosophy adopted for this project.

2.2.2 Bootstrapping techniques

We have seen that the main source of non-linearity of the transistor switches comes from the variation of the on-resistance caused by the variation of the gate-source voltage. Bootstrapping is a technique with which the gate-source voltage is kept approximately constant throughout the voltage range of the input signal. This is achieved by connecting a pre-charged capacitor (termed bootstrap capacitor) between the gate and source terminals of the pass transistor. The bootstrap capac-itor is pre-charged to the supply voltage during the off-state and then connected to the pass transistor through a separate set of switches. With this arrangement the gate voltage follows the source voltage with a DC offset equal to the capacitor voltage. Figure 2.6 shows the concept of the bootstrapping technique. The switch is turned off by simply connecting the gate of the main switch to ground.

V in V out Vboot Cboot Pass Transistor

Figure 2.6: Conceptual schematic of a bootstrapped switch.

Bootstrapping the gate of the switch transistor largely eliminates the variation of the on-resistance due to variation of the gate-source voltage. However, due to the body effect the on-resistance still depends on the source voltage. This effect can be compensated by bootstrapping the bulk of the pass-through transistor as well. However, for a typical CMOS process, the bulk terminals of NMOS transistors are not separately accessible, therefore, PMOS devices must be used instead. Circuits that compensate for the body effect by bootstrapping the bulk have been proposed in [3] and [4].

Since the gate potential of the bootstrapped switch in the on-state is equal to the sum of the input and the supply voltages, special attention must be payed to

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18 Analog Multiplexers and Switches

the devices connected to that node so that circuit reliability is not compromised. The constant G-S voltage achieved by the bootstrapping technique means that the on-resistance is almost independent of the ratio between the supply and the input voltages, allowing the bootstrapped switch to be used for signal voltages that go beyond the supply rails. This makes the bootstrapped switch the perfect (if not the only) candidate for implementation of the video multiplexer, thus it has been selected for realization.

2.3 The implemented analog switch

Several circuits, proposed in [2], [3] and [4], have been considered for the implemen-tation of the bootstrapped switch. The circuits described in [3], despite promissing good performance, were excluded from consideration for implementation due to the fact that they are protected by patents.

The bootstrapped circuit suggested by Waltari et al. in [4] compensates for the harmful body-effect and can be implemented in a standard, single-well CMOS technology. This is made possible by the use of a PMOS device with a boot-strapped bulk as the main switch. Special arrangement of the auxiliary switches is necessary in that case in order to accommodate the large negative voltages that occur at the bootstrapped nodes. Due to the supposed high performance this circuit has been selected for realization and further assessment.

Another circuit implementing the bootstrapping technique which utilizes a NMOS as the pass-transistor is suggested by Lillebrekke et al. in [2]. This circuit is significantly simpler than the one from [4] and despite the supposedly poorer performance due to the body effect has also been considered for implementation. The two selected circuits have been implemented in the target CMOS process and their behavior has be simulated. It was discovered that for comparable siz-ing, and despite the improved variation of the on-resistance, the circuit utilizing a PMOS switch showed much worse performance in terms linearity and bandwidth. This can be explained by the inherently higher on-resistance of the PMOS tran-sistor which limits the bandwidth and linearity of the switch as whole. It should be noted that in the case of the multiplexer the capacitance seen at the output node is significant (at the order of 2 pF), therefore, high on-resistance cannot be tolerated. Also, the output capacitance has a largely non-linear behavior caused by the junction capacitance introduced by the switches in the off-state.

Due to the above reasons the bootstrapped switch in [2] has been selected for the actual implementation and for detailed analysis. The complete circuit of the switch, as originally presented in [2], is shown in figure 2.7.

2.3.1 Bootstrapped switch—principle of operation

The topological diagram of the circuit from figure 2.7 is shown in figure 2.8. The operation is based on two non-overlapping clock/control signals, shown in figure 2.9. When clk1 is high and clk2 is low the gate of the pass transistor is grounded through S5 and the switch is in the off-state, also S3 and S4 are closed and the

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2.3 The implemented analog switch 19

bootstrap capacitor Cboot is charged to the supply voltage difference. In the

on-state the bootstrap capacitor is connected through S1 and S2 to the source and gate terminals of the pass transistor turning it on. The non-overlapping nature of the clocks prevents the bootstrap capacitor from discharging during the transition between the on and off states. In the on-state the potential between the gate and the source is approximately constant and equal to the capacitor pre-charge voltage.

The circuit in figure 2.7 is a direct implementation of the discussed topology. Transistors N3 and P4 implement S3 and S4 respectively, while transistors N1 and P2 – S1 and S2. When the current through the pass transistor changes direction the role of its terminals swaps, this requires the use of N8 which compensates for this effect and allows node A to more precisely track the potential of the terminal acting as the source. For high input voltage levels the potential at node B may become higher than Vdd which requires the transistors connected to that node to be of PMOS type so that they can conduct reliably. It is not possible to turn on transistor P2 by simply connecting its gate to ground as voltages exceeding the gate oxide breakdown limit may appear between its gate (ground) and source (node B). Therefore, in order to to turn on P2 the voltage of the bootstrap capacitor is used, this is achieved by transistors N6 and NS6. The dummy transistor PD is used to compensate for the charge injection due to P7 at node E. Transistors N5 and NS5 implement S5. When the voltage at the gate of the main switch reaches approximately the supply voltage, transistor NS5 cuts off and limits the voltage at node Q to a safe level.

Vdd _swOFF NS5 N5 V out SW G D S V in ChrgHI A N3 N8 N1 N6 NS6 ChrgLO P2 B P4 P7 Vdd Cbootstrap ChrgLO ChrgLO ND

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20 Analog Multiplexers and Switches V out V in Vss Vdd CLK1 CLK2 Cboot S1 S2 S3 S4 S5 A B Vss CLK2 CLK2 CLK1 SW

Figure 2.8: Topological diagram of the bootstrapped switch

clk1

clk2

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Chapter 3

DC restore block

As discussed before, in most analog video systems the external input signals are AC coupled in order to provide protection against dangerous DC currents and to allow each device to set its own common mode level. By specification the external connections of the designed video AFE are AC coupled as well and the first block in the signal path, the input multiplexer, must provide the means to set the DC level. In this chapter we discuss the different implementations of the

DC restoration block, their advantages and disadvantages and the reasons why a

particular implementation is suitable for the video AFE or not.

3.1 The need for DC restoration

A typical AC coupling of a video signal into a processing device is shown in figure 3.1, where Rinrepresents the input impedance of the device. For this arrangement,

the coupling capacitor stores the average value of the input signal, as well as the difference in the DC level of the signal source and the device input bias level. For systems that process zero-mean signals, such as audio, this is not a problem as the bias level is well defined. However, the video signal average level is strongly depen-dent on the image content, this causes the DC level after the coupling capacitor to vary. Figure 3.1 shows this behavior for two video signal cases, one representing a picture with high brightness and the other—with low, shown also, is a zero-mean sinewave signal for which the DC level does not change. The variation in DC level would cause the brightness of the image to change in response to changes in the average brightness. To prevent this effect a DC restoration, or clamp, circuit is needed to fix the level of the video signal to a known reference level.

The simplest form of a DC clamp circuit is shown in figure 3.2. The switch S1 can be activated during the hsync pulse, thus, “clamping” the tip of the hsync pulse to ground level, this is called sync tip clamping. It is, also, possible to activate the switch during the blanking level of the back porch, fixing the black level to 0V, this is called black level clamping. Since the sync pulse voltage is usually not well defined and, also, may not be very stable from line to line, the

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22 DC restore block

V

in _C_couple

Rin

Ileakage

Video precessing device

0V 0V

Figure 3.1: Effects on the signal levels due to AC coupling.

V

in _C_couple

Video precessing device 0V

0V 0V

Clamp Synch tip clamp

Black Level clamp

S1

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3.2 Voltage-mode DC clamp 23

black level clamping provides much better DC stability than the sync tip clamping.

3.2 Voltage-mode DC clamp

The switch in figure 3.2 does not necessarily have to be connected to ground—it can be connected to any other DC reference (figure 3.3) so that the clamp level can be chosen arbitrary. This allows a propper bias level to be defined for the following circuitry by simply changing the reference voltage. This arrangement for which the DC level is directly forced to a known reference voltage is called voltage-mode

clamping. In fact, the specification for the DC restoration for this thesis requires

that the DC level should be possible to be set anywhere in the range from 100 mV to 500 mV—a voltage that should only be reproduced, not generated, by the clamp circuitry.

V

in _C_couple

Clamp

S1

-+

Vref

Figure 3.3: Voltage-mode DC restoration.

The purpose of the operational amplifier in figure 3.3. is to buffer the reference voltage Vref and provide a low-impedance source for charging and discharging

of the coupling capacitor in a reasonable time. However, the precision and the speed of the operational amplifier limit the performance of this circuit. Due to the poor properties of the transistors in sub-micron CMOS technologies, the design of amplifiers with reasonable gain and offset is a challenging task. Due to this reason and the preference for a more “digital” design the voltage-mode clamp is not considered to be an appropriate candidate for implementation in the designed multiplexer.

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3.3 Current-mode DC clamp with current sources

The buffer of the voltage-mode clamp can be substituted by two much simpler current sources, as shown in figure 3.4 When the DC level needs to be increased the current source connected to the input node with its positive terminal is activated and the right plate of the input capacitor is charged to the positive supply voltage. When the DC level needs to be decreased the other current source is activated and the capacitor is charged in the reverse direction. This arrangement is, also, termed

charge pump due to the apparent pumping of charge on the capacitor plates.

V

in _C_couple

Clamp

S1

ctl

Figure 3.4: Current-mode DC restoration.

In a digitizer application, it makes sense to utilize the main ADC in the feed-back loop for sensing the DC level and controlling the DC clamp level. The current-mode clamp, also called charge pump, is readily suited for control directly from the digital domain, that is, the current sources need be just on or off. A conceptual representation of the current-mode clamp with the main video ADC in the loop is illustrated in figure 3.5. Note that this topology highly resembles that of the voltage-mode clamp, but instead of the analog reference voltage a reference digital code is used, and that the analog buffer is replaced by a digital comparator which generates the “UP-DOWN” control signal.

It should be emphasized that the clamp circuit in figure 3.5 does not operate in continuous time. Certainly, the ADC samples the continuous-time input signal and produces output only at certain instants of time. Furthermore, the charge that is stored on the capacitor plates is proportional to the time the charge pumps are activated, thus the loop-gain is dependent on the timing.

Due to its “digital” nature the current-mode clamp is far better suited for implementation in CMOS technology. It should be noted that a digital comparator consumes far less power and die area and is, also, much simpler to design and layout. Due to the above said, the current-mode clamp has been selected for further consideration for implementation in the video AFE.

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3.4 Current-mode DC clamp without current sources 25

V

in _C_couple

Digital Comparator Video ADC Reference word up down

Figure 3.5: Closed-loop operation of the current-mode clamp utilizing the main video ADC.

3.4 Current-mode DC clamp without current

sources

The current sources of the current-mode clamp described above can be imple-mented with two MOS transistors as shown in figure 3.6 where transistor Ns acts

as a current source and transistor Nsw—as switch for turning the clamp on or off.

up/down Iclamp up/down Vbias Iclamp _N sw Ns

Figure 3.6: Realization of the controlable current source.

In order for transistor Ns to be in saturation and actually act as a current

source the condition VGS < VDS + VT H must be met. In the extreme case, the

drain-source voltage (VDS) drops to 100 mV (the minimum clamp voltage) which

means that the maximum overdrive voltage (VGS− VT H) can be at most 100 mV.

Simulations, carried out with these constraints, showed that in order to make the clamp current sufficiently large the width of that transistor must be made in the

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order of 150 µm. Furthermore, the output resistance of the transistors in the target CMOS technology is very low, this directly translates to a low output impedance of the current source making the clamp current strongly dependent on the input voltage.

It should be noted that due to the short channel effects the output resistance (seen at the drain) of short-channel devices does not show significant dependence on the operating mode of the transistor, making the transition between the linear and saturated region smooth and almost indistinguishable. It makes sense, then, for the clamp circuit to remove the current source (transistor Ns) and leave only

the switch (transistor Nsw), significantly reducing the size and complexity of the

circuit.

Let us, now, follow one possible operation of this “stripped down” version of the clamp circuit in more detail. First, the voltage of the part of the video signal that is to be “clamped” is sampled and converted by the ADC, note that the ADC convertion is running independently of the clamp block and the sample of interest is simply taken from the ADC output stream. The sample value (code) is then compared to the reference (target) value and the U P − DOW N signal is generated, i.e. it is decided if the DC level should be increased or decreased. The clamp is then activated for a predetermined amount of time (maximum of 6 pixels, according to the specification) and a specific amount of charge is placed on the input capacitor plates, thus shifting the DC level at the input.

Here it must be emphasized that since the current through the clamp transistors is strongly dependent on the signal level to be clamped, the amount of charge put on the input capacitor per cycle is, also, different for different DC levels. This makes the clamp settling response non-linear, however, this is not of significant importance as only the final, settled value, and the settling time is of interest for the operation of the video digitizer. It is also important to show that the clamp behavior is stable, that is, it does not oscillate from cycle-to-cycle. This will be shown in section 5.3.

Due to its “digital” nature and good results from the initial simulations the topology described above has been selected for the actual implementation in the video multiplexer.

3.4.1 The implemented DC clamp

So far, the topology discussed for the clamp block has been somewhat simplified to ease its presentation. In practice, however, the clamp current cannot be simply switched on and off because this would make the precision with which the DC level is set too low. Let us consider the change in voltage of the input capacitor (and the DC level) for one activation of the clamp, it can be written as:

∆Vin=

∆t · Iclamp

Cin

(3.1)

where Iclampis the clamp current, Cinis the input capacitance and ∆t is the time

the clamp is active, i.e. enabled. The clamp time is more or less fixed, as the clamp can be active for at most 6 pixels and the smallest practical time is one

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3.4 Current-mode DC clamp without current sources 27

system clock period. This means that in order to make the clamp precise the clamp current has to be very small, which would make the transient behavior very slow as well. To circumvent this, the clamp current is made controlable, so that when the error (difference between the target DC level and the actual DC level) is small the current can be set to be small as well, allowing for the DC level to be changed in small increments. For large errors, the clamp current can be made bigger, so as to speed-up the transition.

The adjustment of the clamp current is made possible by connecting several clamp current transistors in parallel and enabling only some of them (note the resemblance to a current steering DAC). The need for more signals to control the operation of the clamp means that the digital comparator of figure 3.6 must now be changed to a subtractor which calculates the error code and applies it to the clamp as a control signal.

It is, also, possible to implement a much more complex control strategy of the DC clamp. For example, during the initial transient, when a particular multiplexer input is selected, the DC level may be at a completely wrong voltage, in that case the clamp may be activeted for much longer time—even during the active video portion of the signal. This will allow shorter settling time than possible if the clamp is activated only during the back porch. Of course, a more complicated control block than the simple subtractor will be required to implement such behavior. The clamp control strategy is, however, out of the scope of this work.

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Chapter 4

Analog Multiplexer

-performance metrics

In this chapter, we will introduce the main performance metrics that were used to guide the design process of the analog multiplexer and the accompanying clamp circuitry. We will first relate each metric to the particular non-ideal behavior that limits the corresponding performance. Then, we will show how the video signal and the digitizer as a whole are affected, giving examples where appropriate.

4.1 Bandwidth

Probably, one of the most common and popular specification parameters for a video or graphics system today is its resolution. The resolution is the ability to distinguish between small details in the reproduced picture. The details of an image can be present both in the light intensity (brightness), or in the color of the objects. High detail in an image corresponds to rapid changes in the video signal, which means that in order to represent high resolution the analog video signals must have wide bandwidth. Figure 4.1a shows a commonly used test pattern for video systems, while in figure 4.1b the same pattern is shown but this time the bandwidth of the underlying signal has been limited. Notice that the vertical boundaries between the different color patches have become blurred and that the fine vertical black-and-white stripes have practically turned into a grey rectangle. Any real analog signal is subject to bandwidth limitation, including the analog video signal when being processed and transmitted. As discussed in chapter 2, the finite on-resistance of the switches in the multiplexer together with the input capacitance of the next module in the digitizer channel form a low-pass filter which limits the bandwidth of the video signal being processed.

In order to accommodate all available video and graphics formats available today the 3 dB bandwidth requirement for the video multiplexer is defined by specification to be 500 MHz. In fact, this is much larger than what is required for the currently available video formats, but is chosen as such in order for future

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30 Analog Multiplexer - performance metrics

(a) Normal (b) Limited bandwidth

Figure 4.1: Effect of bandwidth limitation of the video signal.

formats to be supported as well.

4.2 Linearity

As was discussed in section 1.5, the color and brightness information is contained in the amplitude of the analog video signal during the active video portion. This is why it is important that when video is processed the relative amplitude of the signal is preserved, excluding any gain. Linearity is defined as the property of a system to respond to the sum of any two inputs with an output which is the sum of the output responses corresponding to each of the two inputs taken separately. Any non-linear system introduces non-linear distortion to the signals it processes. If a video signal is non-linearly distorted the color and brightness information is lost and the picture will not be displayed properly. The actual effect of non-linearity on the image depends on the signaling method that is utilized. Suppose that in a RGB system (for example PC graphics) the color yellow, produced by the colors green and blue, is to be displayed, Assume, also, that the green and blue components are with equal magnitudes, corresponding do mid brightness level. If, now, the brightness of the image is doubled (maximum brightness), but the blue channel introduces non-linearity and the intensity of the blue color is increased only 1.5 times, then the green color will dominate and the final image will look greenish. This effect corresponds to color space deformation. Figure 4.2b shows the same test pattern as before but with non-linear distortion applied separately to each of the color channels—red, green and blue. Notice how the color have changed and that the overall picture brightness have increased.

As was discussed in section 2, the switches in the video multiplexer are subject to non-linear behavior, hence the non-linear distortion introduced by the multi-plexer has been the most important performance metric influencing the design de-cisions. The actual performance measure used was the spurious-free dynamic range (SFDR) measured in dBc. Due to the complex non-linear behavior of the switches,

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4.3 Inter-channel isolation 31

(a) Normal (b) Non-linear distortion

Figure 4.2: Effect of non-linear distortion of the video signal.

the SFDR was specified for several input signal amplitudes and frequencies—1 Vp-p

at 20 MHz, 0.8 Vp-pat 40 MHz and 0.2 Vp-pat 1 MHz, with corresponding linearity

of at least 60 dBc, 40 dBc and 80 dBc.

4.3 Inter-channel isolation

It is possible that the signal at a multiplexer input, that is not currently selected, to leak through the open switches and mix with the signal from the active input. Depending on the video formats of the two signals this interference may appear in the final image as noise or as a background ghost image. If the two signals are with completely different formats, for example TV and computer graphics, they are not correlated and the interference appears as noise in the form of “crawling” diagonal lines. However, if the signals are with the same format, for example from two TV tuners, then they have the same horizontal and vertical refresh rates and the image from the interfering input may be visible on the screen.

The inter-channel isolation has been specified to be at least 70 dBc for all frequencies in the range 0-500 MHz.

4.4 Clamp circuit performance metrics

The primary purpose of the clamp circuit is to define the DC level of the video signal and keep it stable throughout the frame, it is also required to initially bring the DC level to the target voltage in a timely manner. If the clamp circuit is not stable, that is the DC voltage oscillates between the lines, then horizontal stripes with varying brightness will be visible on the screen. This is a highly undesirable effect since the human eye is very sensitive to different brightness levels. The result from unstable behavior of the clamp circuit is shown in figure 4.3b. Note that, despite of the small random variation of at most ±5% applied to the DC level the variation in brightness is quite visible.

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32 Analog Multiplexer - performance metrics

The performance measures that guided the design of the clamp circuit were stability and settling time. The settling time was specified to be at most 1 frame.

(a) Normal, stable DC level (b) Unstable DC level

Figure 4.3: Effect of unstable DC clamp. The brightness is varied by 5%.

4.5 Leakage and lower cut-off frequency

As discussed earlier, the video signal is AC coupled to the input of the multiplexer through an external capacitor which “holds” the DC level during the active video portion. If a small current leaks through the internal circuits of the digitizer channel of the video AFE, the DC level of the signal will change throughout the line. On the screen, this will be visible as a changing brightness of the image from left to right as shown in figure 4.4b. This effect can also be viewed as a too high

(a) No leakage (b) Excessive leakage

Figure 4.4: Effect of leakage current through the input capacitor.

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high-4.5 Leakage and lower cut-off frequency 33

pass filter. In the early video systems the problem with leakage through the input coupling capacitor (also called “line droop” or “line tilt”) was quite severe, but in modern systems it is easily corrected in the digital domain. Nevertheless, such correction reduces the available range of the ADC and leakage must be limited as much as possible in the analog domain.

Note that the brightness at the rightmost edge of the image in figure 4.4b. is only 5% lower than that at the leftmost, still it is clearly visible.

The amount of change in DC level per line is not explicitly specified in the design specifications, but a value no bigger than 1 LSB of the main video ADC was targeted in the design of the multiplexer and clamp circuits.

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Chapter 5

Design Details

5.1 Introduction

So far, we have only discussed the different blocks of the input multiplexer in terms of their expected performance and different implementation strategies, we have also selected a particular schematic to be realized for each block. In this chapter, we will describe the design details for each circuit, give detailed transistor sizing strategies and the rationale and trade-offs behind the design decisions.

Due to the relative simplicity of the interaction between the blocks comprising the multiplexer, it was possible to carry-out the design in the meet-in-the-middle fashion, without building behavioral models for the different blocks. Note that the behavior of a switch, even with parasitics, is not particularly interesting.

First, the bootstrapped switch topology, presented by Lillebrekke et al. in [2], was implemented and the circuit behavior studied in detail in order to verify that it is suitable for the purposes of an analog switch in the multiplexer. Several modifications of the original circuit were proposed and successfully implemented. A behavioral model was, then, built for the clamp block and its operation together with the switch was studied and simulated in order to identify potential problems. The clamp circuits were, then, implemented at transistor level and resimulated. Finally, the whole multiplexer was connected together and thoroughly simulated in order to identify shortcomings and potentially fix them. During this phase the analog switches were resized in order for all specifications to be met.

5.2 Bootstrapped switch

The selected in section 2.3 analog switch schematic was implemented in the target CMOS technology and the circuit operation was assessed in terms of performance and robustness. The detailed schematic of the switch is shown in figure 5.1, this is the original schematic as presented by Lillebrekke et al. The Spectre™ simulator analog language VerilogA was used to describe the behavior of the non-overlapping clock generator and the input signal generator. This allowed to quickly switch

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36 Design Details

between different simulation set-ups.

Vdd swOFF NS5 N5 V out SW G D S V in ChrgHI A N3 N8 N1 N6 NS6 ChrgLO P2 B P4 P7 Vdd Cbootstrap ChrgLO ChrgLO ND

Figure 5.1: Detailed schematic of the bootstrapped switch presented in [2]

The primary objective of these initial simulations was to explore the design space and the main trade-offs for the design of the bootstrapped switch. As was expected, the bandwidth and linearity of the switch are highly dependent on the size of the pass transistor (denoted by SW in figure 5.1) and both increase by increasing the transistor width. Also, both linearity and bandwidth increase when a transistor with a lower threshold voltage and/or a thinner gate oxide is used as the main switch. The main loading effect for the switch in figure 5.1 is the output load capacitance, as such, its size also directly affects the performance.

5.2.1 Special design considerations

Originally, the selected bootstrapped switch circuit was designed for switched capacitor (SC) applications which have somewhat different requirements for the switch performance. This imposed different requirements on the design and re-quired some modifications of the original switch circuit.

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5.2 Bootstrapped switch 37

In order to achieve high clock rates in a switched capacitor circuit the switches are required to change state very fast and with minimum delay, in the multiplexer environment this is not the case as the switching time is not of particular interest. Actually, the time needed for the circuits following the multiplexer to resynchronize to a different video source is several orders of magnitude bigger than the time needed for any electronic switch to change state. Hence, the switching time is not taken into consideration when designing the bootstrapped switch.

Also, in order not to introduce significant noise and offset the switches for switched capacitor applications are required to keep the clock feedthrough and charge injection to a minimum. For the video multiplexer it is not a problem if a glitch is introduced at the output when inputs are switched as at that instant the video signal is not even processed further. Hence, the dummy transistor ND from the original circuit shown in figure 5.1 is removed and is not implemented in the final design.

Another big difference in the requirements for the switches designed for switched capacitor applications and those for the video multiplexer is the time for which the switch is supposed to continuously operate in the closed (on) state. For static switches like the transmission gate, for example, this is not a problem, but for the bootstrapped switch, which has a dynamic nature, the charge on the bootstrap capacitor has to be periodically refreshed to compensate for leakages. In SC cir-cuits, where switches are toggled with a few megahertz, this is done during the off-state (open). However, in the case of the video multiplexer, the witches must be closed continuously and cannot be turned off for charging, so there must be a mechanism provided for charging without opening the switch. This is achieved by adding the transistors N8, NS8 and P7 as shown in figure 5.3, this also means that now separate control signals are used for turning the switch off and for charging of the bootstrap capacitor. Since, in order to be recharged the bootstrap capaci-tor has to be disconnected from the main switch transiscapaci-tor terminals, the output signal will be significantly distorted during that time, therefore, the recharge cycle should be executed only during the blanking interval. However, due to the capac-itance present between the source and gate terminals of the main pass transistor the switch will continue to operate in the closed state.

During the initial simulations of the switch circuit it was discovered that a situation potentially damaging the switch circuit may occur. Consider the circuit as shown in figure 5.2, if the input voltage drops to a level such that the voltage at node B becomes lower than the supply voltage with more than the threshold voltage of P4, it will turn on and cause current to flow through the bootstrap capacitor, as shown in figure 5.2. Note that, the gate voltage of P4 is equal to its drain voltage (node B), hence it acts as a resistor for drain voltages higher than Vt. The resulting current will charge the bootstrap capacitor to the voltage

difference of the input and supply voltages, minus one threshold voltage. It is actually possible for negative voltages to appear at the input node which means that the bootstrap capacitor will be charged to a voltage bigger than the supply. For example, if the input voltage drops to 450 mV (the ESD protection operates at approximately 600 mV) and if the supply voltage is at its maximum of 1.2 V then the bootstrap capacitor will be charged to 1.2 V+450 mV-250 mV=1.4 V

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38 Design Details

(assuming that the threshold voltage is 250 mV). This voltage when applied to the gate-source terminals of the main pass transistor will significantly reduce the life of the circuit. Note, also that in some process corners the threshold voltage may be lower than 250 mV, further aggravating the situation.

Vdd swOFF NS5 N5 V out SW G D S V in ChrgHI A N3 N8 N1 N6 NS6 ChrgLO P2 B P4 P7 Vdd Cbootstrap ChrgLO

Figure 5.2: Harmful current through the bootstrap capacitor due to low negative input voltages.

The problem is solved by the addition of the transistor PS4 as shown in figure 5.3. During the on phase the control signal, and thus the gate of P4s, is at a high voltage, approximately equal to the positive supply, this means that the transistor PS4 will stay off for any voltage at node B lower than the supply. For voltages at node B higher than the supply, PS4 will turn on, but this is not a problem since transistor P4 will then be off.

The switch schematic shown in figure 5.3 is the actual schematic implemented in the input multiplexer.

Design of an Input Multiplexer for Video Applications

Institutionen för systemteknik

Department of Electrical Engineering

Examensarbete

Design of an Input Multiplexer for Video

Applications

Design of an Input Multiplexer for Video

Applications

Examensarbete utfört i Elektroniksystem

vid Tekniska högskolan i Linköping

av

Abstract

Acknowledgments

Contents

List of Figures

List of Tables

Chapter 1

Introduction

1.1

Purpose and goals

1.2

Project scope

1.3

Target CMOS process description and

fea-tures

1.4

Video digitizer overview

1.5

Analog video signals

1.5.1

Monochrome video

1.5.2

Color video

1.5.3

Voltage levels

1.5.4

Signal coupling and termination

Chapter 2

Analog Multiplexers and

Switches

2.1

Introduction

2.2

The MOS transistor as a switch

2.2.1

Transmission gate

-

2.2.2

Bootstrapping techniques

2.3

The implemented analog switch

2.3.1

Bootstrapped switch—principle of operation

clk1

clk2

Chapter 3

DC restore block

3.1

The need for DC restoration

3.2

Voltage-mode DC clamp

3.3

Current-mode DC clamp with current sources

3.4

Current-mode DC clamp without current

sources

3.4.1

The implemented DC clamp

Chapter 4

Analog Multiplexer

-performance metrics

4.1

Bandwidth

4.2

Linearity

4.3

Inter-channel isolation

4.4

Clamp circuit performance metrics

4.5