A “Divide-by-Odd Number” Injection-Locked Frequency Divider.

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Institutionen för systemteknik

Department of Electrical Engineering

Examensarbete

A “Divide-by-Odd Number” Injection-Locked

Frequency Divider.

Examensarbete utfört i Elektroniska Komponenter vid Tekniska högskolan vid Linköpings universitet

av

Malik Summair Asghar

LiTH-ISY-EX--13/4653--SE

Linköping 2012

Department of Electrical Engineering Linköpings tekniska högskola Linköpings universitet Linköpings universitet SE-581 83 Linköping, Sweden 581 83 Linköping

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A “Divide-by-Odd Number” Injection-Locked

Frequency Divider.

Examensarbete utfört i Elektroniska Komponenter

vid Tekniska högskolan i Linköping

av

Malik Summair Asghar

LiTH-ISY-EX--13/4653--SE

Handledare: Prof. Michael Peter Kennedy, FIEEE

Electrical and Electronic Engineering, University College Cork

Examinator: Prof. Atila Alvandpour

isy, Linköpings universitet

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Avdelning, Institution Division, Department

Division of Electronic Devices Department of Electrical Engineering Linköpings universitet

SE-581 83 Linköping, Sweden

Datum Date 2012-12-15 Språk Language Svenska/Swedish Engelska/English Rapporttyp Report category Licentiatavhandling Examensarbete C-uppsats D-uppsats Övrig rapport

URL för elektronisk version

http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-88014 http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-88014 ISBN — ISRN LiTH-ISY-EX--13/4653--SE Serietitel och serienummer Title of series, numbering

ISSN —

Titel

Title A “Divide-by-Odd Number” Injection-Locked Frequency Divider.

Författare Author

Malik Summair Asghar

Sammanfattning Abstract

The use of resonant CMOS frequency dividers with direct injection in frequency synthesizers has increased in recent years due to their lower power consumption compared to conventional digital prescalers. The theoretical and experimental aspects of these dividers have received great attention. This masters thesis work is a continuation of earlier work, based on the fundamentals of Injection-Locked Frequency Dividers (ILFD’s). The LC CMOS ILFD with direct injection is well-known for its divide-by-2 capability. However, it does not divide well by odd numbers. The goal of this master thesis work is to modify the LC CMOS ILFD with direct injection so that it can divide equally well by odd and even integers.

In this master thesis report, an introduction to the basic concepts behind Injection-Locked frequency dividers is first presented. Some of the previous work and the background of a reference LC CMOS ILFD design are studied. The author, studied the reference design, and the experimental setup used for characterizing it’s locking behavior. The algorithm used to characterize the locking behavior of this ILFD are explored to reproduce the results for divide-by-even numbers for the existing ILFD topology. Using a Spice model these results are also reproduced in simulations.

Over the years, numerous ILFD circuit topologies have been proposed, most of which have been optimized for division by even numbers, especially divide-by-2. It has been more difficult to realize division by odd numbers, such as divide-by-3. This master thesis work develops a simple modification to an LC CMOS injection locked frequency divider (ILFD) with direct injection, which gives it a wide locking range both in the by-odd number” mode and in the conventional “divide-by-even number” regime, thereby opening up applications which require frequency division by an odd number. The work presents the circuit architecture, SPICE simulations and experimental validation.

Nyckelord

Keywords Injection-Locked Frequency divider (ILFD), Phase Locked Loop(PLL), Frequency divider (FD)

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Abstract

The use of resonant CMOS frequency dividers with direct injection in fre-quency synthesizers has increased in recent years due to their lower power con-sumption compared to conventional digital prescalers. The theoretical and experi-mental aspects of these dividers have received great attention. This masters thesis work is a continuation of earlier work, based on the fundamentals of Injection-Locked Frequency Dividers (ILFD’s). The LC CMOS ILFD with direct injection is well-known for its divide-by-2 capability. However, it does not divide well by odd numbers. The goal of this master thesis work is to modify the LC CMOS ILFD with direct injection so that it can divide equally well by odd and even integers.

In this master thesis report, an introduction to the basic concepts behind Injection-Locked frequency dividers is first presented. Some of the previous work and the background of a reference LC CMOS ILFD design are studied. The author, studied the reference design, and the experimental setup used for characterizing it’s locking behavior. The algorithm used to characterize the locking behavior of this ILFD are explored to reproduce the results for divide-by-even numbers for the existing ILFD topology. Using a Spice model these results are also reproduced in simulations.

Over the years, numerous ILFD circuit topologies have been proposed, most of which have been optimized for division by even numbers, especially divide-by-2. It has been more difficult to realize division by odd numbers, such as divide-by-3. This master thesis work develops a simple modification to an LC CMOS injection locked frequency divider (ILFD) with direct injection, which gives it a wide locking range both in the by-odd number” mode and in the conventional “divide-by-even number” regime, thereby opening up applications which require frequency division by an odd number. The work presents the circuit architecture, SPICE simulations and experimental validation.

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Acknowledgments

First of all I would like to thank Almighty Allah,who gave me strength and knowledge to carry out my masters degree and thesis work. I would like to thank my parents and family who were always there to provide me with moral support and gave me the confidence to accomplish my study tasks.

Secondly, I would like to pay my deepest gratitude to my respected supervi-sor Prof. Michael Peter Kennedy for providing me with the opportunity to work on this project. I feel very blessed to work under his dynamic and encouraging supervision. He is a man of responsibility, divergent knowledge, sharp thinking ability, producing multiple solutions and having excellent leading skills. His guide-lines and knowledge not only helped me with this project but will also remain as a useful asset for my future life, educational and professional career.

Further more, I would like to thank my examiner Prof.Atila Alvandpour and my University, Linköping University, for providing me with the opportunity to do my master thesis as an ERASMUS exchange student and also for helping me out in all administrative issues. I would also like to thank University College Cork Ireland and Tyndall National Institute for providing me with this valuable opportunity to study in Ireland.

Lastly, I would like to thank my classmate M.A.Awan and two UCC students Huiyuan Xing and Xi Wu for their initial guidelines and support for this project. Here, I would like to mention my gratitude for the cooperation and support pro-vided by the MCCI team in Tyndall for the cadence support. This work was supported in part by Science Foundation Ireland under grant 08/IN.1/I854 and by the European Commission under the ERASMUS program.

I hope this work will be a stepping stone for all researchers and future work in the field of Injection-Locked Frequency Dividers.

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Introduction

This chapter provides a brief introduction to the project and the context. Sec-tion 1.1 provides a brief introducSec-tion to applicaSec-tions of PLL based frequency syn-thesizers while Section 1.2 talks about the objectives of this project, highlighting some of the previous and current work in the field of ILFD’s.

1.1 PLL Synthesizer and ILFD

A frequency synthesizer is an electronic system for generating a range of frequen-cies. Frequency dividers (FD) are widely used as building blocks in the imple-mentation of Phase Locked Loops (PLL) based frequency synthesizers for both wireless and wire line communications [1]. The power consumption of the divider is an important consideration when it is integrated into a complete system, partic-ularly in the case of portable communication devices. Nowadays, these have a lot of applications such as GPS systems, radio receivers, radio telephones, mobile tele-phones satellite receivers, etc. Frequency synthesizers are capable of generating a required output signal by combining frequency division, frequency multiplication, and frequency mixing operations. Phase-locked loop based synthesizers are widely used in current wireless applications.

A phase locked loop (PLL) is a feedback control system. A phase detector (PD) compares the phases of its two input signals and, depending on the differ-ence between them, it generates a proportional error signal.The error signal then goes through a low pass filter and afterwards is used as a control voltage for a voltage-controlled oscillator (VCO) which generates an output signal frequency.

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8 Introduction

The output signal frequency is then fed back to the phase detector through a frequency divider, producing a negative feedback loop [2].

Figure 1.1: A simple frequency synthesizer comprised of a PLL.

A simple frequency synthesizer comprised of a PLL is shown in Fig. 1.1. It contains a phase detector (PD), a low-pass filter (LPF), a voltage-controlled oscillator (VCO), and a frequency divider (FD) [3]. The output signal frequency foutis divided to a lower frequency fdivwhich is then locked to the phase of a fixed

reference signal with frequency fref. As can be seen from Fig. 1.1, the frequency

divider comprises two sub blocks. One is called a prescaler; it divides by a fixed number Np. The second one is a programmable divider which divides by a rational

number Nv/M , where Nv and M are positive integers. When the loop is in the

lockes condition, then

Fout=

N

MFref. (1.1)

where N =NpNv. If M =1, the synthesizer is called an integer-N synthesizer.

Otherwise, if M 6= 1, the synthesizer is called a fractional-N synthesizer. The role of the prescaler is to divide the output frequency by a positive integer and to pass this signal to a programmable divider [4]. The prescaler is the focus of the master thesis work carried out in this project.

An Injection-Locked Frequency Divider (ILFD) is capable of dividing an input injection signal with a high frequency to produce an output signal with a lower frequency with a fixed frequency ratio between the injected input signal frequency and the output signal frequency.

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1.2 Objectives 9

The key parameters of an ILFD are:

1. The rotation number ρ: This is the ratio of the input signal frequency to the output signal frequency.

2. The locking range (LR): For a given rotation number ρ, the range of the input signal frequency over which the output signal frequency is rationally locked to the input signal frequency is called the locking range.

3. Phase Noise: The circuit noise can disturb the oscillator’s output phase. Generally, all oscillators possess an amplitude-limiting phenomenon so, at the output of the oscillator, phase noise dominates [5].

1.2 Objectives

The use of digital frequency dividers is constrained at high frequencies by their high power consumption which increases rapidly with frequency [6]. As an alter-native, analog frequency dividers have lower power consumption and high speed and frequency capabilities [7]. FDs can be realized using Common Mode Logic (CML) [8], [9], dynamic logic [10], Miller dividers [11] and Injection Locked Fre-quency Dividers (ILFD) [12]. Compared to CML and Miller dividers, the power consumption of an ILFD does not increase significantly with frequency.

An ILFD is an electronic oscillator which produces an output signal whose period (equivalently, zero-crossing rate) is rationally related to that of the input signal [13]. When there is no injected input signal, the oscillator oscillates with a free-running frequency f0. When an injection signal Viis applied with a frequency

fs, then the output signal Vo oscillates with a frequency fd. The ratio of fs/fd

is called the rotation number, denoted by ρ [14]. This locking behavior is due to the nonlinear phenomenon of synchronization, also known as entrainment or 1 : m order injection locking [15]–[17].

The advantage of the ILFD is that it has the potential for low power operation because the relatively small perturbation by the input signal does not significantly affect the power consumption of the underlying oscillator [18]. However, ILFDs have two major drawbacks. Firstly, they are poorly understood from a theoretical point of view, despite a long history of research and significant progress since the advent of computational nonlinear dynamics [16, 17]. Secondly, the ILFD is bandpass in nature, meaning that it divides correctly only over a small range of frequencies. This is related to the entrainment phenomenon; the oscillator locks to the perturbing input signal with the correct frequency division ratio ρ only over a limited range of frequencies, the so-called Locking Range (LR).

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10 Introduction

Circuit topologies which realize frequency division by even numbers, e.g.divide-by-2 prescalers, have been studied extensively in the literature [19]–[25]. In order to avoid pulling in transceivers, there is a demand from frequency planners for division by numbers other than two, and in particular, division by odd numbers. In recent years, frequency division by odd numbers, particularly divide-by-3, has received increasing attention.

Jang et al. [26] and Lee et al. [27] use CMOS LC oscillator circuits with multiple inductors. In the circuit schematic shown in Fig. 1.2, the drain current Id

of the MOS M 5 at which the injection voltage Viis applied contains odd harmonic

frequency components at ωo and 3ωo [26]. The third harmonic component of the

current at 3ω0 sees a higher impedance load composed of two inductors than the

fundamental drain current harmonic component at ω0. The third harmonic of

the MOS M 5 drain voltage is fed back to the gate of the MOS M 5 through a parasitic gate-drain capacitor, so that the gate voltage of MOS M 5 has a third-order harmonic component. This, in turn, allows the circuit to realize a divide-by-3 locked signal. Most of the chip area and power are consumed by the inductors. Consequently, this circuits occupies a large chip area due to multiple inductors and also has a large power consumption.

Figure 1.2: Jang et al. [26] use a CMOS LC oscillator circuit with multiple induc-tors.

The main objective of this master thesis is to study an existing topology of LC CMOS ILFD, and specifically to modify it so that it has wide locking regions

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1.2 Objectives 11

with odd rotation numbers. In this thesis, we propose a simpler circuit, also based on a CMOS LC oscillator, but with a single inductor. We describe the conventional divide-by-2 oscillator on which this work is based and the method which we have used to characterize its locking behavior. Furthermore, we introduce our modification to the CMOS LC oscillator with direct injection which makes it suitable for division-by-odd numbers.

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Chapter 2

Background and Previous

Work

This chapter presents background information about ILFDs by explaining the existing topologies and exploring previous work done in this field.

Section 2.1.1 describes the classical topology of an ILFD with tail injection while Section 2.1.2 talks about the improved technique of an ILFD with direct in-jection. Section 2.2 discusses bifurcation theory and the Arnold’s tongues scenario of locking regions. Section 2.3 describes the method of the devil’s staircase for characterizing rotation numbers. Section 2.4 explains the brute force method for finding the boundaries of Arnold tongues. Section 2.5 gives an overview of various research results in the field of ILFDs prior to this work.

2.1 LC CMOS Injection Locked Frequency

Di-viders

An injection-locked frequency divider (ILFD) is an oscillator to which a periodic input is applied.This input signal is regarded as the injection signal. ILFDs are generally categorized into two basic topologies: One is indirect injection through the tail and the other is direct injection.

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14 Background and Previous Work

2.1.1 LC CMOS ILFD With Tail Injection

These days, a widely used LC CMOS differential injection-locked oscillator topol-ogy is the LC CMOS ILFD with tail injection [19]. The circuit diagram of an LC CMOS ILFD with tail injection is shown in Fig. 2.1.

Vi

V_in

M

₅

Figure 2.1: LC CMOS ILFD With Tail Injection.

The main disadvantages of this classical topology is its large input capacitance and its small input locking range.Furthermore, the single-ended input is considered to have less advantages when a VCO and divider are integrated on chip.The small locking range of the LC CMOS with tail injection is due to the inefficient injection path through the tail transistor M 5. The injected current of M 5 vanishes into the capacitance of the tail node when we operate at higher frequencies. Similarly, an other disadvantage of this classical topology is that M 5 should have a large width in order to provide the input transconductance and tail DC current. Replacing the tail transistor (M 5) with an N P N transistor could give the benefit of higher transconductance. In order to avoid these problems, an LC CMOS ILFD with direct injection has been developed [19].

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2.1 LC CMOS Injection Locked Frequency Dividers 15

2.1.2 LC CMOS ILFD with Direct injection

We consider a direct injection locked frequency divider (ILFD) in this thesis. The circuit diagram of the LC CMOS ILFD under consideration is shown in Fig. 2.2.

V_i

Figure 2.2: LC CMOS ILFD With Direct Injection.

This LC CMOS ILFD comprises an oscillator and an additional transistor. The oscillator comprises an LC tank and four transistors (M 1-M 4). The LC tank has a capacitor in parallel with a series combination of an inductor and a resistor. The four transistors M1 to M4 include two PMOS transistors and two NMOS transistors.The four transistors M 1 to M 4 work as a negative resistance network. The additional transistor M 5 is an NMOS transistor and is used to couple the injected signal to the LC tank. When no injection signal is applied to M5, the circuit oscillates with an unforced frequency fowhich is also known as the natural

frequency. When we drive our circuit with an injected input signal Vi at frequency

fs then the output signal Vo acquires the frequency fd. The ratio of the input

signal frequency fsto the output signal frequency fd, namely fs/fd is called the

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locks to the injected signal in such a way that the frequency of the input signal is an integer multiple of the frequency of the output signal.

This improved topology with direct injection overcomes the drawbacks of the classical tail injection topology.The injected signal is provided directly through M 5, which can be designed much smaller than the tail transistor due to the more efficient injection scheme. The transistor M 5 acts as a switch which can be realized by an NMOS transistor or a PMOS transistor [19].

2.2 Arnold Tongue Scenario

Nonlinear dynamics provides a paradigm for frequency entrainment (injection lock-ing), namely the so-called standard circle map or sine map [28]. Consider a first (dependent) oscillator with an unforced frequency f0 that is driven by a second

(independent) oscillator with frequency fs. If the phase θ of the first oscillator is

sampled at the frequency of the second oscillator, then samples are described by a discrete time dynamical system of the form

θ[n + 1] = θ[n] + Ω − k

2πsin(2πθ[n]), (2.1)

where Ω= f0/fs is the ratio of the unforced and injected signals and k is

the strength of the coupling.The behavior of this system is summarized in a two dimensional bifurcation diagram, as shown in Fig. 2.3. The bifurcation diagram is organized into regions called Arnold tongues; inside each tongue, the rotation number is constant.

The abscissa (horizontal axis) in Fig. 2.3 shows the relative frequency of the injected signal and the ordinate (vertical axis) k is the strength of the coupling between the input signal and the oscillator. θ is the phase of the first oscillator. The bifurcation diagram is organized into regions called Arnold tongues; the rota-tion number ρ is constant inside each tongue.The bifurcarota-tion diagram in Fig. 2.3 shows Arnold tongues corresponding to rotation number 5/1, 4/1, 3/1, etc. [28].

In this work, we use a similar way to present the locking range for different constant rotation numbers, as shown in Fig. 2.4.

The main idea behind the synchronization of an oscillator and the applied input injected signal can be analyzed in terms of the locking regions which have a typical V-shape called Arnold tongues.The locking behavior is due to the non-linear phenomenon of synchronization. Fig. 2.4 shows locking regions in a typical

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2.2 Arnold Tongue Scenario 17

Figure 2.3: The bifurcation diagram explaining the locking behavior and the Arnold tongues .

Figure 2.4: LC CMOS ILFD With Direct Injection.

LC CMOS oscillator. The abscissa is the ratio fs/fd, the normalized injection

frequency. The ordinate is A, the amplitude if the injected signal. The triangular regions in Fig. 2.4 are called Arnold tongues.These correspond to the ranges of the input frequency over which the division ratio ρ is constant.The width of a tongue at a given input amplitude A is known as Locking range (LR). For a given rotation number ρ, there is a unique tongue which has a left boundary and a right

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boundary.The input frequency where these two boundaries meet is known as the center frequency. For every given rotation number ρ, the center frequency is given by ρ/√LC. For example, for ρ=2 the center frequency would be 2/√LC. These locking regions can be determined accurately by a variety of algorithms which we will discuss in Sec. 2.5.2.

2.3 Devil’s staircase

There is another simple and useful method to characterize the bifurcation diagram. It is known as the Devil’s staircase. The devil’s staircase is a monotonically in-creasing function of fs with horizontal levels of finite width at each rational value

of ρ. We can plot the Devil’s staircase by keeping the value of A fixed and taking a cross section through the bifurcation diagram. As can be seen in Fig. 2.5, the horizontal steps correspond to the different tongues. In each horizontal step of the devil’s staircase plot, the ratio ρ is constant [28].

Figure 2.5: Devil’s staircase diagram showing wide steps for ρ=2,4,6,8 and narrow steps for ρ=3,5,7.

For large values of A, there is overlap between the different tongues. In this region, the devil’s staircase can be useful to determine whether the tongues overlap or not. The overlapping of tongues corresponding to different rotation numbers

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2.4 Brute Force Method 19

leads to hysteresis effects and chaos [29].

2.4 Brute Force Method

The brute force method is another useful method, and it is the basis of the numeri-cal method described in Sec. 2.5.2, for determining the ranges of the different lock-ing regions of the ILFD. The brute force method calculates the rotation number on a grid of points which correspond to fixed values of frequency and amplitude. The distance between two consecutive measurement points is predefined and is known as the step size. The locking regions of the ILFD can be determined by calculating the ratio ρ at each point.The interval from the start boundary point to the end boundary point is known as the locking range for a specific rotation number. One of the major drawback of this method is the time required to find the locking regions for different rotation numbers. Also, it does not provide any information regarding the shapes of the Arnold tongues [29].

2.5 Previous work

Marc Tiebout [19] was the first to describe the CMOS Direct Injection-Locked fre-quency divider. In his paper [19], the author presented a novel circuit topology for ILFD’s to achieve a wider locking range, and experimentally verified the features. The classical Injection-locked frequency divider with direct injection topology by Tiebout is shown in Fig. 2.6.

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Daneshgar, et al. [3], [20], used bifurcation theory and presented a nonlinear approach to predict the widths of locking regions. They presented a nonlinear approach based on the applications of bifurcation theory to predict where the locking range is wider. Daneshgar supported his approach by simulations and experimental verification of the circuit ILFD.

Daneshgar, et al. [3], [20], focused their research experiments and simulation on the injection locked frequency diver with tail injection. They did not publish much on the injection locked frequency divider with direct injection.

Kennedy, et al. [30] carried on the next phase of this research. They reported a phenomenological study of the LC CMOS Injection Locked frequency divider with direct injection. In their work, they considered the effects of various factors on the locking behavior. These factors include the amplitude of the injected signal, the harmonic components of the injected signal, the size of the switching transis-tor, and the DC component of the switching transistor. They also presented a new algorithm for determining the boundary points of the locking regions for charac-terizing the ILFD behavior [4]. In their work, they analyzed the locking regions (Arnold’s tongues). The measured Arnold’s tongues produced in this paper [30] are shown in Fig. 2.7.

Figure 2.7: Measured locking regions in the LC CMOS ILFD with direct injection for ρ=2, 4 and 6 [30].

The measured Arnold Tongues can be separated into 3 regions. Region 1 cor-responds to the low amplitude forcing regime, which is modeled well by the classi-cal Arnold tongue paradigm. Region 2 shows some evidence of overlap. Here, the width of the divide-by-2 tongue grows rapidly with increasing amplitude, and the divide-by-4 tongue bends away to make room for it. In Region 3, the tongues are

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2.5 Previous work 21

again distinct. Their widths remain almost constant with the increasing amplitude of the perturbation signal. This region has been called a saturation region [30].

2.5.1 Divide by even number

In this section, we will discuss the divide-by-even number ILFD, which has been under consideration in previous work. We will describe the experimental charac-terization of the ILFD under test. Furthermore, we explain the circuit implemen-tation and the measurement setup used for the experiments. We will briefly give a description about the algorithms used for the experimental characterization of the locking regions for the ILFD under test. In the end, we will reproduce the pre-vious experimentally measured results for the circuit under test by using various algorithms and analyze these results.

2.5.1.1 Experimental Characterization

Beyond the theory of the Injection locked frequency divider, an experimental char-acterization of different topologies of ILFD’s is necessary. In this section, we will explain and physically realize the circuit topology of the ILFD which has been under consideration in previous research work.

The circuit under test is the LC CMOS ILFD with direct injection, as shown in Fig. 2.2.

To get started with the experimental characterization of the ILFD under test we built a physical prototype of the circuit with discrete components on a breadboard. The breadboard implementation of the LC CMOS ILFD with direct injection is shown in Fig. 2.8.

In our design, we use Texas Instruments CD4007UBE CMOS DUAL COM-PLEMENTARY PAIR PLUS INVERTER for the implementation of the five tran-sistors (M 1-M 5). The CD4007UBE comprises three PMOS trantran-sistors and three NMOS transistors.

In the circuit implementation on the breadboard, two CD4007UBE chips are used. On the first chip, two PMOS transistors (M1 and M2) and two NMOS transistors (M3 and M4) form the core of the ILFD.These two cross-coupled pairs of CMOS inverters act as a negative resistance. On the second CD4007UBE chip the fifth NMOS transistor M 5 is implemented which acts as an input switch through which the injected signal is coupled. M 5 is implemented on another chip because when it is required to increase the size of the NMOS transistor, it can be

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Figure 2.8: LC CMOS ILFD With Direct Injection on Breadboard.

done by using NMOS transistors available on the second chip. It is implemented by connecting three NMOS transistors in parallel.The input transistor M 5 couples the injection signal Vithrough an RC bias network. The values of the components

of the LC tank are shown in the Table 2.1. These values were used in previous research [30] and are used in this work also.

Component Value Units Resistor R 235 Ω Capacitor C 57 pF Inductor L 1246 µH

Table 2.1: Component values of the LC Tank

The circuit is powered by two DC power supplies. One power supply provides 9V DC as V DD while the other power supply provides the DC bias component for the injected input signal. The latter can produce an offset ranging from 0V to 9V DC.

2.5.1.2 Measurement Setup

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Figure 2.9: Measurement Setup.

In the measurement setup, we are using an Agilent 33250A function genera-tor to provide the sinusoidal component of the injected signal. The generagenera-tor is controlled by the computer, which is used to set the frequency fsand amplitude A

of the input sinusoidal signal. The ILFD under test is labeled Nonlinear Oscillator in Figure 3.7. We are using an Agilent 53132A universal counter to calculate the ratio between the frequencies of the input signal and the output signal and also determining the boundary points of the locking regions. We observe the input and output signals using a Tektronix TDS3034B oscilloscope. We connect a PC to the instruments with GPIB cables. The instrument control, data acquisition, and processing algorithms are programmed using LabView. The acquired data is then post-processed using Matlab to calculate the Arnold tongues corresponding to different locking regions

2.5.2 LabVIEW Algorithms

LabVIEW is the abbreviation for Laboratory Virtual Instrumentation Engineering Workbench. LabView is a system design platform which makes use of a visual pro-gramming language. LabVIEW can perform a variety of tasks such as instrument control, data acquisition, and industrial automation. Over the years, a number of different methods and tools have been used by researchers to characterize the locking behavior of ILFD’s. Some of these were explained briefly in the previ-ous sections. To analyze and measure the characteristics and locking behavior of ILFD’s over large amplitude and frequency ranges, an efficient LabVIEW algo-rithm should be used. There are three LabVIEW algoalgo-rithms which the author studied and analyzed for finding the boundary points and the characteristics of the locking behavior of the ILFD under test. These are;

1. Frequency Sweeping 2. Boundary Following

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3. Boundary Finding.

In the Appendix A, a brief description of all the three LabView algorithms is given for the understanding of the reader.

2.5.3 Experimental Results

In the previous section three LabVIEW algorithms were mentioned. In this section, we present results for these algorithms when applied to the LC CMOS ILFD with direct injection shown in Fig. 2.2. The results are produced for the different divide ratios by post processing using Matlab.

2.5.3.1 Frequency Sweeping Results

Experimentally measured results plotted using the frequency sweeping algorithm are shown in the Fig. 2.10. The frequency interval is 5 kHz and amplitude interval is 0.1V . The injection input signal has a DC bias of 6.03V and is applied to the input transistor M 5 with single length and single width. From the plot, it is clear that the divide-by-even regions are wider and the divide-by-odd regions are narrower. The divide-by-3 region disappears when the amplitude is above 3V . Therefore, the LC CMOS ILFD with direct injection under test can divide by even division ratios but is not good at dividing by odd numbers. The Matlab code used for post processing the acquired data is shown in Appendix B.

Figure 2.10: Experimental results forthe Frequency Sweeping algorithm applied to the LC CMOS ILFD with direct injection in Fig. 2.2 .

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2.5.3.2 Boundry Following Results

The experimentally measured results using the Boundary following algorithm are shown in Fig. 2.11. The plot exhibits similar tongues to the frequency sweeping algorithm as expected. The by-even locking regions are wide and the divide-by-odd locking regions are very narrow. The Matlab code used for post processing is shown in Appendix B.

Figure 2.11: Experimental results for the Boundary following algorithm showing locking regions corresponding to ρ=2, 3, 4, 5, 6 and 7.

2.5.3.3 Boundry Finding Results

The experimentally measured results using the boundary finding algorithm are shown in Fig. 2.12. From the plot it can be seen that the divide-by-even num-ber locking regions are much wider than the divide-by-odd locking regions. The tongues becomes almost vertical when the injected input signal amplitude is larger than 3.5 V . The Matlab code used for post processing is shown in Appendix B.

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Figure 2.12: Experimental results for the boundary finding algorithm showing locking regions coressponding to ρ=2, 3, 4, 5, 6 and 7.

2.5.4 Analysis

In previous section, we presented experimental measured results from the three labVIEW algorithms showing the locking behavior of the LC CMOS ILFD with direct Injection. From the three sets of results, it can be seen that the division ratios ρ=2,4,6,8 (divide-by-even) have wide locking ranges. The division ratios ρ=3,5,7 (divide-by-odd) are very narrow and disappear with increasing input signal amplitude. Moreover the Divide-by-2 and divide-by-4 locking regions for the LC CMOS ILFD with direct injection are wider then the LC CMOS ILFD with tail injection [4]. Furthermore, the slopes of the boundaries of the divide regions increase and become almost verticall when the injected input amplitude goes above 3.5 V . This phenomenon was first observed experimentally and reported in [4] and has been reproduced by the author.

From the experimentally measured results, it can be concluded that the device under test, the LC CMOS ILFD with direct injection shown in Fig. 2.2, can divide

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by ρ=2,4,6,8 very well. But it is not as effective at dividing by ρ=3,5,7. This motivates the design of a variant of this circuit which will advance the state of the art by being able to divide as effectively by odd numbers as by even ones.

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Chapter 3

Divide-by-Odd Number

The use of resonant CMOS frequency dividers with direct injection in frequency synthesizers has increased in recent years due to their lower power consumption compared to conventional digital prescalers. Numerous circuit topologies have been proposed, most of which have been optimized for division by even numbers, especially divide-by-2. It has been more difficult to realize division by odd num-bers, such as divide-by-3. This chapter describes a simple modification to a CMOS injection locked frequency divider (ILFD) with direct injection, which gives it a wide locking range both in the “divide-by-odd number” mode and in the con-ventional “divide-by-even number” regime, thereby opening up applications which require frequency division by an odd number.

This chapter presents the circuit architecture and experimental validation of its operations. Section 3.1 proposes a modified ILFD with direct injection. Sec-tion 3.2 explains the circuit architecture, the measurement setup, the algorithms used for experimentally characterizing the ILFD under test and the experimentally measured results. Section 3.3 shows the symmetric circuit architecture and the experimental results for it and in the last Section 3.4 these results are analyzed.

3.1 Developed Model

We consider a direct injection locked frequency divider (ILFD) in this work. The circuit diagram of the modified LC CMOS ILFD under consideration is shown in Fig. 3.1.

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30 Divide-by-Odd Number

C5

V_i

Figure 3.1: Modified LC CMOS ILFD with direct injection for Divide-by-Odd number.

The modified LC CMOS ILFD comprise an oscillator with an additional transistor and capacitor. The oscillator comprises an LC tank and four transistors. The LC tank has a capacitor in parallel with a series combination of an inductor and a resistor. The four transistors M 1 to M 4 include two P M OS transistor and two N M OS transistors.The four transistors M 1 to M 4 work as a negative resistance network. The additional transistorM 5 is an N M OS transistor and is used to couple the injected signal to the LC tank(so-called direct injection). We introduce an additional capacitor between the gate and drain of M 5. When no injection signal is applied to M 5, the circuit oscillates with an unforced frequency f0. When we drive our circuit with an injected input signal Vi at frequency fs,

the output signal V0 has a frequency fd. The ratio of the input signal frequency

fsto the output signal frequency fd, namely fs/fd, is called the rotation number,

denoted by ρ. Under appropriate conditions, the output signal locks to the injected signal in such a way that the frequency of the input signal is an integer multiple of frequency of the signal. With this circuit, we can get both even (divide-by-2) and odd (divide-by-3) rotation numbers over ranges of the input frequency of similar width.

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3.2 Experimental Characterization 31

3.2 Experimental Characterization

Beyond the theory of Injection locked frequency divider, an experimental char-acterization of the developed ILFD is necessary. In this section, we explain and physical realization of the ILFD under consideration. Furthermore, the experi-mental setup which is used in the laboratory for observing the locking behavior of the ILFD under test will be explained.

3.2.1 ILFD on Bread-Board

To get started with the experimental characterization of the ILFD under test, we built a physical prototype of the circuit with discrete components on a breadboard. Fig. 3.2 shows the modified LC CMOS ILFD with direct injection on a breadboard.

Figure 3.2: ILFD implementation On bread-board.

In our design, we use Texas Instruments CD4007UBE CMOS DUAL COM-PLEMENTARY PAIR PLUS INVERTER for the implementation of the five tran-sistors (M 1-M 5). The CD4007UBE comprises three PMOS trantran-sistors and three NMOS transistors.The pin assignment of the CD4007UBE, as provided on the data sheet, is shown in the Fig. 3.3.

In the circuit implementation on the breadboard, two CD4007UBE chips are used. On the first chip, two PMOS transistors (M1 and M2) and two NMOS transistors (M3 and M4) are used to form the core of the ILFD.These two cross coupled pairs of CMOS inverters act as a negative resistance. On the second CD4007UBE chip, the fifth NMOS transistor M 5 is implemented; this acts as an

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Figure 3.3: Pin assignment of CD4007UBE.

input switch through which the injected signal is coupled. M 5 is implemented on another chip. When it is required to increase the size of the NMOS transistorM 5, this is achieved by connecting three NMOS transistors in parallel. An additional capacitor C5 connects the gate to the drain of the input transistor M 5.

3.2.2 Components and Parameters

We are using CD4007UBE transistors manufactured by Texas Instruments. The additional capacitance C5 is 560 pF . The values of the components in the RLC

tank are shown in the Table 3.1

Component Value Units Resistor R 235 Ω Capacitor C 57 pF Inductor L 1246 µH

Table 3.1: Component values of the LC Tank

The injection input signal voltage Vi is applied through an RC bias network,

which is shown in the Fig. 3.4.

The injected input signal is generated by combining a sinusoidal AC signal wave with a DC component, using a resistor and a capacitor. This resistor and

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Figure 3.4: RC network for combining Vac and Vdc.

capacitor network is used because we cannot directly combine two different voltage sources. In the circuit diagram, the input injected signal Vinis a sinusoidal voltage

with 6.03V DC offset, whose amplitude and frequency can be controlled separately. While performing the experiment, the injection input signal was separated into two parts. The first part consists of an AC sinusoidal signal wave Vacand the second

part adds a DC component Vdc of 6.03 V . These two parts were combined using

a resistor and a capacitor network. Equation (3.1) shows how the resistor and capacitor network combines the two signals:

Vin= Vdc+

R

R + _jωC1 × Vac, (3.1)

If the values of R and C are sufficiently large, we can ignore the term _jωC1 , and, at frequencies of interest, i.e. 100kHz<fs<2MHz, the RC network has no

effect on the ac component Vac, i.e:

R

R + _jωC1 ≈ 1 (3.2)

The input sinusoidal voltage signal Viis applied with a 6.03V DC offset. The

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Component Value Units Resistor R 100 KΩ. Capacitor C 57 pF DC Offset Vdc 6.03 V .

Table 3.2: Component values of the RC Network

The circuit is powered by two DC power supplies. One power supply provides 9V DC as V DD while the other power supply provides the DC bias component for the injected input signal. The latter is adjustable to produce an offset ranging from 0V to 9V DC.

3.2.3 Differential Signal

At first, the output signal which is required is the single-ended output of the LC tank. Afterwards, the differential signal is also analyzed to measure the differential signal between the two nodes of the LC tank. To achieve this, an instrumentation amplifier was built using discrete components on a breadboard. The instrumenta-tion amplifier’s circuit diagram is shown in Fig. 3.5.

Figure 3.5: Instrumentation Amplifier for getting differential output. The instrumentation amplifier is implemented by using three LT1229 Dual 100MHz Current Feedback Amplifiers maunfactured by Linear Technology. The pin assignment of the LT1229, as provided by the data sheet, is shown in Fig. 3.6. The instrumentation amplifier is powered by ± 15V DC. This instrumentation amplifier adds the two single-ended outputs and gives a single differential output:

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Figure 3.6: Pin assignment of LT1229 Instrumentation Amplifier.

Vout= Va− Vb (3.3)

3.2.4 Measurement Setup

The experimental set-up in the laboratory is shown in Fig. 3.7.

Figure 3.7: Measurement Setup.

In the measurement setup, we are using an Agilent 33250A function generator to provide the sinusoidal component of the injected signal. The ILFD under test is the Nonlinear Oscillator in Fig. 3.7. We are using an Agilent 53132A universal counter to calculate the ratio between the frequencies of the input signal and the

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output signal and also the boundary points of the locking regions. We observe the input and output signals using a Tektronix TDS3034B oscilloscope. We connect a PC to the instruments with GPIB cables. The instrument control, data acquisi-tion, and processing algorithms are programmed in LabVIEW. The acquired data is post processed using Matlab to observe the Arnold tongues corresponding to different locking regions.

3.2.5 Algorithms

In our work, we use the boundary finding algorithm implemented in LabVIEW which is explained in the Sec. A.3, in order to characterize the ILFD over large ranges of frequencies and amplitudes of the injected signal. For different values of rotation number (i.e. 2,3,4,5,6,7), the LabVIEW program generates an output file which consists of the boundary points of the locking regions corresponding to the selected rotation numbers.

Afterwards, we use Matlab to plot the boundary points for these rotation numbers.

3.2.6 Experimental Results

The experimentally measured Arnold tongues corresponding to ρ =2,3,4,5,6,7 were post processed using Matlab and are shown in Fig. 3.8.

The frequency fs of the input signal is plotted on the abscissa of the

two-dimensional bifurcation diagram and the amplitude A on the ordinate. The ap-proximately triangular regions, called Arnold tongues, correspond to ranges of the input over which the rotation number ρ (equivalently, the division ratio) is con-stant. The width of a tongue at a given input amplitude is the Locking Range (LR). By contrast with the standard circuit, tongues corresponding to even and odd division ratios have similar widths in the modified circuit. This means qual-itatively that the circuit can divide by odd numbers as well as by even ones. In particular, the locking range for divide-by-3 is comparable in size to that for divide-by-2.

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3.3 Symmetric Circuit 37

Figure 3.8: Experimentally measured Arnold tongues corresponding to ρ =2,3,4,5,6 and 7 in the modified circuit of Fig. 3.1 .

3.3 Symmetric Circuit

In order to simplify the analytical analysis of the circuit, the circuit is made symmetric by adding an injection through a PMOS and a capacitor C6.The new developed symmetric circuit for direct injection locking Frequency divider is shown in Fig. 3.9. The proposed changes to previous Asymmetric ILFD with direct injection are highlighted with red lines.M 6 is complementary to M 5, and C6 is equal to C5. Essentially, the ILFD is driven now symmetrically.

3.3.1 Components and Parameters

I am using CD4007UBE transistors manufactured by Texas Instruments. The additional capacitance C5 and C6 are 560 pf. The parameters of Components of LC tank are similar to the Asymmetric ILFD.

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Figure 3.9: Symmetric Circuit of the ILFD with direct injection.

I am applying the input signal Vin as differential inputs through two RC

networks. I am applying the -Vininput signal as a sinusoidal voltage with a 6.03 v

DC offset at the gate of M 5. Similarly I apply the +Vininput signal as a sinusoidal

voltage with a 2.97 V DC offset at the gate of M 6. The parameters of components of RC networks are similar to the Asymmetric ILFD.

The -Vin input signal is generated by using a simple inverting amplifier

(LT1229) to get the 180 degree phase shifted signal.

3.3.2 Experimental Results

The experimentally measured Arnold tongues corresponding to ρ =2,3,4,5,6,7 were post processed using Matlab and are shown in Fig. 3.10.

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3.4 Analysis 39

Figure 3.10: Experimental Results for the Symmetric Circuit of the ILFD with direct injection.

3.4 Analysis

From Fig. 3.10, it can been seen that the tongues for the divide regions corre-sponding to ρ = 2 and 3 are of similar width. The divide region for 3 is signif-icantly wider in this work than in previous works which did not include C5 and

C6. Therefore, the proposed model can divide both by even and odd numbers.

This phenomena was first observed experimentally and then reproduced in simula-tions.The phenomenon has been reported in a conference paper [32] and a patent application [34].

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Chapter 4

Modeling and Simulations

In this chapter, we will discuss the simulations of the divide-by-odd number LC CMOS ILFD with direct injection. Section 4.1 describes the Spice model and the MOSFET model used. It talks about the Spice algorithm used for capturing the locking behavior of the ILFD and describes the corresponding Matlab post processing algorithm. Finally, it shows the Spice simulation results. Section 4.2 describes the implementation of the Symmetric circuit of the LC CMOS ILFD with direct injection by explaining the schematic and simulation results. Finally, section 4.3 gives an overall analysis of the simulation results.

4.1 Modeling and Spice Simulations

In the simulation part of this project, we built a model circuit using Spice, which is intended to replicate the experiments. Spice can predict the circuit behavior and works in the same way as the Frequency Sweeping method which we described earlier. Spice produces its output in the form of an ASCII listing. The listing con-sists of columns of numbers corresponding to calculated outputs V oltages and/or Currents. Therefore, a MATLAB program is needed to post process the output of Spice in order to plot the bifurcation diagrams.

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42 Modeling and Simulations

4.1.1 Spice Model

SPICE is a general purpose open source analogue electronic circuit simulator. It is a powerful program that is used in integrated circuit and board-level design to check the integrity of circuit designs and to predict circuit behavior.

The Spice model under consideration is shown in Fig. 4.1. The schematic is the same as in Fig. 3.1 except for the parasitic output network. In our experiments, we use Texas Instruments CD4007UBE CMOS DUAL COMPLEMENTARY PAIR PLUS INVERTER, which have 3 complementary logic inverters. Each inverter has an input capacitance and an output load capacitance and resistance. Therefore, for matching the experimental results to simulations we add parasitic networks at both outputs in our Spice model. While performing simulations, the most important factor is the MOSFET model. In this project, the basic aim was to match the simulations to experiments for divide-by-odd numbers. Therefore, many types of MOSFET models were tried to get the best results.

C3 180pF R3 160K C4 180pF R4 160K R2 98.7 C5 560pF

Figure 4.1: H-Spice Circuit schematic of the developed Divide-by-Odd ILFD.

The complete Spice code/Spice net-list for the circuit schematic shown in Fig. 4.1 is given in Appendix C.

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4.1 Modeling and Spice Simulations 43

4.1.2 MOSFET Models

In the simulation, the most important component is the MOSFET model. A transistor model is classified according to the level of sophistication, e.g. level 1, 2 or 3. The higher the level, the more precise and detailed the MOSFET model is. The sizes of the transistors in the CD4007UBE used for experiments have been measured by Tyndall National Institute. In this project, in order to match the simulations to experimental result, many types of MOSFET models were tried to get the best results. The transistor model we chose for our simulations is a Level-1 MOSFET model with the factor GAMMA=0, as shown in Fig. 4.2.

Figure 4.2: Spice model for MOS transistors in Figure. 4.1 with zero threshold modulation.

4.1.3 SPICE Runtime Algorithm

In the SPICE algorithm, two variables are used. These are the injection frequency finjand the amplitude of Vinj. In order to capture the ILFD’s locking behavior, we

sweep the input voltage Vinjfrom 0.1V to 5V and the frequency finjfrom 300kHz

to 2000kHz. We then carry out transient simulations and store the results in ASCII format in an output file. The ASCII format output file is shown in Fig 4.3.

4.1.4 MATLAB Post-processing Algorithm

The output file from H-Spice gives us the details (e.g. voltage and time) of each point of the selected output waveforms.

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frequen-44 Modeling and Simulations

Figure 4.3: Spice Output ASCII data file presented to Matlab.

cies and frequency ratios as follows :

1. It collects data from the Spice output file in the form of the output voltage data corresponding to one value of the input frequency.

2. Perform the Fast Fourier Transform and map the voltage data from the time domain to the frequency domain.

3. Find the peak in the frequency domain and record this frequency as the output frequency fd.

4. The frequency ratio is equal to the input frequency fsdivided by the output

frequencyfd.

Important Digital Signal Processing knowledge is also used in MATLAB: 1. The Fast Fourier Transform is used to determine the frequency content of a

digital signal or the frequency response of a digital system.

2. The input to the Fourier Transform is a uniformly-sampled discrete-time signal and the result of the transform is a discrete function of ω.

3. The output of the Fast Fourier Transform is periodic with period 2π. The real frequencies in the range 0 tofs (sampling frequency) are mapped to ω

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4.1 Modeling and Spice Simulations 45

4. The output of the Fast Fourier Transform is a vector of complex numbers that is symmetrical about ω = π.

The key MATLAB functions used are as follows:

1. dlmread reads the numerical data from the Spice output data file which contains the ASCII data, as shown in Fig 4.3. At the top of the Spice Output data file, there is some simulation information which is not required for our analysis. The first column (time) is also unnecessary for the analysis. Therefore, MATLAB reads the data from the first line of the numerical data directly. In this case, the read range in the dlmread function is [166 100156 1 1]. [166 100156] is the number of lines containing relevent numeric data, and [1 1] denotes the second column..

2. fft(x): Fast Fourier Transform of the array x.

3. To find the maximum element in array A, we use [C, I] = max(A). It will find the maximum value element in array A, then return the maximum value to C and assign the index of the maximum value to I.

Complete MATLAB code is listed in Appendix C.

4.1.5 SPICE and MATLAB Simulations Results

Brute force transient simulations were run over a grid of points in the A-fsplane of

the two-dimensional bifurcation diagram and the rotation number ρ was calculated by post-processing the resulting time series using Matlab, as described above. The results are summarized in Fig. 4.4.

Spice simulation results using Level-1 MOSFET models without considering the parasitic input and output impedance networks are shown in Fig. 4.5. From this Figure, it can be seen that, without considering the parasitic input and out-put impedance networks, the center frequency for the tongues shift towards the right. This causes a noticeable mismatch between the experimental and simulation results. By adding parasitic input and output impedance networks to our Spice model, we can reduce this mismatch to a large extent.

Qualitatively, the widths of the divide-by-2 and divide-by-3 regions in the simulations are similar to those found in the physical experimental implementa-tion, confirming our experimental observations that the circuit can divide by odd numbers as well as by even numbers.

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46 Modeling and Simulations 3 4 5 6 7 8 9 1 0 1 1 x 1 05 0 0 . 5 1 1 . 5 2 2 . 5 C a p a c i t o r c o n n e c t e d S i n g l e M 5 , i n c l u d i n g R L C L , 7 V D C b i a s , F r e q u e n c y A m p lit u d e

Figure 4.4: Spice simulation results for divide-by-2 and divide-by-3 locking regions.

Figure 4.5: Spice simulation results for divide-by-2 and divide-by-3 locking regions without parasitic impedance networks.

4.2 Symmetric Circuit

In the simulation part of this project, we built a model circuit using Spice of the symmetric circuit, which is intended to replicate the experiments. Spice can predict the circuit behavior and works in the same way as the Frequency Sweeping which we introduced earlier. Spice produces its output in the form of an ASCII listing. The listing consists of columns of numbers corresponding to calculated outputs V oltages and/or Currents. Therefore, MATLAB program is needed to analyze the output of Spice.

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4.2 Symmetric Circuit 47

4.2.1 Spice Model

The Spice circuit model under consideration of the symmetric circuit is shown in Fig. 4.6. The schematic is the same as in Fig. 3.9 except the output para-sitic network. In our experiments, we use Texas Instruments CD4007UBE CMOS DUAL COMPLEMENTARY PAIR PLUS INVERTER, which have 3 complemen-tary logic inverters. Each inverter has an input capacitance at input and an output load capacitance and resistance. Therefore, for matching the experimental results to simulations we add parasitic network at both outputs in our Spice model. While performing simulations, the most important factor is the MOSFET model. In this project, the basic aim was to match the simulations to experiments for divide-by-odd numbers. Therefor many types of MOSFET models were tried to get the best results.

Vs 2.97V

C6 R5

MN6

Figure 4.6: H-Spice Circuit schematic of the Symmetric Circuit.

The complete Spice code/Spice net-list for the circuit schematic shown in Fig. 4.6 is given in Appendix C.

4.2.2 SPICE and MATLAB Simulations Results

Brute force transient simulations were run over a grid of points in the A-fsplane

of the two-dimensional bifurcation diagram and the rotation number ρ was cal-culated by post-processing the resulting time series using Matlab, as described earlier. The model includes the input and output parasitic network. The results are summarized in Fig. 4.7.

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48 Modeling and Simulations

Figure 4.7: Spice simulation results for divide-by-2 and divide-by-3 locking regions.

4.3 Analysis

Qualitatively, the modified ILFD exhibits both divide-by-2 and divide-by-3 be-havior, which has been observed experimentally and via Spice simulations. From the Symmetric circuit simulations, the divide-by-2 and divide-by-3 regions lie in almost the same input frequency range as was observed in the Spice simulations for the Asymmetric circuit. The implementation of the design in Spice and the simulated results shows that the developed LC CMOS ILFD with direct injection can perform both divide-by-even and divide-by-odd numbers.

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Chapter 5

Conclusion and Future Work

This chapter presents conclusions of the project work and also suggests potentially fruitful directions for future work in the field of ILFD’s.

Section 5.1 concludes the project work with a description of the most impor-tant achievements. Section 5.2 talks about the limitations and drawbacks found during the work on this project. Section 5.3 discusses the post project ideas which can lead to some interesting future research based on this project in the field of ILFD’s.

5.1 Conclusion

Injection-Locked frequency dividers is a well-studied topic and has been under research for many years. In recent years, a lot of research work has taken place. M.P Kennedy’s group in Tyndall National Institute has been working on Injection-Locked frequency dividers for many years. This masters thesis work is a con-tinuation of the previous research in order to study deeply and to analyze the performance of Injection-Locked frequency dividers with direct injection.

This masters thesis work was carried out over a period of twenty-four weeks. In the first phase of the project, the author learned the background about ILFDs, the existing circuit behavior, the experimental setup, and SPICE. In the second phase, the author studied the LabVIEW algorithms and used these algorithms to reproduce various earlier experimental observations and SPICE simulations. In the final phase of the project, the author developed a modified LC CMOS ILFD

A “Divide-by-Odd Number” Injection-Locked Frequency Divider.

Institutionen för systemteknik

Department of Electrical Engineering

Examensarbete

A “Divide-by-Odd Number” Injection-Locked

Frequency Divider.

A “Divide-by-Odd Number” Injection-Locked

Frequency Divider.

Examensarbete utfört i Elektroniska Komponenter

vid Tekniska högskolan i Linköping

av

Abstract

Acknowledgments

Contents

List of Figures

List of Tables

Chapter 1

Introduction

1.1

PLL Synthesizer and ILFD

1.2

Objectives

Chapter 2

Background and Previous

Work

2.1

LC CMOS Injection Locked Frequency

Di-viders

2.1.1

LC CMOS ILFD With Tail Injection

M

2.1.2

LC CMOS ILFD with Direct injection

2.2

Arnold Tongue Scenario

2.3

Devil’s staircase

2.4

Brute Force Method

2.5

Previous work

2.5.1

Divide by even number

2.5.2

LabVIEW Algorithms

2.5.3

Experimental Results

2.5.4

Analysis

Chapter 3

Divide-by-Odd Number

3.1

Developed Model

3.2

Experimental Characterization

3.2.1

ILFD on Bread-Board

3.2.2

Components and Parameters

3.2.3

Differential Signal

3.2.4

Measurement Setup

3.2.5

Algorithms

3.2.6

Experimental Results

3.3

Symmetric Circuit

3.3.1

Components and Parameters

3.3.2

Experimental Results

3.4

Analysis

Chapter 4

Modeling and Simulations

4.1

Modeling and Spice Simulations

4.1.1