Design of a DCO for an All Digital PLL for the 60 GHz Band : Design of a DCO for an All Digital PLL for the 60 GHz Band

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Institutionen för systemteknik

Department of Electrical Engineering

Examensarbete

Design of a DCO for an All Digital PLL for the

60 GHz Band

Examensarbete utfört i Elektroniksystem vid Tekniska högskolan i Linköping

av

Manikandan Balasubramanian and Saravana Prabhu Vijayanathan

LiTH-ISY-EX--12/4563--SE

Linköping 2013

Department of Electrical Engineering Linköpings tekniska högskola Linköpings universitet Linköpings universitet SE-581 83 Linköping, Sweden 581 83 Linköping

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Design of a DCO for an All Digital PLL for the

60 GHz Band

Examensarbete utfört i Elektroniksystem

vid Tekniska högskolan i Linköping

av

Manikandan Balasubramanian and Saravana Prabhu Vijayanathan

LiTH-ISY-EX--12/4563--SE

Handledare: Muhammad Touqir Pasha

isy, Linköpings universitet

Examinator: Dr. J Jacob Wikner

isy, Linköpings universitet

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Avdelning, Institution

Division, Department

Division of Communication Systems Department of Electrical Engineering Linköpings universitet

SE-581 83 Linköping, Sweden

Datum Date 2013-002-21 Språk Language Svenska/Swedish Engelska/English Rapporttyp Report category Licentiatavhandling Examensarbete C-uppsats D-uppsats Övrig rapport

URL för elektronisk version

http://www.commsys.isy.liu.se http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-ZZZZ ISBN — ISRN LiTH-ISY-EX--12/4563--SE

Serietitel och serienummer

Title of series, numbering

ISSN

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Titel

Title

Svensk titel

Design of a DCO for an All Digital PLL for the 60 GHz Band

Författare

Author

Manikandan Balasubramanian and Saravana Prabhu Vijayanathan

Sammanfattning

Abstract

The work was based on digitally controlled oscillator for an all-digital PLL in 65 nm process. Phase locked loop’s were used in most of the application for clock generation and recovery as well. As the technology grows faster in the existing generation, there has to be quick development with the technique. In such case an analog PLL which was used earlier gradually getting converted to digital circuit.

All-digital PLL blocks does the same work as an analog PLL blocks, but the circuits and other control circuitry designed were completely in digital form, be-cause digital circuit has many advantages over analog counterpart when they are compared with each other. Digital circuit could be scaled down or scaled up even after the circuits were designed. It could be designed for low power supply voltage and easy to construct in a 65 nm process. The digital circuit was widely chosen to make life easier.

In most of the application PLL’s were used for clock and data recovery purpose, from that perspective jitter will stand as a huge problem for the designers. The main aim of this thesis was to design a DCO that should bring down the jitter as down as possible which was designed as standalone, the designed DCO would be later placed in an all-digital PLL. To understand the concept and problem about jitter at the early stage of the project, an analog PLL was designed in block level and tested for different types of jitter and then design of a DCO was started.

This document was about the design of a digitally controlled oscillator which operates with the center frequency of 2.145 GHz. In the first stage of the project the LC tank with NMOS structure was built and tested. In the latter stage the LC tank was optimized by using PMOS structure as negative resistance and eventually ended up with NMOS and PMOS cross coupled structure. Tuning banks were one of the main design in this project which plays a key role in locking the system if the DCO is placed in an all-digital PLL system. So, three types of tuning banks were introduced to make the system lock more precisely. The control circuits and the varactors built were all digital and hence it is called as digitally controlled oscillator. Digital control circuits, other sub-blocks like differential to single ended and simple buffers were also designed to optimize the signal and the results were shown.

DCO and tuning banks were tested using different types of simulation and were tested for different jitter qualities and analysis. The simulation results are shown in the final chapter simulation and results.

Nyckelord

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Abstract

The work was based on digitally controlled oscillator for an all-digital PLL in 65 nm process. Phase locked loop’s were used in most of the application for clock generation and recovery as well. As the technology grows faster in the existing generation, there has to be quick development with the technique. In such case an analog PLL which was used earlier gradually getting converted to digital circuit.

All-digital PLL blocks does the same work as an analog PLL blocks, but the circuits and other control circuitry designed were completely in digital form, be-cause digital circuit has many advantages over analog counterpart when they are compared with each other. Digital circuit could be scaled down or scaled up even after the circuits were designed. It could be designed for low power supply voltage and easy to construct in a 65 nm process. The digital circuit was widely chosen to make life easier.

In most of the application PLL’s were used for clock and data recovery purpose, from that perspective jitter will stand as a huge problem for the designers. The main aim of this thesis was to design a DCO that should bring down the jitter as down as possible which was designed as standalone, the designed DCO would be later placed in an all-digital PLL. To understand the concept and problem about jitter at the early stage of the project, an analog PLL was designed in block level and tested for different types of jitter and then design of a DCO was started.

This document was about the design of a digitally controlled oscillator which operates with the center frequency of 2.145 GHz. In the first stage of the project the LC tank with NMOS structure was built and tested. In the latter stage the LC tank was optimized by using PMOS structure as negative resistance and eventually ended up with NMOS and PMOS cross coupled structure. Tuning banks were one of the main design in this project which plays a key role in locking the system if the DCO is placed in an all-digital PLL system. So, three types of tuning banks were introduced to make the system lock more precisely. The control circuits and the varactors built were all digital and hence it is called as digitally controlled oscillator. Digital control circuits, other sub-blocks like differential to single ended and simple buffers were also designed to optimize the signal and the results were shown.

DCO and tuning banks were tested using different types of simulation and were tested for different jitter qualities and analysis. The simulation results are shown in the final chapter simulation and results.

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Acknowledgments

We would like to whole heartedly thank our tutor and examiner Dr. J Jacob Wikner for guiding us through several stages and patiently providing us technical ideas on the topic and tools. Also we would like to thank our supervisor Muham-mad Touqir Pasha for providing us materials and showing us some techniques. We thank our family and friends for their support and prayers.

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4.4.2 Acquisition mode . . . 35 4.4.3 Tracking mode . . . 35 4.5 MOS varactors . . . 35 4.6 Conclusion . . . 37 5 Jitter 39 5.1 Modelling of jitter . . . 39 5.1.1 Jitter types . . . 39 5.1.2 Jitter metrics . . . 40 5.2 Conclusion . . . 43 6 DCO design 45 6.1 The LC tank . . . 45 6.1.1 Q factor . . . 46 6.2 Negative resistance . . . 47

6.2.1 Negative resistance architectures . . . 47

6.2.2 Design of the complementary cross coupled pair . . . 49

7 DCO sub-blocks 53 7.1 Thermometer decoding . . . 53

7.2 4 bit binary to 15 bit thermometer converter . . . 54

7.3 8 bit binary to 256 thermometer decoder . . . 55

7.3.1 Decoder unit cell . . . 56

7.4 Decoder example . . . 57

7.5 Current mirror . . . 58

7.6 Design . . . 59

7.7 Buffer . . . 60

7.8 Single vs. differential . . . 61

7.8.1 Advantages of differential signalling . . . 61

7.9 Differential buffer . . . 62

7.10 Differential to single ended . . . 63

7.10.1 Working of differential to single ended . . . 63

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Contents xi

8 Results and simulation 65

8.1 Analog PLL . . . 65

8.2 Phase locked loop jitter . . . 66

8.3 Project specification and analysis . . . 69

8.4 DCO simulations . . . 70

8.4.1 Comparison of DCO architectures . . . 71

8.4.2 DCO output plot . . . 71

8.4.3 Frequency range of DCO . . . 73

8.4.4 Inductor Q-factor . . . 73

8.5 DCO phase noise and jitter . . . 74

8.5.1 Results of jitter . . . 75

8.5.2 Eye diagram of DCO output . . . 76

8.5.3 Phase noise for center and low frequency . . . 76

8.6 Results and analysis . . . 78

9 Conclusion and future work 79 9.1 Conclusion . . . 79

9.2 Future work . . . 80

A Appendix 81 A.1 Verilog A source code of VCO [4] . . . 81

A.2 Verilog A source code of divider [4] . . . 82

A.3 Verilog A source code of phase detector with charge pump [4] . . . 83

A.4 Verilog A source code of fixed oscillator jitter model [5] . . . 84

A.5 Verilog A source code of VCO-FDN jitter model [5] . . . 85

A.6 Verilog A source code of PFD-CP jitter model [5] . . . 87

A.7 Verilog A source code of binary to thermometer converter . . . 88

A.8 MATLAB code to calculate VCO power spectral density of phase[5] . . . 89

A.9 MATLAB code to calculate jitter . . . 90

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List of Figures

1.1 ADPLL architectures. . . 6

2.1 Phase locked loop. . . 10

2.2 Characteristics of phase detector [9]. . . 11

2.3 XOR phase detector [9]. . . 12

2.4 Response of XOR phase detector [9]. . . 12

2.5 Structure of charge pump [9]. . . 13

2.6 Phase detector with charge pump [9]. . . 14

2.7 First order RC low pass filter. . . 14

2.8 Voltage controlled oscillator. . . 15

2.9 Characteristics of VCO [9]. . . 15

2.10 Block diagram of divider. . . 16

2.11 Integer-N PLL architecture. . . 17

2.12 Fractional-N PLL architecture. . . 17

3.1 Common source amplifier with feedback [9]. . . 20

3.2 Ring oscillator with N-stages. . . 21

3.3 Lossy LC tank. . . 22

3.4 LC tank with active gain. . . 22

3.5 Oscillator phase noise. . . 23

4.1 Block diagram of all-digital PLL. . . 25

4.2 Time to digital converter [10]. . . 26

4.3 Positive phase error [10]. . . 27

4.4 Negative phase error [10]. . . 27

4.5 TDC quantized transfer function [10]. . . 29

4.6 Capacitance change of an LC oscillator [10]. . . 30

4.7 MOS varactors vs. control voltage (deep-submicron) [10]. . . 31

4.8 Physical structure of PMOS transistor. . . 32

4.9 LC tank with varactor array [10]. . . 33

4.10 Modes of tuning [10]. . . 34

4.11 Schematics of differential switched capacitor [11]. . . 36

4.12 Schematics of PMOS varactor [10]. . . 36

5.1 Threshold noise to jitter [5]. . . 40

5.2 edge-to-edge Jitter [5]. . . 41

5.3 k-cycle Jitter [5]. . . 41

5.4 cycle-to-cycle Jitter [5]. . . 42

5.5 Jitter in PLL [5]. . . 43

6.1 Ideal LC tank. . . 46

6.2 S-parameter test setup. . . 46

6.3 PMOS pair negative resistance. . . 48

6.5 Complementary MOS pair. . . 48

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6.6 Negative resistance set-up. . . 50

7.1 Logic of thermometer decoder [1]. . . 54

7.2 Schematic of binary to thermometer converter [1]. . . 55

7.3 8 bit binary to 256 thermometer decoder [1]. . . 56

7.4 Decoder unit cell [1]. . . 57

7.5 Decoder illustration [1]. . . 57

7.6 PMOS current mirror. . . 58

7.7 Schematic of current mirror. . . 60

7.8 Single ended output [9]. . . 61

7.9 Differential output [9]. . . 62

7.10 Differential buffer with bias current. . . 62

7.11 Differential buffer with DC setting [6]. . . 63

7.12 Differential to single ended [3]. . . 64

8.1 Integer-N PLL test setup. . . 65

8.2 VCO tuning voltage. . . 66

8.3 Jitterless PLL. . . 67

8.4 Jitter from fixed oscillator. . . 67

8.5 Jitter from divider. . . 68

8.6 Project specification. . . 69

8.7 DCO test setup. . . 70

8.8 DCO single ended output, F=1.89 GHz. . . 71

8.9 DCO single ended output, F=2.145 GHz. . . 72

8.10 DCO double ended output for high frequency. . . 72

8.11 Frequency vs. coarse code. . . 73

8.12 Inductor Q-factor. . . 74

8.13 pnoise setup. . . 74

8.14 Phase noise for high frequency . . . 75

8.15 Phase noise at 1 MHz, F=2.57 GHz. . . 76

8.16 Phase noise for center frequency. . . 77

8.17 Phase noise for low frequency. . . 77

List of Tables

1.1 Project specification. . . 7

2.1 Edge-triggered D-flip flop [9]. . . 12

5.1 Types of jitter. . . 40

5.2 Table of error rate. . . 43

8.1 Analog PLL simulation values. . . 66

8.2 Analysis used. . . 69

8.3 Comparison of LC architectures. . . 71

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Contents 3

Acronyms

PLL Phase locked loop

VCO Voltage controlled oscillator PD Phase detector

RF Radio frequency LPF Low pass filter LSB Least significant bit MSB Most significant bit

DCO Digitally controlled oscillator Q Quality factor

TDC Time to digital converter DLF Digital loop filter

DC Direct current AC Alternating current

MOS Metal oxide semiconductor

CMOS Complementary metal oxide semiconductor VLSI Very large scale integrated circuits

dBc decibels relative to the carrier RMS Root mean square

DAC Digital to analog converter PVT Process voltage temperature PSS Periodic steady state

CS Common source RF Radio frequency

OTW Oscillator tuning word DFC Digital to frequency conversion

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Chapter 1

Introduction

Phase locked loop are used in most of the applications for clock generation and for recovery as well. As the technology grows faster in the existing generation, there has to be quick development with the technique. In such case an analog PLL which has been used earlier, gradually getting converted to digital and ended up with all digital circuits. The thesis work was based on digitally controlled oscillator for an all-digital phase locked loop in 65 nm process. This project actually had a team which worked on different blocks of an all-digital PLL. In the later part individually designed blocks would be integrated to see if the all-digital PLL works fine.

1.1 Objective

The main aim of this thesis work was to design a digitally controlled oscillator which should operate with wide tuning range and less jitter. The DCO should be constructed by using any one of the oscillator types. Since tuning banks plays key role in locking the system a method using varactors has to be implemented to lock efficiently. In our case, three types of tuning banks were introduced to make the system lock more precisely. The DCO in this project was designed as standalone and control circuits were also designed in digital form to check the result by integrating the circuits with the oscillator. Control circuits and also other sub-blocks like differential to single ended and simple buffers were optimized to get the desired output from the integrated system.

The DCO built would be later used in the closed loop form of all-digital PLL and would be tested by integrating with other blocks and this all-digital PLL would be later used in digital RF front end.

Figure 1.1 depicts a general all-digital phase locked loop structure in which oscillator and phase detector plays a key role. This structure shows that phase detector could be modelled in three different ways. Our thesis work was done by having time to digital converter instead of phase and frequency to digital converter. The time to digital converter was chosen to avoid fractional errors which occurs in both phase and frequency to digital converter. Using a TDC might act effective to

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convert from time to digital bits. In TDC, time period between two events could be considered and taken easily whereas it is difficult to retrieve the data from phase and frequency to digital converter. Input to the oscillator was given from the time to digital converter which produces fractional bits, this kind of structure would produce effective control bits to the DCO. Thus DCO should be designed with different varactor banks, the tracking bank of the DCO would receive fractional bits to make the ADPLL track the signal at each time events and lock the system more effectively than the analog PLL.

Figure 1.1. ADPLL architectures.

1.2 Deep-submicron CMOS

Recently the feature size of the digital CMOS technology is decreasing, at the other end CMOS transistor produces better performance. But this concerns the designers on the flip side of the technology. Because scaling down devices increases the complexity in other possible way, which may lead to flicker noise in the case of oscillator which is caused by carrier trapping near the thin oxide-silicon

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inter-1.3 Background 7

face. This flicker noise would be later upconverted to close in phase noise in the oscillator and would spoil the expected output. Even though the deep-submicron process provides better opportunity, it holds some complications for the design-ers. For example, accomplishing a desired frequency tuning with low voltage was an extremely challenging task due to their highly non-linear frequency vs. voltage characteristics. So, it would be really a challenging task for the designers to design a system in deep-submicron.

1.3 Background

In most of the applications PLL’s are used as local oscillator. Local oscillators are generally used to generate the wanted frequency or it helps in recovering the signal that is being corrupted by the environment. PLL’s are thus used to recover the wanted frequency at the receiver and used as clock generator at the transmitter end. It could be also found in the RF front end. In our project the team con-structing individual blocks of an all-digital PLL would be integrated and used for the RF front end. Therefore PLL’s with huge jitter will affect the system. So in our case, the digitally controlled oscillator that was designed should suppress the jitter at the output.

Jitter is usually denoted as timing variations of a signal frequency. Due to this, system may fail in recovering or generating the desired result. Jitters were usually caused by the noise from the environment and also from device components. So, careful designing should be handled and also choosing of architectures decides the better result of an entire system. In our project, we had chosen an oscillator type that suppressed jitter down well below. So, we as a designer came up with an idea of implementing tuning banks to make the system lock precisely. Eventually ended up with the jitter value that is specified in the project specification table shown in 1.1.

1.4 Project specification

The project specification for the DCO which was designed in 65 nm process can be seen from Table 1.1. The reference clock was 104 MHz with a wide tuning range of 700 MHz. The jitter constraint was less than 3 ps from the digitally controlled oscillator. Finally the DCO was also tested for different process corners.

Table 1.1. Project specification.

Item Min Typ Max Unit Supply voltage - - 1 .0 V Reference frequency - 104 - MHz

Output frequency 2 - 3 GHz Long-term jitter - < 3 - ps Temperature range 40 - 120 deg 1

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1.5 Framework

The initial phase of the thesis was the background literature study which included several reference papers and various architectures. [10] was the primary reference for this thesis. [10] deals in depth about the sub-blocks of the all-digital PLL. The oscillator core was designed with [6] as reference. The DCO was required to have a wide tuning range and hence the tuning scheme was also an important part of the design to help achieve better tuning range. Tuning mechanisms discussed in [10] were incorporated in the design. The thesis had to be implemented mostly in standard cell. Tuning scheme with varactors from standard cells were also designed and tested. [1] and [8] were helpful while designing the digital circuitry for the DCO. The initial phase was the background literature study which included several reference papers and various architectures.

Then we started the behavioral level of an analog PLL, doing jitter analysis for different blocks of analog PLL. Later, the digitally controlled oscillator has to be designed by choosing either ring oscillator or LC tank oscillator with lower phase noise. Being a part of an all-digital PLL project, knowledge on sub blocks of the all-digital PLL was also necessary along with the DCO. The main focus of this thesis work was to implement the entire design in register transistor level. Analog PLL models were initially developed to have an idea about the architectures. This made the transition toward a digital approach quiet easier.

This report was a mere replica of the design flow that was carried out through out the process. The readers would get to know about analog PLL and all-digital PLL basics, the sub blocks involved and the DCO design process and their test case. Starting from chapter second, reader would get an idea about basic blocks of analog PLL, a brief comparison was also shown for analog and digital PLL. In the third chapter a study about oscillators, their type and phase noise associated with the oscillator was also shown. In the next chapter, we would get an idea about all-digital PLL, time to digital converter and the digitally controlled oscillator and their issues would be seen. Also concept about different tuning banks using varactors were also shown. Chapter five explains about the long term jitter and cycle-to-cycle jitter that were associated with the oscillator, chapter six deals with an important issue i.e. design of LC tank. The last two chapters would showcase about the DCO sub-blocks and the simulation results of LC tank and analog PLL.

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Chapter 2

Phase locked loop

PLL is as an essential in most of the wireless application, radio and other electronic circuits. This document would provide the reader with some basic understanding of the PLL, its application and building blocks. Synchronization of RF signals in a system is an important issue in an electronics and communication field. To produce a wide frequency range and synchronization, a phase locked loop (PLL) can be used. The phase locked loop is realized by constructing the system in a feedback loop. A PLL can produce an output frequency which are exact multiples of the reference input frequency from an oscillator.

2.1 Applications

Phase locked loop are used in frequency and amplitude modulation, frequency synchronization and signal conditioning, synchronization for control in CD players, clock recovery, de-skewing, frequency multiplication and jitter reduction, RF and wireless transceivers, optical fiber receivers [9].

2.1.1 Skew reduction

The space variation in arrival time of a clock variation is commonly known as clock skew. In general clock skew will take place due to static mismatches and difference in the clock load. So, to de-skew the clock transition on an integrated chip, PLL can be exploited. The earliest usage of phase locking in digital system is brought up for skew reduction [7].

2.1.2 Jitter reduction

Clock jitter refers to the temporal variation of the clock period at a given point on the chip i.e. the clock can reduce or expand on a cycle basis [4]. PLL aids in suppressing fast jitter components at the input. Clock recovery circuit (CRC) produces the clock from the data itself. Phase locking with the narrow loop

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width, input jitter effect on the recovered clock will be minimized by the CRC [9].

2.1.3 Clock recovery

High serial data streams are sent to the receivers without any clock, from the magnetic head of a disk drive to the receiver. At the receiving side, a clock has been generated from the data which is almost equal to the frequency of the reference signal and eventually PLL aligns the transitions in data stream which is said to be clock recovery. To work properly the stream of data must have a transition frequency which is sufficient enough to rectify the drift in the PLL oscillator.

2.2 Analog phase locked loop

The concept of phase locking was invented in 1930s and it was widely used in elec-tronic and communication field. Since then, the basic phase locked loop remained similar and its use in different applications and different technologies remained challenging for the designers [9]. The phase locked loop’s are exploited in many systems for frequency synthesis, clock/data recovery and de-skewing. PLL syn-thesizes different clocks for different blocks. For example, in digital compensator faster clock is required, while for an embedded micro controller slower clock rate is required [2]. PLL plays a vital role here and helps the system synthesize.

Figure 2.1. Phase locked loop.

A phase locked loop (PLL) is a feedback system which compares the phase of the reference clock and phase of the frequency from the voltage controlled oscillator (VCO) which tries to lock the signal phases eventually. When the phase error between these two signals are likely close to zero or equal, it is said to be locked. Phase locked loop (PLL) comprises of five main blocks phase frequency detector, charge pump, loop filter, voltage controlled oscillator (VCO) and a divider. The block diagram of PLL can be seen in Figure 2.1.

The system functions as follows, the work of the phase detector (PD) is to compare the phase of the reference frequency and the phase of the frequency from

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2.2 Analog phase locked loop 11

the feedback loop and produces an up and down signals accordingly. The up and down signals are then fed into the charge pump (CP) which charges or discharges the loop filter (LPF) according to the phase error. The filter in response produces a control voltage which is fed to the voltage controlled oscillator, thereby it changes the frequency of the VCO and this frequency is given to the divider which divides the voltage controlled oscillator output and fed back into the phase detector, thus it operates in a loop. In response to an error signal the VCO’s frequency is varied and the PLL locks the signal at a phase which is said as phase locking. In summary, PLL produces an output frequency which can be a multiple of the input frequency.

2.2.1 Phase detector

The phase detector in the phase locked loop compares two input signals and pro-duces the phase difference as an output. Two input signals are fed into the phase detector (PD) one is given as the reference clock and another input is the feed-back from the divided signal of the voltage controlled oscillator (VCO). Output from the phase detector is proportional to the phase difference between the inputs, which is shown in Figure 2.2.

Figure 2.2. Characteristics of phase detector [9].

A well-known example of the phase detector is an exclusive OR (XOR). If an input varies in their phase, the width of an output pulses vary accordingly, thereby producing a dc level which is proportional to ∆φ. The XOR circuit produces both

up and down error signals. Here the phase difference of the two input signals

V1(t) and V2(t) produces the phase error ∆φ with the varying input signal which

is shown in Figure 2.4.

The simple implementation of two edge-triggered, resettable D flip flops with their D inputs connected to a logical one always, with two clocks A and B and outputs QAand QB are shown in Figure 2.3. Initially consider QAand QB are in

ground, then when A rises to vdd, QAgoes high. When this transition is followed

by the rise in B, QB goes high. Finally, the AND gate resets both the D-flip flops

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Figure 2.3. XOR phase detector [9].

Figure 2.4. Response of XOR phase detector [9].

Table 2.1. Edge-triggered D-flip flop [9].

D Clock Q

0 1 0

One 1 1

X 0 Pre-state X 1 Pre-state

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2.2.2 Charge pump

The charge pump either pumps current or sucks current from the filter, according to an input signal it receives from the phase detector. An up and down signals from an output of the phase detector controls the charge pump. Up and down signals to the charge pump increases and decreases the voltage respectively, the increased voltage will charge the loop filter and the decreased voltage will discharge the filter. The charge pump with switches S1 and S2 in series with the current

source is shown in Figure 2.5.

Figure 2.5. Structure of charge pump [9].

Basic charge pump

The charge pump consists of two switches S1 and S2 placed in series with the

current sources are placed next to the phase detector. If the voltage from the phase detector is zero from QA and QB, the IOut from the charge pump will be

constant. Suppose, if QAproduces a high voltage, then switch S1 is ON and S2 is

OFF, the source then charges up the capacitor and if QB is high and QA is low,

switch S1is OFF and S2 is ON, discharging of the capacitor takes place. Thus if

A leads B, then QA continues to produce pulses thereby rising the VOut steadily.

The structure along with the PD and LPF can be viewed from Figure 2.6. The entire structure shown in Figure 2.6 does not produce linearity of the system. when the phase difference is doubled the flat section of an output gets doubled, that is if the phase difference is 2∆φ. But, the ramp section does not get

increased, this very clearly shows that the system is not linear. Secondly, if we see the transfer function of the charge pump given in the equation 2.1. It states that the output voltage is raising by IP

Cpφo

TInp

2Π . The phase shift should be less than at

gain cross over. So, by modifying a better phase stability is obtained. By adding zero, that is by adding a resistor in series with a capacitor, stability is increased

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[9]. VOut ∆Φ (s) = IP CP2Π (1 s) (2.1)

Figure 2.6. Phase detector with charge pump [9].

2.2.3 Loop filter

The output from the charge pump is fed to the loop filter which helps in stabilizing the whole system and also produces the control voltage to the voltage controlled oscillator (VCO). The increased voltage from the filter which changes the frequency of the VCO attempts to minimize the error. Filter shown in Figure 2.7 is a first order RC low pass filter which in turn makes the PLL a second order.

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2.2.4 Voltage controlled oscillator

The voltage controlled oscillator (VCO) is generally considered as the heart of the phase locked loop (PLL). Since, it provides an output frequency which is given as an input to the phase detector (PD) in a closed loop feedback system, it is said to be one of the most important part in the PLL. Input to the voltage controlled oscillator is a control voltage from loop filter which controls the frequency of the VCO. Block diagram is shown in Figure 2.8.

Figure 2.8. Voltage controlled oscillator.

Oscillator’s output frequency is linear to its control voltage, which is stated in the equation 2.2

ωOut= ω0+ (KV coVCntl) (2.2)

Figure 2.9. Characteristics of VCO [9].

Figure 2.9 shows the characteristics of VCO which is plotted between output frequency ωOut versus control voltage VCntl which is fed as an input to the VCO.

It depicts that an input frequency of the PLL varies due to an error and also shows that the phase error can be minimized by simply increasing phase detector’s gain and VCO’s gain too i.e KV coKP d [9].

Equation 2.4 gives an idea on which parameters, the phase error depends

V1=

(ω1− ω2)

KV co

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φO= V1 KP d =(ω1− ω2) KV coKP d (2.4)

2.2.5 Divider

The divider in the PLL is placed next to the voltage controlled oscillator (VCO). Output of the oscillator FOut is fed as an input to the divider, which divides the

frequency of the oscillator by the factor of M. i.e. the divider gives an input as

FInp = F_MOut to the phase detector, the phase detector then compares these two

frequencies FInpand FRef gives an output as up and down error pulses as control

voltage to the VCO through the charge pump and low pass filter. The VCO thereby changes its frequency and helps the phase detector locks the FRef and

FInp . A simple block diagram of divider is shown in Figure 2.10.

Figure 2.10. Block diagram of divider.

2.3 Types of analog PLL

In an analog PLL, there are two different architectures exist and they are called as integer-N PLL and fractional-N PLL. As the name suggests the difference between them is the division ratio that can be achieved between the reference frequency

FRef and the output frequency of the VCO, FV co. Two different architectures are

1. Integer-N PLL 2. Fractional-N PLL

Integer-N PLL

N represents the integer part division ratio and f is considered as the fractional part. Thus in an integer-N architecture Fvco= N.Fref [10] and in a fractional-N

type the relation is Fvco = N.f.Fref [10]. The integer-N PLL can thus produce

output frequencies which are an exact integer multiples of the reference frequency, while with a fractional-N PLL any multiples of the reference frequency can be produced at the VCO output. Comparing integer-N PLL with the fractional, fractional will perform far better than the integer. Diagram of integer-N PLL is shown in Figure 2.11.

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2.3 Types of analog PLL 17

Figure 2.11. Integer-N PLL architecture.

Fractional-N PLL

Fractional-N frequency synthesizer has the resolution of frequency that is a frac-tional portion of the reference frequency. The main aim of the fracfrac-tional-N ar-chitecture improves the phase noise. If the reference frequency is increased there might be possibility of better switching speed and also by increasing the loop band-width. Very high frequency resolution can be achieved by the use of fractional-N frequency synthesizer. Fractional divide values are achieved by dithering and thus a better resolution is achieved. Diagram of fractional-N PLL is shown in Figure 2.12.

Figure 2.12. Fractional-N PLL architecture.

Comparison of analog and digital PLL

The standard analog phase locked loop implementation always exhibit problems in most of the applications. Firstly, they are more sensitive to process variation and also the problem arises once an implementation of analog phase locked loop

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progress in the deep-submicron. The cost of implementation is perhaps high. Usually, the capacitors placed in the analog circuit accommodates more space in the chip even if its in first order. So, increasing an order of the phase locked loop means increasing the filter order which yields the size of the capacitor to be high which eventually occupies more space in the chip.

The phase locked loop in the form of digital circuitry has many advantages than the analog PLL and all these advantages are justified by digital PLL over an analog PLL. As digital circuits, the blocks implemented can be scaled down easily as the way of technology improves further on. Possibly, the circuit can function better even at lower supply voltages. As for as linearity is concerned in digital, it is much better than the analog, the difficulty in bringing the analog circuits to linear is high. Digital PLL has shorter lock time compared to analog PLL. On the other hand digital PLL does not have better jitter range than an analog PLL.

2.4 Conclusion

In summary, basic analog phase locked loop blocks and their functions has been illustrated in a way that readers could get better knowledge about the PLL. Even-tually, a brief comparison has been given to show that digital circuits were more advantageous than an analog circuits.

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Chapter 3

Oscillators and phase noise

Oscillators are mostly considered as the most essential part of some application in electronic systems. This chapter takes the reader through a general study of oscillation, types of oscillators and few important constraints which remains as a major issue. Such a basic knowledge is good to know while designing an oscillator.

3.1 Feedback systems

An oscillator produces a periodic output, usually in the form of voltage when a dc is given as an input. To oscillate, it should satisfy the so called Barkhausen’s criteria. Let us consider the negative feedback system. Writing the closed loop function as 3.1. Vout Vin = H(s) 1 + ω.H(s) (3.1)

where s = jω and ω is the angular frequency. If H(jω) = −1, the circuit may oscillate at frequency ω. This condition can be given as

|H(jω)| ≥ 1 (3.2)

|H(jω)| = 1800 _(3.3)

The total phase shift around the loop is said to be 3600 which also includes the 1800phase shift introduced by negative feedback. The 3600phase shift is essential for an oscillation to build up and also unity gain of the loop is required to enable the growth and sustain the oscillation amplitude.

There are some conditions considered as necessary. Firstly, ensure the oscilla-tion sustains during the temperature and process variaoscilla-tion, in that case loop gain must be chosen to twice or thrice the required value.

The second condition is stated as above, for an open loop it should have a phase shift of 1800_{. Whereas for the closed loop, phase shift is 360}0_{in which the}

negative feedback introduces 1800 _{for oscillation build up. CMOS oscillators in}

recent technology are implemented either as ring oscillator or LC oscillator [9]. We shall see the explanation in the following section 3.3.

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3.2 Types of oscillators

Though there are many types of oscillator exist, the following two oscillators are considered as an integral part of the electronic system

1. Ring Oscillator 2. LC Oscillator

3.2.1 Ring oscillator

Usually the ring oscillator consists of a number of gain stages in a loop. A ring oscillator can be built by using common-source stage amplifier placed in several number of stages. But it does not oscillate the way it should be, when the common-source stage is placed as a single stage.

If the common-source stage is said to be open-loop circuit, it will have only one pole. Because it is single pole, it eventually produces the frequency dependent phase shift of 1800_{and the common-source stage exhibits a dc phase shift of 180}0_,

it acts like an inverter when an input is fed to amplifier and produces an output that has phase shift of 1800 _{from that of input. Oscillation of the single stage}

common-source amplifier does not grow or sustain until it has a phase shift of 3600_{. Figure 3.1 shown is a single common-source stage which does not oscillate,}

because it has the maximum phase shift of 2700 _[9].

Figure 3.1. Common source amplifier with feedback [9].

From the previous figure and description it is clearly shown that an oscillation might take place, only if the common-source stage is increased to more number of stages. So, the figure shown above as a single stage is imitated and a second stage placed which consists of multiple stages and multiple poles, thereby in the end it oscillates. Even though this two stage CS amplifier produces a frequency dependent phase shift of 1800_{, it has two poles and eventually the maximum phase}

shift of 3600_{, Still it act as latch rather than a perfect oscillator.}

So, it would be perfect to have the oscillator to be as odd number of stages which would result in dc phase shift of 1800_{and if the oscillator has three number}

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3.2 Types of oscillators 21

of 2700 . So, the total phase shift 4500 or 900. However the cut-off frequency of a stage fp < ∞ the frequency dependent phase shift is 1350 [9]. Thus the odd

number of stages should oscillate and it behaves as an oscillator, it is thus stated that odd number stages placed behaves as a ring oscillator. The ring with odd number of stages is shown in Figure 3.2.

Figure 3.2. Ring oscillator with N-stages.

The frequency of ring oscillator depends on the number of stages and propa-gation delay of each stage. The frequency of oscillation is given in 3.4

fo=

1 2N tp

(3.4)

The ring oscillators are widely used as clock synchronization, data recovery appli-cations. It has both advantages and disadvantages with its behavior. Advantages of the ring oscillator are, it occupies less area than the LC oscillator and it has the benefit of consuming less power. With the ring oscillator wide tuning range can be achieved easily. Though the ring oscillator has many benefits, it has very poor phase noise performance. Thus, LC oscillators are widely chosen in order to exhibit good phase noise performance. A clear description about LC oscillator is given in the following section 3.2.2.

3.2.2 LC oscillator

LC oscillator is widely chosen in most of the applications because for its better phase noise performance. Both the inductor and capacitor stores energy basically. When a voltage across a capacitor is flowing, it stores an electrical energy and same goes for the inductor which stores energy in its magnetic field when current flows across it. Oscillation usually forms when an initial condition is given either to capacitor or inductor. When inductor is initialized by making the current flow across it, it stores energy in the magnetic field and once the inductor is charged, it starts discharging by charging the capacitor and when the inductor is fully dis-charged the capacitor is dis-charged between the plates. Now the dis-charged capacitor starts to discharge and charges the inductor, this process takes place back and forth until internal resistance makes the oscillation dies out and the loss is rep-resented by Rp. In this way the LC tank is built which acts as an perfect resonator.

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Figure 3.3. Lossy LC tank.

The resonance occurs when the reactance of capacitor XC and inductor XL

are equal in magnitude and opposite in sign which forms the resonant frequency at that particular point.

ω =

r 1

LC (3.5)

where ω - Angular Frequency, L - Inductance and C - Capacitance. The resonant frequency is given as 3.7.

ωL = 1

ωC (3.6)

f = 1

2π√LC (3.7)

where ωL - Reactance of inductor and ωC - Reactance of capacitor. To compensate this loss in the resonator and make the oscillation sustain. A parallel negative resistance Rpis placed, it aids in cancelling out the positive resistance of a resonant

LC and hence supports the oscillation.

Figure 3.4. LC tank with active gain.

In the DCO designed, LC oscillator is chosen as the core for it offers a good phase noise with a trade-off for area. The LC oscillator designed will be discussed in detail later in the chapter six.

3.3 Phase noise

PLL generally operate on the phase of the signals, they are susceptible to phase noise or jitter. Jitter in the time domain corresponds to phase noise in the

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fre-3.3 Phase noise 23

quency domain. Phase noise is considered as the random component in the excess phase.

If each and every block used in PLL exhibits noise, then the output will be suffering from noise, the term noise means phase noise. The two main factors that contributes noise and make the PLL suffer are noise in the VCO and the input noise. As the noise propagates through each and every block in the PLL it might affect the wanted output of the system, thus it is good for a designer to have better knowledge about noise sources that exist in a system which might propagate and cause unexpected output. Noise that is introduced into the PLL or an oscillator by external means may provoke the frequency and the amplitude of the output signal to an undesired form.

The phase noise in RF system is considered as a very important issue in oscil-lators and PLL because the signals will be corrupted heavily at the output.

3.3.1 Phase noise in VCO

The phase noise is defined as the measure of the carrier power at an offset of 1 MHz from the center frequency fo. It is measured in dBc which means in dB with respect to carriers. The close-in phase noise affects the spectral resolution. When PLL is in lock state, the phase variation in the VCO can be converted to voltage by the phase detector and this is applied as the control voltage to the VCO thereby accumulating phase in the opposite direction.

Figure 3.5. Oscillator phase noise.

Higher close-in phase noise at the output results from the limited loop band-width, the phase noise of the oscillator is reduced due to the bandwidth of the loop. If the loop bandwidth of the PLL is smaller say some 20 kHz, then the phase noise components at frequency offsets greater than a few kilohertz will be affected with an attenuation. The upconverted 1/f noise of the voltage controlled oscillator will show a serious consequence at the offsets as large as several hundred kilohertz [6].

Two different types of noise must be good to know when designing an oscillator. they are

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1. Flicker Noise 2. Thermal Noise

Flicker noise

The flicker noise is also said as1_f noise or pink noise. The term_f1suggests, the noise is defined by spectral density increases without limit while the frequency decreases. MOSFET usually gets highly affected by the _f1 noise at low frequency. The flicker noise takes place due to the trapping and de-trapping of charge carriers in the gate dielectrics. This might affect the oscillator by phase noise when upconverted [6]. Flicker noise is determined as in 3.8.

N2₌ K

fn∆f (3.8)

where N is rms noise, K is empirical parameter and n is said as exponent close to unity

Thermal noise

Thermally agitated charge carriers in a conductor usually reflects with the ran-domly varying current, which in the end gives rise to a random voltage. It is also considered as one of the important noise source in oscillator due to the random movement of electrons. It has a white spectrum and it is proportional to absolute temperature. The spectral density of Noise Voltage is given as in 3.9.

e2

n = 4kT R∆f (3.9)

3.3.2 Leeson’s phase noise model

LC oscillator’s phase noise is given as follows

L(ωm)∝ 1 V2 0 .kT C . ω0 Q. 1 ω2 m (3.10)

where L(ωm) is phase noise at an offset frequency, V0 is oscillation amplitude, Q

is quality factor of an inductor, ω0is center frequency, ωmis offset frequency, k is

Boltzmann’s constant, T is absolute temperature [6]. From the above equation, it can be clearly seen, that phase noise of the oscillator depends on these parameters shown in 3.10.

3.4 Conclusion

Oscillators were considered as an important block in most of the applications for its kind of work it does. This chapter was all about the two different types of oscillator, its functionality and the phase noise associated with it. As the thesis work was based on oscillator we had to choose one of the oscillator for work. Design of a basic oscillator and the optimization part would be discussed in chapter five.

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Chapter 4

All digital PLL

As the technology grows in great pace, conversion of analog to digital had become frequent in order to improve in every possible way. Phase locked loop plays vital role in many applications, previously PLL’s were partially analog and digital. Nowadays this partial form of analog and digital PLL’s were entirely built in the digital domain. The main aim of implementing the phase locked loop in digital method was due to its flexibility within the circuit, because digital circuits could be easily scaled down, it has better testability and highly immune towards the noise, stability and easy integration of the digital system makes popular.

Figure 4.1. Block diagram of all-digital PLL.

Eventhough the method of implementing the PLL said to be analog, semi-digital or all semi-digital. It end up with the purpose of locking the signals. All semi-digital phase locked loop were chosen to implement the system with good stability and flexibility. The block diagram of all-digital PLL is shown in Figure 4.1.

Although the blocks used were digital the functionality of each and every block imitates analog PLL. In this block diagram the phase detector and charge pump

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were replaced by time to digital converter (TDC) which does the same work as phase detector, digital filter replaces the analog filter and VCO was replaced by digitally controlled oscillator.

The digitally controlled oscillator (DCO) has three operation modes. When the PLL settles, the DCO which was controlled by the loop will pass through the PVT, acquisition and tracking modes with lower frequency range but with higher frequency resolution. In this way PLL achieves a very good stability and locking condition.

4.1 Blocks of all-digital PLL

In all-digital PLL two blocks were considered to be the most essential part. They are

1. Time to digital converter (TDC) 2. Digitally controlled oscillator (DCO)

4.1.1 Time to digital converter

The work of the TDC was to produce an error signal if there is a difference in the DCO clock and the reference frequency and the other condition was to lock the signal and produce zero error if the DCO clock and the reference frequency both are in same phase. It almost does the work of a phase detector (PD) which was used in analog PLL.

The TDC functions as follows, the fractional delay difference and the reference clock (FREF) and the next significant edge of a DCO clock was measured using a time to digital converter with a time quantization resolution ∆tres of an inverter

delay tinv and the digital word was said to be the time difference. It is shown in

Figure 4.2.

An integer output of the time to digital converter (TDC) could not be used in the system during its process it is because the time resolution was a varying parameter. So, to do that it had to be normalized by the DCO clock period. The effective part to be considered is only the fractional error would be used by the phase detector.

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4.1 Blocks of all-digital PLL 27

The smallest time interval that had to be readily resolved in the digital frac-tional and phase detector was a time to digital converter (TDC) inverter delay

tinv. The number of inverters placed would be considered as the back bone of the

time to digital converter [10].

Figure 4.3. Positive phase error [10].

Figure 4.4. Negative phase error [10].

In the digital deep-submicron CMOS process, an inverter could be considered as a basic precision time-delay cell. It should be considered as it is possible to achieve substantially better resolution than an inverter delay for the time to digital converter (TDC) to digit function. A method called vernier delay line with two non-identical chain of buffers were used. It has slower chain and faster chain. The slower chain of buffers were stabilized by negative feedback through a delay line. The buffer time propagation difference produces the resolution and their disadvantage was the power consumption and analog circuit.

Digital fractional phase is defined by feeding the DCO clock through a chain of inverters which was implemented in the time to digital converter, such that each

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inverter output would give out a clock with a slight delay from that of the previous inverter. The staggered clock phases are then sampled by the same reference clock. This is done by an array of registers whose Q outputs form a pseudo-thermometer code. In this structure there would be a series of 1’s and 0’s [10].

The number of taps L required for the TDC is determined by how many in-verters were needed to cover the full DCO period and it is given as

L ≥ max(Tv) min(tinv)

(4.1)

If there are too many inverters placed, the circuit would look more complex and consumes more power than the normal. Consider for example, if there are ten inverters placed, inverters nine and ten would be beyond the first full cycle of eight inverters and are not needed because the pseudo-thermometer decoder is based on a priority detection scheme and earlier bits would always be considered first. It is good to practice and keep a margin to guarantee perfect system operation at the fast corners and in the lower frequency of DCO operation.

If the time to digital converter (TDC), is chosen as a symmetric sense-amplifier based flip-flop, inputs which are in the differential form guarantees substantially identical delays for rising and falling input data [10].

4.1.2 Reference edge estimation to reduce power

consump-tion

Time to digital converter with FREF prediction reduces the power consumption through a power management which has a scheme with intelligence in it. This actually performs periodic gating of the digitally controlled oscillator clock inside the time to digital converter (TDC) by just predicting where the next FREF edge might lie. The timing information lies in the edges of FREF clock.

After a certain length of operational time, an information which is far enough could be gathered about both clock phases and their statistics to reduce power. The selected word registers are only clocked to reduce the power consumption and save the transition power and reduce noise [10].

4.1.3 TDC resolution

The phase error from the time to digital converter is linear which was same as the phase detector’s output in the conventional PLL. But it is quantized in ∆trestime

units.

L ≥ max(Tv) min(tinv)

(4.2)

∆tres = tinv

The TDC quantum step ∆tresdetermines the quantum step of the fractional error

correction, which in normalized unit is expressed as ∆ε = ∆tres

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4.2 Digitally controlled oscillator 29

Figure 4.5. TDC quantized transfer function [10].

4.2 Digitally controlled oscillator

From a theory point of view, stating that time-domain resolution was superior to voltage-domain resolution. The digitally controlled oscillator presented in this implementation was built with only digital inputs and outputs operating in the discrete-time domain, even though the main functionality was continuous time and amplitude in nature. This was a very important consideration since it stops the analogous nature.

A digitally controlled oscillator (DCO) was used in order to perform digital to frequency conversion (DFC). The output was a periodic waveform, frequency f is a certain function of the input oscillator tuning word (OTW) where frequency f is

frequency f = F(OTW)

In general, F(OTW) mapping of digital input to the oscillation frequency was method of non-linear function. The frequency setting function was not known precisely and differ with the process spread, voltage and temperature. An instan-taneous value of the frequency lies on power or ground and substrate noise, flicker noise and thermal noise as well [10].

The digitally controlled oscillator (DCO) described in the following section was built using an LC oscillator with fixed inductance and variable capacitance. The variable capacitance in a digital CMOS process could be built efficiently by using MOS varactors and MIM capacitors.

4.2.1 Digitally controlled oscillator gain

Digitally controlled oscillator was considered as heart of the frequency synthesizer and it was implemented with the digital components. It generates output with an

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oscillation frequency which was considered as an inherent function of the oscillator tuning word (OTW). The input to the DCO was control bits from the time to digital converter.

In general, F(OTW) was a non-linear function of an input. However, within a limited range of operation, it could be approximated by a linear transfer function and the gain of the oscillator is KDCO.

fv = fo+ KDCO.OT W (4.3)

where ∆fv is frequency deviation and fo is center frequency. KDCO is said as

a frequency deviation ∆fv in hertz from a certain oscillating frequency fv in

re-sponse to 1 LSB input change. For this reason, KDCO is identical with the ∆f

frequency resolution. Within a linear range of operation, the DCO gain could also be expressed as

KDCO(fv) =

∆fv

∆(OT W ) (4.4)

4.2.2 DCO tuning word re-timing

Figure 4.6. Capacitance change of an LC oscillator [10].

DCO input tuning word re-timing method is an idea based on changing the tuning control input of a digitally controlled oscillator to adjust its phase and frequency in normal operation of the PLL. The normal operation of the PLL was considered as a disturbing action that produces an output with huge jitter or phase noise.

This could be very well noticed in the DCO, where the frequency of an oscil-lation is commanded to change at discrete times. Since the oscillating frequency of a LC tank was controlled by varactors which does the function of voltage to capacitance conversion.

The total charge should be stored, by changing the capacitance at these time causes the electrical potential to exhibit the largest change ∆V = _∆CQ , as shown

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4.2 Digitally controlled oscillator 31

in Figure 4.6. These perturbations were translated by the oscillator circuit into timing jitter. By changing the capacitance of the varactor during the time when it gets discharged entirely would affect the voltage slightly and thus eventually contribute very little to the oscillating jitter [10].

4.2.3 Design of varactors in deep-submicron CMOS process

Figure 4.7. MOS varactors vs. control voltage (deep-submicron) [10].

Basically the oscillator has the highly non-linear frequency vs. voltage character-istic. Because of this nature of an oscillator, it is quite a difficult task to built an oscillator with low voltage and better frequency tuning in deep-submicron CMOS, thus a careful handling of the design must be considered from the beginning.

Figure 4.7 shows the characterization of the MOS varactors vs. control voltage in both deep-submicron and traditional CMOS process.

Figure 4.7 depicts that bringing the frequency tuning of the digitally controlled oscillator and making it act in linear range is such a difficult task in deep-submicron CMOS process.

4.2.4 Design and behaviour of the PMOS varactor

The PMOS is a good candidate for designing the MOS varactor of the DCO, it is because due to the isolation property in the N-well process. In this configuration, the source, the drain and the well are all tied together to ground. Considering the two stable binary controlled operating points, one is said to be on-state region of the depletion mode and the other is off-state region of the inversion mode.

When the gate was charged positively, it attracts more electrons, which are said to be the majority carriers of an n-type well. Capacitance of the varactor is high, it is because this structure almost acts like a capacitor which imitates the parallel plate capacitor with just silicon oxide dielectric in between. The capacitor is formed as usual capacitor with two plates, in which gate conductor forms a plate

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Figure 4.8. Physical structure of PMOS transistor.

and the other plate is formed by the electrons in the N-well and it is thus termed as the accumulation mode.

When the gate voltage is lowered, very few electrons are attracted to the region which is below the gate, which makes the lower plate to be separated and eventually lowering the gate-to-well capacitance.

As the gate potential becomes zero, it ends in a negative value, the electrons then begin to repel, leaving the depletion mode beneath the gate and it is termed as depletion region. When the depletion is increased further and the capacitance lowering simultaneously results in attracting the holes to the region beneath the gate. Since, the bottom plate is lowered well below the gate oxide the gate capac-itance becomes high again.

In the structure of this varactor, the source, drain, and bulk are tied to ground. This behaves in the similar way as classical MOS varactor behave except which has source and drain, which a classical MOS varactor does not consist. The channel never gets formed and destroyed for the RF frequency range. In order to create a channel, the inversion region in the MOS capacitor relies on a process of regen-eration of electron and regenregen-eration of hole pairs, which takes an extremely long time [10].

4.3 Binary weighted switched capacitors and

var-actors

In this section we would look into an implementation of the tuning banks. Implementation of varactors was shown in this chapter and an idea over binary weighted switched capacitor structure has also been briefed. An array of varactors placed would switch from high to low and low to high capacitance mode. To achieve better resolution varactor banks were designed for three different modes and the modes are

1. PVT

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4.3 Binary weighted switched capacitors and varactors 33

3. Tracking

These modes would be discussed in the following section 4.4 in detail.

4.3.1 Construction of LC tank with switched capacitor

In this section we would discuss on how to build the LC tank along with the varactors. The system level digitally controlled oscillator is shown in Figure 4.9.

As we know the resonant frequency of the LC tank is

f = 1

2π√LC (4.5)

The resonant frequency could be varied by changing either the inductance or ca-pacitance of the LC oscillator. Like we mentioned earlier, the negative resistance helps in building the oscillation of an oscillator. We could not directly change or tune the values of inductor, because inductor should be considered as fixed value. The capacitance could be varied to achieve the desired center frequency. Having the capacitance varied always, helps to tune the oscillator to desired frequency.

Figure 4.9. LC tank with varactor array [10].

N digitally controlled capacitors were said as varactors, which might or might not follow binary weighted pattern of their capacitance. The resonant frequency 4.5 now can be rewritten as

f = 1 2π q LPN −1 k=0 C (4.6)

Digital inputs to the varactors would decide on whether the capacitance should switch to high capacitive state C1,kor to low capacitive state C0,k that was placed

as an array of capacitors. The capacitance difference between the high and low-capacitive states.

The difference is said as

∆Ck = C1,k− C0,k (4.7)

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The oscillation grows when the value of the capacitance was small. So, when the digital input given was increasing, the frequency should also increase. So, the digital bits had to be inverted before feeding it to the varactors and it is shown in 4.8

Ck = C0,k+ bk∆Ck (4.8)

This should make easy from the implementation point of view. Equation 4.6 can be rewritten as f = 1 2π q LPN −1 k=0(C0,k+ bk∆Ck) (4.9)

4.4 Modes of tuning

The digitally controlled oscillator was designed for the frequency synthesizer. This oscillator was intended to operate and track even in low frequency range, so that it makes the system to be locked after the settling time. So, to operate in a better way and make the system lock, the DCO should adjust itself or should be tuned to a center frequency which helps in locking the PLL. There were different types of modes to be followed and they are

1. Process voltage and temperature calibration 2. Acquisition and

3. Tracking

Figure 4.10. Modes of tuning [10].

4.4.1 Process voltage and temperature (PVT)

The PVT was active during the normal operation of the DCO and it operates at the start of the PLL and brings the nominal center frequency of the DCO. This PVT has the wider frequency range ∆fmaxwhich would range upto 500 MHz than

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4.5 MOS varactors 35

which could be denoted as ∆fs. PVT worked efficiently due to 8-bit input. The frequency range was dependent on the value of the capacitance we choose.

4.4.2 Acquisition mode

The acquisition mode starts operating during the settling process of the PLL, it had the medium frequency range which would be smaller than the PVT frequency range ∆fmaxwhich might range in few 100 MHz and it had the medium frequency

step ∆fs _{range in few 100 kHz. It is better to have the resolution of acquisition}

same as PVT mode.

4.4.3 Tracking mode

The tracking mode starts after the PLL was settled, it had the frequency range ∆fmaxranging in few MHz and the frequency resolution ∆fsranging in few kHz.

The capacitance value would range in atto farad (aF).

4.5 MOS varactors

The varactor banks were mainly implemented to achieve better tuning range and help the PLL lock the oscillating frequency with the reference frequency. These types of varactors has both advantages and disadvantages. We earlier discussed about the constraints of the varactors. Now we would look into the design and method of implementing the tuning MOS varactors for the digitally controlled os-cillator. The varactors were implemented in three different ways as three different banks.

PVT bank

The PVT bank had a unit cell with differentially connected metal oxide capacitors on either side of the switch, the switch was placed in series with the capacitors, since NMOS was better candidate in pulling down, two NMOS transistors were placed which effectively pulled down the unit cell between high and low capacitance states [11]. The structure is shown in Figure 4.11.

This structure was chosen for it had good frequency stability and it also had high immunity against the noise with respect to the digital control line voltage. The PVT bank was a 8-bit binary weighted, 256 unit cells were placed inside the PVT bank and with the thermometer decoder (Binary to thermometer decoder), digital input was fed to the PVT bank. The frequency range is ∆fmax.