Investigation of Mechanisms for Spur Generation in Fractional-N Frequency Synthesizers

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Institutionen för systemteknik

Department of Electrical Engineering

Examensarbete

Investigation of Mechanisms for Spur Generation in

Fractional-N Frequency Synthesizers

Examensarbete utfört i Elektroniksystem vid Tekniska högskolan vid Linköpings universitet

av

Sohail Imran Saeed

LiTH-ISY-EX--12/4613--SE

Linköping 2012

Department of Electrical Engineering Linköpings tekniska högskola

Linköpings universitet Linköpings universitet

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Investigation of Mechanisms for Spur Generation in

Fractional-N Frequency Synthesizers

Examensarbete utfört i Elektroniksystem

vid Tekniska högskolan i Linköping

av

Sohail Imran Saeed

LiTH-ISY-EX--12/4613--SE

Handledare: Supervisor

Michael Peter Kennedy, Tyndall National Institute/University College Cork, Ireland

Examinator: Examiner

Mark Vesterbacka, ISY, Linköpings universitet, Sweden

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Avdelning, Institution

Division, Department

Division of Electronics Systems Department of Electrical Engineering Linköpings universitet

SE-581 83 Linköping, Sweden

Datum Date 2012-007-003 Språk Language Svenska/Swedish Engelska/English Rapporttyp Report category Licentiatavhandling Examensarbete C-uppsats D-uppsats Övrig rapport

URL för elektronisk version

http://www.es.isy.liu.se http://www.es.isy.liu.se ISBN — ISRN LiTH-ISY-EX--12/4613--SE

Serietitel och serienummer

Title of series, numbering

ISSN

—

Titel

Title Investigation of Mechanisms for Spur Generation in Fractional-N Frequency Synthesizers

Författare

Author

Sohail Imran Saeed

Sammanfattning

Abstract

With the advances in wireless communication technology over last two decades, the use of fractional-N frequency synthesizers has increased widely in modern wireless communication applications due to their high frequency resolution and fast settling time.

The performance of a fractional-N frequency synthesizer is degraded due to the presence of unwanted spurious tones (spurs) in the output spectrum. The Digital Delta-Sigma Modulator can be directly responsible for the generation of spur because of its inherent nonlinearity and periodicity. Many deterministic and stochastic techniques associated with the architecture of the DDSM have been developed to remove the principal causes responsible for production of spurs. The nonlinearities in a frequency synthesizer are another source for the generation of spurs. In this thesis we have predicted that specific nonlinearities in a fractional-N frequency synthesizer produce spurs at well-defined frequencies even if the output of the DDSM is spur-free. Different spur free DDSM architectures have been investigated for the analysis of spurious tones in the output spectrum of fractional-N frequency synthesizers.

The thesis presents simulation and experimental investigation of mechanisms for spur generation in a fractional-N frequency synthesizer. Simulations are car-ried out using the CppSim system simulator, MATLAB and Simulink while the experiments are performed on an Analog Devices ADF7021, a high performance narrow-band transceiver IC.

Nyckelord

Keywords Frequency Synthesizer, Spurs, Phase Nois CppSim, Digital Delta Sigma Modulator, MASH, Phase Locked Loop)

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Abstract

With the advances in wireless communication technology over last two decades, the use of fractional-N frequency synthesizers has increased widely in modern wireless communication applications due to their high frequency resolution and fast settling time.

The performance of a fractional-N frequency synthesizer is degraded due to the presence of unwanted spurious tones (spurs) in the output spectrum. The Digital Delta-Sigma Modulator can be directly responsible for the generation of spur be-cause of its inherent nonlinearity and periodicity. Many deterministic and stochastic techniques associated with the architecture of the DDSM have been developed to remove the principal causes responsible for production of spurs. The nonlinearities in a frequency synthesizer are another source for the generation of spurs. In this thesis we have predicted that specific nonlinearities in a fractional-N frequency synthesizer produce spurs at well-defined frequencies even if the output of the DDSM is spur-free. Different spur free DDSM architectures have been investigated for the analysis of spurious tones in the output spectrum of fractional-N frequency synthesizers.

The thesis presents simulation and experimental investigation of mechanisms for spur generation in a fractional-N frequency synthesizer. Simulations are carried out using the CppSim system simulator, MATLAB and Simulink while the experiments are performed on an Analog Devices ADF7021, a high performance narrow-band transceiver IC.

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Acknowledgments

First and the foremost, I would like to thank Allah Almighty, who bestowed His mercy upon me throughout the course of my life.

I wish to express my sincere gratitude to Prof. Michael Peter Kennedy at Tyndall National Institute and University College Cork, Ireland, for his enthusiastic super-vision and making this work a magnificent experience for me. This work would not have been accomplished without his valuable guidance, advice, appreciation, and supervision. I would specially, like to thank Prof. Mark Vesterbacka for his appreciation to carryout this research work and being the examiner of this thesis at Linköping university, Sweden. I also acknowledge the support of Vahideh Sadegh Sadat from Babol University, Iran, for her continuous support at all the times during this research work.

I am thankful to all my friends from Linköping University, Sweden and Tyndall National Institute, Ireland. I have taken efforts in this project, however, it would not have been possible without the kind support and help of many individuals and organizations. I would like to thank to the countless people around me who made this day happen.

...

Finally, I dedicate this work to my father, mother and my sister.

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Introduction

This chapter provides a brief description of frequency synthesizers and the research objectives of this project. Section 1.1 describes the background and presents an introduction to frequency synthesis. The need for spectral purity in transceiver applications and problem of spurious tones (spurs) when synthesizing a frequency by phase lock are presented in section 1.2. Section 1.3 explains the spurs in the output spectrum of a frequency synthesizer while section 1.4 provides a brief intro-duction to spurs coming from DDSM when using delta-sigma frequency synthesis. The principal contribution of this thesis in the area of frequency synthesizers is summarized in section 1.5. The organization of the thesis is described in section 1.6.

1.1 Background

With the development in wireless communication technologies over past few decades, the use of frequency synthesizers has become ubiquitous in the current wireless communication systems. Frequency synthesizers was first developed in attempt to tune the local oscillator to generate the required frequencies without manual input.

A wireless transceiver is required to generate a wide range of frequencies to up-convert outgoing data for transmission and then to down-up-convert the received signal [2]. This generation of a range frequencies in transmitter and receiver from a single reference frequency source is generally referred to as frequency synthesis. It is a fundamental part of wireless communication systems. The frequency synthesizer

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8 Introduction

in a transceiver system is responsible for frequency synthesis. Fig. 1.1 shows a transceiver with synthesizer which generates the required frequencies.

Figure 1.1: General block diagram of a transceiver [2]

A number of techniques are used for frequency synthesis but Phase Locked Loop (PLL) based frequency synthesizers are dominant in current wireless communication systems. In the scope of this thesis, we will discuss the only based fractional-N frequency synthesizers.We will also discuss the fundamental blocks of a PLL based frequency synthesizer, problems associated with the phase noise spectrum, and the motivation for carrying out the research on this topic.

1.2 The Need for Spectral Purity in Transceiver

and Issue of Spurs

A frequency synthesizer generates a signal which is ideally a single tone in the frequency domain. In reality, the signal is not pure at all because the unwanted noise is added randomly or deterministically, making the spectrum impure. In transceiver applications it is important to have a pure spectrum without any unwanted tones, in order to avoid the corruption of desired data. Fig. 1.2 shows

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1.3 Spurious Tones (Spurs) in Spectrum of Frequency synthesizer 9

impact of unwanted tone (interferer signal) in the spectrum that may result in false detection of the original signal or reduction of SNR and hence the corruption of data.

Figure 1.2: An illustration of reduction in SNR caused by an interferer signal (Spur) in a wireless receiver

1.3 Spurious Tones (Spurs) in Spectrum of

Fre-quency synthesizer

Spurs are unwanted tones which appear in the spectrum of a frequency synthesizer and distort its performance. There are generally different types of spurs that depend on the sources of their generation. The spurs result from frequency modulation (FM) in the VCO of a PLL during the voltage to frequency conversion process and

is modelled mathematically as:

Vm(t) = ∆Vpeak.sin(fmt), (1.1)

where Vmis a sinusoidal input voltage to the VCO with a frequency equal to fm.

The peak frequency deviation ∆fpeakis given as

∆fpeak= KV CO.∆Vpeak, (1.2)

where KV CO is the gain of the VCO and the FM modulation index is then given

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10 Introduction

m = ∆fpeak

fm

. (1.3)

Figure 1.3 shows a typical plot of power spectral density (PSD) of the phase noise of the synthesizer. The strong periodic components are spurs.

Figure 1.3: Spurious phase noise response of a fractional-N frequency synthesizer Some of the problems related to spurs and phase noise in the spectrum can be alleviated by reducing the PLL bandwidth but then the PLL suffers from long settling time. It also puts strict requirements on the VCO’s noise performance. The trade-offs in characterizing synthesizer’s performance in relation to phase noise, spurious tones, and the settling time are shown in figure 1.4.

1.3.1 Reference Spurs

In the PLL based frequency synthesis, the generation of reference spurs is a common phenomena. The PFD periodically periodically updated its output in a PLL that gives rise to reference spurs in the output spectrum of a synthesizer. Among the other major causes are the leakage currents in the components and current mismatch in the up and down currents of charge pump. Leakage effects are one of the dominant reasons for spurs. The output of a charge pump is ideally constant but there will always be a small leakage current flowing through the circuit because of non-ideal components. This will result in pulses of current with a long period at the output of charge pump [6]. Ideally, there should be no mismatch between the

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1.3 Spurious Tones (Spurs) in Spectrum of Frequency synthesizer 11

Figure 1.4: Trade-offs on synthesizer’s performance in terms of phase noise, spurs, and the settling time [1]

up (source) and down (sink) currents of a charge pump. In reality, there is always a mismatch between the source and sink of a charge pump because of different turn on times of the NMOS and PMOS transistors in the circuitry; this introduces a piecewise linear nonlinearity into the system. The unbalanced operation of the charge pump in the PLL, mainly because of different turn-on times of NMOS and PMOS transistors, is one of the important reasons for the spurs in output of the LO spectrum. [7]. These make the charge pump the dominant block that determines the level of the unwanted FM. Reference spurs generally appear out of the PLL bandwidth therefore the use of higher order loop filter in the PLL can ensure the suppression of these spurs. Other techniques [8], [9] have been developed to minimize the effects of these spurs in a communication system.

1.3.2 Fractional Spurs

Fractional spurs are an inherent problem in fractional-N frequency synthesizers. These spurs generally appear because of the fractional dividers used to instanta-neously modulate the output frequency of the synthesizer.

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12 Introduction

1.3.3 Integer Boundary Spurs

In the spectrum of the output of a fractional-N frequency synthesizer, integer boundary spurs appear close to integer multiples of the reference frequency gener-ated by the VCO. These spurs are a cause of major concern due to the fact that they lie very close to the LO’s centre frequency, often within the loop bandwidth of the synthesizer and where they cannot be removed by filtering.

Fig. 1.5 shows the VCO spectrum with integer boundary spur, obtained using a spectrum analyser measuring an Analog Devices ADF7021 evaluation board with a reference frequency of 19.68 MHz, and a divide value of 45 +₃₂₇₆₈150.5.

Figure 1.5: Spectrum of a synthesizer with integer boundary spurs

1.4 Specific Issue of Issue of Spurs Coming from

DDSM

The fractional divide value in a fractional-N frequency synthesizer is instantaneously modulated using Digital Delta Sigma Modulators (DDSM). It is an inherent property of DDSM that its output spectrum has spurious tones which are introduced into the phase noise spectrum of fractional-N frequency synthesizer. Therefore a DDSM can

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1.5 Contribution of this Thesis 13

be responsible for the production of spurs in the output spectrum of a fractional-N frequency synthesizer. Several deterministic and stochastic techniques have been developed over time to produce a highly pure spectrum at the output of the DDSM but even if the spectrum of the DDSM is clean, the spurs reappear in the output spectrum of the fractional-N frequency synthesizer. These spurs can be integer boundary spurs as well as out-of-band spurs. As discussed earlier, integer boundary spurs cannot be eliminated by increasing the order of the filter because they lie in the pass band. Therefore these are of major concern due to their effect on the performance of fractional-N frequency synthesizers. The DDSM will be discussed in detail in Chapter 3. Figure 1.6 show the spurious output spectrum of a MASH 1-1-1 DDSM when fractional numbers of 0.5 is used as input to the DDSM.

Figure 1.6: Spectrum of MASH1-1-1 DDSM with fractional input of 0.5

1.5 Contribution of this Thesis

In this thesis, we predict the location of spurs in the output the spectrum of a frequency synthesizer. Hosseini and Kennedy [4] predicted the location of the dominant spur in the spectrum of a stand-alone DDSM when its output is passed through a memoryless nonlinearity. Their observations were accompanied by the simulation results using MATLAB. Inspired by the work in [4], we have made observations regarding the generation of spurs in the output of a fractional-N

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14 Introduction

frequency synthesizer. We have predicted the location of spurs in LO spectrum and the results are verified experimentally against the simulations performed using CppSim [10].

1.6 Thesis Organization

The thesis is organized into seven chapters. Chapter 1 introduces the topic under discussion and explains the phenomena of spurious tones in the output spectrum of fractional-N frequency synthesizers, which is the main motivation for underlying research. Constituent parts of a PLL-based Frequency synthesizer are explained in the chapter 2. In Chapter 3, a brief introduction of Digital Delta Sigma Modulator (DDSM) is provided. Concepts related to dithering and spur free DDSM structures are also discussed in this chapter. Chapter 4 presents detailed theoretical and simulation analyses of the spur locations generated by DDSM output signal when it is passed through a memoryless nonlinearity. In Chapter 5, the simulation setup and different parameters used to simulate our fractional-N frequency synthesizer are discussed. An analysis of the simulation and experimental results is provided in Chapter 6, while in Chapter 7 the conclusions of this work are presented along with further exploration possibilities on this topic.

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Chapter 2

Frequency Synthesis

2.1 Integer-N Frequency Synthesizers

The integer-N frequency synthesizers are widely used in wireless communication. It is one of the popular forms of the PLL-based frequency synthesis. The structure of a PLL-based frequency synthesizer consists of a reference oscillator that generates a reference frequency. The PLL is used to synchronize the reference and divided frequency. The phase of reference signal and the divider signal derived from the output of a voltage controlled oscillator (VCO) is compared by the phase frequency detector. The output of phase frequency detector is the current source to the loop filter that generates the current based on phase difference of the two signals. The filter output voltage by loop filter acts as the control voltage of a VCO that adjusts the frequency to keep the phases of both the signals matched. The integer-N frequency synthesizers use digital counter for the division of output frequency generated by VCO. Only the integer values are used to divide the VCO frequency in an integer-N frequency synthesizer. Figure 2.1 shows the block diagram of an integer-N frequency synthesizer. In a digital PLL-based frequency synthesis, the frequency is multiplied by N that raises the signal phase noise by 20log(N ) dB. As the multiplication by N is unavoidable in PLL based frequency synthesis, N becomes the limiting factor to determine the lowest possible phase noise performance of a frequency synthesizer. Phase detector’s noise characteristics of active circuitry is the main source of noise. For instance, a multiplication by of N = 30, 000 adds about 90 dB to the phase detector noise floor. 30,000 is a typical N value which is used in an integer-N PLL frequency synthesizer for a cellular transceiver with 30 kHz channel spacing. In the integer-N frequency synthesizers, large values of N are used to generate a range of output frequencies for desired channel spacing. Other

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16 Frequency Synthesis

Figure 2.1: Block diagram of a typical integer-N frequency synthesizer

than the noise floor issues, the requirement of faster settling time and frequency resolution are the issues of concern with the integer-N Frequency Synthesizers.

2.2 Fractional-N Frequency Synthesizers

A fractional-N frequency synthesizer is a variant of an integer-N frequency synthe-sizer, having the same functional blocks but using a fractional-N divider instead of integer-N divider. Fractional-N frequency synthesizers are used widely in modern wireless communication systems. Particularly, the Delta Sigma fractional-N fre-quency synthesizers are most popular due to their fine grain frefre-quency synthesis, fast settling time, and quick frequency switching [11], [12], [13]. The possibility to implement all the blocks on a single chip using PLL frequency synthesizer architecture has contributed to making it a more viable solution than others.

Figure 2.2 shows the block diagram of a fractional-N frequency synthesizer. It consists of a reference oscillator, a Phase-Frequency Detector (PFD), a Charge Pump (CP), a low pass filter (LPF), a Voltage-Controlled Oscillator (VCO) and a fractional-N whose fractional divide value is modulated by a Digital Delta-Sigma Modulator (DDSM). Negative feedback of divided signal is used to settle the control voltage (VCT RL) of the VCO. A PFD compares the arrival time of output signal of

fractional frequency divider with reference signal which is generated by a reference oscillator. Charge pump (CP) and loop filter relate the output of PFD to the control voltage which is the input to a VCO.

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2.2 Fractional-N Frequency Synthesizers 17

Figure 2.2: Block diagram of a fractional-N frequency synthesizer

2.2.1 Phase Frequency Detector

The output of a PFD is a series of pulses. The widths of these pulses are functions of corresponding phase difference between the rising edges of the reference signal and divided signal [11]. The PFD has phase difference resolution range of ±2π. The operation of a PFD can be divided into three operational modes namely the frequency detect, phase detect and phase locked modes depending on phase difference between these two signals. The PFD is in the frequency detect mode when the phase difference is more than 2π. While in frequency detect mode, the output current of charge pump remains constant. This results in a continuously changing voltage signal at the input of the VCO because of the integration action performed by the filter [2]. The PFD starts operation in the phase detect mode when the phase difference between two input signals falls below 2π. In this mode the Charge Pump will only operate for a part of each cycle of phase detector. Fig. 2.3 [2] shows that the Charge Pump is active only when there is a phase difference between the reference and divided signal. The loop enters in phase locked state once the phase difference between the two signals becomes zero; thus, the PFD operates in phase locked state in this case. In this mode, the VCO receives a constant control voltage signal at its input.

2.2.2 Charge Pump

Charge pump translates the phase difference calculated by PFD into the input current to loop filter. Therefore in a PLL it is used as a current source to the loop filter. Figure 2.4 shows the schematic of a charge pump.

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18 Frequency Synthesis

Figure 2.3: Phase Detector output in the phase-detect mode [2].

2.2.3 Loop Filter

In a frequency synthesizer, a low pass filter is used to eliminate the unwanted out of band tones caused by the quantization of the divider in fractional-N frequency synthesizer and the ones generated by different kind of non-linear behaviours in a PLL-based in a mixed signal system. the figure 2.5 shows a general schematic of a third order passive low pass filter filter.

2.2.4 Voltage Controlled Oscillator

The voltage controlled oscillator generates the output frequency signal of a syn-thesizer. These are feedback amplifiers that consist of a tuned resonator in the positive feedback loop or the ring oscillators [2]. The resonant tank of a VCO can be tuned by the control voltage VCT RL which is applied to a varactor in the tank

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2.2 Fractional-N Frequency Synthesizers 19

Figure 2.4: A general schematic of charge pump where Iinin input current p loop

filter

Figure 2.5: A typical third order passive loop filter

2.2.5 Divider

Divider is used in the feedback path from the VCO to PFD to divide the output frequency and match it with the reference frequency that is input to the PFD. In a fractional-N frequency synthesizer, the divider value is given by

Divider =

Nint+ f rac

(2.1) where, Nintis the integer divide value while f rac represents the fractional part in

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Chapter 3

Digital Delta Sigma

Modulator (DDSM)

3.1 Introduction

Digital Delta Sigma Modulators are widely used in the integrated circuits for digital audio and wireless communications systems. It is particularly, extensively used in the frequency synthesizers and digital to analog converters. It is a nonlinear system that exhibits the properties of dynamical nonlinear systems like sensitivity to initial conditions, oscillations and sensitivity to input [3]. The DDSM reduces the wordlength of an oversampled digital signal with negligible degradation in signal to noise ratio (SNR) in the signal band. DDSM reduces the complexity of circuity in a mixed-signal system by reducing the bus width that adds to viability of using DDSMs in a mixed signal system but it adds the unwanted tones (Spur) in its output spectrum that can have drastic effects on the performance of the system.

DDSM reduces the word length of an oversampled digital signal that reduces the bus width and complexity of analog circuitry in mixed signal syetem. This also results in efficient digital signal processing (DSP) in terms of power consumption and speed with an add-on of negligible performance degradation.

Figure 3.1 shows a general block diagram of a DDSM that takes a band limited digital signal as input which is no-bits wide i.e. quantized to no bits. The input

signal is requantized to produce a shorter m bit(s) wide. The requantization of 21

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22 Digital Delta Sigma Modulator (DDSM)

Figure 3.1: Block diagram of a DDSM (illustration)

input signal introduces additional quantization noise which is high pass filtered. Along the processing chain, this noise is further low pass filtered to be removed.

This chapter explains the behaviour of delta sigma modulator and different issues related to the generation of spurious tones in its output spectrum.

3.1.1 Error Feedback Modulator (EFM)

In the figure 3.2(a) first order error feedback modulator is shown. It comprises of summing node, a quantizer Q(.), memory element which is denoted by z−1 and a scaling element with the scaling factor of M .

The transfer characteristics of 1-bit EFM are analytically given as

Q(v) =

0, v[n] ≤ M

1, v[n] ≥ M (3.1)

where M is the modulus of the quantizer and is defined by M = 2no _{,and n}

ois the

word length of the accumulator. The EFM1 can be implemented as an accumulator that consists of a full adder and register. The signal e[n] refers quantization error and corresponds to the nobit sum. The signal y[n] corresponds to 1-bit carry out

of a full adder which has no-bit input and an no-bit register, see figure3.3.

As seen in figure 3.2(c),the quantization eq noise is added to output and thus can

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3.1 Introduction 23

Figure 3.2: (a) First order EFM; (b) Transfer characteristics of a 1-bit quantizer;(c) A linearised EFM1 model [3]

The output of EFM1 is defined as

y[n] = 1

Mv[n] + eq[n] (3.2)

= 1

M x[n] + s[n] + eq[n] (3.3)

The signal e is given by following equation

e[n] = v[n] − M y[n] (3.4)

= −Meq[n] (3.5)

and

s[n] = e[n − 1] (3.6)

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Figure 3.3: EFM1 DDSM implemented as digital accumulator [3]

y[n] = 1

Mx[n] + (eq[n] + eq[n − 1]) (3.7)

For the frequency domain analysis, we take the z-transform of x, y and eq.

Y (z) = ST F (z)X(z) + N T F (z)Eq(z) (3.8)

where ST F (z) is signal transfer function and N T F (z) is noise transfer function.

X(z), Y (z) and Eq(z) are the z-transform of signals x, y and eq.

In the current discussion, DDSM simply scales the signal x, Therefore, the STF is given by:

ST F (z) = 1

M (3.9)

As discussed earlier, quantization noise is high pass filtered so the NTF is given by

N T F (z) = (1 − z1) (3.10)

This process of filtering the quantization noise in this way is called noise shaping. Therefore the output consists of the signal and high pass filtered quantization noise and is given as

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3.1 Introduction 25

Y (z) = 1

MX(z) + (1 − z

1_)E

(z) (3.11)

By using the correct filtering, the quantization noise can be attenuated from the signal band and then the removed along the signal chain by using the low pass filter. EFM1 can also be called as DDSM1 (First order DDSM)

In an EFM1 the classical model of quantization (CMQ) does not holds [3]. Specially the PSD of quantization noise is not flat/clean. Therefore it generates the spurs in output spectrum that degrades the performance of system.

3.1.2 MASH Structure

In [14] authors have shown that using the DDSM of order three or higher gives a flat noise spectrum. Cascaded blocks of EFM1 can be used to construct the higher order DDSMs. Figure3.4 shows the block diagram of an Lth_{-order DDSM}

constructed by using the cascaded blocks of EFM1 and noise cancellation network.

Figure 3.4: Block diagram of an Lthorder MASH DDSM [3]

3.1.3 MASH 1-1-1

A third order MultistAge noise SHaping (MASH 1-1-1) DDSM is constructed using the cascaded blocks of EFM1 [4]. in the remainder of this thesis, we will use the MASH 1-1-1 DDSM to carry out our simulations and experiments.

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Figure 3.5 shows the block diagram of a third order DDSM (MASH 1-1-1) con-structed from cascaded first order DDSM, used in [4]. Simulations to test the spectrum were carried out in MATLAB and CppSim [15].

Figure 3.5: Block diagram of a MASH 1-1-1 DDSM used in [4] The output spectrum of a MASH 1-1-1 is given in the figure 3.7

3.2 Dithering the input

Digital DSM differs from analog DSM in a way that DDSM are finite state machines (FSM) and it goes through a finite number of states called cycles.The input to DDSM and the output are all the integers and when the input is constant or periodic, the output is repeated based on the length of cycles. Borkowski etal. [16] have shown that DDSM with short cycles lengths produce strong spurs in the output of DDSM. Inspired from [16], Fitzgibbon and Kennedy developed the DDSM architecture that produces long cycles and hence results in a clean spectrum in the output [17]. One of the most common techniques used today to get a clean output spectrum of DDSM is called dithering. Generally pseudo random bits are added with the input of a DDSM to break the periodic patterns(cycles) in the DDSM. In our work, we have added one bit dither to the least significant bit (LSB) of the input to DDSM. Adding dither to the input considerably cleans the output spectrum of a DDSM but at the cost of relatively higher noise floor. We used non-shaped dither that means the random sequence is directly added to the input of DDSM. Figure3.6 shows the output of a DDSM when the dither is not added to the input. The input number to DDSM in this case is X = 0.5

The DDSM simulated with the same settings but with the addition of LSB non-shaped dither is shown in figure3.7. It can clearly be noticed that the addition of dither to the input has significantly removed the spurs from the output spectrum of DDSM.

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3.2 Dithering the input 27

Figure 3.6: Simulated PSD of un-dithered MASH 1-1-1 with the input of M/2

3.2.1 Shaped Dither

Dither adds to the noise floor of DDSM but significantly cleans the output spectrum of DDSM therefore it is widely used in the applications using the DDSMs. Shaping the dither reduces its effects on the noise floor. Shaping refers to the high pass filtering of dither before adding it to the input of DDSM. This filter is given by:

V (z) = (1 − z1)n (3.12)

where n determines the order of shaped dither.

Figure3.8 shows the comparison between the output of DDSM with the addition of non-shaped, first-order and second-order shaped dither

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Figure 3.7: Simulated PSD of output of MASH 1-1-1 DDSM with the LSB dithered input

Figure 3.8: Simulated PSD of MASH 1-1-1 simulated using (i) Non-shaped dither (ii) First order shaped dither (iii) Second order shaped dither

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Chapter 4

Prediction of Spur Locations

in LO Spectrum of DDSM

Followed by Memory-less

Nonlinearity

In this chapter, the analysis of spurs generation by DDSM when its output is passed through a memoryless nonlinearity is presented. The chapter explains that even if the spectrum of a DDSM itself is spur free, the inherent periodicity of the modulator still exists and spurious tones in the spectrum of DDSM can be seen at well defined positions. The idea comes from the fact that in mixed signal systems the non-ideal analog circuitry results in non-linear distortions which can produce the spurs in the spectrum of quantized digital sequence. As discussed in details in

Figure 4.1: Block diagram of DDSM

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30 Prediction of Spur Locations in LO Spectrum of DDSM Followed by Memory-less Nonlinearity

chapter 3, use of DDSM reduces the word length of an oversampled signal that also reduces the complexity of system but it is achieved at the cost of quantization noise and spurious tones in the spectrum. The output spectrum of a DDSM consists of the discrete tones called spurs. Many stochastic and deterministic techniques like using the least significant bit (LSB) dithering [18], [19] and maximizing the quantization error cycle lengths to minimize the power per tone [20] have been developed to address the problem of spurs.

The interaction between the analog circuitry and the quantization error in a mixed signal system results in a raised noise floor and spurs in the output spectrum when a DDSM is used to modulate the division ration [4]. The spurs still occur even if the spectrum if DDSM itself has been purified by using the mentioned techniques. These techniques ensure the clean spectrum of DDSM but when passed through a nonlinearity, the spurs appear in the output spectrum at well defined positions.

To the best of our knowledge, there is no satisfactory reason for the exact phenomena that generates spurs in the spectrum of a DDSM when its output subjected to non linear distortions. This chapters explains the important observations related to the generation of spurs in DDSM spectrum followed by nonlinearity.

4.1 Effect of nonlinear distortions on DDSM

The effect of nonlinear distortions when output of DDSM is subjected to them is discussed in the chapter to follow. Hosseini and Kennedy in [4] used as typical MASH 1-1-1 (DDSM3). MASH is constructed by using three cascaded blocks of single quantizer first order error feedback modulators (EFM1) given in Fig.4.2 . The accumulated Delta − Sigma error is then fed to a memoryless nonlinearity. Block diagram of model used for the simulations is given in Fig. 4.3 The operation

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4.1 Effect of nonlinear distortions on DDSM 31

of the 1-bit quantizer in the EFM1 is given as

Q(v) =

0, v[n] ≤ M

1, v[n] ≥ M (4.1)

where M is modulus of the quantizer and is defined by M = 2no _{, and n}

o is the

word length of the accumulator.

The input to a third-order DDSM which is labelled DDSM3 in Fig 4.5 comprises the signal x[n], which in this case, is a constant value, and the filtered dither. The dither is added in order to to break possible cycles to eliminate tones from the output spectrum of the DDSM [18] [19]. In our example, d[n] is a pseudo random dither sequence and V (z) shows the transfer function of the shaping filter. We consider an unfiltered dither, i.e. V (z) = 1. In a DDSM3, the error of the last stage of the DDSM3 (e∆Σ) is the only contributor to the shaped output quantization

noise.

A one-bit pseudorandom dither sequence d[n] is added to the LSB of the input x[n] and applied to the DDSM. The assumed properties of dither d[n] are as follows:

P (d[n] = 0) = P (d[n] = 1) = 0.5, ∀n ∈ Z (4.2)

The output of the DDSM consists of two components: the desired signal component,

Figure 4.3: Block diagram of Mash 1-1-1 DDSM [4]

which is given in Eq. (4.3) and the filtered dither signal given in Eq. (4.4), both of these signals are scaled by 1/M . The signal component can be removed by subtracting X/M , resulting the filtered dither and quantization noise. The output of MASH 1-1-1 is given as:

Y (z) = 1 M(X(z) + V (z)D(z)) + 1 M(1 − z −1₎3_E 3(z). (4.3)

Thus, The quamtization noise e∆Σ is characterized as:

E∆Σ= 1 MD(z) + 1 M(1 − z −1₎3_E 3(z). (4.4)

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in the equations (4.3) and (4.4), X(z) is Z-transform of input signal E3(z) is the

Z-transform of the quantization error of the third stage and D(z) is the Z-transform

of the dither added to the DDSM.

The DDSM3’s output noise is integrated that corresponds to a frequency-to-phase conversion [4], and the resulting error eaccis subjected to a memoryless nonlinearity.

In this case we considered a MASH 1-1-1 DDSM. The output frequency spectrum of a MASH 1-1-1 has a slope of +60dB/decade. Fig. (4.4) shows the PSD of output signal of a MASH 1-1-1.

Figure 4.4: Simulated PSD of output of MASH 1-1-1 DDSM

4.2 DDSM Followed by Memoryless Nonlinearity

in a Fractional-N Frequency Synthesizer.

A DDSM is responsible to modulate the fractional division ratio of the divider in a fractional-N frequency synthesizer [4]. The quantization noise and frequency error due to DDSM affect the phase noise of a frequency synthesizer. The introduction of a memoryless nonlinearity is motivated by the fact that in a mixed-signal system, the non-ideal behaviour of the circuitry adds nonlinearities. The output of

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4.3 Simulation Results 33

the DDSM is passed through these nonlinearities and this produces the spurious tones in the output spectrum of frequency synthesizer. Therefore, in a fractional-N frequency synthesizer, the DDSM can be considered as the major source of fractional spurs. Before the quantization noise of the DDSM appears as phase noise, it is accumulated due to integration in divider. [11]. The integration also corresponds to the frequency to phase conversion. Therefore, in the model used by Hosseini and Kennedy, shown in Fig.4.5, the output of DDSM is accumulated followed by a memoryless nonlinearity.

Figure 4.5: Hosseini and Kennedy’s model of DDSM followed by memoryless nonlinearity

E∆Σ and Eacc in Fig.(4.5) are time domain signals that correspond to the

quanti-zation error and integrated quantiquanti-zation error.

The accumulated error Eaccis given by:

Eacc(z) = 1 M(1 − z −1₎R−1 D(z) + 1 M(1 − z −1₎2_E 3(z) (4.5)

The reference signal and the divider signal are in phase only when the PLL is in the locked condition [4]. Considering the conversion from frequency to phase, the quantization noise is passed through an integrator. The output of the integrator (Eacc) is then applied to a memoryless nonlinearity.

4.3 Simulation Results

The system was simulated using both Matlab and CppSim. A nonshaped 1-bit dither is added with the LSB of the input sequence of DDSM. The simulation parameters are as follows: the initial conditions of all three stages are the S1[0] =

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S2[0] = S3[0] = 0, M = 215, and the input fractional value is X = 150 which

corresponds to a fractional value of 0.00459 in CppSim. The frequency axis in MATLAB is normalized but in CppSim, the real frequency fref = 19.68 MHz

is used to simulated the model. PWL and polynomial nonliear blocks are used separately to simulate the results for the comparison purposes. The fractional value corresponding to X =150 is given as follow.

X+0.5 M =

150.5

215 = 0.04593

The value of 0.5 is added to represent the mean value of the random dither signal which was added to the input of the DDSM, contributes to the location of the spur in the output spectrum of the DDSM followed by the nonlinearity.

The Fig.(4.6) shows the MATLB model that we used to perform the simulations.

Figure 4.6: MATLAB model used for simulations

The Matlab results are produced using the periodogram method described in [21] while in the CppSim the inbuilt PSD plotting function was used to view the simulated results.

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Figure 4.7 shows the model designed in CppSim to simulate and verify the results.

Figure 4.7: CppSim model used to simulate the results

Figure 4.8 shows the simulated PSD of Eacc using MATLAB. The spectrum has

slope of -20 dB/decade in the low frequencies and a slope of +40 dB/dec in high frequency region that is due to the integration associated with frequency-to-phase conversion, which has decreased the slope in both regions by 20 dB/dec. It can be seen that the spectrum is clean and there is no spur visible in this spectrum.

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The same results have been verified using CppSim and are presented in Fig. 4.9. This curve has the same qualitative behaviour. The small difference between the two curves is because of different methods employed to calculate the PSD of the output spectra.

Figure 4.9: Accumulated quantization noise seen in CppSim The nonlinearity used in the next simulation is defined by

g(eacc) = eacc+ 0.1|eacc| (4.6)

When the output of DDSM is passed through a memoryless PWL nonlinearity, two main observations can be made by looking at the spectra before and after nonlinearity. Firstly, the spectrum after passing through the nonlinearity has a raised noise floor and the spur is now clearly visible in both the MATLAB and CppSim simulations at exactly the same location.It is important to note that there could be more spurs at the integer multiples of the first spur but they are not visible due to the elevated noise floor. Figures 4.10 and 4.11 show the simulated results from MATLAB and CppSim. As per the predictions made by Hosseini and

Kennedy in [4] and [21] about the locations of spur generated by a DDSM when its

output is passed through a memoryless nonlinearity, the results are consistent with their finding for a polynomial nonlinearity. In particular, the location of dominant spur is given by fspur = 2  X + 0.5 M fref/2 = 0.00918fref/2 (4.7) In Fig. 4.10 the frequency axis has been normalized to fref/2 and the dominant

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Figure 4.10: PSD of DDSM followed by PWL nonlinearity

simulated PSD of the DDSM followed by a nonlinearity is shown in Fig. 4.11, the spur can be seen at 0.00459 × 9.84 MHz i.e. 90.331 kHz. The simulation results

Figure 4.11: PSD of DDSM followed by PWL nonlinearity, simulated in CppSim using a polynomial nonlinearity,

g(eacc) = −0.23 + 0.99eacc+ 0.32e2acc+ 0.15e

3

acc, (4.8)

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Figure 4.12: PSD of DDSM followed by polynomial nonlinearity

4.4 Investigation of Spur Free Structures

The proposed novel DDSM structures have a perfectly clean spectrum [17], [22]. Deterministic techniques have been developed that avoid the short cycles and their output spectrum is free of spurs. We investigated these structures by passing their outputs through a memory less non linearity. The simulation results confirmed that even if the the output spectrum of a DDSM is clean, the spur regrowth cannot be avoided when their output is subjected to a memoryless nonlinearity.

4.5 Analysis of Results

Apart from the DDSM structure investigated and presented in this chapter, we simulated different DDSM structures. Two main observations were made; first, the dominant spur appear at exactly the predicted location in the output spectrum, and second, even if the DDSM’s output spectrum is perfectly clean, the spurs regrow in the spectrum when the output of DDSM is passed through a memoryless nonlinearity.

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Chapter 5

Observations Related to

Spurs in Spectrum of

Fractional-N Frequency

Synthesizer

We have seen that performance of fractional-N frequency synthesizers in wireless communications applications is degraded by the presence of spurious tones and that the Digital Delta-Sigma Modulator (DDSM) can be directly responsible for the production of these tones. Several solutions have been prosed to prevent DDSM from producing short cycles and theoretically eliminating the spurs from its own output spectrum.

Unfortunately, cleaning up the spectrum at the output of the DDSM is only part of the solution to eliminating spurious tones. While the spectrum of the DDSM might appear clean, nonlinearities in the synthesizer may cause spurs to reappear in the synthesizer’s output, even though they are not present in the output spectrum of the DDSM itself. If these spurs are within the bandwidth of the synthesizer, they cannot be suppressed by the lowpass filter and therefore appear at the output of the VCO. These in-band spurs are also called integer boundary spurs.

Therefore, there is great practical interest in understanding the source of spurs resulting from nonlinearities and developing solutions to eliminate them.

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40 Observations Related to Spurs in Spectrum of Fractional-N Frequency Synthesizer

Wang et al. [8] have suggested a method for avoiding the regrowth of spurs by replacing the Σ∆ modulator with a new type of digital quantizer and a charge pump offset combined with a sampled loop filter.

Hosseini et al. have suggested that the root cause of the regrowth problem is correlations in the signal which are re-emphasized by frequency-to-phase conversion in the synthesizer [4]. They considered a Matlab model of a third-order MASH DDSM and showed how an integration followed by a polynomial memoryless nonlinearity causes an elevated noise floor and the emergence of spurious tones. Furthermore, they have predicted the existence of spurs at well-defined frequencies caused by this mechanism.

In Chapter 4, the predictions of Hosseini and Kennedy were simulated and verified. Their prediction is based on a simplified model by Perrott which estimates how shaped quantization noise introduced by the DDSM is translated into phase noise at the ouput of the frequency synthesizer.

While condidering the analysis of spurs in fractional-N frequency synthesizer, the two major sources of nonlinearity i.e. PFD and Charge pump are considered in this chapter. Simulation results are shown in the section 5.2

5.1 Nonlinearities in a Fractional-N Frequency

Syn-thesizer

There are several sources of nonlinearity in a fractional-N frequency synthesizer, including reset delay in the PFD, mismatch between the up and down currents in the CP, and a nonlinear voltage to frequency transfer characteristic of the VCO. We have shown that a memoryless piecewise-linear (PWL) nonlinearity, caused by the mismatch between the up and down currents in the CP can lead to an elevated noise floor. Lakhal et al. [23] have suggested that this type of nonlinearity can also lead to a dominant spur at a well-defined frequency.

5.1.1 Current Mismatch

Fig. 5.1 shows the structure of the charge pump we consider in this work. Current mismatch can be modelled by a memoryless nonlinearity with the idealized piecewise-linear transfer characteristic, as shown in Fig. 5.2.

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5.2 Simulation Setup 41

Figure 5.1: A simple structure of a charge pump

Figure 5.2: Transfer characteristic of a charge pump with mismatch

Analytically, we write:

Iin= avg {e(t)} + α|avg {e(t)} |. (5.1)

, where e(t) is difference between up and down currents of the charge pump given by:

e(t) = Down(t) − U p(t)

where U p(t) and Down(t) are source and sink currents of charge pump respectively.

5.2 Simulation Setup

The simulations of a fractional-N frequency synthesizer were carried out using the system simulator CppSim. Many different fractional values were used as input

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Figure 5.3: CppSim model of the fractional-N synthesizer used in this work

to the DDSM as test cases to characterise the phase noise. Different fractional numbers produce spurs at different locations in LO spectrum of Fractional-PLL. In the articles to follow, we have considered two different fractional numbers to analyse the spur in the output spectrum frequency. The input of X=700 produces the out of band spurs while X=150 produces in-band spurs.

A tristate phase frequency detector(PFD) with reset delay is used for simulation. Two sets of simulations were carried out using (i) a second order loop filter and (ii) a third order loop filter, respectively. Figure5.3 shows the model used for

simulations using CppSim.

5.3 Third Order PLL

In this section, simulation results for a third order fractional-N frequency synthesizer with a second order loop filter are presented.

The parameters used to simulate the model are given in the table 5.1

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5.3 Third Order PLL 43

Table 5.1: Parameters for simulation of a third order PLL Parameter Value KV CO 10 MHz/V fP D 19.68 MHz X 150, 1500 Nint 45 M 215 ICP 1.5 mA Filter Bandwidth 110 kHz fout = Nint+ X + 0.5 M fP D = 886.02071 MHz (5.2)

5.3.1 Fractional Input: X=700

When the input to DDSM is X =700, using the method of Hosseini et al. [4], we predict that the nonlinear spur in the output phase noise spectrum will be at an offset from the carrier of:

fspur =  X + 0.5 M fP D = 0.02138fP D = 420.71 kHz. (5.3)

The simulated result is shown in Fig. 5.4. It can be seen that a dominant, out of band spur appears in phase noise at frequently of 420.410 kHz. We believe that the small difference between the theoretical and simulated results is because of limited number of points on the simulated phase noise plot using CppSim.

5.3.2 Fractional Input: X=150

When the X=150 is used as the input to DDSM the spur is expected at

fspur =  X + 0.5 M fP D = 0.00459fP D = 90.3 kHz. (5.4)

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Figure 5.4: Spur in the output phase noise spectrum at 420.41 kHz with fractional input of X=700 and a second order loop filer

Fig. 5.5 shows the simulated phase noise. The dominant spur seen at the expected location

5.4 Fourth Order PLL

To match our simulations with the ADF7021 evaluation board which has a commer-cial fractional-N frequency synthesizer, we used a third oder loop filter to simulate the PLL. The evaluation board and experimental results are discussed in detail in next chapter. The table 5.2 shows the parameter values used for simulation of a fourth order PLL using a third order loop filter

Table 5.2: Parameters for simulation of a third order PLL Parameter Value KV CO 10 MHz/V fP D 19.68 MHz X 150, 1500 Nint 45 M 215 ICP 1.5 mA Filter Bandwidth 110 kHz

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5.4 Fourth Order PLL 45

Figure 5.5: Spur in the output phase noise spectrum with fractional input of X=150 and a second order loop filer

5.4.1 Fractional Input: X=700

Figure 5.3 shows the CppSim model used in this work [15]. The simulated phase noise spectrum at the output of the CP is shown in Fig. 5.6.

As expected, the spectrum contains the shaped quantization noise of the DDSM and its aliases, as well as feedthrough from the reference clock at frequencies fP D

and its harmonics. In addition, the spectrum contains a strong spur at 0.420 MHz, +20 dB above the noise floor. Note that this spur appears at precisely the location

predicted by Hosseini et al.. The simulated phase noise spectrum at the output of the synthesizer is shown in figure 5.7.

5.4.2 Fractional Input: X=150

In this case the spur is in the filter bandwidth and is refereed to as integer boundary spur. This spur can not be suppressed by loop filter. figure 5.8 shows the phase nouse plot with an in-band spur at frequency of 90.3 kHz

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Figure 5.6: The dominant spur after charge pump in a fractional-N frequency synthesizer for input of X=700

Figure 5.7: Spur in the output phase noise spectrum showing the dominant spur at 420.41 kHz with fractional input of X=700 and a third order loop filer

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5.4 Fourth Order PLL 47

Figure 5.8: Spur in the output phase noise spectrum showing the dominant spur with fractional input of x=150 and a third order loop filer

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Chapter 6

Analysis of Simulations and

Experimental Results

In this chapter, the simulated results are experimentally varified. The experiments are carried out using Analog Devices ADF7021 evaluation board. In this chapter we will discuss the results obtained experimentally and will present a comparison of experimental and simulation results.

6.1 Analog Devices ADF7021

The ADF7021 is a narrow band transceiver IC that can use modulation schemes of 2FSK/3FSK/4FSK. The operational frequency range of ADF7021 evaluation board is between 80 MHz to 650 MHz and 862 MHz to 950 MHz. A range of on chip FSK modulation schemes are available which provides the user with flexibility to used these techniques.

The transmitter on chip has VCOs and a PLL based fractional-N frequency syn-thesizer that has the output resolution of <1 ppm. The dual VCOs on chip; one uses an LC tank and other uses the external inductor as a part of its LC tank to transmit and/or receive at a range of specified frequencies.

The block diagram of the fractional-N frequency synthesizer module on ADF7021 is given in Fig. 6.1

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50 Analysis of Simulations and Experimental Results

Figure 6.1: Block diagram of the fractional-N frequency synthesizer module on ADF7021 [5]

6.1.1 Reference Input Frequency

The crystal oscillator on ADF7021 evaluation board uses a quartz crystal to generate the PLL’s reference frequency. The crystal oscillator generates the frequency of 19.68 MHz. Adjustment in the fractional-N value and the automatic frequency control feature available can be used to correct the errors in crystal.

6.1.2 Loop Filter

Current pulses coming from the charge pump are integrated by the loop filter in PLL to generate the control voltage (VCT RL) which is input to VCO. It tunes the VCO

to get desired output frequency at VCO’s output. Loop filter is also responsible to attenuate the spur generated because of different non-ideal phenomena in the mixed signal system.

ADF7021 has a third order passive, low pass loop filter with the pass band of 90 kHz. The loop filter topology used in the on-chip PLL is given in Fig. 6.2

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6.2 Analysis of Results 51

Figure 6.2: Loop Filter configuration ADF7021

6.1.3 Divider

Divider module in the feedback path of fractional-N frequency synthesizer on ADF7021 consists of a 8-bit pulse swallow integer counter. ∆Σ fractional-N divider consists of 15-bits that provides high resolution of frequencies at the output.

The output frequency of the synthesizer is calculated as

fout = Nint+ X M fP D

6.2 Analysis of Results

In this section, measured results for a commercial fractional-N frequency synthesizer, the Analog Devices ADF7021 is presented.

The experiments were carried out for many different fractional inputs which were also simulated earlier by using the CppSim System simulator. In this section we only discuss the inputs of X=700 and X=150.

We do not have access to the signals at the output of the DDSM or the CP. Hence, all results are based on measurements at the output of the VCO.

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Fig. 6.5 shows the display of Agilent Technologies spectrum analyzer attached to the output of the ADF7021 with the parameters in Table 5.2. Figure 6.5 shows

Figure 6.3: The output of VCO monitored on spectrum analyzer for input of X=700

the LO spectrum of the ADF7021 measured using the spectrum analyser. The synthesizer produces a sinusoidal output at 886 MHz, as expected. The first spur is at 422.49 kHz, less than 0.5% from the prediction given by Eq. (5.3). We believe that this small difference is due to the quantization of the frequency axis of the display which has a resolution of just 401 points.

The locations of the spurs were also verified by experiments by using X=150 as input to DDSM of ADF7021. In this case the spur can be seen on spectrum analyser at frequency of 92.5 kHz in figure6.5.

simulated results for frational inputs of X=700 and X=150 can be seen in figures 6.4 and 6.6.

It is interesting to note that the spur location in the simulated and measured results are the same. This verifies that the spur occurs at the predicted location.

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6.2 Analysis of Results 53

Figure 6.4: Simulated phase noise of Fractional-N Synthesizer in CppSim for input of X=700. The spur is seen at 420.41 kHz

Figure 6.5: The output of VCO monitored on spectrum analyzer for input of X=700

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Figure 6.6: Simulated phase noise of Fractional-N Synthesizer in CppSim for input of X=150. The spur is seen at 90.7 kHz

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Chapter 7

Conclusion and Future Work

In this thesis we have shown that even if the output spectrum of a DDSM is free of spurious tones, the spurs reappear when its output is passed through a memoryless nonlinearity. Simulations were carried out using different novel DDSM structures. The regrowth of spur after their output is passed through a nonlinearity is confirmed. We predicted the location of dominant spur in the output spectrum of a frequency synthesizer caused by the DDSM. Simulations were carried out using MATLAB and CppSim to confirm these locations. The experimental conformation of these spur locations were made using Analog Devices ADF7021 evaluation board.

The DDSM can be considered as the sole responsible for the fractional spurs in a fractional-N frequency synthesizer. The stochastic and deterministic techniques that result in a pure output spectrum of the DDSM fail to suppressing the spur when the output of DDSM is subjected to the nonlinearities of a mixed signal system. Extensive research is being carried out in the field but to the best of our knowledge, the exact reason for occurrence of these spurs in a fractional-N frequency synthesizer is not known.

Future work of the presented research can be extended to investigate the exact phenomena in DDSM that generates these spurs. The development of new DDSM structures based on the reason to eliminate the spurs from the output of fractional-N frequency synthesizer has a big potential for future research.

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Bibliography

[1] W. Rhee, “Multi-bit Delta-Sigma Modulation Technique for Fractional-N Frequency Synthesizers,” Ph.D. dissertation, University of Illinois at Urbana-Champaign, August 2001.

[2] C. Barrett, “Fractional/Integer-N PLL Basics,” wireless Communication Busi-ness Unit, Technical Brief SWRA029, TEXAS INSTRUMENTS.

[3] M. Kennedy, “Recent Advances in the Analysis, Design and Optimization of Digital Delta-Sigma Modulators,” Department of Electrical and Electronic Engineering, University College Cork, Ireland Tyndall National Institute, Cork, Ireland.

[4] K. Hosseini, B. Fitzgibbon, and M. Kennedy, “Observations Concerning the Generation of Spurious Tones in Digital (d,” IEEE Transactions on Circuits and Systems II: Express Briefs.

[5] A. D. 2005, “ADF7020-1Datasheet.” [Online]. Available: http://www.analog. com/static/importedfiles/data-sheets/ADF7020-1.pdf

[6] D. Banerjee, PLL Performance, Simulation and Design. National Semicon-ductor, 1998.

[7] W. Rhee, “Design of high-performance CMOS charge pumps in phase-locked loops,” in Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, vol. 2, July 1999, pp. 545 –548 vol.2.

[8] K. Wang, A. Swaminathan, and I. Galton, “Spurious Tone Suppression Tech-niques Applied to a Wide-Bandwidth 2.4 GHz Fractional-N PLL,” IEEE Journal of Solid-State Circuits, vol. 43, no. 12, pp. 2787 –2797, December 2008.

[9] S. Meninger and M. Perrott, “A fractional-N frequency synthesizer archi-tecture utilizing a mismatch compensated PFD/DAC structure for reduced quantization-induced phase noise,” IEEE Transactions on Circuits and Sys-tems II: Analog and Digital Signal Processing, vol. 50, no. 11, pp. 839 – 849, Novmber 2003.

Investigation of Mechanisms for Spur Generation in Fractional-N Frequency Synthesizers

Institutionen för systemteknik

Department of Electrical Engineering

Examensarbete

Investigation of Mechanisms for Spur Generation in

Fractional-N Frequency Synthesizers

Investigation of Mechanisms for Spur Generation in

Fractional-N Frequency Synthesizers

Examensarbete utfört i Elektroniksystem

vid Tekniska högskolan i Linköping

av

Abstract

Acknowledgments

Contents

List of Figures

List of Tables

Chapter 1

Introduction

1.1

Background

1.2

The Need for Spectral Purity in Transceiver

and Issue of Spurs

1.3

Spurious Tones (Spurs) in Spectrum of

Fre-quency synthesizer

1.3.1

Reference Spurs

1.3.2

Fractional Spurs

1.3.3

Integer Boundary Spurs

1.4

Specific Issue of Issue of Spurs Coming from

DDSM

1.5

Contribution of this Thesis

1.6

Thesis Organization

Chapter 2

Frequency Synthesis

2.1

Integer-N Frequency Synthesizers

2.2

Fractional-N Frequency Synthesizers

2.2.1

Phase Frequency Detector

2.2.2

Charge Pump

2.2.3

Loop Filter

2.2.4

Voltage Controlled Oscillator

2.2.5

Divider

Chapter 3

Digital Delta Sigma

Modulator (DDSM)

3.1

Introduction

3.1.1

Error Feedback Modulator (EFM)

3.1.2

MASH Structure

3.1.3

MASH 1-1-1

3.2

Dithering the input

3.2.1

Shaped Dither

Chapter 4

Prediction of Spur Locations

in LO Spectrum of DDSM

Followed by Memory-less

Nonlinearity

4.1

Effect of nonlinear distortions on DDSM

4.2

DDSM Followed by Memoryless Nonlinearity

in a Fractional-N Frequency Synthesizer.