Implementation of an FFT algorithm using a soft processor core
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(6) Abstract This report deals with the modeling of a part of the communication system based on the IEEE 802.11a standard which represents the next generation of wireless LAN with greater scalability, better interference immunity and significantly higher speed, up to 54 Mbps. 802.11a uses Orthogonal Frequency Division Multiplexing (OFDM) where modulation is performed by an IFFT and the demodulation by an FFT. After modeling the FFT in Matlab and C, the FFT implementation has been validated using a soft microprocessor core by Xilinx (Microblaze) and the results were compared..
(7) Acknowledgments I would like to thank my supervisor, Kent Palmkvist, for introducing me to data mining and for all his guidance and support. A number of individuals in the Laboratory for Advanced Computing were very helpful and understanding. I would like to acknowledge Peter Johanson, Greger Karlströms, and Thomas Johanson in particular for their contribution to this work. I wish to thank Ulrik Linblad and Patrik Thalin for encouraging comments, interesting lunch chats, advice, and support. I also would like to thank all my friends who helped me get through these four months..
(8) List of abbreviations ASIC DDR SDRAM DFT DSP FFT FPGA GPIO IEEE IFFT LUT LVDS Tx/Rx MDK MDT MHS MSS OPB RISC TBWDT UART XMD XMP XSI. Application Specific Integrated Circuit Double Data Rate Synchronous Dynamic RAM Discreet Fourier Transform Digital Signal Processor Fast Fourier Transform Field Programmable Gate Array General Purpose Input/Output Institute of Electrical and Electronic Engineer Inverse Fast Fourier Transform Look Up Table Low Voltage Differential Signaling Transmission/Reception MicroBlaze Development Kit Microprocessor Development Tools Microprocessor Hardware Specification Microprocessor Software Specification On-chip Peripheral Bus Reduced Instruction Set Computer TimeBase WatchDog Timer Universal Asynchronous Receiver Transmitter Xilinx Microprocessor Debug Xilinx Microprocessor Project Xilinx Software Integrated.
(9) Contents 1. Introduction......................................................................................................1 1.1. Linköping University.....................................................................................1 1.1.1. Overview................................................................................................1 1.1.2. Linköping Institute of Technology...........................................................1 1.2. Overview of the task ....................................................................................3 2. Descriptions of the board ...............................................................................4 2.1. The Microblaze of Xilinx...............................................................................4 2.2. The Virtex series..........................................................................................4 2.3. The Virtex II Microblaze Development Kit ....................................................4 2.3.1. The Virtex-II System Board ....................................................................5 2.3.2. P160 Communications Module ..............................................................6 2.3.3. P160 Prototype Module .........................................................................7 2.3.4. CoreConnect Bus ..................................................................................7 2.4. MicroBlaze architecture ...............................................................................8 2.4.1. Processor ..............................................................................................8 2.4.2. Peripherals ............................................................................................8 3. Description of the software...........................................................................10 3.1. Microprocessor Software Specification ......................................................10 3.1.1. Keyword...............................................................................................10 3.1.2. Format .................................................................................................11 3.1.3. Comments ...........................................................................................11 3.2. Microprocessor Hardware Specification.....................................................11 3.2.1. Format .................................................................................................11 3.2.2. Comments ...........................................................................................12 3.3. Connection between software and hardware .............................................12 3.4. Microblaze Software Integrated Development Environment.......................15 3.4.1. Project Management............................................................................15 3.4.2. XSI Interface ........................................................................................17 3.4.3. Software Platform Management...........................................................18 3.4.4. Source Code Management ..................................................................18 3.4.5. Flow tool settings .................................................................................19 3.4.6. Tool Invocation ....................................................................................19 3.4.7. Design implementation ........................................................................20 3.5. Design verification .....................................................................................20.
(10) 4. The FFT program details ...............................................................................21 4.1. The Digit Reverse function.........................................................................21 4.2. The FFT butterfly .......................................................................................22 4.3. The Unscramble function ...........................................................................23 5. Description of the work .................................................................................24 5.1. The FFT program in C code.......................................................................24 5.2. The implementation of the FFT program in the MicroBlaze........................24 5.3. Verification of results..................................................................................25 5.3.1. Microblaze GNU Debugger (GDB) .......................................................25 5.3.2. Xilinx Microprocessor Debug (XMD) ....................................................26 6. Conclusion .....................................................................................................27 Appendices ........................................................................................................28 Appendix 1: generate_data.m...........................................................................29 Appendix 2: CT_FFT.cpp..................................................................................30 Appendix 3: MSS file ........................................................................................36 Appendix 4: MHS file ........................................................................................37 Appendix 5: FFT.c ............................................................................................39 Appendix 6: Makefile ........................................................................................65 References .........................................................................................................69.
(11) Figures Figure 1: The Virtex II System board. ....................................................................5 Figure 2: Virtex-II System Board. ...........................................................................6 Figure 3: P160 Communication Module. ................................................................6 Figure 4: P160 Prototype Module. .........................................................................7 Figure 5: MicroBlaze architecture. .........................................................................8 Figure 6: Library generation.................................................................................13 Figure 7: Executable Generation .........................................................................13 Figure 8: Hardware Flow......................................................................................14 Figure 9: Creation of a new project. .....................................................................16 Figure 10: Example of Software IDE....................................................................17 Figure 11:Xygwin shell.........................................................................................20 Figure 12: Translation for the input. .....................................................................22 Figure 13: Butterfly description. ...........................................................................22 Figure 14: GDB Simulator....................................................................................25.
(12) Implementation of a FFT algorithm using a soft processor core.. 1. Introduction 1.1. Linköping University 1.1.1. Overview Since its foundation in the 1960´s, the university has established itself as an innovative and modern institution in both education and research. The university was first founded as an independent college and in 1975 officially became what it is today with the three faculties: Institute of Technology, Faculty of Arts and Sciences and Faculty of Health Sciences. The university offers postgraduate studies and research in more than 100 scientific areas within 20 multidisciplinary departments. These departments, which combine the expertise of several academic disciplines, were pioneers in the Swedish academic world when singlesubject departments were the rule. There are more than 22000 students and 2000 teachers, researchers, and professors.. 1.1.2. Linköping Institute of Technology a) Generality Linköping Institute of Technology (LiTH) has created a unique profile through the introduction of disciplines such as Industrial Engineering and Management, Computer Science and Engineering, and Biomedical Engineering. The Institute continues to develop engineering education in accordance with current needs. Recently the Institute was also entrusted with the task of leading a national project with the aim to renew engineering education in Sweden. Linköping Institute of Technology has nine departments: Department of Biomedical Engineering Department of Computer and Information Science Department of Management and Economics Department of Mathematics Department of Mechanical Engineering Department of Physics and Measurement Technology Department of Production Economics Department of Science and Engineering Department of Electrical Engineering (my department). -1-.
(13) Implementation of a FFT algorithm using a soft processor core.. b) Department of Electrical Engineering ISY, the Department of Electrical Engineering (in swedish the Institutionen för Systemteknik) at Linköping University is divided into nine divisions with a total number of about 160 people employed. All divisions teach students and have their own research projects. The department carries out research and teaches courses in areas dealing with signals and systems, from abstract models down to digital and analogue circuitry. This includes such subjects as telecommunications, control theory, image handling and design of analogue and digital circuits. Many on the staff have won national and international acclaim and awards for their theoretical work, but the research has also resulted in many spin-off companies. International courses are given in the areas of telecommunications, electronic systems, control theory and computer engineering. There are eight divisions in the department: Automatic Control, Computer Engineering, Computer Vision, Data Transmission, Electronics Systems, Image Coding, Information Theory and Vehicular Systems. c) Electronics Systems • Research and Development projects Aspects of design and implementation of signal processing systems, including filter theory and design, implementation of digital and analogue circuits and systems have for many years been fields of interest within the division of Electronics Systems. Of special interest are methodologies for design and implementation of digital signal processing systems, covering computational properties of DSP algorithms and synthesis of application specific integrated circuit (ASIC) architectures. Another field is the design and implementation of analog and mixed analog/digital circuits. • Staff The team of the Electronics System laboratory is composed by: 2 professors: Lars Wanhammar and Mark Vesterbacka. 2 assisting professors: Håkan Johanson and Kent Palmkvist (my supervisor). 2 universitaire adjunkts: Rain Jääger and Jonny Lindgren. -2-.
(14) Implementation of a FFT algorithm using a soft processor core.. 2 visiting researchers: Mikael Rudberg and Shengxian Zhuang. 3 Engineers: Peter Johanson, Greger Karlströms and Thomas Johanson. 11 doctors of phylosophiy (Ph. D students).. 1.2. Overview of the task One of the aims of this department is to model a communication systems based on the IEEE 802.11a standard. In this standard the modulation is performed by an IFFT and the demodulation by a FFT. A C-program describing the Fast Fourier Transform has been written and the FFT implementation has been validated using a soft microprocessor by xilinx. A development kit has been used for this project, and a software for the program implementation. First, this report describes the FFT program and then the specific software that has been used for the implementation.. -3-.
(15) Implementation of a FFT algorithm using a soft processor core.. 2. Descriptions of the board At first, I have studied the Microblaze microprocessor of Xilinx. In fact, the FFT program must be implemented on this microprocessor and this microprocessor is itself on a board. Many different FPGAs can contain the Microblaze, but at the University, the Virtex II is used.. 2.1. The Microblaze of Xilinx Microblaze is a flexible soft core that implements a true 32-bits RISC (Reduced Instruction Set Computer) processor running at 125 MHz. The Microblaze core is organized as a Harvard architecture with separate bus interface units for data accesses and instruction accesses. It requires 800-900 logic cells, and achieves 70 Dhrystone MIPS (Million Instructions Per Second). Microblaze is used to build complex systems for networking, telecommunications, data communications and consumer market.. 2.2. The Virtex series The Xilinx Virtex™ series was the first line of FPGAs to offer one million system gates. Introduced in 1998, the Virtex product line fundamentally redefined programmable logic by expanding the traditional capabilities of field programmable gate arrays (FPGAs). The latest devices in the Virtex-E series, unveiled in 1999, offer more than three million system gates. The Virtex-EM devices, introduced in 2000 is the first FPGAs to be manufactured using an advanced copper process instead aluminium.. 2.3. The Virtex II Microblaze Development Kit The Virtex-II MicroBlaze Development Kit is a solution for developing designs and applications based on the Xilinx MicroBlaze soft processor core. I used this board for my project. The kit bundles the Xilinx MicroBlaze Development Kit (MDK) with an advanced Virtex-II hardware platform, power supply, and reference designs. The MicroBlaze hardware platform is comprised of three boards, the Virtex-II -4-.
(16) Implementation of a FFT algorithm using a soft processor core.. System Board, the P160 Communications Module, and the P160 Prototype Module. The MicroBlaze Development Kit (MDK) includes a soft processor license, the IBM CoreConnect bus, standard peripherals, GNU-based software tools, and system configuration tools.. Figure 1: The Virtex II System board.. 2.3.1. The Virtex-II System Board The Virtex-II platform is based on the one million-gate XC2V1000 FPGA device. The system board includes 2M x 16 double data rate synchronous dynamic RAM (DDR SDRAM) and a 16-bit low voltage differential signaling transmission/reception (LVDS Tx/Rx) port. The Virtex-II system board block diagram is shown in the next figure.. -5-.
(17) Implementation of a FFT algorithm using a soft processor core.. Figure 2: Virtex-II System Board.. The system board includes in addition of a 2M x 16 DDR memory, two clock sources, RS-232 port, and additional user support circuits. The board also supports the Insight P160 expansion module standard, allowing application specific expansion modules to be easily added.. 2.3.2. P160 Communications Module Both P160 modules are daughter cards that can be plugged into the P160 slot resident on the system board.. Figure 3: P160 Communication Module. -6-.
(18) Implementation of a FFT algorithm using a soft processor core.. The P160 Communications Module includes 2M x 32 Flash memory, 256K x 32 SRAM, 10/100 Ethernet port, USB port, RS-232 port, I2C and SPI ports, programmable LCD display connector and a PS/2 keyboard connector.. 2.3.3. P160 Prototype Module The P160 prototype module offers general purpose expansion headers for all 110 user I/O signals, as well as a prototype area for building custom circuits.. Figure 4: P160 Prototype Module.. 2.3.4. CoreConnect Bus As part of this program, Xilinx has already delivered CoreConnect-enable peripherals including an Arbiter and a UART. Also under development are: a 10/100 Ethernet MAC as well as a standard set of peripherals including timers/counters, UARTs, interrupt controllers, GPIOs, external flash memory interfaces, and SRAM memory interfaces. All of these peripherals will be parameterizable.. -7-.
(19) Implementation of a FFT algorithm using a soft processor core.. 2.4. MicroBlaze architecture. Figure 5: MicroBlaze architecture.. 2.4.1. Processor The MicroBlaze soft processor is supporting 32-bit and 16-bit bus widths. The core of the processor is a standard RISC-based engine with a 32 registers by 32 bit Look Up Table (LUT) RAM-based Register File, with separate instructions for data and memory access. It supports both on-chip BlockRAM and/or external memory. The Program Counter is the 32-bit address of the next instruction to be fetched. The Machine Status Register contains the carry flag and enable for interrupts and buslock.. 2.4.2. Peripherals All peripherals including the memory controller, UART (Universal Asynchronous Receiver/Transmitter) and the interrupt controller run off of the On-chip Peripheral Bus bus (OPB).. -8-.
(20) Implementation of a FFT algorithm using a soft processor core.. The on-chip peripheral bus is designed for easy connection of on-chip peripheral devices. It provides a common design point for various on-chip peripherals. The OPB is a fully synchronous bus that functions independently at a separate level of bus hierarchy. It is not intended to connect directly to the processor core. The OPB interfaces provide separate 32-bit address and up to 32-bit data buses. The on-chip peripheral bus arbiter is an internal 32-bit address and 32-bit data bus core designed for on-chip peripheral integration. The OPB arbiter is a soft Intellectual Property (IP) core for Xilinx FPGAs. The Timer/Counter is a 32-bit timer module that attaches to the OPB. The Timer/Counter is organized as two identical timer modules. Each timer module has an associated register that is used to hold either the initial value for the counter for event generation or a capture. The TimeBase WatchDog Timer (TBWDT) is a 32-bit peripherals. A watchdog timer (WDT) is a device or electronic card that performs a specific operation after a certain period of time if something goes wrong with an electronic system and the system does not recover on its own. For example, a common problem is for a machine or operating system to lock up if two parts or programs conflict, or, in an operating system, if memory management trouble occurs. An UART (Universal Asynchronous Receiver/Transmitter) controls a computer's interface to its attached serial devices. Specifically, it provides the computer with the RS-232C Data Terminal Equipment (DTE) interface so that it can "talk" to and exchange data with modems and other serial devices. Interrupt controllers are used to expand the number of interrupt inputs a computer system has available to the CPU and, optionally, provide a priority-encoding scheme. Modern CPUs provide one or more interrupt request input pins that allow external devices to request service by the CPU. The General Purpose Input/Output (GPIO) is a 32-bits peripheral consisting of two registers and a multiplexer for reading register contents and the GPIO I/O signals.. -9-.
(21) Implementation of a FFT algorithm using a soft processor core.. 3. Description of the software The Microprocessor Development Tools (MDT) included in the MicroBlaze Development Kit offer the embedded system designer a set of embedded processor system design tools. The MDT set of tools consist of Processor platform tailoring utilities Software application development tool chain A debug toll chain Device drivers and libraries System design consists of tailoring of the software component, and the hardware component of the embedded processor.. 3.1. Microprocessor Software Specification The software component is defined by the MSS (Microprocessor Software Specification) file. The MSS file defines the standard input/output devices, interrupt handler routines, and other related software features. The MSS file is created by the user. The MSS file has a dependency on the MHS (Microprocessor Hardware Specification) file. This dependency has to be specified in the MSS file as SET attribute HW_SPEC_FILE = <file_name.mhs>. Hence, a hardware platform has to be defined in order to configure the software flow.. 3.1.1. Keyword The MSS file consists of SET statements that assign values to global attributes. It also consists of CSET statements that assign values to instance specific attributes. An instance of a peripheral is selected using the SELECT statement. Every CSET statement between the SELECT and the END statement refers to the selected instance. The MSS syntax is not case sensitive. However, attribute and instance names are case sensitive.. - 10 -.
(22) Implementation of a FFT algorithm using a soft processor core.. 3.1.2. Format The format for assigning global attributes : SET ATTRIBUTE name = value The format for selecting a peripheral instance : SELECT INSTANCE instance_name The format for selecting a file system : SELECT FILESYS filesys_name The format for instance specific assignment statements : CSET ATTRIBUTE name = value The format for ending a peripheral instance definition: END. 3.1.3. Comments Comments can be specified anywhere in the file. A # character denotes the beginning of a comment and all characters after the # till the end of the line are ignored. White spaces are also ignored.. 3.2. Microprocessor Hardware Specification The hardware component is defined by the MHS (Microprocessor Hardware Specification) file. The MHS file defines the bus architecture, the peripherals, one of six configurations of the MicroBlaze bus interfaces, connectivity of the system, and the address space. The MHS file is also created by the user.. 3.2.1. Format a) Peripheral type There are two types of peripherals : master and slave. Peripheral names are in lower-case. The format at the beginning of a peripheral definition : SELECT peripheral_type peripheral_name - 11 -.
(23) Implementation of a FFT algorithm using a soft processor core.. The format for a master peripheral : SELECT master peripheral_name The format for a slave peripheral : SELECT slave peripheral_name b) Assignment type There are two types of assignments : attribute and signal. The format for assignment statements : CSER assignment_type name = value The format for attributes : CSET attribut name = value The format for signals CSET signal name = connection c) Ending a peripheral definition The format for ending a peripheral definition : END. 3.2.2. Comments It is possible to insert comments in the MHS file without disrupting processing. Comments begin also with a pound sign (#) and continue to the end of the line.. 3.3. Connection between software and hardware Software tailoring consists of library generation and executable file generation. Library generation is done with the Library Generator (libgen) tool. Library Generator will configure the libraries and device drivers with the base addresses of the peripherals of the embedded processor system from an MSS file. Refer to Figure 6 for a flow outline.. - 12 -.
(24) Implementation of a FFT algorithm using a soft processor core.. MSS. Libraries/Drivers Sources. libgen. Libraries/Drivers mbio.h Figure 6: Library generation. After the libraries and the device drivers are configured, an executable image can be generated using the GNU tools. The input into the GNU tools are the libraries/drives that are configured by Library Generator and the user input file. Refer to Figure 7 for a flow outline. Program Source (.c, .h). Libraries/Drivers mbio.h. GNU Compiler/Linker. User executable “(.out)” Figure 7: Executable Generation - 13 -.
(25) Implementation of a FFT algorithm using a soft processor core.. Hardware generation is done with the Platform Generator (platgen) tool. Platform Generator will construct the system in the form of hardware netlists (HDL and EDIF files) from an MHS file. Refer to Figure 8 for a flow outline.. MHS. platgen. .edf, .v, .vhd. HDL Synthesizer. file_name.edf. Implementation Tools. file_name.bit. FPGA. Figure 8: Hardware Flow - 14 -.
(26) Implementation of a FFT algorithm using a soft processor core.. 3.4. Microblaze Software Integrated Development Environment Xilinx Software Integrated Development Environment (IDE) provides an integrated Graphical User Interface (GUI) for creating the software specification file for the Microprocessor system. It also provides an editor and a project management interface to create and edit source code. The IDE offers software tool flow customization options. XSI supports the creation of the MSS file and software tool flows associated with this software specification.. 3.4.1. Project Management A project consists of the Microprocessor Software Specification (MSS) and the C source and header files that need to be compiled into an executable. The MSS file also includes a reference to the MHS file. The project also includes the FPGA architecture family for which the system is created. A New Project is created using the New Project menu option in the Project submenu of the main menu. The New Project toolbar button can also be used. A new project requires an MHS file and a project directory where flow tools create output files and directories. Source and Header files required for user application development are created and added as described in the Source Code Management section. Project options are written into an xmp (Xilinx Microprocessor Project) file.. - 15 -.
(27) Implementation of a FFT algorithm using a soft processor core.. Figure 9: Creation of a new project.. An existing xmp file should be opened and worked on using the Open Project menu option (Project submenu of Main menu). New source files and header files can be created and added as described in the Source Code Management section of this documentation.. - 16 -.
(28) Implementation of a FFT algorithm using a soft processor core.. 3.4.2. XSI Interface The figure below shows a screenshot of XSI. The main window is to the right, the project view window is to the left, and the transcript window is at the bottom.. Figure 10: Example of Software IDE.. XSI Main Window All source and header file editing is performed in the main window of XSI. Any number of source and header files can be open simultaneously. Project View Window The project view window shows system components (processor and peripherals), source and header files of the project and software specification options. Transcript Window (Console) The transcript window is the bottom window when XSI is started. This window acts as a console for output, warning and error messages from tools invoked. - 17 -.
(29) Implementation of a FFT algorithm using a soft processor core.. 3.4.3. Software Platform Management In the Project View Window, the system BSP (Board Support Package) and the program options are displayed as a tree structure. System BSP Tree The System BSP tree displays all the peripherals in the system that can be customized for the software flow. Double clicking on each peripheral opens a dialog window displaying user settable software options. Interrupt Handler Routines - The name of the interrupt handling routine is specified for the peripheral interrupt signal. Driver and Driver Version Option - This option sets the driver name and version number used for the peripheral instance. Program Options Boot Peripheral: Designates the peripheral instance as Boot peripheral. Debug Peripheral: Designates the peripheral instance as debug peripheral. Here the peripheral will be used to download the debug stub (xmdstub). STDIN: Peripheral designated as standard input. STDOUT: Peripheral designated as standard output. Bootstrap: Specifies the bootstub file to be created. Xmdstub: Specifies the debug stub (xmdstub) to be created. Executable: Name of the executable.. 3.4.4. Source Code Management XSI has an integrated editor for viewing and editing C source and header files of the user program. Adding Files to Project Files can be added to the project by clicking the right mouse button on the Sources or Headers Tree Item in the Project View Window. Multiple files are added by pressing the control key and using arrow keys (or the mouse) to select in the file selection dialog.. - 18 -.
(30) Implementation of a FFT algorithm using a soft processor core.. Deleting Files from Project Any file can be deleted from the project by selecting the file in the Project View window and pressing the DEL key, or by clicking the right mouse button on the item and choosing Delete File from Project. However the file does not get physically deleted from the system. Editing Files Double clicking on the source or header file in the Project View window opens the file for editing. The editor supports basic editing functions such as cut, paste, copy and search/replace.. 3.4.5. Flow tool settings XSI supports tool flows as shown in Table 1. The Main menu has a Run submenu. In this submenu, the Set Options pull down menu can be used to set various Tool options. Set Compiler Options This menu item allows the user to set various compiler options. Each option is described in detail in the GNU Compiler Tools documentation. Only the Microblaze GNU compiler specific options can be set in this version of XSI. Set Libgen Options A libgen options dialog is presented to the user when this menu item is selected. Peripheral repository directory specifies the directory that contains user peripherals and associated files for the peripherals. This repository should also contain driver directories for the user peripherals.. 3.4.6. Tool Invocation After all options for the compiler and library generator are set, the tools can be invoked from the Run submenu in the Main menu. When the user exits the application, a prompt to save the current project appears. The user can also save the project in another name by using Save Project As in the Project submenu of the Main menu.. - 19 -.
(31) Implementation of a FFT algorithm using a soft processor core.. 3.4.7. Design implementation The user must open another window to generate to the implementation. The user must in Windows open a xygwin shell windows : Start < Programs < Xilinx Microblaze 2.2 < Xygwin Shell, or in Solaris the user must use an xterm. At the command prompt, cd to the directory containing this makefile. The makefile is created by the XSI. This allows the user to perform the implementation by simply calling on the connect make command: make download.. Figure 11:Xygwin shell.. 3.5. Design verification The Xilinx Microprocessor Debug (XMD) Engine is a program that facilitates a unified Graphical User Interface Debugger (GDB) interface for debugging programs on a MicroBlaze system for system verification. The verification is made by starting xmd from a separate window. Xmd needs to run continuously during the debuging session. There are differents options to give after the commande xmd depending what the user want to check.. - 20 -.
(32) Implementation of a FFT algorithm using a soft processor core.. 4. The FFT program details The Fast Fourier Transform (FFT) is a fast algorithm for computing the Discret Fourier Transform (DFT). It allows reducing the number of operations for implementing the DFT. The DFT has opened up new signal processing techniques in the frequency domain, which are not easily realizable in the analog − j2 π 1 N−1 s n .e N = N n =0. kn. domain. The relation calculating the DFT is : Sk. where Sk. represents the DFT output at the kth spectral point (k ranges from 0 to N-1). N represents the number of samples in the DFT, sk represents the DFT input of the kth time sample. In 1965, Cooley and Turkey developed a fast algorithm which requires (N log N) multiplies and adds for computing the DFT of an N-point, while the computation of the DFT of an N-point sequence would take N2 multiplies and adds. The version of the FFT used in this project is called decimation-in-time FFT, because the algorithm is based on the divide-and conquer approach that is applied in the time domain. The N-point DFT is first divided into two N/2-point DFTs. These DFTs are then divided into four N/4-point DFTs, and so on. The quantity of arithmetic operations is reduced to N log N.. 4.1. The Digit Reverse function To obtain the output sequence in the natural order, we must re-ordered the input samples. The process of decimating the signal in the time domain has caused the input samples to be re-ordered. For a signal consigning of 8 points the original order of the sample is : 0, 1, 2, 3, 4, 5, 6, 7. But after the decimation the order is : 0, 4, 2, 6, 1, 5, 3, 7.. - 21 -.
(33) Implementation of a FFT algorithm using a soft processor core.. ORIGINAL INPUT Decimal Binary 0 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111. RE-ORDERED INPUT Binary Decimal 000 0 100 4 010 2 110 6 001 1 101 5 011 3 111 7. Figure 12: Translation for the input.. The bit patterns representing the sample number has been reversed. This new sequence is the order in which the samples enter the FFT.. 4.2. The FFT butterfly The FFT butterfly is a graphical method of showing the multiplications and additions performed on the samples values. Due to its appearance this signal flow graph is called a "butterfly". Most hardware implementations of the FFT are based on one or several processors that implement the butterfly operations. Both special purpose hardware and processors have been developed in order to facilitate realtime signal processing. a W. + +. a+W.b. +. b. -. a-W.b. Figure 13: Butterfly description.. Lower case (‘a’ and ‘b’) represents the time sample and upper letter (‘A’ and ‘B’) represents the DFT output. W is equal to e − j2π . - 22 -.
(34) Implementation of a FFT algorithm using a soft processor core.. The butterfly for decimation-in-time is just two complex multiplications and two complex additions. Each circle is the sum of it's inputs (addition) and the values which appear next to the arrows are the multiplications.. 4.3. The Unscramble function The samples are just recombined in this function to produce the result.. - 23 -.
(35) Implementation of a FFT algorithm using a soft processor core.. 5. Description of the work 5.1. The FFT program in C code The aim of this part is to test the FFT program in the MicroBlaze microprocessor. First, the FFT code was translated from Pascal language to C++ language in order to compile this FFT program. There is only a C/C++ compiler available computer, this is the reason why I have chosen to translate the FFT program in a C++ code. Then, I used Matlab to be sure of the result from my C++ code. The problem was to use the same random data in entry in Matlab and in the C++ code. So, I have generated data from Matlab in a file called generate_data.m and I have saved them in another Matlab file which is data.m. The program generate_data.m is in Appendix 1. It was then possible to use this data.m file when I ran the FFT function from Matlab, and the FFT program (Appendix 2) from my C++ algorithm. In this case, my C++ code was good.. 5.2. The implementation of the FFT program in the MicroBlaze After making sure that the FFT program in C++ code was correct, I translated it into C code and checked the fft function with the software IDE. The software accept just the C code, which is the reason of my second translation. I needed to create a MSS file and a MHS file for the reason I explained in a previous paragraph (3.1 and 3.2). These files are in Appendix 3 and Appendix 4. After the right compilation, I implemented the program in the microprocessor with the shell windows. The FFT program which has been implemented is in Appendix 5. The software did not accept the math.h library, thus I had to generate a cosinus and a sinus array from Matlab and insert the data in the initialization of these arrays which a simple copy and paste. Moreover, I wanted to use the random values from the Matlab file which I used for my test (explained at the beginning of this paragraph), but the software was not able to read a file. Also, I had to insert these random complex values as an initilialisation at the beginning of the C-program. In order to run the FFT program, I had to create also the Makefile. This is given in Appendix 6.. - 24 -.
(36) Implementation of a FFT algorithm using a soft processor core.. 5.3. Verification of results In order to be sure of the results, output data must be read in the memory. There are two possibilities for that. We must use the MicroBlaze GNU Debugger or the Xilinx Microprocessor Debug.. 5.3.1. Microblaze GNU Debugger (GDB) The MicroBlaze GNU Debugger is a flexible tool which provides a unified interface for debugging/verifying a MicroBlaze system during various development phase. I used the GDB Built-in Simulator which is an option in this software. The Microblaze debugger provides an instruction set simulator, which can be used to debug programs that do not access any peripherals. It is possible to see the Cprogram, and the translation in assembler just below in order to know all addresses of the memories.. Figure 14: GDB Simulator - 25 -.
(37) Implementation of a FFT algorithm using a soft processor core.. Thus, after running the simulation, data must be read in the memories if we choose this option (View < Memory). The results of the FFT program are in double data format. Also, we must select this option for reading the result in the memories (Addresses < Preferences < Size < Double Float). However, the simulation for the FFT program is not really correct because the debugger send an error message due to the infinite loop. Actually, a lot of loops turn so many time for it, and it do not understand that. Nevertheless, the first results in the memory are correct, so according to my supervisor, we can conclude my FFT program is good.. 5.3.2. Xilinx Microprocessor Debug (XMD) The second choice is to used directly the Xilinx Microprocessor Debug from the shell windows. It is a program that facilitates a unified GDB interface for debugging programs on a MicroBlaze system. To start the XMD engine, execute xmd from a shell as : xmd[options]. I used xmd –t sim –c s –s com1. -t sim : specify the debug target .xmd supports non-intrusive debugging on the MicroBlaze simulator. -c s : specify the xmd communication. Debugging is supported over serial cable. -s : specify the serial port where the remote hardware is connected. After running this command an error message come : “unable to establish connection target board”. Actually, a memory is reserved just before the user program (from 0x00000000 to 0x00000400) for the xmdstub. Library generator can configure the xmdstub to use the DEBUG_PERIPHERAL in the system. Normaly when libgen is run with –mode xmdstub option, it generates a xmdstub configured for the DEBUG_PERIPHERAL. It is specified in the user’s mss file. I think there is not all the options in the MicroBlaze, or perhaps the memory is not reserved for the option in order to debug by the XMD.. - 26 -.
(38) Implementation of a FFT algorithm using a soft processor core.. 6. Conclusion This project allowed me to have a concrete approach of the microprocessor world. It is very useful to have such a soft scalable microprocessor for building complexes systems and simulate them. It can be a cheap approach with others FPGAs to have a whole system prototype. The software tools are ergonomic and easy to use. However finding research in the MicroBlaze reference guide is sometimes difficult. I had two main difficulties during the progress of my training. The first was to be the first person in the laboratory to get in touch with these new tools and the second was to use several software which were not really up to date because some options was missing.. - 27 -.
(39) Implementation of a FFT algorithm using a soft processor core.. Appendices Appendix 1: generate_data.m...........................................................................29 Appendix 2: CT_FFT.cpp..................................................................................30 Appendix 3: MSS file ........................................................................................36 Appendix 4: MHS file ........................................................................................37 Appendix 5: FFT.c ............................................................................................39 Appendix 6: Makefile ........................................................................................65. - 28 -.
(40) Implementation of a FFT algorithm using a soft processor core.. Appendix 1: generate_data.m %**************************************************************** %name file : generate_data.m % %19-06-2002 % %GALLAY Lucie %****************************************************************. % Random complex Matrix A=complex(rand(1024),rand(1024)); diary data.mat file A(:,1) diary off B=A(:,1);. %Generate complex matrix 1024,1024 %Put the next result in a matlab %Vector A column (1024,1) %Close the file. %Put the result in B matrix for the %utilisation in Matlab (for use the FFT). - 29 -.
(41) Implementation of a FFT algorithm using a soft processor core.. Appendix 2: CT_FFT.cpp /**********************************************/ /* Program Cooley-Tukey FFT */ /* CT_FFT.cpp */ /* */ /* 08-06-2002 */ /* GALLAY Lucie */ /**********************************************/. #include #include #include #include. <iostream.h> <math.h> <fstream.h> <stdlib.h>. /**********************/ /* Prototypes */ /**********************/ int readinputdata(); int fft(); int Digit_Reverse (int Digit); void Unscramble (); int writeoutputdata();. /**********************/ /* Globals variables */ /**********************/ const int N=1024, M=10, Nminus1=1023; const double Pi=3.14159265359; struct Complexe { double re, im; }; Complexe x[N]; values. //. Define. int stage, Ns, M1, k, kNs, p, q; double WCos, WSin, TwoPiN, TempRe, TempIm;. - 30 -. a. matrix. of. complex.
(42) Implementation of a FFT algorithm using a soft processor core.. /**********************/ /* Principal program */ /**********************/ int main () { readinputdata(); fft(); writeoutputdata(); return 0; }. /**********************************************************/ /* readinputdata funtion : */ /* Function which receive values from a infile */ /**********************************************************/ int readinputdata() { ifstream infile("data.mat",ios::in);. // Open file in reading. if(!infile) cout<<"ERROR for opening the file"<<endl; else cout<<"File Open"<<endl; int i=0;. // Position of cursor at the beginning of the file infile.seekg(0,ios::beg); do { infile.seekg(4,ios::cur); infile>>x[i].re; // Put reel data in the matrix cout<<"re["<<i<<"]="<<x[i].re<<'\t'; // Print data. infile.seekg(3,ios::cur);. - 31 -. // Move the cursor of 3 octets.
(43) Implementation of a FFT algorithm using a soft processor core. infile>>x[i].im; // Put imaginary data in the matrix cout<<"im["<<i<<"]="<<x[i].im<<endl; // Print data. infile.seekg(1,ios::cur);. // Cursor go on the next line. i=i+1;. // Incrementation of the tab. // Test the next value equal to the end of file }while((infile.peek()!=EOF)&&(i<N)); infile.close(); cout<<"File close"<<endl;. // Close the file. return 0; }. /****************/ /* FFT function */ /****************/ int fft () { Ns=N; M1=M; TwoPiN=2*Pi/N;. for(stage=1;stage<M+1;stage++) { k=0; Ns=Ns/2; M1=M1-1;. while(k<N) { for(q=1;q<Ns+1;q++) { p=Digit_Reverse(k/(1<<M1)); WCos=cos(TwoPiN*p);. - 32 -.
(44) Implementation of a FFT algorithm using a soft processor core. WSin=sin(TwoPiN*p); kNs=k+Ns; /* BUTTERFLY */ TempRe=x[kNs].re*WCos-x[kNs].im*WSin; TempIm=x[kNs].im*WCos+x[kNs].re*WSin; x[kNs].re=x[k].re-TempRe; x[kNs].im=x[k].im-TempIm; x[k].re=x[k].re+TempRe; x[k].im=x[k].im+TempIm; k++;. } k=k+Ns; } }. Unscramble(); return 0; }. /*************************************************/ /*Digit_Revers function : to re-order input data */ /*************************************************/ int Digit_Reverse (int Digit) { int N,q,NewAddr=0,Rmbit,OldAddr=Digit; for(q=1;q<M+1;q++) { Rmbit=OldAddr%2; OldAddr=OldAddr/2; if(Rmbit==1) { NewAddr=NewAddr*2+1; } else. - 33 -.
(45) Implementation of a FFT algorithm using a soft processor core. { NewAddr=NewAddr+NewAddr; } } return NewAddr; }. /************************/ /* Unscramble function */ /************************/ void Unscramble() { Complexe temp; int k,q; for(k=0;k<N-1;k++) { q=Digit_Reverse(k); if(q>k) { temp=x[k]; x[k]=x[q]; x[q]=temp; } } } /**************************************************************/ /* writeoutput data : */ /* Function for writting data in a outfile */ /**************************************************************/ int writeoutputdata() { cout<<endl<<"Result of FFT in the file : result.mat:"<<endl; //Open a file in writing ofstream outfile ("result.mat",ios::out); //Write in the outfile the result data for(int i=0;i<N;i++). - 34 -.
(46) Implementation of a FFT algorithm using a soft processor core. outfile<< x[i].re<<" + "<<x[i].im<<"i"<<endl; outfile.close();. //Close the file. return 0; }. - 35 -.
(47) Implementation of a FFT algorithm using a soft processor core.. Appendix 3: MSS file ################################################################ # MSS file # mysytem.mss # 04-07-2002 # GALLAY Lucie ################################################################ SET attribute HW_SPEC_FILE = C:\Documents\Lucie\FFT\mysystem\mysystem.mhs SET attribute BOOT_PERIPHERAL = myuart SET attribute DEBUG_PERIPHERAL = myuart SET attribute STDIN = myuart SET attribute STDOUT = myuart SET attribute EXECUTABLE = code/fft.out SET attribute XMDSTUB = code/xmdstub.out SET attribute BOOTSTRAP = code/bootstub.out SELECT instance myuart CSET attribute DRIVER = drv_uartlite CSET attribute DRIVER_VER = 1.00.a END SELECT instance mygpio1 CSET attribute DRIVER = drv_gpio CSET attribute DRIVER_VER = 1.00.a END SELECT instance mygpio2 CSET attribute DRIVER = drv_gpio CSET attribute DRIVER_VER = 1.00.a END SELECT instance mygpio3 CSET attribute DRIVER = drv_gpio CSET attribute DRIVER_VER = 1.00.a END SELECT instance mytimer1 CSET attribute DRIVER = drv_timer CSET attribute DRIVER_VER = 1.00.a END SELECT instance microblaze CSET attribute DRIVER = drv_microblaze CSET attribute DRIVER_VER = 1.00.a END. - 36 -. # # # #.
(48) Implementation of a FFT algorithm using a soft processor core.. Appendix 4: MHS file ################################################################# # MHS file # mysytem.mhs # 04-07-2002 # GALLAY Lucie ################################################################# select bus opb_v20 CSET attribute HW_VER = 1.00.b CSET attribute INSTANCE = myopb_bus CSET signal SYS_Rst = sys_reset CSET attribute C_EXT_RESET_HIGH = 0 end SELECT SLAVE opb_uartlite CSET attribute INSTANCE = myuart CSET attribute HW_VER = 1.00.a CSET attribute C_BASEADDR = 0xFFFF8100 CSET attribute C_HIGHADDR = 0xFFFF81FF CSET attribute C_DATA_BITS = 8 CSET attribute C_CLK_FREQ = 24000000 CSET attribute C_BAUDRATE = 19200 CSET attribute C_USE_PARITY = 0 CSET signal RX = rx CSET signal TX = tx END SELECT SLAVE opb_gpio CSET attribute HW_VER = 1.00.a CSET attribute INSTANCE = mygpio1 CSET attribute C_HIGHADDR = 0xFFFF90FF CSET attribute C_BASEADDR = 0xFFFF9000 CSET attribute C_GPIO_WIDTH = 8 CSET attribute C_OPB_DWIDTH = 8 CSET attribute C_ALL_INPUTS = 0 CSET signal GPIO_IO = gpio_a END SELECT SLAVE opb_gpio CSET attribute HW_VER = 1.00.a CSET attribute INSTANCE = mygpio2 CSET attribute C_HIGHADDR = 0xFFFFA0FF CSET attribute C_BASEADDR = 0xFFFFA000. - 37 -. # # # #.
(49) Implementation of a FFT algorithm using a soft processor core. CSET CSET CSET CSET END. attribute C_GPIO_WIDTH = 8 attribute C_OPB_DWIDTH = 8 attribute C_ALL_INPUTS = 0 signal GPIO_IO = gpio_b. SELECT SLAVE opb_gpio CSET attribute HW_VER = 1.00.a CSET attribute INSTANCE = mygpio3 CSET attribute C_HIGHADDR = 0xFFFFB0FF CSET attribute C_BASEADDR = 0xFFFFB000 CSET attribute C_AWIDTH = 32 CSET attribute C_DWIDTH = 32 CSET attribute C_GPIO_WIDTH = 8 CSET attribute C_OPB_DWIDTH = 8 CSET attribute C_ALL_INPUTS = 1 CSET signal GPIO_IO = gpio_c END SELECT SLAVE opb_timer CSET attribute HW_VER = 1.00.b CSET attribute INSTANCE = mytimer1 CSET attribute C_HIGHADDR = 0xFFFFC0FF CSET attribute C_BASEADDR = 0xFFFFC000 CSET signal CaptureTrig0 = net_gnd CSET signal CaptureTrig1 = net_gnd CSET signal PWM0 = PWM0 END SELECT MASTER microblaze CSET attribute INSTANCE = microblaze cset attribute HW_VER = 1.00.b CSET attribute CONFIGURATION = 3 CSET signal Interrupt = net_gnd CSET attribute C_LM_BASEADDR = 0x00000000 CSET attribute C_LM_HIGHADDR = 0x00001fff END. - 38 -.
(50) Implementation of a FFT algorithm using a soft processor core.. Appendix 5: FFT.c /************************************************************/ /* Cooley-Tukey FFT Program */ /* */ /* File Name: fft.c */ /* Version: 2.00 */ /* Date: August 14, 2002 */ /* Designer: Lucie GALLAY */ /* Company: Linköping University */ /************************************************************/ #include <stdio.h> #include <stdlib.h> #include <string.h> /*********************/ /* Globals variables */ /*********************/ #define N 1024 #define M 10 #define Nminus1 1023 #define Pi 3.14159265359 /**************/ /* Prototypes */ /**************/ int fft(); int Digit_Reverse (int Digit); void Unscramble (); struct Complexe { double re; double im; }x[ ] ={ 0.7089 , 0.1203, 0.9181 , 0.1212, 0.8310 , 0.6029, 0.1355 , 0.8196, 0.7719 , 0.3480, 0.1392 , 0.4582, 0.1384 , 0.4548, 0.7663 , 0.4937,. // Define a x matrix of complex values. - 39 -.
(51) Implementation of a FFT algorithm using a soft processor core. 0.9408 0.6599 0.6390 0.0141 0.2844 0.5542 0.9388 0.6208 0.7502 0.4276 0.7623 0.2892 0.0096 0.0287 0.2969 0.5311 0.5712 0.6487 0.4088 0.5147 0.5681 0.7511 0.2916 0.5232 0.8937 0.7028 0.3011 0.8684 0.9447 0.4288 0.4238 0.5320 0.4523 0.7899 0.4854 0.1540 0.3768 0.3762 0.0502 0.9919 0.6006 0.8742 0.7790 0.9509 0.3302 0.3568 0.2620. , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,. 0.8494, 0.6493, 0.8381, 0.4428, 0.3244, 0.3901, 0.8105, 0.5558, 0.7036, 0.7497, 0.8104, 0.7959, 0.5329, 0.5585, 0.8969, 0.1264, 0.3249, 0.3701, 0.3765, 0.9344, 0.4384, 0.0628, 0.8212, 0.7470, 0.4931, 0.1295, 0.3944, 0.4966, 0.2556, 0.3212, 0.5347, 0.3940, 0.1958, 0.4214, 0.1296, 0.2100, 0.9212, 0.2544, 0.7498, 0.6597, 0.9692, 0.6424, 0.8223, 0.0950, 0.6158, 0.0448, 0.2765,. - 40 -.
(52) Implementation of a FFT algorithm using a soft processor core. 0.2370 0.8853 0.7806 0.3157 0.1755 0.6561 0.3003 0.6590 0.1002 0.2493 0.5567 0.8932 0.9332 0.6961 0.9160 0.0751 0.5540 0.5288 0.2696 0.7152 0.4806 0.1274 0.2148 0.0998 0.3972 0.9090 0.0435 0.7844 0.0175 0.7086 0.2029 0.8735 0.4830 0.6466 0.3325 0.9482 0.2303 0.7090 0.1192 0.0553 0.0758 0.0808 0.0361 0.6565 0.9851 0.4365 0.6476. , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,. 0.6032, 0.8620, 0.4384, 0.6764, 0.3415, 0.6834, 0.1481, 0.3502, 0.8522, 0.3829, 0.2045, 0.0811, 0.7709, 0.2250, 0.1713, 0.8837, 0.6749, 0.4568, 0.8099, 0.8059, 0.6141, 0.9502, 0.4419, 0.0369, 0.5531, 0.1454, 0.8436, 0.0986, 0.4864, 0.9940, 0.6018, 0.1659, 0.1701, 0.9905, 0.1169, 0.3752, 0.1426, 0.6827, 0.7004, 0.5731, 0.0842, 0.5235, 0.0527, 0.4283, 0.7691, 0.6706, 0.4038,. - 41 -.
(53) Implementation of a FFT algorithm using a soft processor core. 0.7531 0.6844 0.3130 0.9688 0.5199 0.8011 0.0384 0.1296 0.7095 0.2268 0.2242 0.7822 0.3128 0.2425 0.0270 0.7921 0.2872 0.9464 0.7066 0.1111 0.6624 0.0977 0.2125 0.0557 0.3731 0.6854 0.2870 0.4120 0.3666 0.8771 0.5930 0.4695 0.1892 0.1199 0.0056 0.2390 0.3532 0.7669 0.7936 0.6103 0.2117 0.9558 0.5678 0.0356 0.2901 0.1186 0.9176. , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,. 0.8453, 0.4168, 0.9226, 0.3918, 0.5240, 0.7938, 0.2050, 0.9304, 0.2129, 0.6677, 0.1648, 0.1780, 0.2737, 0.8532, 0.4642, 0.0198, 0.9010, 0.7767, 0.9487, 0.4129, 0.0794, 0.0999, 0.1366, 0.6123, 0.3907, 0.6074, 0.0101, 0.4530, 0.1793, 0.3371, 0.1993, 0.6509, 0.2177, 0.9540, 0.1768, 0.9153, 0.7816, 0.6263, 0.6845, 0.7883, 0.4790, 0.6076, 0.2491, 0.0094, 0.1835, 0.3683, 0.8150,. - 42 -.
(54) Implementation of a FFT algorithm using a soft processor core. 0.2687 0.1393 0.6481 0.2716 0.3307 0.3653 0.0498 0.5047 0.8342 0.5558 0.1727 0.2589 0.2497 0.1330 0.3129 0.3703 0.1424 0.8626 0.3221 0.6972 0.3239 0.4295 0.2362 0.2782 0.9564 0.0510 0.8156 0.5830 0.5025 0.1940 0.5427 0.1898 0.0447 0.2356 0.4638 0.7459 0.1448 0.8323 0.1716 0.5421 0.9245 0.5993 0.9206 0.0225 0.4942 0.5749 0.5281. , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,. 0.3149, 0.3316, 0.3573, 0.0229, 0.3667, 0.7726, 0.9620, 0.5331, 0.7460, 0.5756, 0.1674, 0.0714, 0.4541, 0.3190, 0.4767, 0.4382, 0.9709, 0.6705, 0.2333, 0.7963, 0.3427, 0.6938, 0.0456, 0.1077, 0.0945, 0.2194, 0.5729, 0.5159, 0.3177, 0.4804, 0.0991, 0.3725, 0.7428, 0.0041, 0.3385, 0.4833, 0.1405, 0.8575, 0.8182, 0.8834, 0.0175, 0.0988, 0.6124, 0.2931, 0.8204, 0.5583, 0.3123,. - 43 -.
(55) Implementation of a FFT algorithm using a soft processor core. 0.4687 0.7816 0.7098 0.9087 0.8716 0.9760 0.0345 0.8653 0.0388 0.2420 0.5938 0.6329 0.3452 0.8311 0.3307 0.0236 0.9065 0.8564 0.8935 0.3142 0.1446 0.8547 0.9224 0.8482 0.0043 0.5300 0.6391 0.5121 0.9091 0.2362 0.0574 0.8338 0.3654 0.6255 0.0594 0.3758 0.6062 0.1774 0.0217 0.1380 0.0286 0.5113 0.0117 0.2349 0.4606 0.8156 0.5572. , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,. 0.8237, 0.3233, 0.7762, 0.2599, 0.8351, 0.7239, 0.8649, 0.8104, 0.5002, 0.7267, 0.7532, 0.1442, 0.6988, 0.3559, 0.8012, 0.1850, 0.3392, 0.6613, 0.5049, 0.0388, 0.9601, 0.2575, 0.1290, 0.6230, 0.6525, 0.4665, 0.1918, 0.3207, 0.0877, 0.0254, 0.5004, 0.3674, 0.0020, 0.6157, 0.2958, 0.7170, 0.4645, 0.5962, 0.6492, 0.2726, 0.5693, 0.2609, 0.4224, 0.1008, 0.0872, 0.8044, 0.4292,. - 44 -.
(56) Implementation of a FFT algorithm using a soft processor core. 0.3686 0.2231 0.1308 0.5927 0.2462 0.0959 0.3181 0.4901 0.3135 0.4309 0.5640 0.0113 0.5813 0.8863 0.2431 0.0517 0.3116 0.5310 0.1540 0.1934 0.4457 0.7318 0.9337 0.7641 0.3496 0.0239 0.4510 0.9513 0.1993 0.7889 0.9971 0.9417 0.4663 0.3090 0.2339 0.4730 0.0069 0.2737 0.2853 0.8087 0.5765 0.9276 0.5423 0.5702 0.3483 0.0555 0.0391. , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,. 0.9453, 0.0603, 0.4488, 0.1744, 0.3702, 0.4024, 0.4044, 0.9289, 0.0046, 0.0597, 0.2891, 0.7983, 0.8871, 0.1468, 0.0584, 0.3257, 0.6786, 0.6301, 0.2649, 0.9727, 0.2268, 0.9935, 0.5054, 0.7331, 0.9807, 0.3725, 0.9969, 0.3120, 0.9833, 0.3282, 0.1183, 0.0670, 0.7796, 0.4536, 0.0037, 0.7979, 0.6822, 0.8632, 0.6338, 0.9031, 0.5857, 0.4280, 0.9324, 0.1120, 0.9235, 0.1582, 0.3021,. - 45 -.
(57) Implementation of a FFT algorithm using a soft processor core. 0.5805 0.2886 0.6540 0.5341 0.5685 0.5623 0.1047 0.8987 0.4570 0.8164 0.2916 0.0408 0.5225 0.1398 0.7202 0.1989 0.9936 0.1744 0.5918 0.9663 0.8406 0.1808 0.5984 0.3320 0.0564 0.1524 0.3852 0.3322 0.0641 0.2626 0.0683 0.4862 0.2599 0.0766 0.8784 0.1850 0.3216 0.9054 0.4707 0.9752 0.7345 0.6677 0.5127 0.6907 0.1821 0.2782 0.8042. , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,. 0.8746, 0.2054, 0.6750, 0.6419, 0.7762, 0.6154, 0.9539, 0.1764, 0.1841, 0.7903, 0.1225, 0.3092, 0.5567, 0.9363, 0.8728, 0.2251, 0.5639, 0.7717, 0.9964, 0.7281, 0.4494, 0.2031, 0.2931, 0.3703, 0.9717, 0.8255, 0.4945, 0.5918, 0.9530, 0.7827, 0.9674, 0.0548, 0.9601, 0.8403, 0.1574, 0.1216, 0.2758, 0.6042, 0.0787, 0.6596, 0.7413, 0.7173, 0.9527, 0.2481, 0.1545, 0.5616, 0.4778,. - 46 -.
(58) Implementation of a FFT algorithm using a soft processor core. 0.4320 0.0376 0.1406 0.6528 0.8142 0.8411 0.3674 0.5441 0.8065 0.7911 0.4029 0.3993 0.0234 0.5471 0.4218 0.6477 0.4145 0.6524 0.7705 0.5773 0.7149 0.8278 0.3973 0.2985 0.9507 0.9605 0.8313 0.3809 0.4179 0.8171 0.1163 0.0580 0.1726 0.4597 0.5748 0.7827 0.0522 0.2079 0.3796 0.3003 0.4964 0.3669 0.2533 0.6341 0.1410 0.3811 0.0154. , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,. 0.6806, 0.1891, 0.1669, 0.9814, 0.9517, 0.2863, 0.2695, 0.0613, 0.4089, 0.3323, 0.7623, 0.4488, 0.6803, 0.5697, 0.9183, 0.8634, 0.2564, 0.6596, 0.3981, 0.3043, 0.2921, 0.9132, 0.1380, 0.1492, 0.6758, 0.9774, 0.8298, 0.0408, 0.1462, 0.6244, 0.3584, 0.6803, 0.1038, 0.4501, 0.1697, 0.8215, 0.2394, 0.1097, 0.1126, 0.1266, 0.4960, 0.7699, 0.6372, 0.2017, 0.2004, 0.0545, 0.6004,. - 47 -.
(59) Implementation of a FFT algorithm using a soft processor core. 0.5763 0.1714 0.8985 0.5368 0.9863 0.9869 0.7229 0.7382 0.2113 0.4762 0.4862 0.5229 0.8021 0.7793 0.8709 0.3828 0.3999 0.5929 0.3854 0.3983 0.7676 0.0452 0.0808 0.3203 0.3985 0.1369 0.8921 0.6558 0.2801 0.0251 0.3894 0.8153 0.9255 0.4435 0.2396 0.1987 0.5215 0.5581 0.9612 0.0327 0.6752 0.0322 0.2499 0.3331 0.6217 0.8001 0.9218. , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,. 0.2195, 0.4572, 0.9132, 0.6118, 0.7874, 0.5915, 0.2324, 0.9050, 0.0389, 0.4726, 0.8472, 0.3835, 0.1476, 0.1749, 0.8207, 0.2273, 0.2520, 0.4155, 0.2141, 0.4962, 0.6019, 0.5805, 0.5462, 0.1907, 0.9266, 0.1140, 0.9300, 0.9659, 0.6671, 0.7678, 0.1335, 0.7660, 0.0308, 0.4152, 0.4287, 0.0630, 0.4194, 0.4514, 0.8395, 0.7072, 0.7881, 0.9357, 0.0921, 0.3529, 0.8645, 0.3118, 0.7591,. - 48 -.
(60) Implementation of a FFT algorithm using a soft processor core. 0.6652 0.5193 0.8578 0.7909 0.9708 0.3802 0.0954 0.5103 0.1098 0.6022 0.3169 0.6637 0.9733 0.9326 0.8884 0.4023 0.8383 0.9744 0.0938 0.5964 0.4830 0.5360 0.1635 0.2537 0.0699 0.9247 0.5276 0.7774 0.8412 0.7092 0.8155 0.6415 0.1141 0.7070 0.9225 0.1924 0.3770 0.2116 0.2252 0.6700 0.2347 0.2355 0.2225 0.2094 0.5869 0.5894 0.5703. , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,. 0.6312, 0.8719, 0.7510, 0.7997, 0.6110, 0.8510, 0.5376, 0.1573, 0.3370, 0.0524, 0.1244, 0.1147, 0.4066, 0.1870, 0.2443, 0.2989, 0.4577, 0.4570, 0.1683, 0.4730, 0.6585, 0.3163, 0.0273, 0.6870, 0.9832, 0.5535, 0.1898, 0.6406, 0.7152, 0.6754, 0.6793, 0.4852, 0.7406, 0.3973, 0.6912, 0.3799, 0.6520, 0.9091, 0.0697, 0.2990, 0.7302, 0.5871, 0.2737, 0.7183, 0.3830, 0.1580, 0.5555,. - 49 -.
(61) Implementation of a FFT algorithm using a soft processor core. 0.6590 0.7917 0.6966 0.7077 0.7539 0.9022 0.2870 0.2508 0.2977 0.9896 0.0477 0.0946 0.6535 0.7422 0.3131 0.7585 0.2900 0.4476 0.1717 0.6374 0.2076 0.3895 0.9752 0.9273 0.1011 0.4080 0.4411 0.6653 0.7301 0.4937 0.3000 0.5162 0.7933 0.0913 0.9988 0.9812 0.3950 0.4351 0.4535 0.4853 0.6875 0.0987 0.8549 0.8615 0.2083 0.6091 0.9069. , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,. 0.9110, 0.7631, 0.6470, 0.2858, 0.5180, 0.6967, 0.3878, 0.3806, 0.1537, 0.8817, 0.9583, 0.1430, 0.0557, 0.1679, 0.7275, 0.0027, 0.9286, 0.8741, 0.3453, 0.8075, 0.9328, 0.9284, 0.3949, 0.2145, 0.6035, 0.6996, 0.3460, 0.2127, 0.0729, 0.1514, 0.0179, 0.3872, 0.0278, 0.5785, 0.9236, 0.5013, 0.5196, 0.3547, 0.1597, 0.1459, 0.6294, 0.3938, 0.0272, 0.7685, 0.1840, 0.1543, 0.0605,. - 50 -.
(62) Implementation of a FFT algorithm using a soft processor core. 0.4323 0.5245 0.3304 0.3627 0.2059 0.8448 0.9445 0.6957 0.6585 0.8263 0.3087 0.0151 0.6471 0.6516 0.8127 0.6132 0.9260 0.4719 0.4356 0.7320 0.6527 0.6169 0.5297 0.6072 0.5732 0.1105 0.9275 0.6256 0.5209 0.0318 0.0335 0.4090 0.5668 0.0039 0.9289 0.8360 0.8268 0.6120 0.9531 0.5133 0.7737 0.1855 0.2185 0.9124 0.6682 0.9922 0.1409. , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,. 0.1407, 0.0275, 0.0996, 0.0193, 0.6574, 0.5018, 0.8015, 0.8881, 0.7771, 0.8060, 0.0916, 0.5060, 0.1577, 0.6236, 0.1607, 0.1789, 0.9119, 0.7839, 0.9215, 0.6192, 0.9359, 0.7870, 0.0976, 0.0357, 0.0458, 0.2666, 0.1156, 0.6424, 0.3610, 0.3560, 0.8138, 0.1738, 0.7498, 0.8847, 0.2058, 0.4428, 0.1240, 0.4040, 0.3238, 0.9745, 0.6333, 0.3032, 0.6140, 0.5259, 0.0823, 0.5435, 0.9774,. - 51 -.
(63) Implementation of a FFT algorithm using a soft processor core. 0.2436 0.1067 0.0533 0.2745 0.1781 0.9640 0.1857 0.9265 0.5060 0.7781 0.5384 0.6757 0.4421 0.0765 0.2515 0.6479 0.2614 0.1097 0.4231 0.9225 0.0243 0.4932 0.4565 0.2302 0.9823 0.7503 0.0898 0.3016 0.4695 0.0457 0.8887 0.9682 0.3309 0.0646 0.5237 0.3034 0.2221 0.8729 0.4618 0.0375 0.2321 0.5825 0.2611 0.3734 0.1693 0.6904 0.8085. , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,. 0.9407, 0.4995, 0.1361, 0.4287, 0.6848, 0.6775, 0.2438, 0.5685, 0.1466, 0.7097, 0.0379, 0.4186, 0.0316, 0.8851, 0.7653, 0.8883, 0.7081, 0.4495, 0.9600, 0.0129, 0.4852, 0.3246, 0.3131, 0.5373, 0.5950, 0.7512, 0.3215, 0.2336, 0.4094, 0.1173, 0.3038, 0.2700, 0.5993, 0.1121, 0.6009, 0.3928, 0.2659, 0.8802, 0.0665, 0.1724, 0.9012, 0.2488, 0.5747, 0.7191, 0.3801, 0.2019, 0.9984,. - 52 -.
(64) Implementation of a FFT algorithm using a soft processor core. 0.1961 0.5364 0.9260 0.2007 0.2814 0.5436 0.8639 0.0132 0.2090 0.0762 0.5135 0.6651 0.8669 0.5759 0.9080 0.5905 0.2378 0.9823 0.3959 0.6627 0.0214 0.3784 0.5026 0.8959 0.8900 0.6639 0.1469 0.5002 0.3474 0.0372 0.2164 0.6660 0.3364 0.5250 0.6599 0.4060 0.9118 0.0256 0.1503 0.6472 0.5766 0.1374 0.3160 0.4862 0.6390 0.4018 0.7405. , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,. 0.2496, 0.0141, 0.4733, 0.4673, 0.1355, 0.6928, 0.6268, 0.3535, 0.2687, 0.3160, 0.9560, 0.4117, 0.4017, 0.7759, 0.6796, 0.0241, 0.5943, 0.0868, 0.8225, 0.2087, 0.9197, 0.1326, 0.3560, 0.6859, 0.0968, 0.8185, 0.2435, 0.8452, 0.5853, 0.7464, 0.2231, 0.6922, 0.0051, 0.4659, 0.9439, 0.2101, 0.5360, 0.8728, 0.7380, 0.2978, 0.8075, 0.9891, 0.1975, 0.0267, 0.8492, 0.8103, 0.5134,. - 53 -.
(65) Implementation of a FFT algorithm using a soft processor core. 0.3477 0.4537 0.2845 0.6723 0.7722 0.6021 0.8224 0.6195 0.0794 0.7195 0.1203 0.0364 0.9292 0.8571 0.7445 0.2855 0.1365 0.9684 0.8439 0.9762 0.7600 0.2906 0.9593 0.8586 0.2960 0.4427 0.2305 0.7135 0.5100 0.2303 0.2218 0.9048 0.9199 0.3415 0.4050 0.4324 0.7724 0.2884 0.1971 0.0009 0.0633 0.4036 0.7694 0.7532 0.3736 0.8624 0.3516. , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,. 0.2815, 0.7715, 0.5441, 0.4400, 0.1919, 0.4804, 0.7395, 0.4601, 0.0971, 0.1887, 0.9378, 0.6463, 0.4791, 0.4477, 0.9240, 0.0642, 0.3548, 0.4726, 0.6932, 0.7788, 0.0890, 0.2340, 0.4645, 0.8938, 0.3578, 0.6295, 0.0573, 0.9147, 0.7905, 0.6431, 0.8386, 0.9348, 0.7913, 0.4660, 0.7285, 0.6381, 0.2453, 0.0481, 0.4989, 0.4830, 0.2781, 0.7266, 0.6614, 0.4995, 0.3846, 0.4726, 0.6583,. - 54 -.
(66) Implementation of a FFT algorithm using a soft processor core. 0.5071 0.1725 0.4497 0.5143 0.7977 0.5293 0.1918 0.0214 0.8520 0.2081 0.2809 0.9305 0.9047 0.5805 0.1635 0.0446 0.1072 0.3647 0.0172 0.0160 0.6776 0.7173 0.3183 0.9046 0.7337 0.0615 0.7256 0.1493 0.6916 0.7084 0.4958 0.4334 0.2002 0.6004 0.2970 0.6518 0.4519 0.7007 0.2109 0.2344 0.2095 0.7682 0.4734 0.1717 0.9877 0.8762 0.4808. , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,. 0.3898, 0.0149, 0.9889, 0.9838, 0.8142, 0.6795, 0.9056, 0.8643, 0.7306, 0.6300, 0.7463, 0.1283, 0.6364, 0.8352, 0.9560, 0.7091, 0.8283, 0.5065, 0.5534, 0.8221, 0.4475, 0.6776, 0.6431, 0.8749, 0.1892, 0.3531, 0.8874, 0.4285, 0.9891, 0.6733, 0.0425, 0.8225, 0.9466, 0.7532, 0.0509, 0.1398, 0.2725, 0.6061, 0.7287, 0.8541, 0.1184, 0.2143, 0.0904, 0.8255, 0.9010, 0.4980, 0.6533,. - 55 -.
(67) Implementation of a FFT algorithm using a soft processor core. 0.1554 0.7917 0.2398 0.4224 0.5486 0.1327 0.9340 0.4468 0.4536 0.6428 0.1822 0.1055 0.0708 0.5803 0.8844 0.3172 0.2150 0.8849 0.9764 0.1050 0.0455 0.4431 0.8563 0.7209 0.2374 0.0951 0.3277 0.0770 0.7416 0.4877 0.6457 0.3939 0.5130 0.4372 0.5396 0.6898 0.2709 0.5592 0.3882 0.0098 0.7319 0.3884 0.2288 0.2706 0.4499 0.8542 0.3186. , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,. 0.9019, 0.8534, 0.9155, 0.8166, 0.6092, 0.9124, 0.4947, 0.7055, 0.5264, 0.6148, 0.1644, 0.0245, 0.3820, 0.5668, 0.7871, 0.9676, 0.1275, 0.2421, 0.7881, 0.9379, 0.8469, 0.5212, 0.2015, 0.4227, 0.5224, 0.4747, 0.0861, 0.7765, 0.5178, 0.3598, 0.1827, 0.1205, 0.0502, 0.1092, 0.7632, 0.3471, 0.9619, 0.4610, 0.1004, 0.4808, 0.9696, 0.5348, 0.7757, 0.6235, 0.9732, 0.2010, 0.5141,. - 56 -.
(68) Implementation of a FFT algorithm using a soft processor core. 0.5066 0.7850 0.2204 0.9560 0.6819 0.6310 0.0154 0.1768 0.5674 0.6826 0.0112 0.9958 0.6317 0.5530 0.9148 0.6265 0.5311 0.9747 0.5073 0.1637 0.9412 0.4128 0.6630 0.9583 0.3419 0.0403 0.2369 0.4976 0.5609 0.7597 0.1100 0.3959 0.9444 0.3150 0.6147 0.0856 0.3341 0.0189 0.3923 0.5798 0.7184 0.1602 0.0949 0.7941 0.8450 0.6567 0.2618. , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,. 0.4219, 0.2274, 0.0791, 0.6836, 0.7309, 0.4177, 0.6123, 0.8095, 0.3857, 0.3032, 0.6173, 0.8883, 0.3171, 0.0685, 0.9620, 0.9330, 0.2173, 0.1426, 0.8563, 0.5585, 0.2992, 0.6449, 0.3246, 0.6462, 0.3110, 0.7883, 0.5332, 0.1647, 0.5121, 0.0244, 0.6395, 0.5124, 0.1230, 0.8284, 0.4959, 0.4037, 0.0104, 0.7768, 0.0901, 0.9293, 0.5647, 0.4380, 0.1385, 0.4011, 0.9300, 0.4615, 0.6626,. - 57 -.
(69) Implementation of a FFT algorithm using a soft processor core. 0.9235 0.9693 0.4483 0.6581 0.4910 0.8340 0.7262 0.6358 0.4132 0.1365 0.6138 0.0876 0.9842 0.4010 0.9734 0.5715 0.0448 0.5222 0.8571 0.8743 0.3499 0.9179 0.9743 0.1883 0.5477 0.9010 0.1627 0.0250 0.1189 0.5879 0.9876 0.2974 0.4984 0.0761 0.0922 0.9020 0.9718 0.6018 0.0305 0.3144 0.8344 0.0538 0.3675 0.3527 0.4057 0.7354 0.3635. , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,. 0.5244, 0.3212, 0.8508, 0.4182, 0.2604, 0.9981, 0.9308, 0.1018, 0.3224, 0.6051, 0.6575, 0.3698, 0.9876, 0.3491, 0.1495, 0.5948, 0.3420, 0.0380, 0.9516, 0.3942, 0.9292, 0.2988, 0.4695, 0.6419, 0.6544, 0.0971, 0.3311, 0.7194, 0.8302, 0.3706, 0.3035, 0.6742, 0.8289, 0.8959, 0.2005, 0.4439, 0.0834, 0.7334, 0.0125, 0.8994, 0.7542, 0.4085, 0.3504, 0.7126, 0.8255, 0.0742, 0.6057,. - 58 -.
(70) Implementation of a FFT algorithm using a soft processor core. 0.8390 0.8363 0.1470 0.9804 0.3647 0.5891 0.5188 0.3079 0.1749 0.6171 0.5827 0.5454 0.4280 0.6583 0.1362 0.7328 0.6189 0.0985 0.6906 0.0254 0.7662 0.8963 0.2763 0.5559 0.8941 0.1443 0.8671 0.1371 0.7371 0.9124 0.2058 0.5220 0.8278 0.6917 0.5876 0.9839 0.1959 0.9173 0.6587 0.9738 0.2642 0.5108 0.3226 0.8863 0.3910 0.7411 0.7868. , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,. 0.7225, 0.9874, 0.2085, 0.1980, 0.0214, 0.3669, 0.7466, 0.4325, 0.6016, 0.0461, 0.9834, 0.8739, 0.2483, 0.6988, 0.7108, 0.5697, 0.6145, 0.6656, 0.7059, 0.3516, 0.1601, 0.5751, 0.2724, 0.4154, 0.8632, 0.6802, 0.0098, 0.1183, 0.4921, 0.7775, 0.6197, 0.3181, 0.9573, 0.9589, 0.0163, 0.6603, 0.5965, 0.8595, 0.0942, 0.6303, 0.3392, 0.8020, 0.8956, 0.3146, 0.7444, 0.8660, 0.6895,. - 59 -.
(71) Implementation of a FFT algorithm using a soft processor core. 0.0410 0.3890 0.1851 0.2259 0.7858 0.2499 0.5410 0.2314 0.6928 0.5107 0.5276 0.4794 0.2844 0.8138 0.2489 0.8991 0.5069 0.5732 0.5583 0.3197 0.9474 0.9107 0.3220 0.3751 0.8343 0.9394 0.2812 0.6223 0.4749 0.3273 0.6601 0.2932 0.5557 0.1181 0.3266 0.3059 0.4489 0.0802 0.8982 0.1076 0.7850 0.1332 0.1902 0.4655 0.7565 0.2288 0.0328. , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,. 0.4888, 0.5676, 0.5217, 0.9011, 0.1877, 0.8641, 0.5976, 0.7539, 0.2498, 0.1038, 0.0619, 0.1518, 0.9919, 0.0864, 0.7293, 0.1432, 0.6646, 0.7164, 0.9292, 0.6309, 0.7500, 0.4878, 0.1550, 0.5134, 0.6260, 0.1901, 0.5818, 0.5801, 0.9753, 0.0529, 0.7667, 0.5813, 0.3770, 0.5757, 0.4208, 0.4979, 0.8206, 0.2000, 0.6225, 0.3033, 0.5155, 0.6430, 0.5707, 0.2219, 0.8675, 0.5750, 0.3269,. - 60 -.
(72) Implementation of a FFT algorithm using a soft processor core. 0.9865 0.2548 0.6072 0.8316 0.0987 0.8250 0.6100 0.6723 0.5273 0.7675 0.2903 0.6956 0.1804 0.3846 0.3386 0.1229 0.5520 0.7708 0.6040 0.4721 0.1652 0.4763 0.2121 0.2787 0.2485 0.2465 0.2967 0.2894 0.3764. , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,. 0.5051, 0.2308, 0.0183, 0.2302, 0.9942, 0.3459, 0.6787, 0.6320, 0.3162, 0.6799, 0.5364, 0.7665, 0.3436, 0.5051, 0.8106, 0.5817, 0.1448, 0.1812, 0.7752, 0.2847, 0.9021, 0.0656, 0.1965, 0.7252, 0.5982, 0.6086, 0.2282, 0.0843, 0.8422};. // Define cosinus and sinus array float tabcos[] = {1.0000, 0.9952, 0.9808, 0.9569, 0.9239, 0.8819, 0.8315, 0.7730, 0.7071, 0.6344, 0.5556, 0.4714, 0.3827, 0.2903, 0.1951, 0.0980, 0.0000, 0.0980, -0.1951, -0.2903, -0.3827, -0.4714, -0.5556, -0.6344, -0.7071, -0.7730, -0.8315, -0.8819, -0.9239, -0.9569, 0.9808, -0.9952, -1.0000, -0.9952, -0.9808 -0.9569, -0.9239, -0.8819, -0.8315, -0.7730, -0.7071, -0.6344, -0.5556, 0.4714, -0.3827, -0.2903, -0.1951, -0.0980, 0.0000, 0.0980, 0.1951, 0.2903, 0.3827, 0.4714, 0.5556, 0.6344, 0.7071, 0.7730, 0.8315, 0.8819, 0.9239, 0.9569, 0.9808, 0.9952 };. - 61 -.
(73) Implementation of a FFT algorithm using a soft processor core. float tabsin[] = {0.0000, 0.0980, 0.1951, 0.2903, 0.3827, 0.4714, 0.5556, 0.6344, 0.7071, 0.7730, 0.8315, 0.8819, 0.9239, 0.9569, 0.9808, 0.9952, 1.0000, 0.9952, 0.9808, 0.9569, 0.9239, 0.8819, 0.8315, 0.7730, 0.7071, 0.6344, 0.5556, 0.4714, 0.3827, 0.2903, 0.1951, 0.0980, -0.0000, -0.0980, -0.1951, 0.2903, -0.3827, -0.4714, -0.5556, -0.6344, -0.7071, -0.7730, -0.8315, -0.8819, -0.9239, -0.9569, -0.9808, -0.9952, 1.0000, -0.9952, -0.9808, -0.9569, -0.9239, -0.8819, -0.8315, -0.7730, -0.7071, -0.6344, -0.5556, -0.4714, -0.3827, 0.2903, -0.1951, -0.0980}; int stage, Ns, M1, k, kNs, p, q; double WCos, WSin, TwoPiN, TempRe, TempIm;. /**********************/ /* Principal program */ /**********************/ int main () { fft(); return 0; }. /*******************/ /* FFT function */ /*******************/ int fft () { int i; Ns=N; M1=M; TwoPiN=2*Pi/N;. for (stage=1;stage<M+1;stage++) { k=0; Ns=Ns/2; M1=M1-1;. - 62 -.
(74) Implementation of a FFT algorithm using a soft processor core.. while(k<N) { for (q=1;q<Ns+1;q++) { p=Digit_Reverse(k/(1<<M1)); WCos=tabcos[p]; WSin=tabsin[p]; kNs=k+Ns; /* BUTTERFLY */ TempRe=x[kNs].re*WCos-x[kNs].im*WSin; TempIm=x[kNs].im*WCos+x[kNs].re*WSin; x[kNs].re=x[k].re-TempRe; x[kNs].im=x[k].im-TempIm; x[k].re=x[k].re+TempRe; x[k].im=x[k].im+TempIm; k++; } k=k+Ns; } } Unscramble(); return 0; } /***************************/ /* Digit_Reverse function */ /***************************/ int Digit_Reverse (int Digit) { int q,NewAddr=0,Rmbit,OldAddr=Digit; for(q=1;q<M+1;q++) { Rmbit=OldAddr%2; OldAddr=OldAddr/2; if(Rmbit==1) { NewAddr=NewAddr*2+1;. - 63 -.
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