Design and Development of Data Acquisition/Processing and Communication Interface for Radar Front-End

Department of Science and Technology Institutionen för teknik och naturvetenskap

Linköping University Linköpings universitet

g n i p ö k r r o N 4 7 1 0 6 n e d e w S , g n i p ö k r r o N 4 7 1 0 6 -E S

LiU-ITN-TEK-A-16/036--SE

Design and Development of Data

Acquisition/Processing and

Communication Interface for

Radar Front-End

Daniel Käll

Emelie Lannerhjelm

LiU-ITN-TEK-A-16/036--SE

Design and Development of Data

Acquisition/Processing and

Communication Interface for

Radar Front-End

Examensarbete utfört i Elektroteknik

vid Tekniska högskolan vid

Linköpings universitet

Daniel Käll

Emelie Lannerhjelm

Handledare Qin-Zhong Ye

Examinator Adriana Serban

Upphovsrätt

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Abstract

This thesis follows the design process of a back end. The purpose of this back end is to interface a radar front end, developed by Acreo Swedish ICT, and stream it’s digitalized output to a PC using Universal Serial Bus (USB) 3.0.

The front end, which acts as a basis for this project, is a Frequency Modulated

Continuous Wave (FMCW) radar which is connected to the back end by a header.

The header connects the digitalized radar signals, together with two SPI-buses and a few GPIO pins. Thus, enabling configuration and set up of the front end

board via a PC.

The result of the thesis is a data acquisition board that can be used to inter-face with the front end. The implemented back end features an FPGA to han-dle the ADC data from the front end, so the board has DSP capabilities, but can also stream the raw radar data. The FPGA is connected to a USB 3.0 controller through a 32-bit parallel interface.

The configuration of the front end, via the produced board, is verified in it’s func-tionality and can be controlled by a PC using a simple GUI. Commands are sent through the USB 3.0 controller to a front end controller which handles the com-munication.

Since getting the hardware functional has been the main objective of the thesis, the project has been deemed to be successful. The final result is a back end radar prototype, which has the requested core hardware functionalities. In addition to this, the prototype has the capacity to act as a platform for further expanding its functionality after a hand over of the project to Acreo Swedish ICT.

Acknowledgments

Apart from our supervisors, we would also like to thank Duncan Platt, at Acreo Swedish ICT Norrköping, for being available and giving advice.

Norrköping, July 2016 Daniel Käll och Emelie Lannerhjelm

Contents

1.4.2 Back end design . . . 3

1.4.3 VHDL . . . 3

1.4.4 Software- and hardware programming . . . 3

1.4.5 GUI design . . . 3 1.4.6 Algorithm implementation . . . 4 1.5 Delimitation . . . 4 1.6 Report outline . . . 4 1.7 Litterature overview . . . 5 2 FMCW Radar 7 2.1 Radar Basics . . . 7 2.2 FMCW Basics . . . 9

3 Interfaces for On-board Communication 13 3.1 SPI . . . 13

3.2 I2C . . . 14

3.3 UART . . . 15

3.3.1 USB . . . 16

4 Front End_{overview 19} 4.1 Front end design specifications . . . . 19

4.2 Architecture overview . . . 20

4.3 Simulated performance . . . 21

4.4 Back end/front end interface . . . 21

4.4.1 PSU . . . 21

viii Contents

4.4.2 Radar controller and transmitters . . . 22

4.4.3 Power amplifiers . . . 23

4.4.4 Receivers . . . 23

4.4.5 ADCs and level-shifter . . . 24

4.4.6 Sensor . . . 24

5 Back End Design 27 5.1 Design considerations . . . 27

5.2 Architecture . . . 28

5.3 Power Distribution . . . 30

5.3.1 Altera Cyclone V power supply . . . 30

5.3.2 FPGA decoupling . . . 34

5.3.3 Front end power supplies . . . 34

5.3.4 MCU power supplies . . . 37

5.4 Schematic and Layout . . . 39

6 Programming 41 6.1 STM32 . . . 41

6.1.1 MCU communication . . . 42

6.1.2 Peripheral devices . . . 44

6.2 Cypress FX3 . . . 45

6.2.1 Virtual COM port . . . 45

6.2.2 Synchronous Slave FIFO Interface . . . 45

6.3 FPGA . . . 46 6.3.1 UART . . . 46 6.4 User Interface . . . 46 7 Result 49 7.1 Initial testing . . . 49 7.1.1 Boot test . . . 51 7.2 USB interface . . . 53 7.3 GUI . . . 54

7.4 SPI and UART communication test . . . 55

8 Conclusions 59 8.1 Discussion . . . 59 8.1.1 Result evaluation . . . 59 8.1.2 Issues . . . 60 8.2 Further work . . . 60 A Schematic i B Errata i Bibliography 65

x Notation

Notation

Abbreviations

Abbreviation Meaning

acm Abstract Control Model

adc Analogue-to-Digital Converter

api Application Programming Interface

bom Bill of Materials

cdc Communications Device Class

com COMunnication (port)

cpha Clock PHAse

cpol Clock POLarity

cpu Central Processing Unit

cs Chip Select

cts Clear To Send

cw Continous Wave

dll Dynamic Linked Library

dma Direct Memory Access

dsp Digital Signal Processing

eeprom Electrically Programmable Read-Only Memory

epcq Quad Serial Configuration Device

fifo First In First Out

fmcw Frequency-Modulated Continuous Wave

fpga Field Programmable Gate Array

hid Human Interface Device

gpif General Purpose InterFace

gui Graphical User Interface

i2c Inter-Integrated Circuit (I-squared-C)

iad Interface Association Descriptor

ic Integrated Circuit

ide Integrated Development Environment

if Intermediate frequency

ic Input/Output pin

ip Intellectual Property

LDO _{Low Drop-Out}

Notation xi Abbreviations

Abbreviation Meaning

lfm Linear Frequency Modulated

lo Local Oscillator

mcu MicroController Unit

miso Master-In, Slave-Out

mosi Master-Out, Slave-In

nop No OPeration

nss Negative Slave Select

oe Operation Enable

pc Personal Computer

pcb Printed Circuit Board

pg Power Good

pid Product ID

psu Power Supply Unit

radar RAdio Detection And Ranging

rf Radio Frequency

rts Request To Send

sck Serial ClocK

sdi Serial Data In

sdk Software Development Kit

sdo Serial Data Output

spi Serial Peripheral Interface

soc System On Chip

spdt Single Pole Double Throw

spst Single Pole Single Throw

uart Universal Asynchronous Receiver/Transmitter

uvlo Under-Voltage Lock-Out

uwb Ultra-Wide Band

usart Universal Synchronous/Asynchronous

Re-ceiver/Transmitter

usb Universal Serial Interface

vco Voltage-Controlled Oscillator

1

Introduction

This Chapter introduces the thesis assignment, the disposition of the report and an outline on the planned execution of the project.

1.1

Background

A typical data acquisition system consists of four main subsystems with the fol-lowing functions:

• Sensing physical phenomena

• Electrical (analog) signal conditioning and pre-processing • Analog-to-digital conversion

• Processing, analyzing, storing, and displaying the acquired digital data with the help of software and/or hardware.

Acreo Swedish ICT’s Frequency Modulated Continuous Wave (FMCW) radar front

end already includes the first three subsystems, integrated onto the same Printed Circuit Board (PCB) called the front end board.

Figure 1.1: System overview

The task of this thesis is to design and develop the last subsystem, which is to be integrated on another PCB, referred to as the back end board. The back end

2 1 Introduction

board is programmed and controlled with software via a personal computer (PC), related to each other as in Figure 1.1.

1.2

Task

The primary assignment of the thesis is to design the data acquisition system, to allow interfacing between Acreo’s front end board and a PC.

1. The back end should include a Serial Peripheral Interface (SPI) with enough channels to interface with the front end. It should also include a number of required Input/Output pins (IOs) to control the front end. The back end registers should be accessible (for both read and write) from a PC using a

Graphical User Interface (GUI).

2. The back end should be able to send the digitized data directly to a PC and be linked to MATLAB for Digital Signal Processing (DSP).

3. Alternatively, the back end should include a Field-Programmable Gate Array (FPGA) to handle high-speed radar signal processing algorithms. The pro-cessed data from the FPGA should then be sent to a PC and linked to MAT-LAB for further low-speed radar data processing.

The secondary assignment of the thesis concerns the radar signal process-ing. This is to be implemented if the primary assignment is fulfilled, with time marginal. The performance of the developed data acquisition and processing shall then be verified by implementing a few fundamental signal processing algo-rithms. This should be done using either FPGA or MATLAB.

Gathering large quantities of measurement data is required for proper evalu-ation of the algorithms. This is a difficult task for practical radar scenarios with moving objects, and requires certain facilities. Therefore, artificial radar data generation, using software tools, should be investigated and utilized in this sce-nario.

1.3

Purpose

The objective of the thesis is trying to answer the following three questions: 1. How can a back end be designed, so that it enables streaming of data from

the front end to a PC?

2. How can a GUI be implemented so that it enables read/write to registers on the front end?

3. (Secondary) How can algorithms be utilized to process the radar data in MATLAB?

1.4 Method 3

1.4

Method

To estimate the disposable time, a number of activities have been identified. The different activities generate result in the form of milestones, which subsequent activities rely on. The activities are presented in this Chapter.

1.4.1

Pre-study

The initial phase of the thesis work is a pre-study. This activity mainly includes reading up on theory behind FMCW radar, and the communication protocols to be utilized.

This block also includes research concerning technical solutions and com-ponents that could be used in the architecture. The knowledge of (Very High

Speed Integrated Circuit) Hardware Description Language (VHDL) basics are to be

refreshed with the help of lab sessions.

1.4.2

Back end design

The hardware design is divided into two sub activities. First a schematic is drawn, which in turn is used to create the PCB layout.

The schematic is based around the choice of components which are deter-mined by the first milestone (Architecture review). Altium Designer will be used to create the schematic, layout and production files.

1.4.3

VHDL

Alongside the PCB-design, software for the FPGA can be prototyped to stream-line work. Adjustments of the prototyped VHDL algorithms are done when the resulting hardware is received.

For the implementation of the VHDL code on the FPGA, Quartus Prime 16 from Altera will be used. Quartus is a developer tool for Altera FPGA’s. It in-cludes functionality to set up pin connections, VHDL coding either directly or in a graphical schematic view, programming among other useful functions.

1.4.4

Software- and hardware programming

Software for the Microcontroller Unit (MCU) is written to handle the serial inter-faces, and also to stream data from the radar front end to a computer. The MCU software will be dependent on the hardware and the VHDL implementations. On the computer end, software is required to handle/store the incoming data. This activity will also include actual test that determines if the hardware is working as intended.

1.4.5

GUI design

Changing registers at the front end have a need to be simple. Therefore a GUI is required, which keep track of the different registers in a human readable fashion.

4 1 Introduction

This GUI is to be implemented in MATLAB.

1.4.6

Algorithm implementation

This will be the last activity, which would validate that the received data can be used for radar algorithms on a PC using MATLAB. Algorithms to extract Doppler and range information, detection, classification and target tracking will be con-sidered, if there is sufficient time.

1.5

Delimitation

The front end is a product that was designed during this thesis project. The design of the back end is dependant upon the front end development. Thus the design part of the project will be delimited to working with the digital signals after the

Analogue-to-Digital Converter (ADC) of the front end, and the interface to a PC.

Although the thesis gives some overviewing theory on FMCW radar, to anchor the thesis’ practical applications on a system level, the main focus is to construct the data acquisition board.

The USB terminology will only be discussed briefly to give the reader suf-ficient knowledge to follow the text. The same applies to the utilized First-In,

First-Out (FIFO) and Direct Memory Access (DMA) protocols.

The implementation of post processing algorithms in MATLAB will only be done if the rest of the requirements are met in good time before the project’s end-date. Therefore a Chapter on DSP theory will only be included in the report if the project reaches the implementation of this functionality.

The post processing of the acquired data in MATLAB is not required to take place in real-time.

To some extent this project contains elements of secrecy, regarding the front end. However some basic functionality of the front end has to be discussed, since it acts as a theoretical basis for this thesis. This will be done without delving into much detail, since the datasheets and identities of the specific components in the radar chip-set used for the front end are confidential.

This is the reason the only source cited in this Chapter will be the design report for the front end.

1.6

Report outline

The Chapters 2-4 presents the theoretical basis of the thesis, which concerns some basic FMCW radar- and communication protocol theory, in addition to a section containing a brief overview of the front end. Chapters 5-6 focuses on the design process of the back end PCB, the GUI interface and the programming of the back

1.7 Litterature overview 5 The report concludes with appendices containing schematics of the designed PCB and an errata for the assembled prototype.

1.7

Litterature overview

Since a large number of sources are referenced in this thesis, this section will give a brief overview of their function and purpose in appearing order.

Chapter 2, which concerns radar theory, opens with a brief introduction of a few antenna technology basics from the book Foundations of Antenna Theory and

Tech-niques [1]. The basic radar theory in the continuation of the chapter comes mostly

from the books Radar: Principles, technology, applications [2] and Design of

multi-frequency CW radars [3], with some complement from Handbook of RF, microwave, and millimeter-wave components [4]. An article from the Access Science database

[5] is referenced to give the definition of the Doppler effect and the formulas for the radial velocity of a radar target are from The electrical engineering handbook [6].

Chapter 3, concerns common communication interfaces, which are utilized in the project. The references [7] and [8] are general specifications for these interfaces. The article USART vs UART: Know the difference [9] is quoted for the difference between UART and USART.

The only source referenced in Chapter 4, is the 79 GHz UWB Imaging Radar

Pro-totype 1 Front-End Design Report [10] from Acreo Swedish ICT, because of the

secrecy concerning the front end. The details in the report are confidential. Chapter 5, is about the projects design phase. The reference [11] is an overview of an Altera FPGA product category, and [12]-[13] are examples of third-party solutions for USB 3.0 implementations for Altera FPGAs. These citations serves mainly to give a comparison and motivate design choices.

The datasheets [14] and [15] are for the MCUs chosen for the back end, while [16] is an overview of the Cyclone V product family, which has been considered before choosing a FPGA. The source [17] provides pin-connection guidelines in addition to PSU recommendations for the Cyclone V family.

PowerPlay Early Power Estimators and Power Analyzer [18] is a macro, used

for estimating the needs of the FPGA power rails, the datasheet [19] is for the regulator used to power those. Alteras Power Distribution Network [20] macro is used for making the de-coupling design for the FPGA.

The datasheets [21]-[22] are for the regulators used on the back end and [23] is an application note of how to reduce power dissipation in one of those.

STM32CubeMX [24] is a software-tool used for making power estimation for

the STM32 MCU in addition to simplifying the code initialization for this device. Power estimation for the other MCUs have been made using a spread-sheet [25] provided by Cypress Semiconductor.

Hardware design guidelines for both MCUs [26] [27] are also cited in this Chapter. Inspiration from development boards [28], [29] and [30] for the MCUs

6 1 Introduction

have been used in addition with the hardware design guidelines, when develop-ing the back end.

The datasheets [31] and [32] are for two additional regulators utilized on the

back end.

Chapter 6, which concerns the programming part of the project, cites [33] that refers to the debugger used for the programming of the STM32 MCU, in addition to [34] which gives some background on the STM32CubeMX-software tool.

For the code implementation the FX3 MCU from Cypress, the EZ-USB FX3

Software Development Kit [35] is used. The background of the slave FIFO interface

is referenced in the design guidelines [36].

For the programming of the FPGA configuration device, the reference [37] has been utilized.

The reason why there are few academic journals and books cited is simply because the practical orientation of this thesis. Datasheets and application notes are therefore over represented.

2

FMCW Radar

2.1

Radar Basics

RADAR is a technology which uses transmissions of electromagnetic waves and their echoes for detection, ranging and sensing of various other characteristics of remote targets, by the use of antennas.

A few central parameters, that usually are discussed concerning antenna perfor-mance are the beamwidth, sidelobe levels and return losses.

The sidelobes of an antenna’s far-field radiation pattern are radiation maximas directed at other angles than the main lobe of the antenna. Where the main lobe is in the direction of the maximum field strength. The sidelobe pattern and levels thus affects the directivity of the antenna. Directivity is, as it sounds, a measure of how directional an antenna’s radiation pattern is (2.1). If sidelobes are minimal to non-existent compared to the main lobe, the higher the directivity of the antenna. A lower directivity results in lower antenna gain in the main lobe direction. Gain is the quota of the maximum power received from a radiating antenna and by

isotropic source (2.2). [1, 3.2, 2.4]

D = Radiation intensity in direction of main lobe

Averag e radiation intensity over all directions (2.1)

G = M aximum radiated power received f rom an antenna

M aximum radiated power received f rom an isotropic source (2.2)

The beamwidth is defined from the points where the power of the radiation pattern has half the power (-3 dB), in relation to boresight. This parameter is called the half power beamwidth (HPBW), also referred to as the 3 dB beamwidth. [1, 3.2]

8 2 FMCW Radar

The return loss of an antenna system is also a valuable measure of the systems functionality. It is defined as the quota of the input power to the system and the reflected power received. [1, 6.1]

The most basic radar type is the pulse radar. It works by transmitting out a burst of energy and then wait for the echo to appear at the receiver antenna, while the transmitter is silent. Ranging measurements by this sort of radar are achieved by measuring the time propagation delay between transmission and reception of the echo.

To determine the maximum detection range of a pulsed radar, an inequality needs to be formulated where the received power is larger than the receiver an-tennas equivalent signal noise.

The power arriving at the receiver antenna P_R (2.3) depends primarily on the

power reflected by the target. PT is the transmitted power, GT the gain of the

transmitter, GR the gain of the receiver, σT is the radar cross section area of the

target, λ is the wavelength and d is the separation between target and antenna. [2, 1.1-1.4]

P_R = PTGTGRλ

2_σ

T

(4π)3_d4 (2.3)

The equivalent noise at the receiver (2.4) can be expressed as a product of

Boltzmann’s constant k, effective system noise temperature T_N, the receiver noise

figure FR, the bandwidth of the receiver B and the detectability factor D0.

P_N = kTNFRBD0 (2.4)

The maximum range of the radar can then be calculated by rewriting the in-equality in equation (2.5). The left hand side represents the power at the receiv-ing antenna and the right is the equivalent noise of the receiver. [3, 1.2 ]

P_TG_TG_Rθ_Tλ2σ_T

(4π)3_d4_L > kTNFRBD0 (2.5)

There is an approximately inverse relationship between the bandwidth and the width τ of the transmitted pulse of a pulsed radar device. In addition to this

the product τP_T equates the energy of a transmitted pulse and can be rewritten

as E_T. Thus it is shown that the range equation for a pulsed radar can be written

as (2.6).

The aforementioned equation (2.6) is independent of both B and τ, and is therefore applicable to all radars types. [3, 1.2]

R_max = ETGTGRλ 2_σ T (4π)3_LkT NFRD0 !1/4 (2.6) The range resolution of a radar, is the ability of the radar to distinguish be-tween different targets. This ability is greatly affected by the pulse duration of the radar and to some extent, of the efficiency of the receiver/transmitter.

Theoretically, assuming maximum efficiency, the target separation is limited to half the pulse duration (2.7). [3, 2.3.1]

2.2 FMCW Basics 9

s_r ≥ c0τ

2 (2.7)

2.2

FMCW Basics

A continuous wave (CW) radar continuously outputs waves of low power, instead of the high peak power pulses of traditional radar. Thus, on the most superficial level, a CW radar differs from a regular pulse radar in that it has a 100% duty cycle and therefore transmits and receives at the same time. This results in a lower, continuous power, which makes the radar signal harder to detect. This was a main reason for the development of CW technology during the cold war and can be classified as an Low Probability of Intercept radar. [3, 1.1 ]

Figure 2.1:Typical FMCW system overview

The block diagram of a typical FMCW radar is shown in Figure 2.1. It is a type of CW radar that uses a ramp generator, which produces a control signal for a Voltage-controlled oscillator (VCO). This way up and/or down chirps (frequency ramps) can be produced. The significance of this frequecy modulation will be dis-cussed in greater detail in the end of this Chapter.

The transmitted signal can be described as a cosine function (2.8), while the received signal is a phase shifted cosine function (2.9).

These signals are passed trough a mixer which performs a time domain mul-tiplication of the two signals. The resulting output frequencies in the two cosine terms correspond to the sum and the difference of the input frequencies (2.10). After low-pass filtering, a down converted intermediate frequency (IF) has been achieved.

This IF-signal can be digitalized using an ADC and then DSP can be used to perform radar calculations, which extract properties of the target(s).

The filtering of the received signals serves to remove signal components which are outside the range of the ADC, and thus prohibits saturation of the converter, which otherwise might give rise to conversion errors. [4, 8.1].

u1(t) = U1cos(2πf1t) (2.8)

u₂(t) = U2cos(2πf2t + φ) (2.9)

y1(t) =

k₁U₁U₂

10 2 FMCW Radar

One of the most common forms to express the range equation for a CW radar is (2.11). [3, 1.2 ] R_max = PCWGTGRλ 2_σ T (4π)3_{LkT F} RBRoS N RRo !1/4 (2.11)

In (2.11), D0has been substituted with the output signal-to-noise ratio S N RRo

and B is expressed as the output bandwidth BRo. PCW is the average power in

watts for the continuous wave.

The most basic CW radar sends out continuous, monotonic, unmodulated waves. The range of an object can not be detected unless the continuous wave is modu-lated by a signal that varies over time. [2, 2.4]

Ranging can be achieved by using linear frequency-modulated (LFM) wave-forms or modulating using a sinusodial waveform. Either triangular, up- or down ramped signals (more often refered to as up- or down chirp) can be used for linear

frequency modulation. This is referred to as LFM waveform compression. [3, 4.2 ]

Figure 2.2: Dopper shift due to radial velocity of target

The Doppler effect is a shift in wavelength (λ’) that occurs when waves are reflected off an object that has a radial velocity (v) relative to the wave source. (Figure 2.2)

In a radar system, this results in a frequency shift (f_d) of the transmitted wave

due at the receiver antenna. (2.12) [5]

f_d = 2v

λ (2.12)

For simplicity, let’s assume that a LFM sawtooth wave with consecutive

up-chirps is transmitted, corresponding to f_T (Figure 2.3). The frequency is ramped

around a centre frequency (e.g. 79 GHz) with a bandwidth B. As the transmitted wave travels through space and is reflected back by an object, a propagation delay (τ) is introduced. The frequency difference between the currently transmitted

and received signal (δf_U), depends on the time shift introduced by the distance

to the object. If the target has no radial velocity the shift corresponds to the beat

frequency. If the object is has a velocity, a Doppler shift (fd) term is added to the

2.2 FMCW Basics 11

Figure 2.3: Transmitted and recieved chirp

If instead considering a triangular FM carrier, the beat frequency which is pro-portional to the round-trip propagation time (2.13), is equal for both the up- and

down chirp periods of the wave when no Doppler shift is imminent. In (2.13) δf_R

represents the frequency difference between transmit and receive signals while

T is the time of one ramp. The range to the target is then found by using (2.14).

[2, 6.5] τ = δf_RT B (2.13) R = cτ 2 = cδfR T 2B (2.14)

When the target is moving, a Doppler shift fd is introduced, which will result

in an amplitude shift of the received signal. In turn, different frequency shifts

δf_U and δfD for the up- and down chirp are introduced. By conducting both

up and down chirp, the Doppler shift due to target velocity and range shift can be separated using (2.15) and (2.16). [6, 10.10.2]. By using the definition of the Doppler effect, the radial velocity of the target can then be calculated (2.12) [6, 10.10.1]

f_d = δfD −δfU

2 (2.15)

δf_R = δfD + δfU

2 (2.16)

Two important characteristics of a radar are range- and Doppler resolution. Range- and velocity (2.18) resolution determines the minimum required devia-tion between two targets at which they are separable. The range resoludevia-tion (2.17) of a CW-radar differs from that of a pulsed radar. The bandwidth of the transmit-ting antenna acts as the limitransmit-ting factor for the resolution. [2, 6.5]

∆_{R =} c

12 2 FMCW Radar

∆_{v =} λ

3

Interfaces for On-board

Communication

On the back end, a number of communication interfaces are used. SPI is utilized to communicate with the front end. Other relevant communications interface for this thesis is Universal Asynchronous Receiver/Transmitter (UART) and

Inter-Intergrated Communication (I2C).

This Chapter aims to review the basics of these interfaces, since the communi-cation with these are central to the design of the front end to PC interface.

3.1

SPI

SPI is a synchronous communication protocol initially developed by Motorola. The interface has become a de facto standard in the electronics industry. This makes SPI more flexible than, for example the USB protocol, which has an oblig-atory standard [7], that the SPI lacks. This makes the implementation of a SPI protocol more customizable, and might vary between electronic devices from dif-ferent suppliers.

Essentially the interface, as apparent by the naming, is a serial data trans-fer interface. This means that all data is transtrans-ferred sequentially between the communicating devices. Most common, is for the protocol to use four pins for communication between a master and a (or multiple) slaves.

One of these pins is the Serial Clock-pin, commonly referred to as SCK. This pin can be either pulled high or low, when inactive, depending of the require-ments of the communication. This level is referred to as clock polarity (CPOL). Another consideration that has to be taken into account, considering the timing of the SPI-protocol, is the clock phase (CPHA), which specifies on which clock edge the data is latched in by the devices.

On the master-side, there are the data pins MISO (Master-In, Slave-Out) and MOSI (Master-Out, Slave-In), which are connected to the Serial Data In/Out- (SDI

14 3 Interfaces for On-board Communication

and SDO) pins on the slave side. Since the SPI uses different pins to receive and send data, full-duplex communication is supported.

The last pin of the interface is the Chip Select (CS). A slave device is selected by activating it’s CS pin (which is usually active-low), therefore each slave requires a dedicated CS. [38]

Figure 3.1: SPI communication with CPOL=0 and CPHA rising edge

A simple example of the signal levels during SPI communication is displayed in Figure 3.1. The master initializes communication with a slave by activating the corresponding CS-pin. SCK leaves it’s idle state and data will be latched from MOSI on the active edge of the clock, starting with a start bit, and concluding each word with a stop bit. Usually data is latched out MSB first. In turn the selected slave starts to sample data at SDI when receiving the active edge of the clock, which has to be the same for both devices, otherwise this mismatch will lead to errors in the communication. In the same manner the slave, when it has transmission data ready, latch the data out on the SDO-pin.

For a MCU to recognize whether there is data to be sent or received, either in-terrupts can be used to indicate theses states, or checking to see if data is available at regular intervals (polling). [38]

3.2

I

C

Figure 3.2: I2C

The I2C protocol was invented by Philips in the 80’s to connect low-speed

devices.

Like the SPI protocol (Section 3.1), I2C transfers data sequentially and

syn-chronous between a master and one or multiple parallel slave-devices.

One difference between the I2C and SPI is that it utilizes only two pins per

device for the communication; the clock pin (SCL) and a Serial Data pin (SDA). These pins should be pulled high when inactive, and have to be either open collector- or drain. An unique address (usually 7-bits long) has to be written to a slave device for it to communicate with the master. Communication can only be half-duplex, as a result of the single data line used.

Communication is initialized by a start condition (SDA pulled low while SCK is high) and ended with a stop condition (SDA pulled high while SCK is high).

3.3 UART 15 Data is shifted out at SDA at the falling edge of SCK and latched in at the rising edge, thus data has to be stable while SCK is high and can only be allowed to change while it is low. The data line is seen as occupied between the start- and end commands. After the initial start command, an additional ’1’ might be sent to indicate start of another transaction to the slaves, without releasing the bus. Then the 7-bit address of the selected slave device is latched out from the master (MSB to LSB), followed by a bit that indicates whether reading or writing to the target device will take place. For each byte received by the slave it will answer with an

acknowledgement bit if it is ready to read the next byte. If no acknowledgement

bit is received by the master, it is an indication that there is no more data for the slave to read, and the master has to either supply a new start- or end command.

After the first acknowledgement-bit has been received by the master, it will continue to send out data in 8-bit packets, if write mode has been chosen. Al-ternatively receive data from the slave, if read has been chosen. When the slave answers the read request from the master, the communication works in the same way, except no address or read/write command has to be sent.

I2C can also be used in either polling- or interrupt mode. [39] [40]

3.3

UART

Unlike the previously mentioned communication interfaces in Section 3.1 and Section 3.2, UART communication is not an actual communication protocol, but a physical circuit. UART communication takes place between two devices only. It is based on the TL16C550 industry standard.

The UART-circuit shifts data (commonly bytes) in and out to enable a two-wire serial communication mode with a peripheral device. The RX-pin is used to receive data and is connected to the TX-pin of the other device, which transmits data. Hence full-duplex mode communication is made possible by using two separate lines for the communication. Upon reception of data, the UART circuit on the receiving side converts it back to parallel form. [8, 1.1]

UART is asynchronous, and the communicating devices need to share a prede-fined baud rate in order to read and write data correctly. This baud rate is equal to the devices communication rate, and is dependant on the input clock of the UART circuit. The baud rate generator provides the required value, utilizing a

clock-divider inside the UART circuitry. This divider is in the range 216−1 and

is calculated with the formula (3.1).

Oversampling in the UART is the process of sampling each sent bit multi-ple times, to compensate for errors in the transmission. For exammulti-ple: if x-bit oversampling is used, each bit is sampled x times, a counter is used to find the middle-point of the bit, the counter is then reset and counts to the end of the received bit. A majority vote of the sampled values will then take place to decide on the polarity of the received bit. Common oversampling rates are 8- or 16 bits. [8, 2.1]

Clock divider = U ART input clock f requency

16 3 Interfaces for On-board Communication

When data for transmission is ready, it is transferred to a shift register, the data is serialized and transmission begins by sending a start bit, which is a logic zero. This is because the RX/TX pins are pulled high when idle. Then the trans-mission of the serialized data is initialized, starting with LSB. A parity bit might be included after the data bits. This parity bit is set by the transmitting device to be ’0’ if the transmitted word contains an even number of 1s (even parity), or ’1’ if the parity is odd. Hence, the peripheral device, upon receiving a word, can utilize this parity bit to conclude whether or not a transmission error has occured. The transmission is ended by sending a stop bit (pulling the line high). Usually the communication is taking place using either interrupt- or polling mode. [8, 2.1, 2.5]

Figure 3.3 displays the signal timing on the RX-line of the receiving device, during the transmission of a 8-bit word, not including parity-bit.

Figure 3.3: UART RX

Most UARTs can utilize two additional pins for hardware flow control:

Re-quest To Send (RTS) and Clear To Send (CTS). The RTS-pin can be pulled low by

a device, when it is ready to transmit data. If the responding device is ready to receive, it will in turn re-assert its CTS-pin (which is connected to the RTS of the other device). This provides a hand-shaking capability to the communication. [8, 2.5]

A similar means of communication between ICs is the Universal Synchronous/

Asynchronous Receiver/Transmitter (USART). With USART it is possible to utilize

synchronous communication by using an extra clock pin, this enables the USART to operate at higher rates than the UART. [9]

3.3.1

USB

When connecting two USB units, one is acting as host (master) and the other as a device (slave). In this application, the PC will always act as a host while the back

end act as device. Whenever a device is connected to the host bus, an enumeration

follows where the device sends it’s descriptors. The descriptors are divided into the following categories:

• Device

• Configuration • Interface • Endpoint • String

3.3 UART 17 Each device has one device descriptor with parameters such as the vendor ID (VID), product ID (PID) and which USB revisions the device has targeted (full-/high-/super- speed). The VID/PID pair is used to identify the USB device so that the correct driver is chosen.

After the device descriptor follows a number of configuration descriptors. Multiple configurations can be utilized if the device runs in different power modes, but are not relevant for this thesis and thus a single configuration descriptor is implemented. The configuration also states how many interfaces the particular configuration has.

The interface descriptors then follow, which describes the function of a group of endpoints. A class code is used to distinguish interface functionalities such as

Human Interface Device (HID), Printer, Image etc. Multiple interface descriptors

are useful when a device has multiple functional blocks that should be separated. The endpoints are defined in the endpoint descriptors. Each endpoint has a parent interface, a type, direction and address. There are different endpoint types but this thesis uses bulk endpoints exclusively. The directions are host centric so a bulk in endpoint defined by a device, streams data from the device to the host.

Finally the string descriptors contains human readable strings that are con-nected to different information such as the manufacturer and product name. [7] A device with two or more interfaces and multiple functionalities can enumerate as two devices on the host, which assigns different drivers. This is called a com-posite device and is defined by using the Interface Association Descriptor (IAD). The IAD comes before the interface descriptions and specifies how many inter-faces it includes and sets it’s functional class, subclass and protocol to that of the first interface included.

The composite device then enumerates as three separate devices. The first is the composite device itself which has no intrinsic functionality, with VID/PID as in the device descriptor. Then the two interfaces enumerates as stand alone devices and can be identified with the additional interface number (MI). [7]

4

Front End

_overview

The design of the back end, which is the subject of this thesis, relies heavily on the front end, for which it is designed to interface. The front end is a 79 GHz

Ultra-Wide Band (UWB) radar platform prototype, developed by Acreo Swedish

ICT.

This Chapter will give a brief overview of the architecture, interface, param-eters and functionality of the front end, to provide a theoretical basis on the re-quirements of the back end. For the confidential chip-set, the largest focus will be on their serial communication protocols, since the use of these are a central part of the back end-design considerations.

4.1

Front end

_{design specifications}

The goal of the front end prototype was to reach a 5 GHz bandwidth, (between 76-81 GHz), and range separation down to approximately 5 cm. An improved range in the radar resolution, compared to already existing radar solutions was also strived for.

For DSP of the radar signals to take place, the analogue output signals from the receivers need to be digitalized using ADCs, with a sample rate high enough to handle the highest instantaneous IF-bandwidth from the receiver.

The front end was designed to replace an earlier prototype developed by a third party company. This predecessor utilized the same chip-set, but had issues with self-resonating inductors and strong low frequency tones.

Here are some requirements and specifications for the earlier board listed, which the new prototype strived to achieve or exceed:

• CW bandwidth of 500 MHz.

20 4 Front End overview

• An IF-bandwidth of up to 10 MHz.

• A high-pass filter cut-off frequency of 10 kHz.

• CW beat frequency of 33 Hz, which is well below the cut-off frequency • CW pulse duration of 10 ms.

• Object separation down to approximately 10 cm. • CW-waveforms, in addition to chirps.

Also the back end has a predecessor made by the other company. [10]

4.2

Architecture overview

The radar chip-set, which is the core of the front end consists of the following ICs: • Transmitter:

A single transmitter-chip with three output channels provides the local

os-cillator (LO) for the receiver- and power amplifiers chips.

• Receivers:

Two receivers, which together outputs eight differential IF- channels. • Power amplifiers:

Two amplifiers, with two output-channels each. They together power the four channels used for the transmission antennas.

• Radar controller:

The radar controller serves to simplify control and configuration of the transmission side of the radar chip-set. This is done by mirroring the reg-isters of the connected transmitter chip. Also generates the ramp of the radar.

In addition to the radar chip-set there are a few other central components on the board:

• Analogue IF-filter:

The analogue IF-signals are filtered before beginning the processing through the ADCs. This keeps the input levels to the ADC within its processing range and provides anti-aliasing capabilities.

• ADCs:

Two ADCs with four input channels each, connected to the IF signals on the receiver outputs. These signals are digitalized in an 12-bit conversion. • PSU:

The PSU for the front end board contains linear LDOs (Low-dropout voltage

4.3 Simulated performance 21 • Level shifter:

A bidirectional level-shifter is used to provide a voltage signal level of 1.8 V from the 3.3 V SPI-channel.

• Sensor:

Measures temperature and power dissipation.

The components listed basically provides the same functionality as the system described in Figure 2.1. [10]

4.3

Simulated performance

To verify the high-frequency design and functionality of the radar antennas, sim-ulations were conducted by Acreo Swedish ICT.

Simulation of a single antenna element shows a bandwidth up to 7 GHz with return loss below -10 dB for the required frequency range.

The radar antennas consists of a number of different formations of these an-tenna elements. These groups had been simulated separately.

The Transmitter (TX) and Receiver (RX) antennas are divided into differently distributed groups, each connected to a corresponding channel of the radar chip-set.

The required bandwidth (76-81 GHz), with a return loss better than -10 dB is nearly fulfilled by all antenna groupings separately. The beamwidth also ap-pears to be within reasonable limits from the specifications for both RX- and TX elements. Side lobe levels are reasonable during the largest part of the frequency span. [10]

4.4

Back end

_{/front end interface}

The front end is to be connected with the back end with a SAMTECH

QTH-060-04-L-D-A connector. The main purpose of the back end is to enable DSP of the

digitalized signals from the front end: either on-board or by streaming the raw data directly to a PC.

The back end is also purposed to power the prototype (as mentioned in Sec-tion 4.2) and configure the devices on the front end. [10]

4.4.1

PSU

To power the front end’s PSU, the back end-board needs to provide a 4 V power rail. It has to be designed to meet the maximum power- and current consumption of the front end which are 11.26 W respectively 4.055 A. The use of linear regulators provides voltage levels without switching noise. Two kinds of LDOs are used in the PSU: providing maximum load currents of 1 A and 2 A.

For the PSU to become active, the enable-pins of the regulators needs to be taken high. The RX_EN and TX_EN signal traces that are connected to the

22 4 Front End overview

SAMTECH-connector fills this purpose by allowing the back end to control these

pins using GPIOs. When held high, RX_EN enables the ADCs and receivers.

TX_EN enables the operation of the transmitters, power amplifiers and the

sen-sor. The radar controller chip is powered by a separate 5 V net that also needs to be provided by the back end.

Each regulator has a power good-pin connected to the header, with the inten-tion of checking their power status. [10]

4.4.2

Radar controller and transmitters

The transmitter chip contains a mixer circuitry, including an integrated power amplifier on each output. These outputs then provides the differential LO-signals for the receiver side.

As mentioned in Section 4.2, the register configuration of the transmitters are executed through the radar controller through mirrored registers. The commu-nication between these two devices uses the serial interface in combination with a protocol handler, which makes the transmitter registers directly configurable through the radar controller.

The radar controller also has an internal ramp-memory, in which parameters for the frequency ramping can be stored.

Two operation modes are available: configuration and run. The device enters into

configuration-mode upon reset. This mode enables direct configuration of the

registers and ramp-memory access, but no firmware functions can be utilized. To switch between the modes a global register bit has to be toggled.

Run enables execution of a number of firmware functions available in the

device, which further simplifies the register configuration by limiting the number of registers to be accessed through SPI.

The contents of the ramp-memory and the configuration registers can be read in both modes. Some registers might be written during run mode.

The IC has a reset-pin, which is connected to the front end. By pulling this low the configurable registers of the device returns to their reset values. Hence this pin, which is connected to the back end should be held high during- and after register configuration.

The registers and ramp-memory configuration is done using a four-wire slave SPI interface. Communication is utilized with 32-bit words. MSB is a command-bit. When pulled high, write mode is initiated, otherwise read mode is enabled. The command-bit is followed by a 15-bit address which is used to target a register in the device. The last two bytes (the data), are ignored in read mode.

The device latches in the received data on the falling edge of SCLK. Data is read at the rising edge. CPOL for the device is by default low, and a maximum SCLK frequency of 40 MHz can be utilized for the communication.

Even though the SPI-communication is full duplex, reading from the registers takes two communication cycles. The answer received by the master during a cycle will be the answer corresponding to an earlier command. When sending a

4.4 Back end/front end interface 23 command a readback will first be sent, followed by the answer from the target register. It is possible to write a new command during the second cycle.

Executing a write-command is similar to the read-command, with the differ-ence being that the whole word received by the master during the second cycle is an echo of the transmitted.

In addition to a serial communication interface, the radar controller-chip shares two GPIOs with the front end. [10]

4.4.3

Power amplifiers

The power amplifiers take a differential LO-input and output two differential RF (radio frequency) signals. The power of the output signals for each channel can be adjusted by configuring the device’s serial interface.

The configuration registers of the amplifiers are programmed using 16-bit words. The first two bits make up the command. Three different commands are available: write-verify, read or No Operation (NOP). The command-bits are followed by a 6-bit address and lastly 8-bits of data. Data is latched in on the SDI pin at the falling edge of the SCK and out at rising edge, which has a low polarity. The maximum frequency of SCK is 50 MHz.

The read mode ignores the received data bits, and echoes the command-bits, followed by read address and the requested data during the second communica-tion cycle.

Write-verify works in the same manner as a read command, with the exception

of the received data bits during the second cycle being an echo of the written data. The power amplifers have an additional communication-mode apart from read and write. This is the NOP-mode, in which the bits shifted into the device during the first cycle are simply shifted back out during the second. Using this mode is a simple way of verifying the functionality of the SPI-communication between the amplifier and a master.

In addition to the serial interface of the power amplifiers, four additional pins are wired to the connector. These pins can be utilized to directly turn on/off- and invert the phase of the amplifiers. [10]

4.4.4

Receivers

The receiver IC is provided a differential LO signal from the transmitter chip. It also receives four differential RF input signals, which are mixed with the LO signal and thereby outputs four differential IF signals.

The serial interface of the receiver is almost identical to that of the power amplifier discussed in Section 4.4.3, in regards to phase, polarity, enable signal, available commands, word length- and sequence. In addition, there is one ex-tra communication command-mode: chip-ID read-out. This mode is selected by setting the two MSBs low. In this mode, the 48-bit ID of the chip can be read. The ID is divided into three sections, and if the correct address for this section is sent, the answer received by the master in the second will be the targeted 16-bit ID-section.

24 4 Front End overview

The receiver has a clock signal input called DIGTST, which is connected to the

back end. It can provide the clocking for an internal test signal generator, that can

be used to test the mixer functionality. [10]

4.4.5

ADCs and level-shifter

The two ADCs have four input channels each, connected to the differential IF signals on the receiver outputs. These signals pass through a low noise amplifier, equalizer and a gain amplifier before the ADC 12-bit conversion takes place at 25 Msps. The digitized output is then put through a 4:1 multiplexer for time-multiplexing.

For normal communication with the ADCs, the level-shifters Operation

En-able-pin (OE) needs to be initially held low and then activated. This is achieved

by OE being connected to the output of the LDO that provides the voltage for the transmitter ICs. Hence, OE is initially low but goes high after the PSU is activated.

Upon power-up, all registers of the ADC must be reset to ensure proper oper-ation. This can be done by applying a pulse on the reset-pin. This pin is wired to the connector, to enable configuration from the front end.

The serial interface of the ADC communicates using 24-bit words. The first part of the word is an 8-bit address, followed by 16-bits of data.

Data is shifted in on the SI-pin at the rising edge of SCLK and out at SO on the falling edge. Multiple words can be received during a low CS-pulse, and are kept track of using an internal 24-bit counter. Excess bits are ignored. The maximum SCLK-rate is 20 MHz.

The device is in the write-mode per default. Writing to a register takes one cycle and no read-back of the written data is provided to the connected master.

To change to read mode, a read enable-bit has to be set in the register. When this is done, and an 8-bit address has been provided to the chip, the required data will be shifted out on SO during the last two bytes of the cycle.

The chip has an active-high standby-pin, which is connected to the back end. When the standby is activated, the ADC will enter into a power-down mode, in which all functional blocks in the device, except the ADC reference circuitry are powered down. The serial interface is available during the power-down mode. [10]

4.4.6

Sensor

The sensor IC contains a SPI-interface and ADC-conversion for its sensor input. It can be used for temperature and power measurements.

In contrary, to the other devices used on the front end, only two registers are available in the device: a conversion- and a configuration register. The conversion register contains the result from concluded conversions (ADC sensor data), and can only be read by the serial interface.

In the configuration register, bits can be toggled to switch operation- and sen-sor modes, activate conversions-, integrated devices or configure parameters.

4.4 Back end/front end interface 25 The device can work in either continuous- or single-shot mode. The single-shot mode is active per default upon power-up, and modes are switched by toggling a

mode select bit in the devices configuration register. During single-shot operation

the device is in a power-down state, with the serial interface remaining active. Conversions in this mode are made by setting a single-shot bit in the configuration register. This causes the device to temporarily wake up from its down-powered state, upon which the bit is reset and a conversion is started. Upon finishing the conversion the device re-enters power-down mode.

During the continuous mode new conversions are continuously executed. When the device is started, the bits in the registers are automatically reset. The serial interface of the device uses 16-data bit words for communication, which are latched out at the rising- and in at the falling edge of SCK.

Per default the device is in 16-bit conversion mode. During this operation no read-back from the configuration register takes place. The output from the device in this mode is the conversion results. The configuration register is only updated by the received data if two operational bits of the data are set to enable this action.

In the 32-bit transmission mode, read-back of the configuration register takes place during the second half of the transmission cycle. [10]

5

Back End Design

5.1

Design considerations

The initial step of the design phase was to understand the back end requirements based on the front end. The core demands for the hardware are controlling the

front end, providing sufficient bandwidth for the radar data transfer, and to

pro-vide two power rails.

Since the data rate, corresponding to 1.2 Gbps for each of the two ADCs on the front end, are to be streamed to a PC, a natural choice of interface is USB 3.0 because of it’s availability and a data rate of 5 Gbps. The real maximum throughput can more realistically be estimated at 3.2 Gbps, which is due to the 8b/10b encoding and other factors including protocol overhead. [7, 4.4.11 p.4-19].

To set up the front end’s chips, two SPI-channels are used, together with some op-tional GPIOs. This demands that the solution supports at least two SPI-channels. The maximum current ratings for both power rails were estimated by sum-ming up the power requirements for each internal rail on the front end. The summed up maximum delivered power gives a pessimistic current estimate that can be used to dimension the back end’s regulators. The 4 V rail requires at most 4.055 A, while the 5 V rail only consumes about 100mA.

To sum up the requirements with some other prerequisites the following should be supported by the back end.

• USB 3.0 or greater

• Two SPI channels with enough GPIOs for every CS and additional GPIOs required by front end.

• Two dedicated power supplies, 4 V @ 4 A and 5 V @ 1 A

28 5 Back End Design

• Preferably include FPGA for on board signal processing

For some calculations in this Chapter, 4 A is used for the 4 V net, instead of the maximum value of 4.055 A. The reason for this is that the PCB design is based on earlier power- and current consumption estimates received from Acreo Swedish ICT, before the design report [10] for their front end was available. When this report was received, the design of the back end was already completed and sent for manufacturing. However, the maximum estimated from Acreo Swedish ICT is not far above 4 A, hence these calculations are still deemed to be applicable.

5.2

Architecture

A considered architecture alternative would be a development board for an FPGA device. Acreo Swedish ICT’s partners had previously used a development board from Altera featuring a Cyclone V FPGA for this purpose.

Altera offers six device families of the Cyclone V FPGA, three of those are regular FPGAs and the other three are System on Chips (SoC)s. Cyclone V SoC contains an integrated hard processor system meant to simplify the architecture of FPGA-applications [11].

For the reasons listed, it would appear that the simplest solution would be to use a development board with a SoC chip for the project. An issue with this approach is that there are no Cyclone V boards which come ready with support for USB 3.0. To implement USB 3.0 intellectual property cores (IP-cores) would have to be purchased and used, as well as physically adding an USB 3.0 breakout board with a connector via the development boards IO-pins. Alternatively, there are third-party solutions available [12], [41], [13].

For implementation of USB 3.0 and not adding too much complexity and cost, a MCU with USB 3.0 support was decided to be preferred. As the internal pro-cessor did not readily make USB 3.0 communication available, the development board solution was abandoned for a customized PCB, which led to an early draft which is close to the final architecture. (Figure 5.1).

The considerations resulted in a search for suitable components, and the fol-lowing were chosen for the core architecture:

• A Cyclone V FPGA for on-board signal processing • A MCU for USB 3.0 interfacing

• A MCU with two separate SPI-busses and a large number ofGPIOs for inter-facing with the front end

The MCU chosen for the USB interface was the EZ-USB FX3 from Cypress [14], which is a USB 3.0 peripheral controller. A STM32L073 device [15] was chosen for the interfacing to the front end because of its multiple SPI channels and relative low complexity.

At the design stage it was unclear how much processing power would be needed for- and whether or not time would be sufficient to implement DSP on

5.2 Architecture 29

Figure 5.1: System Overview First Draft

the FPGA. Therefore, a Cyclone V GX device was chosen. The GX family is the medium of three Cyclone V variants, in terms of both cost, number of gates, power consumption and transceiver speed. [16]

After some considerations, the SRAM-bank included in the draft in Figure 5.1 was left out. This was mainly because, as stated, the requirements of the on-board DSP was not completely clear, as well as second in priority to the data streaming. Hence the internal memory capabilities of the Cyclone V CX was deemed to be sufficient to store a few hundred samples, if needed for flow control.

A more detailed overview of the back end and the interface with the front end are shown in Figure 5.2. The blocks are positioned approximately as on the first revision of the PCB layout (Figure 5.1) to make it easy to follow the de-sign steps. CYUSB3014 is the Cypress FX3 MCU, which is connected to the M24M02 Electrically Erasable Programmable Read-Only Memory (EEPROM). Be-low is the FPGA (5VGFXC7C7F23) with connected Quad Serial Configuration

De-vice or EPCQ (EPCQ128), and left of the FPGA is the front end controller (STM32).

30 5 Back End Design

Back End

Front End Samtec QTH 120 pin connector

STM32L073 CYUSB3014-BZXI Cypress FX3S PSU AP1122DL-13 LP3855EMP-3.3/NOPB LP3855EMP-3.3/NOPB ADP5050ACPZ-R7 MIC37502WU MCP1826S-5002E/DB 5CGXFC7C7F23C8N Altera Cyclone V 4 V 4 A

32-bit FIFO interface w control signals STM_FPGA_UART µUSB 3.0 type B U S B 3 .0 PWR 5.5 V 8 A 4mm STM_FX3_UART S P I1 S P I2 G P IO FX_1V2 FX_3V3 STM_3V3 CORE_1V1 VCCIO_3V3 VCCIO_1V8 VCC_2V5 STM_3V3 P A C O N [4 ..1 ] 5 V 1 A D a ta [4 .. 0 ] EPCQ128SI16N Serial Configuration D C L K M24M02-DRMN6TP EEPROM I2 C 19.2 MHz 8 MHz 100 MHz D 0 [1 5 ..0 ] D 0 C L K + D 0 S Y N C D 1 [1 5 ..0 ] D 1 _ C L K + D 1 _ S Y N C 0 D IG T S T

Figure 5.2: Detailed block diagram

5.3

Power Distribution

The power rails for the Cyclone V are supplied by multiple low noise switching regulators on one chip. Power supplies for the MCUs, and those required by the

front end were all implemented by using linear LDO regulators to improve the

performance and minimize switching noise on the board.

5.3.1

Altera Cyclone V power supply

The FPGA needs a 1.1 V power supply for its core, and an additional auxiliary voltage supply of 2.5 V. These supplies need to have a maximum of ±30 mV respectively ±5% tolerance. The power rails can be shared by the transceiver power pins using ferrite beads as isolation filters.

The two rails need to be powered by low noise regulators. For the PSU the

line regulation needs to be below 0.4% and the load regulation to be below 1.2%

for. Line regulation is the ability to maintain a steady output voltage despite input fluctuations. Load regulation is a measure of the deviation in voltage due to load changes. [17]

Since the signals from the ADC on the front end have a level of 1.8 V and the IO-level of the FX3 MCU from Cypress is 3.3 V, both of those levels were also needed for the FPGA’s IO-supplies.

5.3 Power Distribution 31 Power estimations for the FPGA were conducted with the help of PowerPlay Early

Power Estimator which is a Microsoft Excel Macro provided by Altera. [18] With

approximately 85% of on-chip memory and logical elements enabled, the esti-mated power consumption for the FPGA are shown in Figure 5.3.

Figure 5.3:PowerPlay Early Power Estimator

As these are the maximum ratings, and enabled logic elements and IOs are de-fined with a high 50% toggle rate at 100 MHz, the real application will probably consume somewhat less core power, even if higher internal frequencies are used. The rails have therefore been given the following current requirements with the corresponding names:

• 1.1 V 4 A, VCC_CORE • 2.5 V 1 A, VCC_2V5 • 3.3 V 1 A, VCCIO_3V3 • 1.8 V 1 A, VCCIO_1V8

Analog Devices provides an integrated power solution compatible with the de-mands on the FPGA design. The ADP5050 [19] is a 5-channel buck-regulator, with four switched channels and one LDO.

The ADP505x Buck Regulator Design Tool is a Microsoft Excel macro that is provided by Analog Devices. The macro can be used to generate a proposed schematic and Bill of Materials (BOM) based on the device chosen, required