Low Power and Area Efficient Semi-Digital PLL Architecture for High Brandwidth Applications

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Institutionen för systemteknik

Department of Electrical Engineering

Examensarbete

LOW POWER AND AREA EFFICIENT

SEMI-DIGITAL PLL ARCHITECTURE FOR

HIGH BANDWIDTH APPLICATIONS

Examensarbete utfört i Elektroniksystem vid Tekniska högskolan vid Linköpings universitet

av

Vivek Elangovan LiTH-ISY-EX--11/4439--SE

Linköping 2011

Department of Electrical Engineering Linköpings tekniska högskola

Linköpings universitet Linköpings universitet

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LOW POWER AND AREA EFFICIENT

SEMI-DIGITAL PLL ARCHITECTURE FOR

HIGH BANDWIDTH APPLICATIONS

Examensarbete utfört i Elektroniksystem

vid Tekniska högskolan i Linköping

av

Vivek Elangovan LiTH-ISY-EX--11/4439--SE

Handledare: Dr. J Jacob Wikner

isy, Linköpings universitet

Markus Dietl & Puneet Sareen

Texas Instruments

Examinator: Dr. J Jacob Wikner

isy, Linköpings universitet

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Avdelning, Institution

Division, Department

Department of Electrical Engineering Department of Electrical Engineering Linköpings universitet

SE-581 83 Linköping, Sweden

Datum Date 2011-09-23 Språk Language Svenska/Swedish Engelska/English Rapporttyp Report category Licentiatavhandling Examensarbete C-uppsats D-uppsats Övrig rapport

URL för elektronisk version http://www.es.isy.liu.se http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-71029 ISBN — ISRN LiTH-ISY-EX--11/4439--SE

Serietitel och serienummer

Title of series, numbering

ISSN

—

Titel

Title

Svensk titel

LOW POWER AND AREA EFFICIENT SEMI-DIGITAL PLL ARCHITEC-TURE FOR HIGH BANDWIDTH APPLICATIONS

Författare

Author

Vivek Elangovan

Sammanfattning

Abstract

The main scope of this thesis is to implement a new architecture of a high bandwidth phase-locked loop (PLL) with a large operating frequency range from 100 MHz to 1 GHz in a 150 nm CMOS process. As PLL is the time-discrete system, the new architecture is mathematically modelled in the z-domain. The charge pump provides a proportionally damped signal, which is unlikely as a re-sistive or capacitive damping used in the conventional charge pump. The new damping results in a less update jitter and less peaking to achieve the lock fre-quency and fast locking time of the PLL. The new semi-digital PLL architecture uses N storage cells. The N storage cells is used to store the oscillator tuning information digitally and also enables analogue tuning of the voltage controlled oscillator (VCO). The storage cells outputs are also used for the process voltage temperature compensation. The phase-frequency detector (PFD) and VCO are implemented like a conventional PLL. The bandwidth achieved is 1/4th of the PFD update frequency for all over the operating range from 100 MHz to 1 GHz. The simulation results are also verified with the mathematical modelling. The new architecture also consumes less power and area compared to the conventional PLL.

Nyckelord

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Abstract

The main scope of this thesis is to implement a new architecture of a high band-width phase-locked loop (PLL) with a large operating frequency range from 100 MHz to 1 GHz in a 150 nm CMOS process. As PLL is the time-discrete system, the new architecture is mathematically modelled in the z-domain. The charge pump provides a proportionally damped signal, which is unlikely as a resistive or capac-itive damping used in the conventional charge pump. The new damping results in a less update jitter and less peaking to achieve the lock frequency and fast locking time of the PLL. The new semi-digital PLL architecture uses N storage cells. The

N storage cells is used to store the oscillator tuning information digitally and also

enables analogue tuning of the voltage controlled oscillator (VCO). The storage cells outputs are also used for the process voltage temperature compensation. The phase-frequency detector (PFD) and VCO are implemented like a conventional PLL. The bandwidth achieved is 1/4th of the PFD update frequency for all over the operating range from 100 MHz to 1 GHz. The simulation results are also ver-ified with the mathematical modelling. The new architecture also consumes less power and area compared to the conventional PLL.

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Acknowledgments

At first, I would like to thank Texas Instruments for providing me an interest-ing topic for Master Thesis with good technical support from my supervisors Mr. Markus Dietl and Mr. Puneet Sareen. And then, I would like to thank my Pro-fessor Dr. J Jacob Wikner at the Department of Electronics System in Linköping University, for being my academic supervisor and examiner of the Master Thesis. I also like to thank my friends for their support.

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Background Theory

The phase-locked loop (PLL) [5], [6] generates the well-timed on-chip clocks for various applications such as clock and data recovery, microprocessor clock gen-eration and frequency synthesizer. The basic concept of the phase locking has remained the same, since its invention in the 1930’s. However, the design and the implementation of the PLL continue to be challenging as the design requirements of a PLL system such as clock timing uncertainty, power consumption and area become more stringent. A phase-locked loop (PLL) is a control system which gen-erates the signal, which is in phase and frequency with the input reference signal. The frequency generated from the PLL will be same as the input frequency or it is N times higher than the input frequency. The following section describes the PLL building blocks and its operation. The new PLL architecture is also described briefly.

1.1 Conventional PLL architecture

The PLL consists of the phase-frequency detector, the charge pump, the loop filter, the voltage controlled oscillator (VCO) and the divider. The conventional PLL architecture is shown in Figure 1.1. The block 1/s represents the integration. The phase of the signal can be obtained by integrating its frequency. The following section explains each block of PLL.

1.1.1 Phase-Frequency Detector

The phase-frequency detector (PFD) [4] compares the rising edge of the reference signal, φref to the feedback signal, φout and gives the difference as a phase

dif-ference, ∆t. The phase difference depends upon the lag or lead of the feedback signal with the reference input. If it is lag, it generates an UP pulse and if it is lead means, it generates a DOWN pulse. The conversion gain of the PFD is denoted by

Kd. The operation of the PFD is shown for two cases: (a) the two input signals

have the same frequency, and (b) one input has higher frequency than another input in Figure 1.2.

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8 Background Theory

Figure 1.1. Conventional PLL architecture

1.1.2 Charge Pump

Based on the phase difference from the phase-frequency detector, the charge pump [4] pumps in or out the current in the loop filter. During the UP pulse, the charge pump charges the capacitor in the loop filter and during DOWN pulse, vice versa.

1.1.3 Loop Filter

The loop filter converts the digital output of the phase-frequency detector to the DC control voltage, Vctrl for the VCO. The loop filter plays a main role for the

PLL bandwidth. The filter can be active or passive. It can be any order based on the PLL application.

1.1.4 VCO

The voltage controlled oscillator is the heart of the PLL. With a zero control voltage, the VCO generates a free running frequency, fo. The gain of the VCO is

denoted as Ko. If the control voltage, Vctrl is high, the frequency increases and

if the control voltage is low, the frequency decreases. Once, the PLL locks, the output frequency is constant. The VCO can be tuned based on the control voltage. The function of the VCO can be expressed as.

fout= f0+ (Ko· Vctrl) (1.1)

Hence, the frequency change of the VCO depends on the change of the control voltage.

1.1.5 Divider

If the output of the VCO is higher than the reference frequency, then it must be divided by N times and is fed back as one of the input to the phase detector. If the division ratio is 1, then the PLL tracks the input frequency and acts as a buffer.

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1.2 PLL operation 9

Figure 1.2. PFD operation: (a) fref=fCLK and (b) fref > fCLK

1.2 PLL operation

The PLL [6] is basically a feedback control system that controls the phase of a voltage controlled oscillator (VCO). The input reference signal is applied to one input of the phase-frequency detector. The other input is connected to the output of a divide by N counter. Normally, the frequency of both signals will be same, when the PLL is locked. The output of the phase-frequency detector is a pulse proportional to the phase difference between the two inputs. This signal is applied to the loop filter. It is the loop filter that determines the dynamic characteristics of the PLL. The filtered signal controls the oscillator. Note that the output of the VCO is at a frequency that is N times frequency of the reference input. The frequency range by which the PLL will accept and lock on is called the capture range. Once the PLL is locked and tracking a signal, the range of frequencies that the PLL will follow is called the tracking range. The loop filter also determines how fast the signal frequency can change and still maintains lock. This maximises the slewing rate.

1.3 New PLL architecture

In the conventional PLL architecture, there is a big capacitor in the loop filter, which cannot be integrated. In the new architecture, this big capacitor is divided into N storage cells, which has the two advantages.

1. The tuning information can be stored in the storage cells, when the cell is not active.

2. Analogue tuning can be implemented, when the cell is active.

In the conventional PLL architecture, the damping is usually achieved using ei-ther a resistor or a capacitor. The charge pump in the new PLL architecture provides a new active proportional damping to the VCO, which results in a very high damping factor and less peaking to achieve the right frequency to lock. The

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10 Background Theory

REFCUR block mirrors the current to the N storage cells based on the outputs from the PFD. The other blocks of the PLL like, the phase-frequency Detector, the divider, and the VCO are implemented as conventional ones. The divider is used in low bandwidth PLL applications. Here, the main focus is to design a high bandwidth PLL. So, the divide ratio is 1 or no divider is implemented. The new PLL architecture is shown in Figure 1.3.

In the new architecture [1], [2], the phase-frequency detector produces four

out-Figure 1.3. New PLL architecture

puts. The UP and DOWN are the same signals as in the conventional PFD. The UPB and DOWNB are just the inversion of UP and DOWN. All the four signals are given to the charge pump and the REFCUR. Additionally, the reference CLK and feedback signal is also connected to the charge pump. This is to ensure that when both the signals are zero, the voltage at the capacitor is pulled back to

V dd/2 (Active Damping). Depending on the DOWN and UP pulse, the charge

pump pumps current to the capacitor. The output of charge pump, prop is the proportional damped signal given to one input of VCO. The other input to the VCO is from the N storage cells, B < 1 : N >.

The signal INIT is to reset all the node voltages in the PFD to zero and is also given to N storage cells, to initialise all the capacitors to Vdd. Based on the UP and DOWN pulse from the PFD, the capacitor in the storage cells starts discharg-ing or chargdischarg-ing one by one. This leads to either filldischarg-ing 0’s or 1’s in the storage cell one by one. Based on the filling, the frequency of the VCO gets increased or decreased. This helps in frequency tuning of the VCO.

Thus, there will be two VCO gains respective to its two control voltages, Vctrl.

One is the proportional gain, Kp from the output of charge pump and the other

is the step gain, Ko being the frequency difference of one more storage cell being

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1.3 New PLL architecture 11

architecture is implemented for an operating range of 100 MHz to 1 GHz with a PLL bandwidth of (1/4)thof input frequency. The mathematical modelling of the new architecture is performed in z-domain, since PLL is a time discrete system. The results of the simulation are also matched with the mathematical modelling of the new architecture.

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Chapter 2

Mathematical Modelling of

the PLL

In this chapter, the conventional PLL is modelled using the z-domain. It is then modified to the new PLL architecture. Generally, the PLL is modelled using the s-domain. The s-domain modelling updates the information continuously for all the time, which is useful for a continuous system. Since, the PLL is a time-discrete system; each block of PLL can be accurately modelled in the z-domain. The z-domain modelling updates the information only at the edges of the signal. For example, in a PLL, we need information only at the rising edge of the reference clock i.e., 0, 2π, 4π, 6π,...., 2nπ. The model includes frequency and phase of the signals, thus reflects both, frequency and phase behaviour of the PLL.

2.1 Z-Domain model of a conventional PLL

The conventional architecture of the PLL consists of the phase-frequency detector, the charge pump, the loop filter, the voltage controlled oscillator and the frequency Divider. Each component of the PLL is described by its transfer function to obtain an overall input-output behaviour for the frequency and phase domain.

2.1.1 Z-Domain model of frequency to phase transfer

The frequency to phase transfer converts frequency information into phase infor-mation evaluated at discrete time stamps, Tref. The input to the frequency to

phase converter is a signal with frequency f(t) and time period, Tref. The phase

of the signal can be obtained by integrating the frequency of the signal and it is given as.

Φ(t) = Z

f(t) dt (2.1)

The integration in the z-domain is the accumulation of Tref with respect to

pre-vious Tref. So, at the ithtime period, the time is sum of all the periods before i

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14 Mathematical Modelling of the PLL

and it is given as.

t(i) =

i

X

j=0

Tj (2.2)

This can be implemented in the z-domain with an adder and a delay element as the following equation and it is also shown in the Figure 2.1, where z(s) = exp (−s · Tref).

t(i) = Ti+ t(i-1) (2.3)

Figure 2.1. Z-Domain model of frequency to phase transfer

2.1.2 Z-Domain model of phase-frequency detector

The PFD detects the phase difference between the feedback signal and the refer-ence signal. Using the frequency to phase transfer, the phases are applied as an input to the PFD. So, the PFD can be modelled as a subtractor in the z-domain and it is shown in the Figure 2.2.

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2.1 Z-Domain model of a conventional PLL 15

2.1.3 Z-Domain model of capacitor and resistor in loop filter

The PFD generates the phase difference ∆t as a pulse, and the charge pump pumps the current during the time period ∆t. This current is deposited as a charge of size, Q(i) in the capacitor.

Q(i) = Icp· ∆t (2.4)

The same size of charge is deposited to the capacitor for each update pulse from the PFD. So, after the n update pulse of ∆t, the total charge deposited is given as. Q(n) = n X i=0 Icp· ∆t (2.5)

The voltage across the capacitor is V = Q/C. So, the capacitor translates the charge into voltage, Ustored. Hence, the capacitor along with the charge pump can

be modelled in the z-domain is shown in Figure 2.3.

U(n) = n X i=0 Icp· ∆t C (2.6)

In case of a damping resistor, during the pulse ∆t, the charge pump current causes

Figure 2.3. Z-Domain model of capacitor and charge pump

a voltage drop across it with a size of V(i) = R·Icp . In the rest of update period

Tupdate, no voltage drop is produced across the damping resistor. So, the average

voltage drop is given as.

Uprop(i) =

∆ti

Tupdate

· R · Icp (2.7)

Hence, the resistor along with charge pump can be modelled in the z-domain as shown in the Figure 2.4.

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Figure 2.4. Z-Domain model of resistor and charge pump

2.1.4 Z-Domain model of VCO

The transfer function of voltage controlled oscillator is Fout = K · Vctrl. The time

period is given by 1/Fout, Tout = 1/(K · Vctrl). The frequency range of the VCO

must be linear with respect to the control voltage. For linearization, the time Tout

can be written as.

T = Tout|ctrl0+ dTout dVctrl _ctrl0 · (Vctrl− Vctrl0) (2.8) Differentiate Tout w.r.t Vctrl. δTout δVctrl = −1 K · (Vctrl)2 (2.9) Hence, the VCO can be modelled in the z-domain based on above equation.

2.1.5 Z-Domain model of conventional PLL

Each component of the PLL is modelled in the z-domain. The frequency divider is implemented as a multiplier in the time domain. The complete z-domain model of the PLL is shown in the Figure 2.5. The block 1/z(s) before the charge pump, Icp

is to ensure the one time period delay between the feedback signal and reference CLK.

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2.2 Z-Domain model of new PLL architecture 17

Figure 2.5. Z-Domain model of conventional PLL

2.2 Z-Domain model of new PLL architecture

In the new PLL architecture [2], the capacitor in the loop filter is divided into many storage cells. Each storage cell is used for tuning the oscillator. Once, the capacitor in the storage cell starts to discharge/charge below/above V dd/2, it activates the next storage cell. When, the capacitor discharges, it increases the frequency of the VCO and when the capacitor charges, it decreases the frequency of the VCO. The step change from one storage cell to another cell is given as dt. This makes a change in frequency by a step in the oscillator. The total control voltage to the oscillator is given as.

Ucontrol(n) = Ustored(n) + Uprop(n) (2.10)

The frequency change in the oscillator can be written as a gain Ko, times the

Ucontrol(n).

f(n) = Ko· Ucontrol(n) (2.11)

The Uprop(n) is the voltage drop across the periodically charged capacitor. Uprop(n)

should be multiplied by the VCO gain, Kpropto change the frequency of the VCO.

Ustored(n) is obtained from both the active and non-active storage cells. At a

par-ticular time, two consecutive storage cells X and X+1 are active. Hence, it is given as Kstep positive during the UP pulse and negative during the DOWN pulse.

U< x >(n) = n X activei=0 Icp· ∆ti C (2.12) U< x + 1 >(n) = n X activei=0 Icp· ∆ti C (2.13)

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The storage cell next to the active cell gets activated only when the current storage cell discharges below V dd/2. Ustored(n) should be multiplied by the VCO gain,

Kstep to change the frequency of the VCO. Hence, the frequency change in the

oscillator is given as.

f(n) = Kprop· Uprop(n) + non−active(B<i>=0) X i Kstep+ Kstep· 2 · Icp· ∆ti Vdd · C 2activebit (2.14) The frequency change in the oscillator caused by the step change, dt from the storage cells is given as.

dtstep=

2 · Icp

Vdd · C (2.15)

Hence, finally the frequency change of the oscillator can be re-written as.

f(n) = Kprop· Uprop(n) + non−active(B<i>=0) X i Kstep+ Kstep· ∆ti dtstep 2activebit (2.16)

The z-domain model of the new PLL architecture is shown in the Figure 2.6.

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2.3 Transfer function of new PLL architecture 19

2.3 Transfer function of new PLL architecture

From the Figure 2.6, the transfer function of the output to the input can be ob-tained from forward path and feedback path. So, the whole PLL can be described like a linear loop and its transfer function is given by.

OU T IN =

F orward(z)

1 + (F orward(z) · F eedback(z)) (2.17) Forward(z) is the path from the output of the PFD to the input of the PFD. It is obtained by multiplying the gain of each block placed in the path. The forward path consists of the proportional part, the storage cells, the VCO, and the feedback divider. The forward path is shown in the Figure 2.7. From the Figure 2.7, the

Figure 2.7. Z-Domain model of PLL forward path

Forward(z) is given as. Tsys= ( Kprop f2 · Icp C + 1 1 − _z(s)1 · Kstep f2_{· dt}) · N z(s)(1 −1_z) (2.18) Since, the divider is included in the forward path of the transfer function, the feedback(z) is considered as a unity gain feedback. Hence, the transfer function of the new PLL architecture is given as.

H(Z) = (Kprop f2 · Icp C + 1 1− 1 z(s) ·Kstep f2_·_dt) · N z(s)(1−1 z) 1 + (Kprop f2 · Icp C + 1 1− 1 z(s) ·Kstep f2_·_dt) · N z(s)(1−1 z) (2.19)

The transfer function is used for the mathematical modelling of the PLL [2]. The parameters used for designing the PLL is the digital step dt, the charge pump cur-rent Icp, the proportional gain Kp, the step gain Ko, the divide ratio N , the input

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update frequency, Fref and the damping capacitor C. The mathematical

mod-elling is performed using Mathcad . From the PLL transfer function, magnitude and phase response of the PLL can be obtained. For example, the magnitude and the phase response of the PLL operating at 500 MHz is shown in the Figure 2.8.

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2.3 Transfer function of new PLL architecture 21

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Chapter 3

Design of PLL blocks

The design of the new PLL blocks at 150 nm CMOS process with a supply voltage of 1.5 V is described in this chapter.

3.1 PFD

The phase detector compares the phase difference between the reference CLK and the feedback CLK and produces the error as a phase difference (δT ). But when the frequency difference between the two signals is very high, the phase detector alone cannot generate the exact phase error. This kind of phase error accumulates and results in phase oscillation between > 180◦ and < 180◦ from cycle to cycle. Since the phase detector is insensitive to frequency difference at the input, the PLL may fail to lock. To overcome this problem, the phase-frequency detector (PFD) is used to detect both phase and frequency difference of the input signals. The phase-frequency detector [4], [8] uses two D-flip flops and one NAND gate to detect both the phase and frequency. The design and operation is explained in the following section.

3.1.1 D-flip flop

The D-flip flop takes CLK, CLR, CLRZ as inputs and Q and Qz as outputs. The schematic of D-flip flop is shown in the Figure 3.1. Let’s consider the case, when CLK is high and CLR input is low. Initially, the wire Q1 is set to zero. The inverted CLK signal, CLKZ turns on the transistor MP7 and transistor MP6 is already activated due to wire Q1. This results in the output Q to be pulled to Vdd. The signal Q gets inverted by an inverter, which generates the output Qz. In each time period, the signal Q1 and Q are passed into the buffers connected with the wires. If CLR input is high, the inverted CLR signal, CLRz activates the transistor XP46, which results in signal Q1 to be pulled to VDD. The CLR signal activates the transistor MN6, which pulls back the output Q to zero. Thus, the output of the D-flip flop get resets to zero, when CLR signal is high.

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24 Design of PLL blocks

Figure 3.1. Schematic of D-flipflop

3.1.2 NAND gate

The NAND gate generate the output as high, when both of its inputs are zero and generate the output as low, when both of its inputs are high. When the INIT signal is high, it enables the transistor XN32 and the output Y is pulled back to zero. This happens even when both the input signals A and B are high at the same time. This helps in resets the PFD, when both UP and DOWN pulse are high at the same time. The schematic of the NAND gate is shown in the Figure 3.2.

3.1.3 PFD schematic

The inputs to the two D-flip flops are reference clock signal and feedback signal. INIT signal is an initialization signal, which resets all the node voltages and output of PFD to zero at the start. The D-flip flop generates two outputs, Q and Qz. Qz is complement of Q. One of the outputs of D-flip flop, Q is connected to a NAND gate, which is used to reset the flip-flops, when the output Q from both the D-flip flop are high at the same time. Thus, both the signals cannot be high at the same time. This means the PFD generates either an UP or DOWN pulse but not both. The phase difference between the REFCLK and SYSCLK is measured by whichever rising edge occurs first. The complemented outputs Qz of each flip-flop are inverted and taken as UP and DOWN signals for Charge Pump and REFCUR block. The schematic of PFD is shown in Figure 3.3.

The PFD circuit can be analyzed in two different ways: one way in which REFCLK leads SYSCLK and the other is SYSCLK leads REFCLK. The first scenario is when REFCLK leads SYSCLK. At this stage, an UP pulse is generated. This UP pulse is the phase difference between the phases of the two clock signals.

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3.1 PFD 25

Figure 3.2. Schematic of NAND gate

Figure 3.3. Schematic of PFD

This UP pulse indicates to the rest of the circuit that the SYSCLK needs to speed up or increase the frequency. This scenario is shown in the Figure 3.4.

In other scenario, DOWN pulse is generated and this will indicate that SYSCLK needs to slow down or decrease the frequency. This scenario is shown in the Figure 3.5.

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Figure 3.4. REFCLK leads SYSCLK

Figure 3.5. SYSCLK leads REFCLK

3.2 Charge Pump

The charge pump [1] pumps in or out the current from the damping capacitor. When the PFD generates an UP pulse, the charge stored in the capacitor starts discharging. When a DOWN pulse is generated, the capacitor starts to charge. The frequency of the VCO decreases/increases based on the capacitor being

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dis-3.2 Charge Pump 27

charges/charges. Additionally, the reference clock and the feedback signal is also connected to the charge pump to ensure the active damping. Whenever these two signals are zero at the same time, the voltage in the capacitor should be pulled back to V dd/2. At this stage, the PLL is in locked state. The damping used here results in very high damping factor, which in turn results in less peaking to achieve the lock frequency. The schematic of charge pump is shown in Figure 3.6.

When the PFD generates an UP pulse, the transistor MN8 gets turned on. The

Figure 3.6. Schematic of charge pump

transistor MN7 mirrors the current from the transistor MN6, which results in a path from CP1 to GND. Hence, the capacitor started discharging until the pulse width of UP. The UPB enables the transistor MN9, which maintains the transistor MN7 to be in saturation for the time of UPB pulse.

When the PFD generates the DOWN pulse, the transistor MN0 gets turned on. The transistor MN2 mirrors the current from the transistor MN6, which is same as the UP current. The transistor MP4 again mirrors the DOWN current, which result in charging path from Vdd to the CP1. Hence, the capacitor started charging until the pulse width of DOWN. Similar to UPB, DOWNB turns on the transistor MN1 to maintain the transistor MN2 to be in saturation for all the time of DOWNB pulse.

When the PLL is in the locked state, both UP and DOWN currents flowing out and in to the capacitor should be same. At the same time, the output of NAND gate will be 1, when reference clock and feedback signal goes to zero. This results in transistor MN13, MP8 to be turned on, which leads to pull back the capacitor voltage, CP1 to V dd/2. So, the charge pump is switched off and the voltage settles at V dd/2. The proportional voltage at the ithupdate is given as.

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Vprop(i) =

Icp· ∆Ti

C (3.1)

Where,

Icp- Charge Pump current (CP1)

C - Effective damping capacitor

∆Ti - Phase Difference of the ith update at the PFD inputs

3.3 Storage cell and Reference current

The storage cell [1], [2] is the important part of this PLL architecture. It is used to tune the frequency of the voltage controlled oscillator. The tuning range of the VCO is divided into N steps and the N storage cells are used for that N steps. Each storage cell has a capacitor to charge and discharge. This changes the control voltage of the VCO. The storage cells has two advantages:

1. It is used to for analogue tuning of the VCO from one step to another step, when a cell is active.

2. It is used to store the digital tuning information, when a cell is inactive. The N Storage cells are connected in a fashion as shown in Figure 3.7. The inputs LEFT and RIGHT are connected to the A outputs of the left and right neighbouring storage cells. So, at the same time, two storage cells are active and remaining storage cells are inactive. The B outputs of the storage cells are used for step tuning the VCO. From the outputs of the PFD, FAST and SLOW signals are generated from REFCUR, which generates the current for the storage cells.

3.3.1 Reference current block

The schematic of the REFCUR is shown in the Figure 3.8. When the PFD gen-erates an UP signal, it enables the transistor, MN0. When the transistor, MN0 is enabled, fast signal is mirrored to the storage cell. And, when PFD generates a DOWNB signal, it enables the transistor, MP13. Then the slow signal is mirrored to the storage cell. Based on the fast and the slow signal, the storage cell output B is either low or high. When an UP pulse enables the transistor, MN0 the voltage at the drain of the transistor, MN3 starts building up. The transistor MN13 is also used to pull the voltage at the drain of MN3 to a suitable level to trigger the transistor MN1 at the storage cell. The transistor MN8 is used to pull back the voltage at the drain of MN3 to zero, when PFD generates the UPB signal. Similarly for the DOWN signal from PFD, the transistor MP14 is used to pull down the voltage at the drain of transistor MP0, and transistor MP9 is used to pull back the voltage to Vdd.

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3.3 Storage cell and Reference current 29

Figure 3.7. Block diagram of N storage cell

Figure 3.8. Schematic of REFCUR

3.3.2 Storage cell block

The schematic of single storage cell is shown in the Figure 3.9. Initially, each capacitor in the storage cell is initialized to Vdd by turning on the transistor MP5 using INI signal. This makes the voltage at B to Vdd and zero at A. The LEFT signal of the first storage cell is connected to Vdd. This enables the transistor

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MN0 and disables the transistor MP0 for the first storage cell. The RIGHT signal is connected to the A output of the neighbouring cell. This enables the transistor MP4 and disables MN2 for the first storage cell.

During a fast signal from REFCUR, the transistor MN1 gets enabled and the

Figure 3.9. Schematic of single storage cell

charged capacitor started discharging. Once, the voltage at B started to decrease, the voltage at A started to increase. When A increases above V dd/2, transistor MN2 turns on and pulled down the voltage at B to zero. This turns on the pmos transistor in proportional part of VCO, which results in frequency increase.

During a slow signal from REFCUR, the transistor MP3 turns on and pulls up the voltage at B to Vdd which results in frequency decrease of VCO. The charging and discharging time depends on the current mirror ratio from the REFCUR to Storage cell. All the B output of the storage cell is connected to the pmos tran-sistor in the VCO. So at the start, the VCO is operating at the lowest frequency, because all the B output of the storage cells is high.

B[1:N]_i= Vdd (3.2)

A[1:N]_i= 0 (3.3)

When the PLL tries to lock the phase of the output signal to the input signal, the PFD generates a wide UP pulse. The REFCUR generates the FAST signal of same width as UP and copies the FAST signal to the storage cells. This turns on the transistor MN1 in S1. So, the capacitor in S1 starts discharging during the width of the UP. However, the capacitor in S2..SN, remains at Vdd, because the LEFT input of S2..SN is connected to A output of previous storage cells. Once,

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3.3 Storage cell and Reference current 31

the voltage at B1 decreases below V dd/2, voltage at A1 starts to increase. This turns on the second storage cell S2 and the capacitor in S2 starts discharging. By this time, the RIGHT signal in S1 pulls down the B1 to zero and inactivates S1. When B2 is pulled down below V dd/2, S3 gets enabled and it becomes active. So, at a particular time, only two storage cells are active and all other storage cells are inactive.

Thus, the PLL starts filling 0 in the capacitor from S1..SN. At the same time, the frequency controlling pmos transistors in VCO turns on one by one. This re-sults in the increasing current flow in the oscillator and frequency gets increased. At the lock stage of PLL, when B is low, X-1 storage cells are inactive and when B is high, N-(X+1) are inactive. Storage cells with B(X:X+1) are active. This means for the length of ∆T of the ith_{UP or DOWN pulse charge will be dumped}

at C1.

B[1:(X-1)_i] = 0 (3.4)

B[(X+2)_i:N] = Vdd (3.5)

The whole process of the storage cells is shown in the Figure 3.10. Depending on

Figure 3.10. Process of storage cells

the current mirror ratio in REFCUR and the capacitor in the storage cell, it would take a pulse of length dt to change the voltage from Vdd to Gnd.

B[m]_i= Vdd · ( X B[m]_active,Down ∆ti dt − X B[m]_active,Up ∆ti dt ) (3.6)

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32 Design of PLL blocks B[m+1]_i= Vdd · ( X B[m+1]_active,Down ∆ti dt − X B[m+1]_active,Up ∆ti dt ) (3.7)

f(i)=K_prop· Vprop(i) + m−1 X j=1 Kstep+ Kstep· vdd-B[m]_i vdd + Kstep· vdd-B[m+1]_i vdd (3.8) Where,

f(i) - average VCO frequency during ithupdate Kprop - VCO proportional gain

Vprop(i) - average voltage at PROP during ithupdate pulse

Kstep - Frequency change per digital step

dt - Digital Step

3.4 Voltage Controlled Oscillator

The voltage controlled oscillator [11] is a differential oscillator. The high band-width PLL needs a good oscillator in terms of the duty cycle. This leads to a symmetric differential design.

3.4.1 Single stage of VCO

Each stage of VCO is a differential stage ring oscillator. It has two inputs which are differential to each other. It produces two outputs complement of each other. Both the outputs are connected to a buffer and the output of the buffer is given as input to next stage. The control voltage of each stage is applied through array of pmos and nmos transistors. The schematic of the single stage ring oscillator is shown in the Figure 3.11. The differential inputs are INN and INP. The input INN is given to the transistors MN1, MP1 and INP is given to the transistors MN2, MP2. When the input INN is high, transistor MN1 is turned on. These results in output node OSCP to pulled down to zero by the transistors MN15, MN1 and array of nmos transistors M N < 1 : N >. When the input INN is low, OSCP is pulled up to Vdd by transistors MP16, MP1 and array of pmos transistor

M P < 1 : N >. The same procedure happens for the other input INP. Since both

INN and INP are complementary to each other, output OSCP and OSCN are also complementary to each other.

The array of transistor M P < 1 : N > and M N < 1 : N > controls the frequency of the oscillation. This array of transistors has one transistor for pro-portional part biased to V dd/2 by the capacitor in the charge pump. The gate voltage of all other transistors are connected to the B < 1 : N > outputs of the

N storage cell. Basically, the control signal V n < 1 : N > is just a mirror of the

control signal V p < 1 : N >. When all the transistors < 1 : N > are turned on, this results in more current flow in the oscillator results in the highest frequency of oscillations. When all the transistors < 1 : N > are turned off, this leads to less

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3.4 Voltage Controlled Oscillator 33

Figure 3.11. Schematic of VCO single cell

current flow, which results in lowest frequency of oscillations. The schematic of 5 stage differential ring oscillator is shown in the Figure 3.12. The frequency range

Figure 3.12. Schematic of five stage VCO

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Chapter 4

Measuring PLL parameters

The schematic of the PLL [1], [2] is shown in the Figure 4.1. It consists of the PFD, the charge pump, the VCO, and the storage cells. The frequency of VCO is tuned by the B0s output of the storage cells. The output of the VCO is passed into

the buffer and is given back to the PFD as feedback signal. The PFD generates four outputs UP, UPB, DOWN and DOWNB. All the four outputs are given to charge pump and the REFCUR. The prop signal from the charge pump is used for the proportional damping of the PLL. For example, given operation at 500 MHz, the reference signal, CLK should be with a period of 2 ns and a pulse width of 1 ns to achieve a 50 % duty cycle. The rise time and fall time of the reference signal is given as 50 ps. Initial signal is given to the storage cell for a time of 10 ns to initialize all the capacitor in storage cell to Vdd. It is also given to PFD to stop generating UP or DOWN pulse until all the capacitor in storage cell get initialized.

The whole setup is simulated in spice in a nominal process. The phase and frequency lock of the feedback signal, SYSCLK and the reference signal, CLK is shown in the Figure 4.2. There is an offset of 14 ps between SYSCLK and CLK. The time it takes to lock is 1.1 µs and the number of storage cells required for tuning the VCO to 500 MHz is 10.

The PLL bandwidth achieved in the simulation results should be matched with mathematical modelling. The closed loop transfer function calculated in the equation 2.19, is used to obtain the magnitude plot of the PLL. The mathematical modelling of the PLL operating at 500 MHz is shown in the Figure 4.3. From the Figure 4.3, Hz(s) is the magnitude plot and Ez(s) is the error function from

the VCO output to the VCO input. To verify the bandwidth obtained in the mathematical modelling with the simulation results, the following parameters must be measured.

1. Ko, Step gain of VCO.

2. Kp, Proportional gain of VCO.

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36 Measuring PLL parameters

Figure 4.1. Schematic of PLL operation at 500 MHz

Figure 4.2. Phase and frequency lock of PLL operating at 500 MHz

3. dt, time taken to step from one storage cell to another storage cell. 4. Icp, current drawn by charge pump during UP and DOWN pulse.

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sim-4.1 Setup for measuring PLL parameters 37

Figure 4.3. Mathematical modelling of PLL operating at 500 MHz

ulation results.

4.1 Setup for measuring PLL parameters

To measure the PLL parameters, separate simulation to be performed, which has the same behaviour as in the PLL simulation.

4.1.1 VCO proportional gain measuring setup

The proportional gain is the measurement of change in frequency of VCO for a change in the proportional control voltage. It has almost the same setup like step gain measurement. From the PLL simulation, at the lock state, the variation of the prop signal is from 0.73 to 0.8. Hence, the prop signal is ramped from 0.7 to 0.9 and the respective B0s should be turned on by the corresponding DC source

to achieve 500 MHz signal. This setup is shown in Figure 4.4. From Figure 4.5, the frequency change with respect to change in control voltage is measured, df /dv. The prop voltage is pulled back to V dd/2, when CLK and feedback signal are zero

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at the same. Since, the proportional gain, Kp is seen only for half of the time

period, it should be divided by 2, hence Kp = Kp/2.

Figure 4.4. Proportional gain measuring setup

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4.1 Setup for measuring PLL parameters 39

4.1.2 Charge pump current measuring setup

The current, Icpcan be measured in two ways. One is directly plotting the drain

current of transistor MN8 and MP4 of the charge pump, Figure 3.6. The other way is measuring the change in the voltage of prop signal with respect to an UP or DOWN signal and then multiplying the slope with the capacitor gives the current,

Icp. It is given as.

Icp= C ·

dv

dt (4.1)

The Figure 4.6 shows the second way of measuring Icpfrom the PLL simulation.

Figure 4.6. Icp, Charge pump current

4.1.3 Digital step measuring setup

The digital step, dt is the time taken for an inactive cell to become active cell. This can be measured by applying a constant UP pulse to the REFCUR block. This will generate a constant FAST pulse, which leads to discharging the capacitor one by one. The measuring set up for dt is shown in the Figure 4.7.

4.1.4 VCO step gain measuring setup

The step gain is the measurement of change in frequency of VCO per digital step. It is measured by simulating the VCO alone with a constant DC source of V dd/2 for the proportional part. From the PLL simulation, the number of storage cells

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Figure 4.7. dt, Digital step

required to achieve 500 MHz is 10. So, in the control signal of VCO from storage cell B < 1 : 28 >, a DC source of zero is given to B < 1 : 9 > and Vdd is given to

B < 11 : 28 >. The remaining one control signal B < 10 > is ramped from Vdd

to zero. This setup is shown in Figure 4.8. From the Figure 4.9, the frequency change with respect to change in control voltage is measured, df /dv. This is the step gain Ko.

The parameters measured for the PLL operating at 500 MHz under nominal process are shown in the Table 4.1. All the measured parameters are applied in the

Parameters Values

Vdd 1.5

Temperature 25◦C

Kp, Proportional Gain 60 MHz

Ko, Step Gain 53 MHz

Icp, Charge Pump current 420 µA

dt, Digital Step 34 ns

Table 4.1. PLL parameters in nominal process

mathematical modelling and the resulting magnitude plot of the transfer function is shown in the Figure 4.3. It shows the -3 dB bandwidth of the PLL operating at 500 MHz is greater than 1/10th of the input frequency (i.e) 50 MHz.

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4.2 Bandwidth test 41

Figure 4.8. Ko, Step gain measuring setup

Figure 4.9. Ko, Step gain

4.2 Bandwidth test

To verify the bandwidth of the PLL operating at 500 MHz, the reference signal CLK should be modulated by the corresponding modulating frequency. The PLL

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operating at 500 MHz with the same setup as in the Figure 4.1 is simulated with a modulated CLK at 5 MHz and 50 MHz with 500 MHz as carrier frequency. In each simulation, the output signal SYSCLK follows the modulated CLK. So, how much the modulated SYSCLK gets deviated from the modulated CLK can be calculated using

s=20 · log(∆fSY SCLK ∆fCLK

) (4.2)

s=-3 dB, implies the -3 dB bandwidth of the PLL, which is at 50 MHz. Hence, the same bandwidth of 50 MHz in the mathematical modelling is achieved in simulation too.

4.2.1 Process corners compensation

The PLL shown in the Figure 4.1 is simulated in nominal process with Vdd = 1.5 V. The same setup has to be simulated under different process variations like strong and weak process. In strong process, the Vth of transistors gets reduced,

which results in very fast switching and in weak process the vice versa. The uncompensated PLL operating at 500 MHz is simulated under strong and weak process conditions. During strong simulations, the temperature of the simulation must be changed to −40◦ celsius and the supply voltage should be 1.6 V. Dur-ing weak simulations, the temperature should be +125◦ _{celsius and Vdd should}

be 1.4 V. The measured parameters values for strong simulation is shown in the Table 4.2 and for weak simulation is shown in the Table 4.3. From the table,

Parameters Values

Vdd 1.6

Temperature −40◦_C

dt, Digital Step 32ns

Table 4.2. Uncompensated PLL parameters in strong process

Parameters Values

Vdd 1.4

Temperature 125◦C

dt, Digital Step 33ns

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it can be realized that the proportional gain, the step gain and the charge pump current for strong process simulation, has increased by approximately 50% from the nominal process values. These results in a very high bandwidth above than the bandwidth achieved for the nominal process. For the weak process simulation, the parameters have been decreased. This results in a very low bandwidth than nominal process. The parameters measured in both strong and weak process are substituted in the mathematical modelling and the resulting bandwidth are shown in the Appendix A.

The PLL should be compensated for all the process corners. The compensa-tion is applied in the proporcompensa-tional part of the VCO. The compensated proporcompensa-tional part of the VCO is shown in the Figure 4.10. Based on the process, the number of storage cells required to achieve the lock frequency differs. From the Figure 4.10, the transistors V BP < 7 : 14 > gets activated based on the number of active storage cells. This in turn increases the proportional gain of the VCO. This re-sults in achieving the same bandwidth as achieved in the nominal process of the PLL operating at 500 MHz. The compensated PLL parameters under all the three

Figure 4.10. Compensated proportional part of VCO

process are shown in the Table 4.4, Table 4.5 and Table 4.6.

The measured compensated PLL parameters are substituted in the mathemat-ical modelling and the resulting bandwidth for the nominal process is shown in Figure 4.11. The PLL parameters measuring graphs for the compensated PLL operating at 500 MHz in all the process corners are shown in the Appendix A.

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44 Measuring PLL parameters Parameters Values Vdd 1.5 Temperature 25◦C Kp, Proportional Gain 95 MHz Ko, Step Gain 100 MHz

dt,Digital Step 34ns

Table 4.4. Compensated PLL parameters in nominal process

Parameters Values

Vdd 1.6

Temperature −40◦_C

Table 4.5. Compensated PLL parameters in strong process

Parameters Values

Vdd 1.4

Temperature 125◦C

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Chapter 5

PLL operating range

The operating range of the PLL is from 100 MHz to 1 GHz. The bandwidth of the PLL over the large range should be more than 1/10th of the reference frequency. Two separate PLL are designed at extreme operating frequency range in this chapter. Then finally in the chapter 6, two PLL’s are combined in a single PLL schematic to operate all over the frequency range. The REFCUR block is also modified in this chapter to make sure that the final PLL schematic operates all over the range from 100 MHz to 1 GHz.

5.1 Modified REFCUR block

To make the PLL to operate from 100 MHz to 1 GHz range, the digital step, dt should vary for a range of values. This can be achieved by varying the current copied from the REFCUR block to the storage cells. The REFCUR in the Fig-ure 3.8 is not flexible with the change of current copying to storage cells when the value of the resistor gets changed. Because even when the value of resistance is changed, same current flows through the transistors MP12 and MP11 and gets copied to FAST and the same for the SLOW. Hence a REFCUR block, which is very much flexible with the resistance, is designed. It is shown in the Figure 5.1. It works exactly the same manner as the previous REFCUR and is also flexible with the value of resistance.

When the PFD generates an UP pulse, it enables the transistor MN3 and the current gets copied by the transistor MP5. This will start build up the voltage at the drain of transistor MN4, which enables the corresponding transistor in the storage cell. During an UPB pulse from the PFD, the FAST voltage gets pulled down to zero by transistor MN5. The same concept applies for the SLOW pulse.

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48 PLL operating range

Figure 5.1. Schematic of modified REFCUR

Figure 5.2. Schematic of PLL operating at 100 MHz

5.2 PLL operating at 100 MHz

At 100 MHz as the input reference frequency, the resistor in the charge pump has a value of 40 KΩ, to achieve a charge pump current of 90 µA. The resistor in the REFCUR block has a value of 40 KΩ to get a digital step value, dt as 40 ns. The schematic of the PLL operating at 100 MHz as the input frequency is shown in the Figure 5.2. The VCO has the respective step gain and the proportional gain to achieve the respective lock frequency. The number of storage cells required to tune the PLL to 100 MHz is 3. The phase and frequency lock of the PLL operating

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5.2 PLL operating at 100 MHz 49

at 100 MHz is shown in the Figure 5.3. It has a phase offset of 91 ps and the lock time is 200 ns. The measurement graphs for the PLL parameters like Ko, Kp, Icp

and dt are shown in the Appendix B. The measured parameters under the nominal process are shown in the Table 5.1.

Figure 5.3. Frequency and phase lock of PLL operating at 100 MHz

The measured parameters are substituted in the mathematical modelling and the resulting bandwidth is greater than 50 MHz. The maximum modulation fre-quency of a signal is fsignal/2. The maximum modulating frequency is 50 MHz for

the reference frequency of 100 MHz. Hence, the bandwidth achieved in the PLL operating at 100 MHz is very high bandwidth. So, it can transfer all the signals from the input to output with a offset of 91 ps. The description of the PLL is shown in the Figure 5.4.

5.2.1 Bandwidth test of PLL operating at 100 MHz

To test the bandwidth of the PLL operating at 100 MHz, the reference signal is modulated at certain modulating frequency with 100 MHz as a carrier signal.

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Figure 5.4. Mathematical modelling of PLL operating at 100 MHz

The output of the PLL follows the input modulated signal. The magnitude of the deviation of the output to the input frequency of the modulated signals is shown in the Table 5.2. The measurement graphs for the modulated signals with 100 MHz as carrier frequency are shown in the Appendix B. Hence, the values of the modulated frequencies are roughly matched with the description in the Figure 5.4.

5.3 PLL operating at 1 GHz

At 1 GHz as the input frequency to the PLL, the resistor in the charge pump and REFCUR should be changed to 1 KΩ to obtain the charge pump current of 670 µA and the digital step, dt as 15 ns. The VCO has the respective proportional and step gain to achieve damping and frequency. The number of storage cells required to achieve the right frequency is 13. The phase and frequency lock of PLL at 1 GHz is shown in Figure 5.5. It has a phase offset of 67 ps and lock time as 2 µs. The measurement graph for all the PLL parameters is shown in the Appendix B. The measured parameters under nominal process are shown in the

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5.3 PLL operating at 1 GHz 51 Parameters Values Vdd 1.5 Temperature 25◦C Kp, Proportional Gain 90 MHz Ko, Step Gain 10 MHz

Icp,Charge Pump current 90 µA

Table 5.1. Parameters of PLL operating at 100 MHz in nominal process

Modulation Frequency (MHz) 20 · log(∆fout

∆fref) 2 0 7 1.1 13 1 25 -0.2 50 -0.8

Table 5.2. Bandwidth test for PLL operating at 100 MHz

Table 5.3. As usually, the measured parameters are substituted in the description

Parameters Values

Vdd 1.5

Temperature 25◦C

Icp,Charge Pump current 672 µA

Table 5.3. Parameters of PLL operating at 1 GHz in nominal process

and the resulting -3 dB bandwidth is 100 MHz. The mathematical modelling of PLL at 1 GHz is shown in the Figure 5.6.

5.3.1 Bandwidth test of PLL operating at 1 GHz

To test the bandwidth of the PLL operating at 1 GHz, the reference signal is modulated at certain modulating frequency with 1 GHz as a carrier signal. The magnitude of output to input frequency deviation of the signals modulated at 10 MHz, 20 MHz, 50 MHz, 100 MHz and 200 MHz is shown in Table 5.4. The measurement graphs for the modulated signals with 1 GHz as carrier frequency are shown in the Appendix B. The values obtained in the simulation for the particular modulated signal is not matched with the description in the Figure 5.6

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Figure 5.5. Frequency and phase lock of PLL operating at 1 GHz

for frequency higher than 100 MHz. At higher frequencies, the curve is steeper. So, there may be an extra pole occurs at the higher frequency. This is discussed more in the Chapter 6.

Low Power and Area Efficient Semi-Digital PLL Architecture for High Brandwidth Applications

Institutionen för systemteknik

Department of Electrical Engineering

Examensarbete

LOW POWER AND AREA EFFICIENT

SEMI-DIGITAL PLL ARCHITECTURE FOR

HIGH BANDWIDTH APPLICATIONS

LOW POWER AND AREA EFFICIENT

SEMI-DIGITAL PLL ARCHITECTURE FOR

HIGH BANDWIDTH APPLICATIONS

Examensarbete utfört i Elektroniksystem

vid Tekniska högskolan i Linköping

av

Abstract

Acknowledgments

Contents

List of Figures

List of Tables

List of Abbreviations

Chapter 1

Background Theory

1.1

Conventional PLL architecture

1.1.1

Phase-Frequency Detector

1.1.2

Charge Pump

1.1.3

Loop Filter

1.1.4

VCO

1.1.5

Divider

1.2

PLL operation

1.3

New PLL architecture

Chapter 2

Mathematical Modelling of

the PLL

2.1

Z-Domain model of a conventional PLL

2.1.1

Z-Domain model of frequency to phase transfer

2.1.2

Z-Domain model of phase-frequency detector

2.1.3

Z-Domain model of capacitor and resistor in loop filter

2.1.4

Z-Domain model of VCO

2.1.5

Z-Domain model of conventional PLL

2.2

Z-Domain model of new PLL architecture

2.3

Transfer function of new PLL architecture

Chapter 3

Design of PLL blocks

3.1

PFD

3.1.1

D-flip flop

3.1.2

NAND gate

3.1.3

PFD schematic

3.2

Charge Pump

3.3

Storage cell and Reference current

3.3.1

Reference current block

3.3.2

Storage cell block

3.4

Voltage Controlled Oscillator

3.4.1

Single stage of VCO

Chapter 4

Measuring PLL parameters