Digital compensation of nonidealities in time-interleaved ADCs

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Digital compensation of nonidealities in time-interleaved ADCs

ANDERS HAPONEN

Master’s Degree Project

Stockholm, Sweden 2014

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Abstract

Mismatches between the analog to digital converters (ADCs) in time-interleaved sampling causes spurious signals, limiting the performance of the architecture. This thesis introduces the most commonly modeled mismatches, analyses their effects and reviews and evaluates state-of-the art compensation methods published in recent papers. A novel method for choosing calibration signal for non-blind compensation is suggested, and how it can be used for current blind compensation methods (relaxing input signal requirements). Application of some common compensation methods is demonstrated with simulated data as well as data captured by a development board with two time-interleaved ADCs sampling at a high rate.

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Sammanfattning

Skillnader mellan analog-till-digital-omvandlarna (AD-omvandlarna) vid tids-interleavad sampling orsakar falska signaler, vilket kan bergränsa arkitekturens prestanda. Den här masterupp- satsen introducerar de skillnader som vanligtvis modelleras, analyserar dess effekter och granskar och utvärderar de främsta metoderna i nyligen publicerade artiklar. En ny metod för val av kalibreringssignal till icke-blinda kompenseringsmetoder föresl˚as, och hur den kan användas för blinda kompenseringsmetoder (vilket mildrar kraven p˚a insignalen). N˚agra kompenseringsmetoder tillämpas p˚a simulerad data s˚aväl som data insamlad av ett utvecklingskort med tv˚a tids-interleavade AD-omvandlare med hög sampelfrekvens.

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Acknowledgment

This masters thesis was conducted at Saab AB, business area Electronic Defense Systems, in J¨arf¨alla, Sweden.

I would like to thank my supervisors at Saab, Johan Zhang and Lars Albihn, for our valuable discussions and their excellent supervision. I would also like to thank all my co-workers at Saab as well as my examiner and supervisor at KTH, Peter H¨andel and Arash Owrang respectively.

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List of Abbreviations

ADC Analog to Digital Converter

CW Continuous Wave

DC Direct Current

dBFS Decibels relative to Full Scale

FIR Finite Impulse Response

FPGA Field-Programmable Gate Array FxLMS Filtered-X Least Mean Squares

LMS Least Mean Squares

SFDR Spurious-Free Dynamic Range SMER Signal-to-Mismatch-Error Ratio

TI-ADC Time-Interleaved Analog to Digital Converter

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Chapter 1

Introduction

Applications such as digital communication, radar and high-speed oscilloscopes increase the need for analog-to-digital conversion at high sample rates. Time-interleaved sampling allows surpassing the sample rate of a single ADC by sampling the same signal with multiple ADCs, interleaved in time. Time-interleaved sampling can increase the achievable sample rate (at a given accuracy) in analog-to-digital conversion, however the architecture introduces some problems, caused by the nonidealities of any practical implementation. Some of these problems are however predictable and can be compensated for to some degree.

To illustrate why there is a need to compensate for nonidealities we can use the following example. Imagine a TI-ADC with two ADCs, sampling two signals that are added together, one strong continuous sine-wave (CW) and one weak pulsed signal. When sampling this signal we would expect to be able to identify both of these signals clearly in our digital output (assuming it’s sampled at a frequency higher than the Nyquist rate) . However, if the two ADCs have slightly different gains and the sample clocks are not perfectly aligned in time spurious signals will emerge, at frequencies related to the input signals frequency, possibly making the identification task impossible.

Figures 1.1 and 1.2 shows the spectrograms of simulated samples from such a signal, uncompensated and compensated respectively. In this example the frequencies of the CW and pulsed signal was chosen such that the spurious signal of the CW coincides with the frequency of the pulsed signal. From the uncompensated figure there is no way to see that there is a pulsed signal at the higher frequency, since it is buried in the spurious signal of the strong CW. After the compensation however, the spurious signal from the strong CW is highly attenuated and the pulsed signal is unveiled.

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0 2¹² 2¹³ 0

π/4 π/2 3π/4 π

Sample number

Normalizedangularfrequency(radians/sample)

−30

−20

−10 0 10

dB

Power

Figure 1.1: Spectrogram of CW and pulsed signal before compensation.

0 2¹² 2¹³

0 π/4 π/2 3π/4 π

Sample number

Normalizedangularfrequency(radians/sample)

−30

−20

−10 0 10

dB

Power

Figure 1.2: Spectrogram of CW and pulsed signal after compensation.

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1.1 Scope of the thesis

This thesis introduces the most common nonidealities, analyses their effects and reviews and evaluates state-of-the art compensation methods published in recent papers. The evaluation of the current methods includes performance, type of model for nonidealities, complexity and input signal requirements. The most promising methods are also evaluated by applying them to simulated and captured data.

The methods considered are all-digital compensation methods. Priority is given to methods which could be effectively implemented on a modern FPGA.

A novel method for choosing calibration signal for background (non-blind) compensation methods is suggested, and how it can be used for current foreground (blind) compensation methods (relaxing input signal requirements).

1.2 Organization of the Report

Chapter 2 explains the concept of time-interleaved sampling, it introduces and analyses the effect of common nonidealities. Current compensation methods are compared in chapter 3, the methods that have been tested are also briefly explained. The contributions/novel methods of this thesis are described in chapter 4. Chapter 5 presents results from simulated and captured data, the performance of the selected methods is compared and evaluated. Chapter 6 concludes the thesis by summarizing the report and suggesting possible future work.

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Chapter 2

Time-interleaved ADCs

This chapter explains the concept of time-interleaved sampling (section 2.1) and the effect of nonidealities (section 2.2).

2.1 Concept

In time-interleaved sampling multiple (denoted M ) ADCs sample the same analog signal, interleaved in time. All ADCs sample at the same rate, the effective sample rate is thus increased by a factor of M . [1]

Figure 2.1 shows the concept of time-interleaved sampling. The digital output, y[n], is a sampled version of the analog input, x(t). The samples are taken sequentially in time from the M ADCs, with T_s seconds between each sample. The ADCs in the figure are considered ideal, and the linear nonidealities of the physical ADCs are modeled by H_i(jΩ).

With this model, the effects of nonlinearities in actual ADCs are ignored. This is justified in section 2.2.1.

To make sure that, in the ideal case, time-interleaved sampling corresponds to regular sampling at a higher sample rate, introduce ˜xi(t), the analog input signal distorted by linear nonidealities of ADC i:

˜

xi(t) = hi(t) ∗ x(t), (2.1)

x(t) H₁(jΩ)

H0(jΩ)

HM −1(jΩ)

ADC₀

ADC1

ADCM −1

y[n]

˜ x₁(t)

˜ x2(t)

˜ x_{M −1}(t)

Ts

Figure 2.1: The concept of time-interleaved ADCs.

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T_s

M T_s

Master clock ADC Clock 0 ADC Clock 1

ADC Clock M-1

Figure 2.2: Possible timing diagram for TI-ADCs.

where hi(t) is the impulse response corresponding to Hi(jΩ). Assuming that the sample at time 0 is taken by ADC 0 the output can now be written as:

y[n] = ˜xn mod M(nTs).

In the ideal case all ADCs would be equivalent, having unity gain and no phase shift, corresponding to Hi(jΩ) = 1:

˜

xi(t) = δ (t) ∗ x(t)

= x(t)

⇒ y[n] = x(nTs),

which is equivalent to ideal sampling with a sampling period of Ts (compared to M Ts for the individual ADCs).

In practice there will be mismatches between the different ADCs, due to fabrication spread, differences in temperature, component aging, etc. These mismatches can often be estimated and compensated for to some extent. However, most of these mismatches vary slowly with time, which means that a one time factory calibration might not be good enough.

The model in figure 2.1 could be used to model static linear mismatches, whereas nonlinear effects such as DC-offset or clipping would require a nonlinear model. The effects of mismatches and other nonidealities are introduced in section 2.2.

Figure 2.2 illustrates how the sample clocks could be generated to the different ADCs. Each individual ADC has a sampling period of M Ts. Since the samples are taken interleaved in time the interleaved signal gets a sampling period of Ts. From this we can see that for a given sampling period Ts, we can increase the sampling period of the individual ADCs by increasing the number of interleaved ADCs, M . While this relaxes the sample rate requirements of the individual ADC, each ADC still has to handle the full analog bandwidth of the input signal.

This requirement along with the mismatches between the ADCs limits the performance of the TI-ADC architecture.

2.2 The effect of nonidealities

The performance of a TI-ADC is often limited by its nonidealities. The TI-ADC structure suffers from the same nonidealities as a single ADC, as well as nonidealities stemming from the time- interleaved sampling. These two types of nonidealities are described in sections 2.2.1 and 2.2.2 respectively.

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2.2.1 Common ADC nonidealities

The performance of a single ADC is often limited by nonlinearity, quantization noise or sampling jitter. This section introduces these three nonidealities and their effect in a TI-ADC.

Quantization errors occur when the amplitude of the sampled signal is discretized. This error is deterministic but under certain assumptions it is well modeled by additive white Gaussian noise, with a variance that depends only on the number of bits used (decreasing with the number of bits). Under certain assumptions a TI-ADC is affected by quantization errors equivalently to a conventional ADC [2]. It is therefore not considered further.

Sampling jitter (sometimes distinguished as ADC aperture jitter and external sampling clock jitter) is (usually aperiodic) sample-to-sample variations in the sample clock instant. These variations are most often modeled as i.i.d. zero-mean Gaussian random variables. With this model the spectrum of the error introduced by the jitter will be white, increasing the noise-floor of the sampled signal [3]. The variance of the noise will be signal-dependent.

While quantization and sampling jitter are also nonlinear, an ADCs nonlinearity usually refers to deterministic nonlinear errors that causes harmonic distortion. This nonlinearity is often described by integral nonlinearity and differential nonlinearity. While nonlinear mismatches affect the TI-ADC architecture differently than a single ADC it can be treated as a separate problem, since each ADCs nonlinearity can be compensated for independently, leaving only linear mismatches between the ADCs.

2.2.2 TI-ADC specific nonidealities

In this section the frequency response of a time-interleaved ADC suffering from linear mismatches is derived and compared to the frequency response of ideal sampling at the same effective rate.

As an running example for intuition, imagine M = 2 and the following input spectrum:

ΩT_s

|X(jΩ)|

−3π −2π −π 0 π 2π 3π

Figure 2.3: Example amplitude spectrum of x(t).

Starting from equation (2.1):

˜

xi(t) = (hi∗ x) (t)

⇒ ˜x_i[n] = ˜x_i(nM T_s+ iT_s)

= ˜x⁰_i(nM Ts).

Which has the following discrete-time Fourier transform [4]:

X˜i(e^jω) = 1 M Ts

∞

X

k=−∞

X˜_i⁰

j ω − 2πk M Ts

,

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where ˜X_i⁰(jΩ) is the Fourier transform of ˜x⁰_i(t).

X˜_i⁰(jΩ) = e^jiT^s^ΩX˜i(jΩ)

⇒ ˜Xi(e^jω) = 1 M T_s

∞

X

k=−∞

e^jiT^s(^ω−2πk_{M Ts} ) ˜Xi

j ω − 2πk M T_s

, (2.2)

which, for our example, could look something like this:

ω

X˜i(e^jω)

−3πM −2πM −πM 0 πM 2πM 3πM

Figure 2.4: Example amplitude spectrum of ˜xi[n]. The actual spectrum is the sum of all spectral copies (dashed and solid). The spectrum will be aliased due to each ADC sampling below the Nyquist rate of the input signal. The spectral copies that causes aliasing are dashed while the others are left solid. This corresponds to odd and even k from equation (2.2) respectively.

Introduce upsampled signals:

ˆ x_i[n] =

x˜_i[n/M ] n ≡ 0 (mod M )

0 Otherwise

⇒ ˆXi(e^jω) = ˜Xi(e^jωM)

= 1

M Ts

∞

X

k=−∞

e^jiT^s(^{ωM −2πk}_{M Ts} ) ˜Xi

j ωM − 2πk M Ts

e^jiT^s(^{ωM −2πk}_{M Ts} ) = e^jiωe^−ji^2πk^M ,

which, for our example, could look something like this:

ω

Xˆi(e^jω)

−3π −2π −π 0 π 2π 3π

Figure 2.5: Example amplitude spectrum of ˆxi[n]. The actual spectrum is the sum of all spectral copies (dashed and solid). Similar to figure 2.4 but the upsampling causes scaling of the frequency axis.

Interleaved signal:

y[n] =

M −1

X

i=0

ˆ

xi[n − i],

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which has the discrete-time Fourier transform:

Y (e^jω) =

M −1

X

i=0

e^−jiωXˆi(e^jω)

= 1

M Ts M −1

X

i=0

e^−jiω

∞

X

k=−∞

e^jiωe^−ji^2πk^M X˜_i

j ωM − 2πk M Ts

= 1

M Ts M −1

X

i=0

∞

X

k=−∞

e^−ji^2πk^M H_i

j ωM − 2πk M Ts

X

j ωM − 2πk M Ts

= 1

M Ts

∞

X

k=−∞

X

j ωM − 2πk M Ts

^{M −1} X

i=0

e^−ji^2πk^M H_i

j ωM − 2πk M Ts

. (2.3)

Which, for our example, could look something like this:

ω Y (e^jω)

−3π −2π −π 0 π 2π 3π

Figure 2.6: Example amplitude spectrum of y[n]. The actual spectrum is the sum of all spectral copies (dashed and solid). The spectral copies not positioned at integer multiples of ^2π_M (dashed) will ideally cancel perfectly when the delayed ˆx_i[n] are added together.

Compare equation (2.3) with the discrete-time Fourier transform for ideal sampling

Yideal(e^jω) = 1 T_s

∞

X

k=−∞

X

j ω − 2πk T_s

.

From equation (2.3) we see that instead of spectral copies separated by 2π we get spectral copies separated by ^2π_M and multiplied by the factor

1 M

M −1

X

i=0

e^−ji^2πk^M Hi

j ωM − 2πk M T_s

, (2.4)

which for Hi(jΩ) = H(jΩ) simplifies to 1

MH

j ωM − 2πk M Ts

^{M −1} X

i=0

e^−ji^2πk^M

= (

H j

ωM −2πk M Ts

k ≡ 0 (mod M )

0 Otherwise .

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Giving the frequency spectrum:

Y (e^jω) = 1 T_s

X

k∈Z|k≡0 (mod M )

H

X

= 1 Ts

∞

X

k=−∞

H

j ω − 2πk Ts

X

j ω − 2πk Ts

.

Which is equivalent to ideal sampling of the signal x(t) filtered by H(jΩ) with sampling period Ts.

For a sine-wave input with angular frequency Ω0, amplitude A and initial phase ϕ:

x(t) = A cos(Ω0t − ϕ)

= A cos

Ω0

t − ϕ

Ω0

, which has the discrete-time Fourier transform:

X(jΩ) = A√

2πe^−j^Ω0^ϕ^Ω(δ (Ω − Ω₀) + δ (Ω + Ω₀))

⇒ X

j ωM − 2πk M Ts

= A√

2πe^−j^Ω0^ϕ(^{ωM −2πk}_{M Ts} )

δ ωM − 2πk M Ts

− Ω0

+ . . . . . . + δ ωM − 2πk

M Ts

+ Ω₀

(2.5) e^−j^Ω0^ϕ(^{ωM −2πk}_{M Ts} ) = e^−j^ϕTs^ω0(^{ωM −2πk}_{M Ts} )

= e^−jϕ

_{ωM −2πk}

ω0M

(2.6) δ ωM − 2πk

M Ts

− Ω0

= δ ωM − 2πk M Ts

−ω0

Ts

= Tsδ ωM − 2πk M

− ω0

= Tsδ

ω − 2πk M + ω0

(2.7) δ ωM − 2πk

M Ts

+ Ω₀

= T_sδ

ω − 2πk M − ω0

. (2.8)

Inserting equations (2.6), (2.7) and (2.8) into equation (2.5):

X

= A√

2πTse^−jϕ

_{ωM −2πk}

ω0M

δ

ω − 2πk M + ω0

+ . . . . . . + δ

ω − 2πk M − ω0

, (2.9)

which corresponds to tones at frequencies ^2πk_M ± ω0, again multiplied by equation (2.4).

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For the special case of M = 2: Inserting equation (2.9) into equation (2.3):

Y (e^jω) = 1 M T_s

∞

X

k=−∞

A√

2πTse^−jϕ

_{ωM −2πk}

ω0M

δ

ω − 2πk M + ω0

+ . . .

. . . + δ

ω − 2πk M − ω0

^{M −1} X

i=0

e^−ji^2πk^M Hi

= A√ 2π 2

∞

X

k=−∞

e^−jϕ

_ω−πk

ω0

(δ (ω − (πk + ω0)) + . . .

. . . + δ (ω − (πk − ω₀)))

1

X

i=0

e^−jiπkH_i

j ω − πk Ts

.

Assume 0 < Ω0< ^Ω₂^s ⇒ 0 < ω0< π and evaluate Y (e^jω) in the range 0 ≤ ω ≤ π:

Y (e^jω) =A√ 2π 2

1

X

k=0

e^−jϕ

ω−πk ω0

(δ (ω − (πk + ω0)) + . . .

. . . + δ (ω − (πk − ω0)))

1

X

i=0

e^−jiπkHi

j ω − πk T_s

=A√ 2π

2 e^−jϕ^ω0^ω (δ (ω − ω0) + δ (ω + ω0))

1

X

i=0

Hi

j ω

T_s

+ . . . .

. . . + e^−jϕ^ω−π^ω0 (δ (ω − (π − ω0)) + δ (ω − (π + ω0)))

1

X

i=0

e^−jiπHi

j ω − π T_s

!

=A√ 2π 2

e^−jϕ^ω0^ω0δ (ω − ω0)

H0

j ω₀

Ts

+ H1

j ω₀

Ts

+ . . . . . . . + e^−jϕ^π−ω−π^ω0 δ (ω − (π − ω0))

H0∗

j π − (π − ω₀) Ts

− H1∗

j π − (π − ω₀) Ts

=A√ 2π 2

e^−jϕδ (ω − ω₀)

H₀

j ω₀

Ts

+ H₁

j ω₀

Ts

+ . . . . . . . + e^jϕδ (ω − (π − ω₀))

H₀^∗

j ω0

T_s

− H₁^∗

j ω0

T_s

. Which corresponds to a tone at ω = ω₀ with complex amplitude:

A√ 2πe^−jϕ

H0

j

ω0

Ts

+ H1

j

ω0

Ts

2 , (2.10)

and one at ω = π − ω₀ with complex amplitude:

A√ 2πe^jϕ

H0∗ j

ω0

T_s

− H1∗ j

ω0

T_s

2 . (2.11)

We now know how a general frequency-response mismatch between the channels affects the output spectrum and where the spurious tones of a single sine-wave input show up in the spectrum

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of the sampled signal. To motivate some of the compensation methods presented in chapter 3 we now analyze the effect of three commonly modeled mismatches, DC-offset, timing and gain. These three mismatches are commonly modeled since they represent common physical nonidealities in a time-interleaved ADC structure.

The DC-offset and gain mismatches between the channels are realistic since the interleaved ADCs are very likely to differ slightly due to differences in the ADCs internal input buffer/amplifier.

These differences are mainly caused by fabrication spread. The timing mismatch can also be caused by internal factors, but also due to factors outside of the ADC, such as difference in trace lengths between the clock source to the ADCs sample clock input. These three mismatches might also vary slowly with time, due to temperature changes, component aging, etc.

DC-offset mismatches

Even though there is no input present at an ADCs input its output usually has a small DC-value.

Since the DC-offset is unaffected by the input signal the transfer characteristics of an ADC with DC-offset is not LTI, therefore the DC-offset cannot be modeled into Hi(jΩ). However, if the same model as in figure 2.1 is used with the addition of different DC-offsets before the input of each ADC the effect of the offset on the output y[n] will be independent of the input signal x(t) [5]. In reality this is not completely accurate due to nonlinearities (such as quantization) in the ADC.

Introducing o_i, the offset before the input of each ADC, the effect on the output is simply:

y_o[n] = o_{n mod M}

⇒ Y_o(e^jω) =

∞

X

n=−∞

o_{n mod M}e^−jωn

=

M −1

X

i=0

∞

X

n=−∞

o_ie^{−jω(M n+i)}

=

M −1

X

i=0

oie^−jωi

∞

X

n=−∞

e^{−jωM n}.

Let ω⁰= ωM

⇒

∞

X

n=−∞

e^{−jωM n}=

∞

X

n=−∞

e^−jω⁰ⁿ

= FDT F T(1)|_ω0

=

∞

X

k=−∞

2πδ (ω⁰− 2πk)

=

∞

X

k=−∞

2πδ (ωM − 2πk)

=

∞

X

k=−∞

2π Mδ

ω −2πk M

⇒ Yo(e^jω) = 2π M

M −1

X

i=0

o_ie^−jωi

∞

X

k=−∞

δ

ω −2πk M

.

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Which corresponds to tones at frequencies ^2πk_M with complex amplitude ^2π_M PM −1

i=0 oie^−jωi. Gain mismatches

The most common model for gain mismatches is that each channel has its own specific static gain g_i. This corresponds to H_i(jΩ) = g_i. With only this mismatch the output spectrum becomes:

1 M T_s

∞

X

k=−∞

X

^{M −1} X

i=0

e^−ji^2πk^M gi.

Timing mismatches

The most common model for timing mismatches is that each channel is sampled with a slight delay, which is different for each channel, denoted by ∆t_i. This corresponds to Hi(jΩ) = e^−jΩ∆^ti. With only this mismatch the output spectrum becomes:

1 M Ts

∞

X

k=−∞

X

j ωM − 2πk M Ts

^{M −1} X

i=0

e^−ji^2πk^M e^−j(^{ωM −2πk}_{M Ts} )^∆ti.

Gain and timing mismatches in two-channel TI-ADCs

To get some intuition of how the gain and timing mismatches affect the performance of a TI-ADC we can look at how the SFDR is affected by the mismatches. For a two-channel TI-ADC we can, without loss of generality, assume that g₀ = 1, g₁ = g, ∆_t₀ = 0, ∆_t₁ = ∆_t. This corresponds to H0(jΩ) = 1 and H1(jΩ) = ge^−jω⁰^∆t^Ts. Inserting this into equation (2.10) and equation (2.11) gives the SFDR (assuming the spurious signal will limit the SFDR):

SFDR =

A√

2πe^{−jϕ H}⁰(^j(^ω0_Ts))^+H1(^j(^ω0_Ts))

2

A√

2πe^jϕ^H⁰

∗(^j(^ω0_Ts))−H1∗(^j(^ω0_Ts))

2

=

H0

j

ω₀ T_s

+ H1

j

ω₀ T_s

H₀^∗ j

ω₀ T_s

− H₁^∗ j

ω₀ T_s

=

1 + ge^−jω⁰^∆t^Ts 1 − ge^jω⁰^∆t^Ts

.

Figure 2.7 and 2.8 show SFDR versus gain and timing error for two different ω0. From these figures we can see that the time-interleaved structure is more sensitive to timing error as the frequency increases.

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0.8 0.9 1 1.1 1.2

−0.2

−0.1 0 0.1 0.2

g

∆t Ts

18.06 24.08 30.10 36.12 42.14 48.16

dB

SFDR

Figure 2.7: SFDR vs ∆_tand g for ω₀= 0.3π.

0.8 0.9 1 1.1 1.2

−0.2

−0.1 0 0.1 0.2

g

∆t Ts

18.06 24.08 30.10 36.12 42.14

dB

SFDR

Figure 2.8: SFDR vs ∆_tand g for ω₀= 0.7π.

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Chapter 3

Compensation methods

This chapter introduces some all-digital compensation methods. Section 3.1 describes a few properties that can be used to categorize compensation methods.

3.1 Compensation properties

The list below describes a few fundamental properties that can be used to characterize all-digital TI-ADC compensation methods.

Number of ADCs

The number of ADCs that the compensation methods works for.

Blind/non-blind¹

Non-blind methods requires interrupting the data acquisition for a short period of time and capturing some sort of calibration signal. This has the disadvantage of data being lost while the calibration signal is applied. In contrast, blind compensation methods uses the signal of interest to calibrate continuously. This usually puts stricter limitations on the input signal. Most of the blind compensation methods can be adapted to be used as a non-blind method to relax the input signal requirements.

Frequency response mismatch modeling/gain and timing mismatch modeling Many compensation methods model only static gain and timing mismatches, while some model a more general frequency response mismatch. A more general frequency response mismatch might be needed if the sampling frequency is very high (giving a more varying frequency response) or if the analog input bandwidth of the ADCs are close half the over all sample rate.

Off-line estimation

Many methods can be separated into estimation and compensation, allowing the estimation to be performed off-line. For some compensation methods the complexity of the estimation is very high (it might include large matrix inverses, filter design, etc.) which means that off-line estimation might be needed for a real-time compensation implementation.

1There are also semi-blind compensation methods where a calibration signal is injected into the signal of

interest.

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3.2 Current compensation methods

The following subsections presents the methods which have been tested and for which results are presented in the results chapter.

Table 3.1 lists a few compensation methods that fall within the scope of this thesis (see section 1.1). The compensation methods have been categorized according to the properties in section 3.1 and according to the following very loose definitions of their realizability on an FPGA:

Low

Should be implementable in real-time on a modern high-end FPGA at high sample rates.

Medium

Should be implementable in real-time on a modern high-end FPGA at low, moderate and possibly high sample rates, requiring more chip area than low complexity.

High

Not realistic for real-time implementation on an FPGA (this would typically be the case only for the estimation, thus requiring off-line estimation).

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AuthorYearBlindGain & timing only MComplexity compensation

Complexity estimationAdditional Jamal,S.M.; Fu,D.;Chang, N.C.-J.;Hurst, P.J.;Lewis,S.H.

2002YesYes2MediumMediumRequiresanaloginputchopper foroffsetadjustment.Ideafor gainandtimingadjustmentis tomultiplytheinterleavedsignal withachoppedversion,result- inginaDC-offsetproportionalto thegain/timingerror. Matsuno,J.; Yamaji,T; Furuta,M; Itakura,T.

2013YesYes2kLowLowSimilarto(2004:Jamal,S.M.; Fu,D.;Chang,N.C.-J.;Hurst, P.J.;Lewis,S.H.)butforalarger numberofADCs.Chopperisre- placedbypseudoaliasingsignals. MunkyoSeo; Rodwell,M.; Madhow,U.

2007YesNo2Dependson model.HighaIdeaistominimizedifferencebe- tweentheinterleavedautocorre- lationsforthetwochannels.Fre- quencyresponsemismatchas- sumedtobeparametrizedarbi- trarily. Saleem,S.;Vo- gel,C.2010YesYesAnyLowLow/MediumRequiresinputsignaltobeband limitedslightlybelowhalfthe overallsamplerate.Idea istominimizeenergyinthe ”mismatch-band”usingFxLMS. Saleem,S.;Vo- gel,C.2011YesNo2MediumMediumSimilarto(2010:Saleem,S.; Vogel,C.)butcompensates frequencyresponsemismatches. Sub-ADCmodelispolynomialin jω. Singh,S.;Epp, M.;Vallant,G.; Valkama,M.; Anttila,L.

2013YesNo2-b -c Transformsthemismatchprob- lemintoaI/Qmismatchprob- lem. Table3.1:Somecompensationmethodsandtheirmainproperties. aThisalsodependsonthemodelusedbutwillgenerallybehigh. bDependsmainlyonIQ-mismatchcompensationmethodused. c—”—

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3.2.1 A 10-b 120-Msample/s time-interleaved analog-to-digital con- verter with digital background calibration [6]

In this paper Jamal, Fu, Chang, et al. present a method to compensate gain, timing and DC- offset mismatches. The compensation, as presented, has the following properties:

• Gain and timing mismatch modeling,

• For 2 ADCs,

• Blind.

The idea behind the DC-offset compensation is to modulate the analog input such that it has no DC-component at the input of the ADCs. Any DC-offset still present at the digital output of each ADC will then correspond to the DC-offset of that ADC and can be removed using a feed-back loop. Since the exact modulation of the analog input is known the original signal can be reconstructed in the digital domain.

While this analog modulation would require special hardware which might not even be feasible at high sample rates this method was included since the idea can be used without the modulation if further input signal assumptions are made. Also, the gain and timing mismatch compensation does not require special hardware.

Figure 3.1 illustrates the DC-offset compensation. Here C[m] is a white, zero-mean, pseudo- random binary sequence taking values ±1. Since the C[m]² = 1 the output of ADC i can be reconstructed by multiplying the ADCs output with C[m] again.

The idea behind the gain- and timing-mismatch compensation is to form signals which have DC-components that are proportional to the gain and timing mismatches respectively. These signals are then, similar to the DC-offset, used in a feed-back loop the remove the mismatches.

The gain-mismatch compensation structure is illustrated in figure 3.2. Here a1and a2 correspond to the DC-offset compensated signals from each ADC. Ignoring the sample-time calibration block the signal that enters the gain-error detector block is the interleaved signal, with the sec- ond channel multiplied by G[n]. If we also ignore the 1 + z⁻² filter the gain-modified interleaved signal y[n] is modulated by (−1)ⁿ. In the paper the authors reason that for a sine-wave input this modulation will shift the spurious signal to the frequency of the input signal and the input signal to the frequency of the spurious signal. Therefore multiplying the interleaved signal with the modulated signal will produce a signal with a DC-component proportional to the gain mismatch.

This signal is then used in a feed-back loop controlling G[n].

The timing-mismatch compensation structure is illustrated in figure 3.3. The timing-mismatch compensation works much like the gain-mismatch compensation, with the feed-back loop controlling a fractional delay filter instead of the gain. In the presence of timing mismatch, the modulated signal (yc[n] in figure 3.3) will be 90^◦ out of phase with the input and will therefore not produce a signal with a DC-component proportional to the timing mismatch. This is solved by adding a single-sample delay to the modulated signal, causing some phase-shift for all frequencies.

The 1 + z⁻² filter is used in both the gain and timing mismatch compensation since it filters out input signals at frequency ^π₂. Input signals at this frequency could generate a DC-component to the input of the accumulators in figure 3.2 and figure 3.3 even if there are no gain or timing mismatches.

The parameters µ_o, µ_gand µ_tcontrol the convergence rate for the feedback loops for the offset, gain and timing respectively. These parameters as well as the filter length of the fractional delay filter are the main design-considerations for this compensation method.

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The idea of the DC-offset compensation can be used non-blindly (for any number of ADCs) without special hardware, as long as the calibration signal does not have energy at frequencies close to ^2πk_M . This simplified idea is illustrated in figure 3.4.

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x(t)

C[m]

ADC_i +

−

ai[m]

C[m]

µo

Accum.

Figure 3.1: DC-offset compensation structure (slightly modified).

a1[m] x

2

1 + z⁻²

a2[n] x

2 z⁻¹

Samp.

Time Cal

(−1)ⁿ

µ_g β1[n]

β₂[n]

y[n] yc[n]

Accum.

G[n]

Gain-error Detector

Figure 3.2: Gain mismatch compensation structure.

β1[n] Fixed Delay

1 + z⁻² z⁻¹

β2[n] Adaptive FIR

(−1)ⁿ

µt

y[n] yc[n] yd[n]

Accum.

Calculate or Look-up Coefficients ∆t Phase Detector

Figure 3.3: Timing mismatch compensation structure.

x(t) ADC_i +

−

ai[m]

µo

Accum.

Figure 3.4: Simplification of the DC-offset compensation structure for non-blind use.

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3.2.2 All-Digital Background Calibration Technique for Time-Interleaved ADC Using Pseudo Aliasing Signal [7]

In this paper Matsuno, Yamaji, Furuta, et al. presents a method to compensate gain and timing mismatches. The compensation, as presented, has the following properties:

• For any number of ADCs,

• Blind.

The idea behind the compensation is similar to [6] but generalized for any number of ADCs.

Figure 3.5 shows the compensation structure. The signals Ti[n] in this figure are the aliasing signals. In the paper the authors describes how to choose these signals when the number of ADCs is a power of two. With this particular number of ADCs these signals can be binary sequences taking values ±1, which would require much less hardware than arbitrary sequences. For M = 4 the authors present the following sequences:

T1[n] =











1 n ≡ 0 (mod 4)

−1 n ≡ 1 (mod 4) 1 n ≡ 2 (mod 4)

−1 n ≡ 3 (mod 4)

T₂[n] =











1 n ≡ 0 (mod 4) 1 n ≡ 1 (mod 4)

−1 n ≡ 2 (mod 4)

−1 n ≡ 3 (mod 4)

T3[n] =











1 n ≡ 0 (mod 4)

−1 n ≡ 1 (mod 4)

−1 n ≡ 2 (mod 4) 1 n ≡ 3 (mod 4)

.

The mismatch estimation block is shown in figure 3.6. The weights from the correlator block in the mismatch estimation has the following update equations:

ωgk[n + 1] = ωgk[n] + µgky[n]ˆyek[n]

ω_tk[n + 1] = ω_tk[n] + µ_tky[n]ˆy_ek⁰ [n],

which is similar to the accumulators in [6]. The parameters µ_gkand µ_tkcontrol the convergence rate of the weights. The notch filter filters out signals at frequencies ^kπ_M, with the same purpose as the 1 + z⁻² filter in [6].

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x[n] y[n]

jω

+

−

MismatchEstimation

T1[n]

TM −1[n]

T1[n]

TM −1[n]

ωg1

ωg(M −1)

ωt1

ω_{t(M −1)}

Pseudo Aliasing Generator

Figure 3.5: Mismatch compensation structure.

y[n]

Notch filter

yn[n]

Pseudo Aliasing Generator

Correlator ˆ

y_e1[n]

ˆ

y_{e(M −1)}[n]

ωg1

ω_{g(M −1)}

ˆ

y⁰_{e(M −1)}[n]

ˆ y_e1⁰ [n]

ω_{t(M −1)} ωt1

Figure 3.6: Mismatch estimation structure.

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3.2.3 On Blind Identification of Gain and Timing Mismatches in Time- Interleaved Analog-to-Digital Converters [8]

In this paper Saleem and Vogel presents a method to compensate gain and timing mismatches.

The method is mainly a simplification of [9]. The compensation, as presented, has the following properties:

• For any number of ADCs,

• Blind.

The idea behind the compensation is to use the LMS algorithm [10] to minimize the energy in a mismatch-band, a frequency band where no input signal is assumed to be present. Since there is no input signal energy in this band all most of the energy will be stemming from interleaving- mismatches. For the simulations demonstrated in the paper the authors assumed the input signal was slightly oversampled, leaving a mismatch-band close to half the over all sample rate.

Figure 3.7 shows the compensation structure. In the figure hd[n] is an ideal differentiator [4], f [n] denotes a high-pass filter (with the purpose of filtering out the input signal), m[n] is a modulation vector (similar to the aliasing signals in previous methods) and ˆcg[n] and ˆcr[n] are coefficient vectors from the LMS-algorithm.

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y[n] = G₀x[n] + e[n] +

−

ˆ x[n]

m[n]

ˆ cg[n]

m[n]

ˆ c_r[n]

h_d[n]

FxLMS y_g[n]

y_r[n]

f [n]

ε[n]

Figure 3.7: Mismatch compensation structure. The thick lines and bold symbols indicate vector signals.

3.2.4 Adaptive Blind Background Calibration of Polynomial-Represented Frequency Response Mismatches in a Two-Channel Time-Interleaved ADC [11]

In this paper Saleem and Vogel presents a method to compensate frequency response mismatches.

The compensation, as presented, has the following properties:

• Frequency response mismatch modeling,

• For 2 ADCs,

• Blind.

The idea behind the compensation is similar to in [8] but the model is limited to 2 ADCs and extended to more general frequency response mismatches. The compensation structure models the frequency response mismatches as a polynomial in jω.

Figure 3.8 shows the compensation structure. In the figure d_k[n] are ideal differentiators of order k [4], f [n] denotes a high-pass filter (with the purpose of filtering out the input signal), and ˆc_k[n] are coefficients from the LMS-algorithm.

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y[n] = ¯x[n] + e[n] +

−

ˆ x[n]

d0[n]

ˆ c0[n]

d1[n]

ˆ c1[n]

dP[n]

ˆ cP[n]

y₀[n]

y₁[n]

y_P[n]

(−1)ⁿ

f [n]

F xLM S ε[n]

Figure 3.8: Mismatch compensation structure.

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Chapter 4

Contributions

Section 4.1 proposes a choice of calibration signal for methods that require the actual input signal to be removed from the digital output.

4.1 Choise of calibration signal

Some compensation methods (e.g. [8] and [11] introduced in section 3.2) require the actual input signal to be removed from the digital output, leaving only spurious signals. The actual signal is usually removed using a digital filter, e.g. if you assume that the analog input signal was oversampled you could use a high-pass filter. When adapting such blind methods to become non-blind, a suitable calibration signal and filter is needed. In a practical implementation with a high sample-rate it is natural to use sine-waves as calibration signals and to desire a simple filter.

In this section I introduce an idea of how a very simple filter can be used.

The starting point is a simple comb notch filter:

H(z) = 1 − z^−l, which has nulls at:

H(z) = 0 ⇒ 1 = z^−l

⇒ e^j0= e^j(−ω⁰^l+2πk) ∀ k ∈ Z

⇒ 0 = −ω0l + 2πk ∀ k ∈ Z

⇒ ω0=2πk

l ∀ k ∈ Z. (4.1)

If we choose the input signals at these frequencies they will be removed by the notch filter.

For practical reasons we might not want to generate calibration signals at DC or the half the over all sample rate. If we introduce K_i ⊂ Z as the set of indexes of k in equation (4.1) where

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we place our calibration sine-waves this corresponds to:

2πki

l 6= πk ∀ ki∈ Ki, k ∈ Z

⇒ 2ki

l 6= k ∀ ki∈ Ki, k ∈ Z

⇒ 2ki6≡ 0 (mod l) ∀ k_i∈ Ki

⇒ Ki= {ki∈ Z|2ki6≡ 0 (mod l)} .

If the DC-offset calibration is performed simultaneously we must avoid input and spurious signals at frequencies ^2πk_M . For the input signal this corresponds to:

2πki

l 6= 2πk

M ∀ k ∈ Z, kⁱ∈ Ki

⇒ k_i l 6= k

M ∀ k, k_i∈ Z | 2ki6≡ 0 (mod l)

⇒ 2lk⁰+ k⁰⁰

l 6= k

M ∀ k, k⁰, k⁰⁰∈ Z | 0 < k⁰⁰< 2l

⇒ 2k⁰+k⁰⁰ l 6= k

M ∀ k, k⁰, k⁰⁰∈ Z | 0 < k⁰⁰< 2l

⇒ k⁰⁰ l 6= k

M ∀ k, k⁰⁰∈ Z | 0 < k⁰⁰< 2l

⇒ k⁰⁰⁰+ l l 6= k

M ∀ k, k⁰⁰⁰∈ Z | − l < k⁰⁰⁰ < l

⇒ k⁰⁰⁰ l 6= k

M ∀ k, k⁰⁰⁰∈ Z | − l < k⁰⁰⁰ < l

⇒ M

l 6= k

k⁰⁰⁰ ∀ k, k⁰⁰⁰∈ Z | − l < k⁰⁰⁰ < l, which means that ^M_l is irreducible ↔ M and l are coprime. For the spurious signals:

2πk⁰

M ±2πki

l 6= 2πk

M ∀ k, k⁰∈ Z, ki∈ Ki | k⁰6≡ 0 (mod M )

⇒ 2πk_i

l 6= 2π(k + k⁰)

M ∀ k, k⁰, k_i∈ Z | 2ki6≡ 0 (mod l), k⁰ 6≡ 0 (mod M )

⇒ 2πki

l 6= 2πk

M ∀ k, ki∈ Z | 2ki6≡ 0 (mod l), which is the same inequality as for the input signal.

Introduce ωm:

ωm= arg max

ω

|H(z)| .

Ideally all spurious signals would be located at ω_m, however we can show that (for arbitrary coprime pairs l and M ):

1. No spurious signals will be located at a null.

2. If l is odd and M is even we are guaranteed at least one spurious signal at w_m.

3. It is impossible to ensure that all spurious signals get located at ωm, except for M = 2.

For proof see appendix A.

Statement 1 and 2 are positive.

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Chapter 5

Results

This chapter presents results from the different compensation methods. The compensation is demonstrated for simulated data in section 5.1 and for captured data in section 5.2.

5.1 Simulated data

This section presents results from data simulated in MATLAB [12]. All data is simulated without quantization or other nonlinearities.

All compensation methods are tested non-blindly by first letting them converge on a training signal, then locking its parameters and evaluating it on a test signal.

Since most compensation methods assume that there is no DC-offset, DC-offset compensation is tested separately in section 5.1.1. All other data is simulated without adding DC-offsets.

Since all tested methods are capable of modeling static gain and timing mismatches these two mismatches are primarily used to evaluate the methods. This is done in section 5.1.2 and 5.1.3 for 2 and M ADCs respectively. The main measure used to evaluate the performance is the SFDR.

5.1.1 DC-offset

To simulate DC-offset white Gaussian noise with mean zero and standard deviation σ is used as training and test signal, this represents the inherent noise of the system. Figure 5.1 shows the power spectrum of the sampled signal for a four-channel TI-ADC with only DC-offset mismatches.

From this figure we can verify that the spurious signals do occur at the frequencies stated in section 2.2.2.

Figure 5.2 shows the same signal, but with the DC-offset compensated according to figure 3.4, after the accumulator has converged and the parameters have been locked.

Figure 5.3 shows the same signal and compensation (also after convergence), but with a significantly higher value for µo. From these figures we can see that we might need to adjust µo

until the spurious signals are low enough for our application.

Figure 5.4 and 5.5 show the output of the accumulators over time, for the low and high µo

respectively. From these figures we can see how the µoparameter affects the convergence rate as well as the steady state behavior in the presence of noise.

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0 π/4 π/2 3π/4 π

−160

−140

−120

−100

−80

−60

−40

Normalized angular frequency (radians/sample)

Power(dB-scale)

Figure 5.1: Power spectrum of a four-channel TI-ADC with DC-offset mismatches. σ = 1, [o1, o2, o3, o4] = [−1.64, −3.33, 1.25, −1.37].

0 π/4 π/2 3π/4 π

−160

−140

−120

−100

−80

−60

−40

Power(dB-scale)

Figure 5.2: Power spectrum of a four-channel TI-ADC with compensated DC-offsets. σ = 1, µo = 0.00025, [o1, o2, o3, o4] = [−1.64, −3.33, 1.25, −1.37], small µo.

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0 π/4 π/2 3π/4 π

−160

−140

−120

−100

−80

−60

−40

Power(dB-scale)

Figure 5.3: Power spectrum of a four-channel TI-ADC with compensate DC-offsets. σ = 1, µo = 0.02, [o1, o2, o3, o4] = [−1.64, −3.33, 1.25, −1.37], large µo.

0 2¹⁶ 2¹⁷

−4

−3

−2

−1 0 1 2

Sample number (n)

DC-offsetaccumulatoroutput

Figure 5.4: Convergence of the accumulator output. σ = 1,

[o₁, o₂, o₃, o₄] = [−1.64, −3.33, 1.25, −1.37], small µ_o.

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0 2¹⁶ 2¹⁷

−4

−3

−2

−1 0 1 2

Sample number (n)

DC-offsetaccumulatoroutput

Figure 5.5: Convergence of the accumulator output. σ = 1,

[o1, o2, o3, o4] = [−1.64, −3.33, 1.25, −1.37], large µo.

5.1.2 Gain and timing mismatches - 2 ADCs

In this section the methods are tested for M = 2 using only static gain and timing mismatches (see section 2.2.2). The gain and timing mismatches are generated randomly according to:

g = U (0.9, 1.1)

∆_t Ts

= U (−0.1, 0.1) .

All methods are trained using sine-waves, single- or multi-tone depending on the compensation method. All methods are tested using single-tone sine-waves at frequencies between 0 and half the sample rate. White Gaussian noise is added to the input during training and testing, giving an SNR of 40 dB for single-tone sine-waves (the same amplitudes are used for each tone for multi-tone calibration).

The convergence parameters are chosen such that all parameters seemingly converge some- where after the first half of the training samples.

To compare the methods fairly (for a non-blind use) all methods are trained using the same number of samples, namely 2¹⁷. All methods are tested using Monte Carlo simulations with 100 runs. The methods are trained and tested using the same set of gain and timing mismatches, with uniquely generated data for training but the same data used for testing.

Figure 5.6 shows an annotated frequency spectrum of data simulated similarly to the test data of each method, at the frequency 0.4π.

Figure 5.25 compares the average SFDR improvement versus input frequency for the Monte Carlo simulations for all tested methods.

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0 π/4 π/2 3π/4 π

−180

−160

−140

−120

−100

−80

−60

Power(dB-scale)

Input signal Spurious tone

Figure 5.6: Power spectrum of a TI-ADC with M = 2. The input signal is a sine-wave input at frequency 0.4π.

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0 π/4 π/2 3π/4 π 0

20 40 60

SFDRimprovement(dB)

Figure 5.7: SFDR improvement vs frequency. Note that the performance of the methods [8] and [11] are highly over-lapping. The legend is appended below:

A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration [6]

All-Digital Background Calibration Technique for Time-Interleaved ADC Using Pseudo Aliasing Signal [7]

On Blind Identification of Gain and Timing Mismatches in Time-Interleaved Analog-to- Digital Converters [8]

Adaptive Blind Background Calibration of Polynomial-Represented Frequency Response Mismatches in a Two-Channel Time-Interleaved ADC [11]

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5.1.2.1 A 10-b 120-Msample/s time-interleaved analog-to-digital con- verter with digital background calibration [6]

This method is calibrated with a single sine-wave at 0.2π.

The convergence parameters used are µg = 6e-4, µ^t = 3e-4. The fractional-delay filter is re-designed for each new sample of the timing accumulator (see figure 3.3) by symmetrically truncating (using 51 taps) the true impulse response, which is [6]:

h[n] = − sin

π^∆_T^t

s

π

n −^∆_T^t

s

. (5.1)

Figure 5.8 shows the average SFDR improvement versus input frequency for the Monte Carlo simulations. Figure 5.9 shows the SFDR versus input frequency from one simulation. Figure 5.10 shows the parameter convergence from one simulation.

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0 π/4 π/2 3π/4 π 20

40 60

SFDRimprovement(dB)

µ µ ± σ

Figure 5.8: SFDR improvement vs frequency.

0 π/4 π/2 3π/4 π

20 40 60 80

SFDR(dB)

Before compensation After compensation

Figure 5.9: SFDR vs frequency.

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0 2¹⁶ 2¹⁷ 0

5 · 10⁻³ 0.01

Sample number (n)

Delayaccumulatoroutput

Estimated value Simulated value

0 2¹⁶ 2¹⁷

1 1.005 1.01 1.015 1.02

Sample number (n)

Gainaccumulatoroutput

Estimated value Simulated value

Figure 5.10: Parameter convergence.

5.1.2.2 All-Digital Background Calibration Technique for Time-Interleaved ADC Using Pseudo Aliasing Signal [7]

This method is calibrated with a single sine-wave at 0.2π. The convergence parameters used are µ_gk= 2⁻¹⁴, µ_gk= 2⁻¹⁵. The differentiator filter is designed using MATLABs [12] ”firpm” using 51 taps and a cut-off frequency of 0.9π.

Figure 5.11 shows the average SFDR improvement versus input frequency for the Monte Carlo simulations. Figure 5.12 shows the SFDR versus input frequency from one simulation.

Figure 5.13 shows the parameter convergence from one simulation.

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0 π/4 π/2 3π/4 π 20

40 60

SFDRimprovement(dB)

µ µ ± σ

0 π/4 π/2 3π/4 π

20 40 60 80

SFDR(dB)

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0 2¹⁶ 2¹⁷

−0.012

−0.01

−8 · 10⁻³

−6 · 10⁻³

−4 · 10⁻³

−2 · 10⁻³ 0 2 · 10⁻³ 4 · 10⁻³

Sample number (n)

Parameterconvergencevalue

ωt1

ωg1

5.1.2.3 On Blind Identification of Gain and Timing Mismatches in Time-Interleaved Analog-to-Digital Converters [8]

This method is calibrated with a multi-tone sine-wave and filter according to section 4.1 using l = 27. The LMS convergence-parameter used is µ = 2e-6. The differentiator filter is designed using MATLABs [12] ”firpm” using 51 taps and a cut-off frequency of 0.9π.

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0 π/4 π/2 3π/4 π 20

40 60

SFDRimprovement(dB)

µ µ ± σ

0 π/4 π/2 3π/4 π

20 40 60 80

SFDR(dB)

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0 2¹⁶ 2¹⁷

−0.012

−0.01

−8 · 10⁻³

−6 · 10⁻³

−4 · 10⁻³

−2 · 10⁻³ 0 2 · 10⁻³ 4 · 10⁻³ 6 · 10⁻³

Sample number (n)

Parameterconvergencevalue

ˆ cr[n]

ˆ c_g[n]

5.1.2.4 Adaptive Blind Background Calibration of Polynomial-Represented Frequency Response Mismatches in a Two-Channel Time-Interleaved ADC [11]

This method is calibrated with a multi-tone sine-wave and filter according to section 4.1 using l = 27. The polynomial order used is P = 2. The LMS convergence-parameter used is µ = 5e-6.

The differentiator filter is designed using MATLABs [12] ”firpm” using 51 taps and a cut-off frequency of 0.9π.

Digital compensation of nonidealities in time-interleaved ADCs