DIGITAL ON/OFF
AM MODULATOR
AMIT R SHARMA
&
AKRAM SHAZAD
AIM OF THE PROJECT
1. To Design a dedicated hardware module that performs on/off AM MODULATION.
2. The Modulated signal should be 8 bit sinus signal of 13.56 MHz (carrier freq).
3. The Amplitude of the carrier signal should be configured from microcontroller.
4. The maximum clock freq is 100 MHz.
What is on on/off AM Modulation. ?
• Modulation is the process of facilitating the transfer of information over a medium
• The process of converting information so that it can be successfully sent through a medium is called modulation
• In amplitude modulation the amplitude of the signal is changed in response to information and all else is kept fixed. (phase and freq)
REQUIRED WAVEORMS clk
i/p
o/p
No i/p
Bit stream from base band coder of 10ns.
WISHBONE INTERFACE
The output is a Sine wave With a carrier freq of 13.56 MHz
OSCILLATOR
MODULATOR
Design of Oscillator
• The clock freq is of 100 MHz and required freq of the carrier signal should 13.56 MHz hence we can have a maximum of 8 levels for defining a sine wave.
COUNTER
SINE LOOKUP
TABLE
WAVEOUT clock
Reset Enable
Amplitude
Time (ns)
/2 2
oscillator
MUX
0/1
Amplitude is controlled By microcontroller using
Wishbone interface
Low Amplitude Reg High amplitude Reg
Input data stream
1 2
s1
o/p
13.56 MHz
Idle mode Reg
s0 3
4
High amp
Low amp
Low high Idle low
00-idle low 01 idle high 10 ”0”
11 ”1”
H
L
H L
i/p bit stream
Check the I/p bit
IF i/p bit =1 IF No input
IF i/p bit=0
Sine wave generator Look up
table
select S0S1=’11’
OUT- A
select S0S1=’10
OUT- B
select S0S1=’01’
OUT-C
select S0S1=’00’
OUT- D
MUX
High Ampl Reg Const c1
Low Ampl Reg Const c2
Idle Ampl Reg Const c3
A B C D
SOS1
OUT
Loop- Repeat forOther bit
WISHBONE
RESULTS
•
Results from Matlab
RESULTS FROM VHDL SYNTHESIS REPORT
HDL Synthesis Report Macro Statistics
# FSMs : 1
# Multipliers : 2
8x8-bit multiplier : 2
# Adders/Subtractors : 2
7-bit adder : 1
1-bit addsub : 1
# Registers : 8
1-bit register : 6
8-bit register : 2
# Multiplexers : 3
1-bit 2-to-1 multiplexer : 1
8-bit 2-to-1 multiplexer : 1
16-bit 2-to-1 multiplexer : 1
Device utilization summary Selected Device: 3s4000fg900-5
Number of Slices: 11 out of 27648 0%
Number of Slice Flip Flops: 6 out of 55296 0%
Number of 4 input LUTs: 19 out of 55296 0%
Number of bonded IOBs: 11 out of 633 1%
Number of MULT18X18s: 2 out of 96 2%
Number of GCLKs: 1 out of 8 12%
Timing Summary Speed Grade: 5
Minimum period: 2.725ns (Maximum Frequency: 366.973MHz) Minimum input arrival time before clock: 3.470ns
Maximum output required time after clock: 11.521ns Maximum combinational path delay: 7.385ns
CONCLUSION
•
