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(1)

Access to on-chip test structures via functional buses

ERIK LARSSON

(2)

Semiconductors

CPU Memory

MBIST Interconnect

JTAG Interconnect Functional part

Test part

(3)

Standards

• IEEE Std. 1149.1 - Standard for Test Access Port and

Boundary-Scan Architecture - (Joint Test Action Group (JTAG))

(4)

IEEE Std. 1149.1

CPU Memory

MBIST Interconnect

JTAG TDR

Run MBIST

EDA

Protocol

Interconnect Interconnect

Description language

(5)

IEEE Std. 1149.1

CPU Memory

MBIST Interconnect

JTAG TDR

Run MBIST

EDA

HW for translation SW for

translation Protocol

Protocol

Protocol Interconnect Interconnect

Description language

Run MBIST

(6)

Standards

• IEEE Std. 1149.1 - Standard for Test Access Port and

Boundary-Scan Architecture - (Joint Test Action Group (JTAG))

• IEEE Std. 1687 - Standard for Access and Control of

Instrumentation Embedded within a Semiconductor Device - (Internal JTAG (IJTAG))

(7)

IEEE Std. 1149.1+1687

CPU Memory

MBIST Interconnect

JTAG TDR

Run MBIST

EDA

HW for translation SW for

translation Protocol

Protocol

Protocol

Interconnect 1687

Description languages

Run MBIST

(8)

Standards

• IEEE Std. 1149.1 - Standard for Test Access Port and

Boundary-Scan Architecture - (Joint Test Action Group (JTAG))

• IEEE Std. 1687 - Standard for Access and Control of

Instrumentation Embedded within a Semiconductor Device - (Internal JTAG (IJTAG))

IEEE Std. P1687.1 - Standard for the Application of Interfaces and Controllers to Access 1687 IJTAG Networks Embedded Within Semiconductor Devices

(9)

IEEE Std. 1149.1+1687+1687.1

CPU Memory

MBIST Interconnect

F.P. TDR

Run MBIST

EDA

HW for translation SW for

translation Protocol

Protocol

Protocol

Interconnect 1687

Description languages

Functional port

HW Run MBIST

X

(10)

HW5

HW4

HW3HW2

0 HW1

200000 400000 600000 800000 1000000 1200000 1400000 1600000 1800000

50 100 150

Number of transported bits

Number of instruments

HW2 HW3

HW1

0 5000 10000 15000 20000 25000

50 100 150

Number of transported bits

Number of instruments

CPU Memory

MBIST Interconnect

F.P. TDR

Interconnect HW 1687

How much data?

All five HW solutions Top HW 3 solutions Protocol

(11)

Standards

• IEEE Std. 1149.1 - Standard for Test Access Port and

Boundary-Scan Architecture - (Joint Test Action Group (JTAG))

• IEEE Std. 1687 - Standard for Access and Control of

Instrumentation Embedded within a Semiconductor Device - (Internal JTAG (IJTAG))

IEEE Std. P1687.1 - Standard for the Application of Interfaces and Controllers to Access 1687 IJTAG Networks Embedded Within Semiconductor Devices

IEEE Std. P2654 - Standard for System Test Access

Management (STAM) to Enable Use of Sub-System Test Capabilities at Higher Architectural Levels - (System JTAG (SJTAG))

(12)

IEEE Std. 1149.1+1687+1687.1+2654

CPU Interconnect

F.P.

Run MBIST

EDA

Protocol

1687 HW

Memory

MBIST

F.P. TDR

HW F.P. HW 1687

Protocol Run MBIST

X

(13)

IEEE Std. 1149.1+1687+1687.1+2654

CPU Interconnect

F.P.

Run MBIST

EDA

1687 HW

Memory

MBIST

F.P. TDR

HW F.P. HW 1687

MBIST response

X

Polling Interrupt

(14)

Data overhead

INTERRUPT POLLING INTERRUPT POLLING INTERRUPT POLLING 50 INSTRUMENTS 100 INSTRUMENTS 150 INSTRUMENTS

(15)

Shared access to test structures

CPU Memory

MBIST Interconnect

JTAG Interconnect Functional part

Test part Run MBIST

Run MBIST

(16)

Advanced eXtensible Interface (AXI)

CPU Run

MBIST

EDA

1687 JTAG

Memory

MBIST TDR HW

Run MBIST

TDR M

M

S

S Run MBIST AXI

(17)

Some future perspectives

CPU Run

MBIST

EDA

1687 JTAG

Memory

MBIST TDR HW

Run MBIST

TDR M

M

S

S AXI

Run MBIST

(18)

Our papers

• Functional port instead of JTAG – IEEE Std. P1687.1

– Erik Larsson, Prathamesh Murali & Gani Kumisbek, IEEE Std. P1687.1:

translator and protocol, 2019, International Test Conference.(paper)(presentation)

– Erik Larsson, Zilin Zhang & Prathamesh Murali, Accessing general IEEE Std. 1687 networks via functional ports, 2021, International Test Conference (paper)(video)

• Test and secure network of instruments

– Erik Larsson, Zehang Xiang & Prathamesh Murali, Graceful Degradation of Reconfigurable Scan Networks, 2021 May 27, In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 29, 7, p. 1475-1479.

(paper)(video)

• Board-level access – IEEE Std. P2654

– Erik Larsson, Shashi Kiran Gangaraju & Prathamesh Murali, System-Level Access to On-Chip Instruments, 2021 Apr 1, IEEE European Test

Symposium (ETS). p. 1-6. (paper)(video)

(19)

IEEE-SA Test Technology Standards Committee (Chair Ian McIntosh)

IEEE Std 1149.1 “Standard for Test Access Port and Boundary-Scan Architecture” expires at the end 2023.

• Contact Heiko Ehrenberg (h.ehrenberg@goepelusa.com) to join the group or for further details.

IEEE Std 1687 “Standard for Access and Control of

Instrumentation Embedded within a Semiconductor Device”

expires at the end of 2024.

• Contact Jeff Rearick (Jeff.Rearick@amd.com) to join the group or for further details.

(20)

Access to on-chip test structures via functional buses

ERIK LARSSON

References

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