Automotive Radar Demonstrator : Phase-locked loop and filterdesign

Full text

(1)LiU-ITN-TEK-A--09/029--SE. Automotive radar demonstrator Nima Parash Par 2009-05-08. Department of Science and Technology Linköping University SE-601 74 Norrköping, Sweden. Institutionen för teknik och naturvetenskap Linköpings Universitet 601 74 Norrköping.

(2) LiU-ITN-TEK-A--09/029--SE. Automotive radar demonstrator Examensarbete utfört i Elektronikdesign vid Tekniska Högskolan vid Linköpings universitet. Nima Parash Par Handledare Lars Pettersson Handledare Duncan Platt Examinator Adriana Serban Craciunescu Norrköping 2009-05-08.

(3) Upphovsrätt Detta dokument hålls tillgängligt på Internet – eller dess framtida ersättare – under en längre tid från publiceringsdatum under förutsättning att inga extraordinära omständigheter uppstår. Tillgång till dokumentet innebär tillstånd för var och en att läsa, ladda ner, skriva ut enstaka kopior för enskilt bruk och att använda det oförändrat för ickekommersiell forskning och för undervisning. Överföring av upphovsrätten vid en senare tidpunkt kan inte upphäva detta tillstånd. All annan användning av dokumentet kräver upphovsmannens medgivande. För att garantera äktheten, säkerheten och tillgängligheten finns det lösningar av teknisk och administrativ art. Upphovsmannens ideella rätt innefattar rätt att bli nämnd som upphovsman i den omfattning som god sed kräver vid användning av dokumentet på ovan beskrivna sätt samt skydd mot att dokumentet ändras eller presenteras i sådan form eller i sådant sammanhang som är kränkande för upphovsmannens litterära eller konstnärliga anseende eller egenart. För ytterligare information om Linköping University Electronic Press se förlagets hemsida http://www.ep.liu.se/ Copyright The publishers will keep this document online on the Internet - or its possible replacement - for a considerable time from the date of publication barring exceptional circumstances. The online availability of the document implies a permanent permission for anyone to read, to download, to print out single copies for your own use and to use it unchanged for any non-commercial research and educational purpose. Subsequent transfers of copyright cannot revoke this permission. All other uses of the document are conditional on the consent of the copyright owner. The publisher has taken technical and administrative measures to assure authenticity, security and accessibility. According to intellectual property law the author has the right to be mentioned when his/her work is accessed as described above and to be protected against infringement. For additional information about the Linköping University Electronic Press and its procedures for publication and for assurance of document integrity, please refer to its WWW home page: http://www.ep.liu.se/. © Nima Parash Par.

(4) Abstract As technique and requirement of today’s products keeps expending, Acreo AB has been researching for automotive radar that fulfills these requirements, e.g. higher resolution, faster system and lower cost. The purpose of this master thesis work has been to evaluate a previous design and implement changes. The work has resulted in a PCB card that will be used to compare the performance between two radar modules. The demonstrator has been developed in two versions – first based on the existing GaAschipset (Gallium Arsenide) and a second with the inclusion of a low cost SiGe-chipset (Silicon Germanium). The outcome of this work proves that some requirements cannot be fulfilled and therefore a nextgeneration radar demonstrator has been proposed. The new radar demonstrator includes changes that can fulfill the requirements.. i.

(5) Acknowledgments I would sincerely like to thank all employees at Acreo AB’s office in Norrkoping for their friendly welcoming and their assist for completing this thesis work. Especially thanks to my supervisors Lars Petterson and Duncan Platt for their help and support. I would also like to thank Oscar Eriksson and Johnny Svensson for their previous thesis on the radar demonstrator, which has helped me through this master thesis. My examiner Adriana Serban has been helpful all the way through my thesis and I am grateful for all her support and our long discussions. My final thanks go to my friends and family contributing with interest in my thesis work.. -. Nima Parash Par May, 2009. ii.

(6) To my family. iii.

(7) Table of Contents Chapter 1. Introduction ......................................................................................................................... 1. 1.1. Background ............................................................................................................................. 1. 1.2. Goal ......................................................................................................................................... 1. 1.3. Method..................................................................................................................................... 1. 1.4. Outline ..................................................................................................................................... 2. Chapter 2 2.1. Radar Systems ..................................................................................................................... 3 Radar Equation ........................................................................................................................ 3. 2.1.1. Frequency Modulation..................................................................................................... 7. 2.1.2. Frequency-Modulated Continues-Wave Radars .............................................................. 8. 2.2. The Phase-Locked Loop ........................................................................................................ 11. 2.2.1. Phase Detector ............................................................................................................... 12. 2.2.2. Loop-Filter..................................................................................................................... 14. 2.2.3. Voltage-Controlled Oscillator ....................................................................................... 16. Chapter 3. The Radar demonstrator .................................................................................................... 17. 3.1. Radar Block Diagram ............................................................................................................ 17. 3.1.1. SiGe-Module ................................................................................................................. 18. 3.1.2. The IF-filter ................................................................................................................... 19. 3.1.3. USB Interface ................................................................................................................ 19. 3.1.4. Frequency Synthesizer................................................................................................... 20. 3.1.5. PLL ................................................................................................................................ 20. 3.1.6. The loop-filter................................................................................................................ 21. 3.1.7. DDS Firmware Update .................................................................................................. 22. 3.2. Design requirements .............................................................................................................. 22. 3.2.1. FMCW-specification ..................................................................................................... 22. 3.2.2. Input Power specification .............................................................................................. 24. Chapter 4. Circuit design and Simulation Results .............................................................................. 25. 4.1. IF-filter Design ...................................................................................................................... 25. iv.

(8) 4.2. Loop-filter Design ................................................................................................................. 26. 4.3. The 3rd-Order Chebyshev-Filter ............................................................................................ 28. 4.4. DDS Firmware ...................................................................................................................... 29. Chapter 5. Discussion ......................................................................................................................... 31. 5.1. PLL and Loop-Filter .............................................................................................................. 31. 5.2. The IF filter ........................................................................................................................... 32. 5.3. PCB ....................................................................................................................................... 33. Chapter 6. Next Generation................................................................................................................. 35. Chapter 7. Conclusion ......................................................................................................................... 36. v.

(9) List of Figures FIGURE 1 -. ILLUSTRATION OF THE RADAR PRINCIPLE ..................................................................................................................... 3. FIGURE 2 -. ARCHITECTURE OF BASIC RADAR .................................................................................................................................... 4. FIGURE 3 -. ANTENNA ARRAY (SIDE VIEW) WITH ILLUSTRATION OF 90˚ RADIATION, W (WIDTH) D (SPACING) H (HEIGHT) . 4. FIGURE 4 -. 8 BY 1 ANTENNA ARRAY LAYOUT ....................................................................................................................................... 4. FIGURE 5 -. RADIATION OF THE ANTENNA ARRAY .............................................................................................................................. 5. FIGURE 6 THE USE OF A DUPLEXER AND A COMMON ANTENNA TO A TRANSMITTER AND A RECEIVER WITH ISOLATION BETWEEN THE TWO........................................................................................................................................................................................ 5 FIGURE 7 -. ILLUSTRATION OF A MIXER ............................................................................................................................................... 6. FIGURE 8 -. FREQUENCY MODULATED TRIANGULAR WAVE............................................................................................................. 7. FIGURE 9 -. THE TRANSMITTED AND RECEIVED SIGNAL ................................................................................................................... 7. FIGURE 10 -. TRIANGULAR WAVEFORM .................................................................................................................................................. 8. FIGURE 11 -. DOPPLER SHIFTED TRIANGULAR WAVE.......................................................................................................................... 9. FIGURE 12 -. THE RELATION BETWEEN THE BEAT AND DOPPLER FREQUENCY ............................................................................. 9. FIGURE 13 -. ILLUSTRATION OF THE R-V RELATION WITH ONE OJBECT PRESENT ....................................................................... 10. FIGURE 14 -. THE PRESENT OF GHOST TARGETS ................................................................................................................................ 10. FIGURE 15 -. ALTERNATIVE FMCW SWEEP TIME ................................................................................................................................. 11. FIGURE 16 -. ILLUSTRATION OF ELIMINATION OF GHOST TARGETS ............................................................................................... 11. FIGURE 17 -. BASIC PLL ARCHITECTURE .............................................................................................................................................. 11. FIGURE 18 -. FREQUENCY SYNTHEZISER ARCHITECTURE ................................................................................................................ 12. FIGURE 19 -. THE OUTPUT OF THE PHASE DETECTOR ...................................................................................................................... 12. FIGURE 20 -. ERRORSIGNAL OF THE PHASE DETECTOR .................................................................................................................... 13. FIGURE 21 -. (A) RS FLIP-FLOP PHASE DETECTOR AND (B) WAVEFORMS ...................................................................................... 13. FIGURE 22 -. BASIC MIXER (A) WITH BLOCK REPRESENTATION (B) ................................................................................................. 14. FIGURE 23 -. INTEGRATION OF THE ERROR SIGNAL........................................................................................................................... 14. FIGURE 24 -. PASSIVE LAG-LEAD LOOP-FILTER .................................................................................................................................. 15. FIGURE 25 -. BLOCK DIAGRAM OF THE RADAR ................................................................................................................................... 17. FIGURE 26 -. ILLUSTRATION OF HOW THE CLOCK FREQUEYNCY WILL CAUSE A LAG IN THE SYSTEM .................................... 19. FIGURE 27 -. IF MIXER ............................................................................................................................................................................. 19. FIGURE 28 -. FRACTIONAL DIVIDER, THE DDS USED AS PLL ............................................................................................................ 20. FIGURE 29 -. PLL CIRCUITRY OF THE SYNTHESIZER .......................................................................................................................... 21. FIGURE 30 -. ACTIVE LOOP-FILTER ....................................................................................................................................................... 21. FIGURE 31 -. BLOCK REPRESANTATION OF THE FMCW SIGNAL GENERATION ............................................................................. 22. vi.

(10) FIGURE 32 -. THE DDS AND PLL ............................................................................................................................................................. 23. FIGURE 33 -. FFT POINTS OF A TRIANGULAR WAVE ........................................................................................................................... 23. FIGURE 34 -. LINEAR VS NONLINEAR FMCW WAVEFORM .................................................................................................................. 23. FIGURE 35 -. THE IF-FILTER: (A) SCHEMATICS AND (B) SIMULATION RESULTS ............................................................................ 26. FIGURE 36 -. EXEMPLE OF LPF DESIGNED WITH ADISIMPLL ........................................................................................................... 27. FIGURE 37 -. RESULT OF A LOW-PASS-FILTER DESGINED WITH ADISIMPLL ................................................................................. 27. FIGURE 38 -. THE ACTIVE LOOP-FILTER ............................................................................................................................................... 27. FIGURE 39 -. THE TIME DOMAIN SIMULATION OF ACTIVE FILTER .................................................................................................. 28. FIGURE 40 -. SIMULATION RESULT OF THE ACTIVE LOW PASS FILTER .......................................................................................... 28. FIGURE 41 -. SCHEMATIC LAYOUT OF 3RD ORDER CHEBYSHEV FILTER .......................................................................................... 29. FIGURE 42 -. SIMULATIONS OF THE 3RD ORDER CHEBYSHEV FILTER.............................................................................................. 29. FIGURE 43 - LEFT FIGURE IS THE OUTPUT OF THE PLL, THE RIGHT FIGURE IS THE FREQUENCY ERROR ON THE INPUT OF THE PLL. PICTURES TAKEN FROM THE ADISIMPLL APPLICATION................................................................................................ 32 FIGURE 44 -. ILLUSTRATION OF THE PCB CARD ................................................................................................................................. 33. FIGURE 45 -. ILLUSTRATION OF THE PCB CARD FOR PLUTO MODULE .......................................................................................... 34. FIGURE 46 -. FINAL PCB CARD FOR PLUTO MODULE ........................................................................................................................ 34. vii.

(11) Abbreviation Abbreviation. Explanation. µC. Micro Controller. ADC. Analog-to-Digital Converter. aPLL. Analog Phase-Locked loop. DDS. Direct Digital Synthesizer. DSP. Digital Signal Processor. FFT. Fast Fourier Transform. FM. Frequency Modulated. FMCW. Frequency Modulated Continues-Wave. FTW. Frequency Tuning Word. GaAs. Gallium Arsenide. GUI. Graphical User Interface. IC. Integrated Circuit. IF. Intermediate Frequency. IIP3. 3rd Order Input Intercept Point. LDO. Low Dropout Regulator. LPF. Low-Pass Filter. PCB. Printed Circuit Board. PD. Phase Detector. PLL. Phase-Locked Loop. SiGe. Silicon Germanium. VCO. Voltage-Controlled Oscillator. viii.

(12) Chapter 1 Introduction 1.1 Background The use of radar systems in a variety of automotive applications has increased in the past few years. For example, radar systems can be used in Anti-Collision (AC) and in Adaptive Cruise Control (ACC) systems. This is also the field in which Acreo AB has increased its leading role recently with focus on high-performance and low-cost solutions. 79 GHz Frequency-Modulated Continuous Wave radar module by Acreo includes the new Silicon Germanium (SiGe) integrated circuit (IC) and advanced antenna technology. Using SiGe technology, high-cost Gallium Arsenide (GaAs) implementations are avoided.. 1.2 Goal The goal of this master thesis is the design, fabrication and evaluation of a radar demonstrator. A previous design [12] was used as a start point for analysis and redesign of the new system. The new radar specifications are • Center frequency, f0 = 79 GHz • Frequency sweep, ∆f = 4 GHz • Sweep times, Tm = 50 µs, 100 µs and 4 ms • Intermediate frequency band, fIF = [0.001 – 10] MHz • Higher input stability. 1.3 Method Theory study on radar systems and phase-locked loop circuits was performed. Electronic design automation (EDA) tools such as Cadence OrCAD and pSpice were used to do the design from initial simulations to final layout. The phase-locked loop was designed and simulated with ADiSIM from Analog Devices[10]. The design process is mainly carried out in three steps, schematic level, simulations and finally printed circuit board (PCB) layout.. 1.

(13) 1.4 Outline This report is organized as follows: •. Chapter 2 consists of the basic theory used in this thesis work. This will introduce the basic concept behind radar used in automotive applications and the basic theoretical background about phase-locked loops. •. Chapter 3 presents the block diagram of the radar module. •. Chapter 4 covers the design flow from specifications to implementation on layout level. •. Chapter 5 displays the simulation results for the designed blocks. •. Chapter 6 contains the next generation proposals. •. Chapter 7 presents the conclusions. 2.

(14) Chapter 2 Radar Systems Radar has been used for a long time to detect moving or stationary objects and also to identify their range, altitude, direction and speed. The development of radar – radar stays for Radio Detection and Ranging – started 1904 with Christian Hülsmeyer’s work who demonstrated the feasibility of detecting objects by using radio waves. [1] The first radar system was used as an anti-collision detector for ships, but has over the years been improved to detect in both vertically and horizontally direction, moving or stationary objects and even multiple objects. The radar is used in many applications, such as basic anti-collision applications in Ships and Automotives to more advanced and sophisticated applications used in airplanes and combat aircrafts.. 2.1 Radar Equation The detection of an object using radar is based on transmitting an electromagnetic wave (carrier wave) with the use of an antenna. The wave will be reflected on an object and received by the antenna as illustrated in Figure 1. The reflected wave (echo signal) is then further used to determine the speed and range of the object [2].. Figure 1 -. ILLUSTRATION OF THE RADAR PRINCIPLE. The frequency difference between the echo signal and carrier wave is caused by the relative velocity of an object (Doppler Effect). The time delay between the carrier wave and echo signal corresponds to the distance to the object [3]. A basic radar consists of an antenna, transmitter / receiver, decoder, waveform generator and a graphical unit as illustrated in Figure 2.. 3.

(15) Figure 2 -. ARCHITECTURE OF BASIC RADAR. The antennas main purpose is to convert electrical signals into electromagnetic waves, and vice versa. The usual transistor radio (FM/AM receiver) use one antenna to receive an electromagnetic wave, while the advanced radar use antenna arrays to receive and transmit signals. The antenna array can be designed to radiate in either broadside (i.e. radiation perpendicular to array orientation, which is the zaxis as illustrated in figure 3) or end fire (i.e. radiation in the same direction as the array orientation, which is the y-axis) [4]. In this thesis, only the broadside antenna arrays will be discussed. To give an equally distributed radiation, each antenna in the array will be designed with equal spacing and dimensions, (as illustrated in figure 3).. Figure 3 -. ANTENNA ARRAY (SIDE VIEW) WITH ILLUSTRATION OF 90˚ RADIATION, W (WIDTH) D (SPACING) H (HEIGHT). Figure 4 -. 8 BY 1 ANTENNA ARRAY LAYOUT. 4.

(16) The radiation pattern of an antenna shows where the radiation is concentrated as most, as illustrated in Figure 5.. Figure 5 -. RADIATION OF THE ANTENNA ARRAY. The source of the electrical current to the antenna is generated within the transmitter, by means of a modulator circuit. To be able to transmit the signal for long distance, the signal will be then amplified by a power amplifier, as the signal travels through a medium, it loses power.. Figure 6 -. THE USE OF A DUPLEXER AND A COMMON ANTENNA TO A TRANSMITTER AND A RECEIVER WITH ISOLATION BETWEEN THE TWO.. On the receiving part a low-noise amplifier (LNA) amplifies the signal and reduces the unwanted high-frequency noise. This noise in the received signal contributes to a false view of the object. For a radar system with the transmitter and receiver in the same location, the radar equation is given by [5]: . . 4

(17) . where •. Pt = transmitter power. •. Gt = gain of the transmitter. •. Ar = effective aperture (area) of the receiving antenna 5.

(18) •. σ = radar cross section, or scattering coefficient, of the target. •. F = pattern propagation factor. •. R = distance from the transmitter and receiver to the target. This shows that the received power declines as the fourth power of the distance, which means that the reflected power from distant targets is relatively small. The distance and velocity of a detected object can be found by studying the frequency change and the time delay between the transmitted and received signals. The frequency change i.e. the frequency difference between the transmitted signal and the received signal can be determined by using a mixer [6], as shown in Figure 7.. Figure 7 -. ILLUSTRATION OF A MIXER. The mixer multiplies two sinusoidal signals and produced the difference and sum of the transmitted and received signal. Consider the transmitted and received signals: sin sin . where AT, AR and 2

(19) , 2

(20) are the amplitude and the angular frequency of the transmitted and received signals.. By using the trigonometric identity: 1 sin · sin cos " " cos # $ 2 the mixer output of two sinusoidal signals becomes: · . cos " " cos # $ 2. After low-pass filtering the output signal is: %& . cos " cos 2

(21) ∆ 2 2 6.

(22) With this solution, both the difference and the sum components can be found. By using a graphical unit interface (GUI) or an oscilloscope both frequency components can be seen. Some radar application has a GUI that displays the object with distance, size and velocity. The GUI often consists of a digital signal processor (DSP) and an analog/digital converter (ADC) that converts mixer output signal into a digital signal that can be processed by the GUI. 2.1.1. Frequency Modulation. To be able to detect a stationary object, a frequency modulated (FM) wave is used. This technique is also called FM-ranging. A FM signal with a linearly variation in the frequency is called a chirp1 signal. In figure 8 the principal of a chirp is shown, including the bandwidth ∆f and sweep time Tm [2] [7].. Figure 8 -. FREQUENCY MODULATED TRIANGULAR WAVE. By using a receiving antenna, the echo signal 2 from the object can be detected. The echo signal is then compared with the transmitted signal and by various calculations the distance to the object can be calculated. The echo signal received by the antenna from a stationary object will be delayed with 2R/c as illustrated in Figure 9, where R is the distance to the target and c is the speed of light in vacuum.. Figure 9 -. THE TRANSMITTED AND RECEIVED SIGNAL. The delay between the transmitted and received signals is called the beat frequency (fb) and can be calculated as follows:. 1 2. Chirp is a term used to describe a linear frequency sweep. Echo signal is the wave that “bounces” on a target, back to the transmitter.. 7.

(23) Consider the transmitted signal as: ( # ) · Where α is the chirp rate of the transmitted signal and f1 the starting frequency (at t=0) The received signal delayed with τ is given by ( # ) " * The beat frequency fb can be calculated as + " ( # ) · " ,( # ) " * - ), " " * - ) · * Where ). ∆ ./. *. 2 0. and. Finally, the distance (R) to the object can be calculated with the radar range equation 0 + ./ 2 ∆ 2.1.2. Frequency-Modulated Continues-Wave Radars. In automotive radars, both the distance to an object and its velocity are required. A single up-sweep of the chirp signal as discussed in the previous section is not sufficient to detect both velocity and distance. If the FM-ranging is enhanced with a down-sweep, as illustrated in Figure 10, a triangular wave is generated.. Figure 10 -. TRIANGULAR WAVEFORM. 8.

(24) An object in movement will cause the triangular wave to Doppler shift, as illustrated in Figure 11.. Figure 11 -. DOPPLER SHIFTED TRIANGULAR WAVE. The beat frequency + and the frequency of the Doppler shifted wave 1 can be used to determine both the distance and the relative velocity to an object. Figure 12 shows the linear relationship between ∆(, ∆ as defined in Figure 11 and + , 1 .. Figure 12 -. THE RELATION BETWEEN THE BEAT AND DOPPLER FREQUENCY. The cross point between these two lines, equals to a solution for fb and fd. ∆( # ∆ 2 ∆ " ∆( 1 2 + . The range equation for radar can now be used to calculate the distance to the object in movement 0 + 0 ∆( # ∆ ./ ./ 2 4 ∆ 2 As mentioned previously, the Doppler shift of the wave is caused by the relative velocity of the object. The current frequency will be Doppler shifted with v/λ to fd, where v is the relative velocity and λ is the wavelength of the carrier signal. As the wave travels two ways the total Doppler shift becomes: 9.

(25) 1 2. 3. From this equation the relative velocity of the object in movement can be found: . 1 3 2. However, the regular triangular wave method can cause problems when multiple objects are present, e.g. false objects can be identified by the radar. The relation between the distance (R) and the velocity (v), graphically illustrated in Figure 13, can be useful when finding a solution for the multiple objects identification.. Figure 13 -. ILLUSTRATION OF THE R-V RELATION WITH ONE OJBECT PRESENT. When multiple objects are present, the R-v relation will change and the false targets, also known as ghost targets, will appear, as illustrated in Figure 14.. Object 1 Object 2 Real Object Ghost Object. Figure 14 -. THE PRESENT OF GHOST TARGETS. To minimize the ghost targets the triangular wave can be alternated with different sweep times (Tm), as illustrated in Figure 15.. 10.

(26) Figure 15 -. ALTERNATIVE FMCW SWEEP TIME. The alternating FMCW sweeps will generate more R-v slopes that eliminate the ghost targets, as illustrated in figure 16.. Object 1 Object 2 Real Object. Figure 16 -. ILLUSTRATION OF ELIMINATION OF GHOST TARGETS. 2.2 The Phase-Locked Loop Phase-locked loop (PLL) circuits are used for high frequency signal generation that has a fixed relation to the phase and frequency of a reference signal. The reference signals often consist of a simple sinusoidal wave generated by an oscillator with a desired frequency [8] [9]. A basic PLL consist of a phase detector (PD), loop-filter and a voltage-controlled oscillator (VCO).. Figure 17 -. BASIC PLL ARCHITECTURE. 11.

(27) Figure 18 -. FREQUENCY SYNTHEZISER ARCHITECTURE. The principle of a basic PLL can be described as follows: The frequency and phase of two signals are compared and an error signal is generated, where the error signal is proportional to the phase difference between the two input frequencies. The error signal is then low pass filtered and converted into a voltage level that drives a VCO. The VCO will either increase or decrease the frequency of the output signal depending on the error signal. To be able to drive the VCO to the correct output frequency, the generated signal is used as a feedback signal and compared with the reference signal. 2.2.1. Phase Detector. The phase and frequency detector (PFD) is often a mixer (analog) or a D-flip-flop based PFD (digital). The PFD output corresponds to the phase difference (error) between the reference and feedback signals.. Figure 19 -. THE OUTPUT OF THE PHASE DETECTOR. The error signal tells us how much the VCO output (which is the PLL output) differs in phase and frequency compared to the reference. Three cases can be identified: (I) the reference signal leads the feedback signal, (II) the reference signal lags the feedback signal and (III) the reference and feedback signal have the same frequency while their phase difference is small and constant.. 12.

(28) Figure 20 -. ERRORSIGNAL OF THE PHASE DETECTOR. To get the same phase and desired frequency at the output, the frequency of the VCO is slightly adjusted, depending on the error signal, to either increase or decrease. This is achieved by converting the error signal into a voltage level that drives the VCO to either increase or decrease the output frequency. When integrated on an IC, most common phase detectors have a charge pump3 circuit. It converts the voltage error signal from the PFD into a current pulse driving the loop-filter. A simple RS flip flop triggered by the input signals A and B is illustrated in Figure 21. The output of the flip flop is a result of the time difference between changes on A and B, which equals to the phase difference of the signals. If A is triggered as 1, the state on Q will be 1, if B triggers 1, the state of Q will be 0, creating a pulse corresponding to the error signal.. Figure 21 -. (A) RS FLIP-FLOP PHASE DETECTOR AND (B) WAVEFORMS. If the signals to be compare consist of sinusoidal waves not digital, an analog PFD is used, e.g. a mixer. A basic mixer consists of only a resistor and a diode that will output the difference and the sum of two signals frequencies, as discussed in Chapter 2 part 1.. 3. A charge pump consist of transistors that source or sinks a capacitor. The transistors work as a switch that either source current to the capacitor, or sinks current from the capacitor to ground.. 13.

(29) Figure 22 -. BASIC MIXER (A) WITH BLOCK REPRESENTATION (B). Two sinusoidal waves will be injected through the resistor, and the non-linearity of the diode will produce the difference- and sum frequency and with filtering the output signal will contain an undesirable DC component and the desired difference frequency. The structure of the simple mixer can be enhanced into a more complex architecture and it can be developed into more advanced balanced mixer that will filter the output of the simple mixer and only output the desired difference-frequency. 2.2.2. Loop-Filter. The VCO needs to be driven by a control signal to either increase or decrease the output frequency. This is achieved with an either complex or a simple loop-filter. A possible loop-filter is shown in Figure 23. It consists of a resistor and capacitor that integrates the error signal coming from the PFD and charge pump circuit.. Figure 23 -. INTEGRATION OF THE ERROR SIGNAL. The loop-filter characteristics determine how fast a PLL will be able to achieve lock. Passive loop-filters, or low-pass filters, can have different topologies with different characteristics. An useful low-pass filter is showed in Figure 24.. 14.

(30) Figure 24 -. PASSIVE LAG-LEAD LOOP-FILTER. The transfer function for the passive filter is 4 . 5 # 1/ 74 1 # 74 1 # * 4 1 # 4/8 5( ( # # 1/ 74 1 # ( # 74 1 # *( 4 1 # 4/9. where *( :. 1 ( # 74 9. and * :. 1 74 8. Some important PLL parameters determined by the loop-filter transfer function are the stability of the PLL, damping factor (;), natural angular frequency (< ) and the PLL bandwidth. Once determined,. these parameters can be used to predict the lock-time of the PLL and the stability of the loop. The natural frequency < can be calculated with:. >9 >? < = *(. Where >9 is the PFD gain and >? is the VCO gain. And the damping factor can be calculated with: ;. 1 < * # 2< *( 2. The loop-filter can also be implemented as an active filter. An active filter commonly consist of an operational amplifier combined with a passive (RC, RL, RLC) network. The operational amplifier will 15.

(31) provide voltage gain, while the passive network provides frequency stability and defines the filter transfer function. However, there are some drawbacks when using an active filter, e.g. input noise will be amplified. The draw-back of passive filters is that the PLL systems characteristics are depended on the values of the passive components in the loop-filter. There is a trade-off between the natural frequency, loop bandwidth and the lock speed, which is depended on these values. When designing a fast PLL the lock speed needs to be small which will cause the natural frequency to be increased, but to be able to get a higher natural frequency, the bandwidth of the loop has to increase. To increase the bandwidth of the PLL to a very high bandwidth, the values of the components has to be decreased down to sizes (such as 10-3 Ω and 10-15 farad) that are practically impossible to realize with discrete components4. Instead of using passive components, an active component (amplifier) with a complex network of discrete components will be able to draw the lock time down to values lower than realizable with passive filter, due to a high gain introduced by the amplifier. 2.2.3. Voltage-Controlled Oscillator. A voltage-controlled oscillator (VCO) is an adjustable oscillator that can output a signal of variable frequencies. By changing the control voltage, VTUNE the frequency of the output signal can vary between fmin and fmax. In most common analog PLL (aPLL) circuits, the VCO tuning voltage operates between 0 V and 5 V; where 0 V represent the minimum frequency and 5 V the maximum frequency.. 4. Discrete components is a electrical component, other than integrated circuits (IC). 16.

(32) Chapter 3 The Radar demonstrator 3.1 Radar Block Diagram The block diagram of the radar demonstrator illustrated in Figure 25 consists of the SiGe-radar module, the IF-filter, the IF-mixer, the USB interface, the synthesizer, the VCO, the Multiplier amplifier block, crystal oscillators and the loop-filter. SMA contacts of 50Ω impedance can be used between the loop-filter and the VCO for feeding externally generated triangular wave to the VCO or replacing the available loop-filter with an external loop-filter. Another SMA contact is used between the VCO and synthesizer to measure the output frequency of the VCO. In previous radar module, the IF signal from the mixer was converted to a digital signal and then processed in an external digital signal processor (DSP) for graphical representation of the analog signals. Here, as the main purpose of the new design is to prove the performance of the SiGe-module, the use of an Analog/Digital-converter is neglected and replaced by an oscilloscope.. Figure 25 -. BLOCK DIAGRAM OF THE RADAR. 17.

(33) 3.1.1. SiGe-Module. The SiGe-module designed by Acreo AB is a project which evaluates a new IC-technology for radar systems. Thus, circuits on SiGe substrate are compared to more common solutions on standard GaAs substrate. The new IC-technology may enable highly integrated, low cost radar solutions. The SiGe-module consists of a VCO chip, frequency multipliers, power amplifiers, antenna arrays for transmitter and receiver, mixers and power splitters. The VCO chip is developed by United Monolith Semiconductors (UMS), to match requirements of the center frequency and frequency span. The VCO is a MMIC (Monolith Microwave Integrated Circuit) operating at center frequency of 13.165 GHz with a frequency range of 640 MHz. It also includes a programmable divider with divide ranges between 8 and 128. The frequency multiplier is used to multiply a base frequency with a predetermined number. To raise the VCO center frequency to the required Radar center frequency, the VCO needs to be multiplied with an integer. The receiving antenna is system consists of several channels. Each receiving channel includes a frequency multiplier, mixer and an antenna array. As discussed previously, the transmitted signal and the received signal are injected in the mixer, providing the desired beat frequency. The transmitting channel consists of frequency multipliers, an antenna array and power amplifiers that increase the signal level before transmitting, making it possible to transmit for longer distances. . Due to the high frequency and high transmitting power, some of the transmitted signal will be reflected back to the VCO and interfere with the receiver. By using power splitters the transmitted signal will be isolated from the receiver. The oscillator for the USB interface is chosen to generate a sinusoidal signal with the frequency of 24 MHz as recommended by the USB chip manufacturer. In order to optimize the Synthesizer current operation, a clock frequency of 100 MHz was chosen. In Figure 26, the frequency response of the Synthesizer is shown. A settling time of 10 ns is found for a clock signal of 100 MHz.. 18.

(34) Figure 26 -. 3.1.2. ILLUSTRATION OF HOW THE CLOCK FREQUEYNCY WILL CAUSE A LAG IN THE SYSTEM. The IF-filter. The main purpose of the IF-filter is to filter the output signal of the IF-mixer, as depicted in Figure 27. The power and the frequency of the echo signal will change as the distance to the object increase, due to the propagation in air. This will cause a power change according to the Radar Equation. To compensate for the power loss, the IF filter should be designed to amplify with 20 db/decade in the IF frequency range (0.001 to 10 MHz). The block schematics of the IF filter will be discussed in the next Chapter.. Figure 27 -. 3.1.3. IF MIXER. USB Interface. The USB interface controls the signal generated by the Direct Digital Synthesizer (DDS), which is either a signal for stationary objects or for objects in movement. In previous design, the USB interface also had the task to control the communication between the Graphical Unit Interface (GUI) and the hardware, but as the new design only uses the USB interface to control the DDS, it can be reused 19.

(35) without any changes except the removal of the analog-to-digital IF-converter. The control of the DDS firmware is done with a micro controller (µC) from CY7C68013A Cypress Semiconductor Corporation [11]. 3.1.4. Frequency Synthesizer. The accuracy of detecting objects is determined also by the noise in the system. The frequency synthesizer, AD9956 from Analog Devices, has been tested and proves both low noise and good dynamic characteristics. The AD9956 uses advanced Digital Direct Synthesis (DDS) technology, an internal high speed, high performance DAC, and an advanced phase frequency detector/charge pump combination, which, when used with an external VCO, enables the synthesis of digitally programmable, frequency-agile analog output sinusoidal wave-forms up to 2.7 GHz or as in this project it will be used, with a loop-filter, as a PLL. The DDS can create digital phase relationships by clocking a 48-bit accumulator. The incremental value loaded into the accumulator, known as the frequency tuning word, controls the overflow rate of the accumulator. Similar to a sine wave completing a 2π radian revolution, the overflow of the accumulator is cyclical in nature and generates a base frequency [10]. The DDS is used to digitally create arbitrary waveforms, e.g. sine wave or saw-tooth [13].. Figure 28 -. FRACTIONAL DIVIDER, THE DDS USED AS PLL. The LPF 1 is the loop-filter designed to translate the current pulses into a corresponding voltage level, and the second LPF 2 is a Chebyshev filter of 3rd-Order to provide a very steep damping. 3.1.5. PLL. The synthesizer chosen for the radar application have an integrated PLL circuitry with a phase detector and charge pump. 20.

(36) Figure 29 -. PLL CIRCUITRY OF THE SYNTHESIZER. The phase detector has two differential inputs, PLLREF (the reference input) and PLLOSC (the feedback or oscillator input), that can be driven as single-ended signals. Both inputs are limited to 200 MHz when M/N dividers are bypassed. By adding a loop-filter and a VCO, the synthesizer can be used as a PLL. 3.1.6. The loop-filter. The purpose of the loop-filter is to stabilize the PLL and minimize to transform the current from the charge-pump to voltage level that the VCO can interpret. The loop-filter in this design is an active filter with an amplifier, as illustrated in Figure 30.. Figure 30 -. ACTIVE LOOP-FILTER. 21.

(37) 3.1.7. DDS Firmware Update. Figure 31 -. BLOCK REPRESANTATION OF THE FMCW SIGNAL GENERATION. In figure 31, the block representation of the FMCW signal generation is illustrated. As discussed previously the crystal oscillator was chosen to 100 MHz. The signal produced at the VCO output will be fed back to the synthesizer and with a scaling factor, recreated as a signal with a base frequency around 100 MHz.. 3.2 Design requirements Radar module specification for accurate radar operations are presented as follows. 3.2.1. FMCW-specification. The alternating triangular wave has three different sweep times, and during this sweep time the frequency has to change from 77 GHz to 81 GHz: •. 50µs. •. 100µs. •. 4ms. The main function of the PLL is to sweep continuously between two desired frequency generated by the DDS, as illustrated in Figure32.. 22.

(38) Figure 32 -. THE DDS AND PLL. The DDS core will generate a triangular wave in Fast Fourier Transform (FFT) points. The PLL has to track these sweeps as illustrated in figure 33.. Figure 33 -. FFT POINTS OF A TRIANGULAR WAVE. The frequency sweep between the two points results in a VCO linearity requirement and is defined as the 3rd order input intercept point (IIP3). To improve the linearity, the VCO is used within a PLL loop.. Figure 34 -. LINEAR VS NONLINEAR FMCW WAVEFORM. 23.

(39) The design of the loop-filter will determine the linearity of the PLL. To prove good linearity the PLL has to lock on each frequency step before the next FFT point comes. Thus, the PLL has to work rapidly and accurate. To improve the PLL lock time loop-filter design, the natural frequency, the PLL bandwidth and the lock time must be carefully considered and simulated. 3.2.2. Input Power specification. Noise in radar systems can be a critical problem. One possible noise source is the supply voltage. To minimize the noise, low-dropout regulators (LDO) must be used.. 24.

(40) Chapter 4 Circuit design and Simulation Results The design of the radar circuits on schematic level was made using OrCAD Capture, Cadence Design Systems. OrCAD Capture from Cadence is a printed circuit board (PCB) design tool, including schematic editing and simulation. Considering the new radar requirements in Chapter 3, this project work was focusing on: •. Redesign of the IF-filter. •. Redesign of the PLL. Some other modifications and new simulations must be also considered, such as stability of the power supply.. 4.1 IF-filter Design The IF-filter is designed to amplify with 20 dB/decade in the frequency range 1 kHz to 10 MHz [12]. The schematics for the IF-filter are shown in Figure 35a. The first stage (steg1) is a high-pass filter with the transfer function given by: @ 4 . 4 7( · 1 # 47( . The filter was designed for a cut-off frequency of 250 MHz. The next stage (steg2) is a non-inverting amplifier using LMH6624 from National Semiconductors. The transfer function of the non-inverting amplifier is given by: @ 4 1 #. A C7DEF< B. The amplifier was designed for a gain of 46 dB. The last stage (steg3) of the IF-filter is a second order active filter using AD8138 from Analog Devices, as amplifier. It has a Butterworth response and utilizes multiple feedback band-pass (MFB) technique. Simulation results of the IF-filter are presented in figure 35b with the gain of each stage.. 25.

(41) Non-inverting amplifier. IF-filter High-pass filter. MFB filter. Figure 35 -. THE IF-FILTER: (A) SCHEMATICS AND (B) SIMULATION RESULTS. 4.2 Loop-filter Design The loop-filter used for this project is an active filter designed for a small lock-time while providing a high gain and a small noise level. The ADIsimPLL tool [14] is used to design the loop-filter. It provides great flexibility when choosing both component values and filter configuration. A first loop-filter design was a passive filter shown in. 26.

(42) figure 36. Simulation results have shown that PLL specifications can be reached as shown in Figure 37. However, the filter component values were of unrealistic values, e.g. capacitors below 100 fF.. C1 206pF. R1 488. C2 1.47fF. Figure 36 -. Figure 37 -. EXEMPLE OF LPF DESIGNED WITH ADISIMPLL. RESULT OF A LOW-PASS-FILTER DESGINED WITH ADISIMPLL. Instead, an active loop-filter was designed. As discussed previously the benefits of an active filter is the high level gain provided by the amplifier. By introducing filter gain in the PLL, the entire PLL gain will increase and thus become more agile (shorter lock-time). The appliciation ADIsimPLL was used to design the active loop-filter. The schematics of the loopfilter are shown I Figure 38.. Figure 38 -. THE ACTIVE LOOP-FILTER. 27.

(43) Simulation results of the PLL with the new active loop-filter gave a much faster and accurate PLLresponse, as shown in figure 37.. Figure 39 -. THE TIME DOMAIN SIMULATION OF ACTIVE FILTER. Finally, the active filter was designed and simulated in OrCAD. It was shown that the new filter contributes with a 46 dB gain while high frequency components, e.g. noise, are filtered out. The cutoff frequency of the filter is 1 kHz. The simulation results of the loop-filter is shown in Figure 40.. Figure 40 -. SIMULATION RESULT OF THE ACTIVE LOW PASS FILTER. 4.3 The 3rd-Order Chebyshev-Filter As mentioned in Chapter 3, the output from the internal DAC connected to the PLL oscillator of the synthesizer, needs to be a clean oscillating signal. To remove all the noise a Chebyshev-filter must be used. A Chebyshev-filter has a steeper roll-off transfer function than other filters, e.g. Butterworth or. 28.

(44) lag-led filters. The 3rd-order Chebyshev used for this radar demonstrator is designed with a cut-off frequency fc = 170 MHz. The schematics of the filter are shown in Figure 41 and the simulation results are presented in Figure 42.. Figure 41 -. Figure 42 -. SCHEMATIC LAYOUT OF 3RD ORDER CHEBYSHEV FILTER. SIMULATIONS OF THE 3RD ORDER CHEBYSHEV FILTER. 4.4 DDS Firmware The DDS use a frequency tuning word (FTW) to scale the system clock frequency to a base frequency [10]. GG%HI J · H It can be calculated as follows: J. .K 2 L 29.

(45) or J. GG%HI H. where fs is the system clock frequency. Combining these two equations gives: GG%HI . .K 2 L H. where fs can be calculated as: H . M7N%& / OPQRPST UVVUQR W M7N OPQRPST UVVUQR W CCX. Since this PLL is designed to do a linear sweep, some calculations can be simplified and rewritten M7N%& . 12.83 # 13.5 @] 2. The center frequency of the PLLref was chosen to 100 MHz and by using the same FTW values as the previous design the new span of the PLLosc can be found: Parameter. Value. FTW0. 35.1 T. FTW1. 35.56 T. PLL0osc. 99.35 MHz. PLL1osc. 100.65 MHz. 30.

(46) Chapter 5 Discussion In this chapter, the obtained results of the radar demonstrator design will be discussed.. 5.1 PLL and Loop-Filter The requirement for a 50µs sweep time could not be realized to give a linear triangular wave that is fully linear. The requirement of 0.5% non-linearity can be realized with an active filter, but due to the requirements of low system noise a passive filter is more proper. The linearity of the triangular wave is determined by PLL dynamics, e.g. lock time. To decrease the lock-time, and therefore improve the linearity, the bandwidth of the loop-filter has to be increased. The PLL bandwidth, as discussed previously, is approximately the natural frequency of the circuit and thus depends on the loop-filter component values. Larger bandwidth results in impractical low values of the discrete components values. To achieve a linear triangular wave the passive filter needs to be redesigned. One solution is to make the loop-filter on a silicon (Si) substrate, i.e. an IC, and by that decreasing the component value to a level that will improve the loop-filter. Another solution is to increase the sweep time, but do to the requirement of high resolution and a fast system, this solution will be neglected. The variation in linearity between the desired triangular wave and the simulated triangular wave can be found using the simulation result from ADiSIM, the calculated FFT time interval and the number of FFT points. The PLL is designed to give the best linearity for the worst case scenario, which is the shortest sweep time. The number of FFT points has been calculated as 1024 FFT points and the FFT time interval has been calculated as 30 ns. The frequency change between each FFT point is given by: ∆ . /E^ " /F< . _WVP4. Where fmin and fmax is are the minimum and maximum frequencies of the VCO output signal. With ∆ 654 J@], the maximum allowed variation for the specified linearity is given by: aF<bE < · 0.5%. where < /F< # ∆ · P 31.

(47) and n is a FFT point, n = 1..1024 For n = 1 the maximum variation in frequency equals to 64.15 MHz. By using the ADIsimPLL simulation tool, the simulated variation for n = 1 was found to be within the frequency interval 146 Hz (at 27.5 ns) to 848.9 Hz (at 36.0 ns) on the input. Furthermore, the linearity of the output signal of the PLL was analyzed considering that %& e · fg , where N = 131.65 (which is the scaling factor). |Freq Error| 10k. Frequency 12.8634. 1k Abs Frequency Error (Hz). 12.8634. Frequency (GHz). 12.8634. 12.8634. 12.8634. 100. 10. 12.8634. 1 12.8634. 100m. 12.8634 0. 10. 20. Figure 43 -. 30. 40. 50. 60. 70. 80. 90 100 Time (ns). 0 10 20 34.96ns 938.50 Hz. 30. 40. 50. 60. 70. 80. 90 100 Time (ns). LEFT FIGURE IS THE OUTPUT OF THE PLL, THE RIGHT FIGURE IS THE FREQUENCY ERROR ON THE INPUT OF THE PLL. PICTURES TAKEN FROM THE ADISIMPLL APPLICATION. The corresponding frequency variation: /EâF<bE P · aF<bE 1024 · 146@] W 848.9@] 150J@] W 869J@] or, after the VCO: /EâF<bEijk /EâF<bE · e 150J@] W 869J@] · 131.65 19.75 m /EâF<bEijk m 114.4. 0.15 m /EâF<bEijk m 0.85. n@]. %. One first conclusion is that 0.85% linearity results in less accurate radar functionality. Therefore, the loop-filter and the entire PLL must be reconsidered.. 5.2 The IF filter As discussed, the power of the beat frequency will decrease as it travels through a medium. To compensate for the power loss, an IF filter was designed to amplify the beat frequency as the wave travels for a distance R. The beat frequency is proportional to the distance to the object. As the 32.

(48) distance increases, the beat frequency will increase while the power loss will also increase. The new requirements of amplifying the beat frequency signal with a 20 dB/decade slope within the required bandwidth of [0.001-10] MHz, cannot be achieved with the existing IF filter. The non-inverting stage of the IF filter will determine the cut-off frequency of the IF-filter. However, the amplifier have a maximum gain limitation which will affect the properties of the IF filter. The bandwidth of the designed IF filter was found to be [0.0025 – 8.9] MHz compared to the desired [0.001 – 10] MHz. To increase the IF filters bandwidth the non-inverting amplifier has to amplify more, but as the maximum gain already is achieved the op.amp has to be replaced.. 5.3 PCB The final step of the project was to design the PCB layout by using OrCAD design tool. The PCB card created is a 4-layer substrate. The power layer is routed separately as shown in Figure 44. Analog and digital circuits are placed on the top layer using the bottom layer for additional routing. To isolate the digital circuitry from the analog, the ground layer is divided into a digital and analog region.. Figure 44 -. ILLUSTRATION OF THE PCB CARD. The final task will be to manufacture and test three different radar modules, the Pluto module and two Charon modules. However, the testing of these modules is not a subject of this work. The main focus was made on the Pluto-module. It consists of antenna arrays on both sides, providing a full field of view. Transmitted electromagnetic waves needs a free path without any interference of any power planes or ground planes. As shown in Figure 45, a “hole” is made on the PCB providing a free path for the transmitted waves.. 33.

(49) Figure 45 -. ILLUSTRATION OF THE PCB CARD FOR PLUTO MODULE. The final PCB card produced by an international company is illustrated below. Due to long processing time, the final PCB test with components will be carried out by Acreo AB.. Figure 46 -. FINAL PCB CARD FOR PLUTO MODULE. 34.

(50) Chapter 6 Next Generation The components designed for the radar application has been simulated on schematic level. The new design has shown that more attention and new specifications are needed in order to improve the entire radar module. As the loop-filter was designed as an active filter, it brought some new questions to the project. “How will an active loop-filter change the performance of the system?” As discussed in this thesis report, an active filter will introduce more noise to the radar system. To minimize the noise the active components should be chosen considering their noise characteristics. Another solution is to use a passive filter integrated on a chip with a low cut-off frequency. In this way the high-frequency noise will be filtered. The benefit of introducing an active loop-filter is that the system will work more agile then a passive system, making it possible to decrease the lock-time to the desired level. “What happens if we choose an active filter with high level gain, to increase the lock-speed even further?” A higher gain on the filter will increase the loop gain of the PLL. The stability of the PLL varies with the loop gain [15] and choosing a higher gain can cause instability of the PLL, e.g. higher overshoot. For the next generation of the radar demonstrator, there are some changes that can improve its performance. 1. Introducing LPF on IC The first designed passive filter can be realized with small component value that can improve the lock-time even more than an active filter. By implementing the LPF in IC-technology the values of the components can be smaller than practically possible with discrete components. 2. Changing the DDS core The maximum allowed input frequency of the PLL ref was limited to 200 MHz, by choosing a DDS core that allows a higher input frequency can cause the PLL to minimize the lag (i.e. start earlier) 3. Changing the character of FMCW The proposed sweep time can be increased to give better linearity. The reason why an active filter was chosen was mainly because of the small FFT step time. By increased sweep time, the FFT step time will increase giving a longer time period for the PLL to lock. In this way the use of the passive filter will be facilitated. 35.

(51) Chapter 7 Conclusion The task of this thesis work was to design and evaluate new circuit solutions for FMCW radar system and to generate, if time permitted, the radar module PCB layout. The result presented in this thesis is mainly simulation results. Testing and finale evaluation of the radar module will be made separately. Some conclusions drawn are: •. For better and more accurate radar functionality, the linearity of the PLL circuit is a bottle neck. •. Two PLL loop-filters have been analyzed in this thesis: o. A passive loop-filter. For given triangular wave specifications it results in filter components of too small nominal values. o. An active loop-filter. It could improve the dynamics of the PLL (lock-time) but it results in amplified noise in the system. •. The proposed solution is to use a passive filter integrated on an IC, a solution which permits passive components of smaller values. •. The PLL linearity can also be improved by relaxing the PLL specifications as given by the sweep time of the triangular wave. 36.

(52) Bibliography [1] Radar History http://www.radarworld.org/huelsmeyer.html (2008-08-15) [2] Skolnik, M. I., “The Radar Handbook”, 2nd Edition, New York, McGraw-Hill, 1990. [3] Skolnik, M. I., “Introduction to radar systems”, 3rd Edition, New York, McGraw-Hill, 2001. [4] The Basics of Antenna Arrays, G. J. K Moernaut And D. Orban, http://www.orbanmicrowave.com/The_Basics_of_Antenna_Arrays.pdf (2008-11-21). [5] Curry, R., “Radar System Performance Modeling”, 2nd Edition, Ebrary, http://site.ebrary.com/lib/linkoping/Doc?id=10081989&ppg=1 (2008-09-08). [6] Pozar. David M., “Microwave and RF design of Wireless systems”, Wiley & Sons, 2000. [7] Development the Concept of 340 GHz FMCW Single Channel Radar, http://www.eng.tau.ac.il/research/FEL/reports2007/Appendix%20I.pdf (2009-01-17). [8] Egan, William F., “Phase-Lock Basics”, 2nd Edition, Wiley & Sons, 1998. [9] Egan, William F,. “Frequency Synthesis by Phase-lock”, 2nd Edition, Wiley & Sons, 1999. [10] Analog Devices, AD9956 datasheet, http://www.analog.com/UploadedFiles/Data_Sheets/AD9956.pdf [11] Svensson, J., “Implementation of an FMCW Radar Platform With High-Speed RealTime Interface”, LITH-ISY-EX--06/3779--SE, 2006. [12] Eriksson, O., “Filterdesign och hårdvarukonstruktion för FMCW-radar”, LiTH-ISYEXET--06/0320--SE, 2006 [13] L. Cordesses, "Direct Digital Synthesis: A Tool for Periodic Wave Generation (Part 1)" IEEE Signal Processing Magazine, DSP Tips & Tricks column, pp. 50-54, Vol. 21, No. 4 July 2004. [14] Analog Devices, ADIsimPLL, http://www.analog.com/static/imported-files/eval_boards/adisimpll.pdf [15] Nash, Garth. “Phase-Locked Loop Design Fundamentals.” February 2004 37.

(53)

No results found