Implementation of a Digital Radio Frequency Memory in a Xilinx Virtex-4 FPGA

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Implementation of a Digital Radio Frequency

Memory in a Xilinx Virtex-4 FPGA

Examensarbete utfört i elektroniksystem vid Tekniska högskolan i Linköping

av

Kristian Gustafsson

LITH-ISY-EX--05/3742--SE Linköping 2005

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Implementation of a Digital Radio Frequency

Memory in a Xilinx Virtex-4 FPGA

Examensarbete utfört i elektroniksystem

vid Tekniska högskolan i Linköping

av

Kristian Gustafsson

LITH-ISY-EX--05/3742--SE

Handledare: Anna Goman

Saab Bofors Dynamics AB

Anders Nyhlén

Saab Bofors Dynamics AB

Examinator: Kent Palmkvist

isy, Linköpings Universitet Linköping, 22 December, 2005

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Avdelning, Institution Division, Department

Division of Electronics Systems Department of Electrical Engineering Linköpings universitet S-581 83 Linköping, Sweden Datum Date 2005-12-22 Språk Language Svenska/Swedish Engelska/English Rapporttyp Report category Licentiatavhandling Examensarbete C-uppsats D-uppsats Övrig rapport

URL för elektronisk version http://www.es.isy.liu.se http://www.ep.liu.se/2005/3742 ISBN — ISRN LITH-ISY-EX--05/3742--SE Serietitel och serienummer Title of series, numbering

ISSN —

Titel Title

Implementation av ett digitalt radiofrekvent minne för en Xilin Virtex-4 FPGA Implementation of a Digital Radio Frequency Memory in a Xilinx Virtex-4 FPGA

Författare Author

Kristian Gustafsson

Sammanfattning Abstract

Digital Radio Frequency Memory (DRFM) is a technique widely used by the de-fense industry in, for example, electronic countermeasure equipment for generating false radar targets. The purpose of the DRFM technique is to use high-speed sam-pling to digitally store and recreate radio frequency and microwave signals. At Saab Bofors Dynamics AB the technique is used, among others, in the Electronic Warfare Simulator (ELSI). The DRFM technique is implemented in a full-custom ASIC circuit that has been mounted on circuit boards in ELSI. Today, the progress in the programmable hardware field has made it possible to implement the DRFM design in a Field Programmable Gate Array (FPGA). The FPGA technology has many advantages over a full custom ASIC design.

Hence, the purpose of this master’s thesis has been to develop a new DRFM design that can be implemented in an FPGA, using a hardware description lan-guage called VHDL. The method for this master’s thesis has been to first establish a time plan and a requirement specification. After that, a design specification has been worked out based on the requirement specification. The two specifications have served as a basis for the development of the DRFM circuit. One of the requirements on the design was that the circuit should be able to communicate through an external Ethernet interface. A part of the work has, thus, been to review available external Ethernet modules on the market. The result is a DRFM design that has been tested through simulations. The tests shows that the design works as described in the design specification.

Nyckelord

Keywords FPGA, DRFM, VHDL, Xilinx, Saab Bofors Dynamics, Mentor Graphics, Virtex-4, Ethernet, VMEbus

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Abstract

Digital Radio Frequency Memory (DRFM) is a technique widely used by the de-fense industry in, for example, electronic countermeasure equipment for generating false radar targets. The purpose of the DRFM technique is to use high-speed sam-pling to digitally store and recreate radio frequency and microwave signals. At Saab Bofors Dynamics AB the technique is used, among others, in the Electronic Warfare Simulator (ELSI). The DRFM technique is implemented in a full-custom ASIC circuit that has been mounted on circuit boards in ELSI. Today, the progress in the programmable hardware field has made it possible to implement the DRFM design in a Field Programmable Gate Array (FPGA). The FPGA technology has many advantages over a full custom ASIC design.

Hence, the purpose of this master’s thesis has been to develop a new DRFM design that can be implemented in an FPGA, using a hardware description lan-guage called VHDL. The method for this master’s thesis has been to first establish a time plan and a requirement specification. After that, a design specification has been worked out based on the requirement specification. The two specifications have served as a basis for the development of the DRFM circuit. One of the requirements on the design was that the circuit should be able to communicate through an external Ethernet interface. A part of the work has, thus, been to review available external Ethernet modules on the market. The result is a DRFM design that has been tested through simulations. The tests shows that the design works as described in the design specification.

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Acknowledgements

This master’s thesis work has been carried out at Saab Bofors Dynamics AB in Linköping as a part of a Master of Science in Applied Physics and Electrical Engineering. The result will hopefully be of great use in the Electronic Warfare Simulator at SBD. I would like to thank everyone that have helped and encouraged me during the work with this thesis. Especially, I would like to thank the following people:

• Ulf Malmqvist at SBD, for giving me the opportunity to do my master’s thesis at SBD and for all help and support during my time at the company. • My supervisor Anna Goman at SBD, for all help with the computer

re-sources, software and the VHDL coding.

• Anders Nyhlén, my second supervisor at SBD, for all the time he has spent on explaining the complex systems in ELSI for me and for all support given. • Sture Carlson at SBD, for the detailed review of my thesis report and for all

help with litterateurs used for the technology chapter of this report. • Leif Tranell at SBD, for all the support with troublesome software.

• My opponent Oskar Ståhl for his valuable comments and feedback on my thesis report.

• My examiner Kent Palmkvist at the Division of Electronics Systems, De-pertment of Electrical Engineering at Linköping University for valuable com-ments on the report.

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List of Acronyms

A/D Analog to Digital

ADC A/D Converter

ASIC Application Specific Circuit

ASMBL Advanced Silicon Modular Block

BRAM Block RAM

CLB Configurable Logic Block

CMOS Complementary Metal-Oxide Semiconductor

CSMA/CD Carrier Sense Multiple Access with Collision Detection

CW Continuous Wave

D/A Digital to Analog

DAC D/A Converter

DCM Digital Clock Manager

DIX Digital Intel Xerox

DRFM Digital Radio Frequency Memory

DSP Digital Signal Processing

ECM Electronic Countermeasure

ELSI Electronic Warfare Simulator

FPGA Field Programmable Gate Array

FSM Finite State Machine

GPIO General Purpose Input/Output

HSD High-Speed Data

HSDE High-Speed Data Enhanced

HWIL Hardware-in-the-loop

IC Integrated Circuit

IF Intermediate Frequency

IEEE Institute of Electrical and Electronics Engineers

IOB Input/Output Block

IP Intellectual Property

IP Internet Protocol

LAN/MAN Local and Metropolitan Area Network

LiU Linköping University

LUT Look-Up Table

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MAC Media Access Control

MDI Media Dependent Interface

MII Media Independent Interface

OUI Organizationally Unique Identifier

PAR Place and Route

PHY Physical Layer

PRF Pulse Repetition Frequency

RAM Random-Access Memory

RF Radio Frequency

SBD Saab Bofors Dynamics AB

SLOS Synthetic Line of Sight

SoC Software-on-Chip

TCP Transmission Protocol

TEG Target Echo Generator

UDP User Datagram Protocol

UUT Unit Under Test

VHDL VHSIC Hardware Description Language

VHSIC Very High Speed Integrated Circuit

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Introduction

This chapter serves as an introduction to this master’s thesis. It starts with de-scribing the background to why this project was initiated. After that the purpose of the master’s thesis is described and the chapter ends with a description of the method used and the limitations of the thesis.

1.1 Background

The Electronic Warfare Simulator, ELSI, is situated at Saab Bofors Dynamics AB (SBD) in Linköping. ELSI is used to test and verify radar seekers capabilities against simulated scenarios of targets and countermeasures [1] . The simulator is depending on a huge amount of advanced hardware. To be able to broaden the type of seekers that can be tested and to meet upcoming new demands the facility is undergoing a constant upgrading. One part of the equipment needed to be upgraded is a Digital Radio Frequency Memory (DRFM) circuit. The original DRFM circuit is a full custom Application Specific Integrated Circuit (ASIC) design developed at SBD in the early 90’s. The circuit is running at 200 MHz, a very fast circuit at the time. Due to the technical development in programmable hardware field, a new DRFM circuit should be possible to develop using FPGA technology instead of ASIC.

Field Programmable Gate Arrays (FPGAs) have undergone a major transition the last few years: From being small basic programmable logic hardware, to the newest FPGAs, being large circuits, with transistor count equivalent to the newest PC processors and having advanced integrated logic such as embedded processors and Ethernet capabilities. Designs, earlier only possible to implement as an ASIC, can now be implemented in a single FPGA. There are still benefits of developing ASICs due to the small chip size, low power consumption and very low chip costs per unit when a large amount of units have to be manufactured. The disadvan-tages are the long design time of ASICs, the difficulty to alter the design after manufacturing and the expensive development cost when only a small series of chips are needed. Using FPGAs on the other hand, the design can quickly be altered and tested during the development. When only a few chips are needed an

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FPGA solution will be very cheap, both in time and cost, in comparison to an ASIC solution. This is why a solution using an FPGA has been chosen by SBD.

This master’s degree thesis has been performed in the form of a project, i.e. setting up a time plan and writing a requirement specification as well as a design specification. The idea was to use a working method similar to the methods used at high-tech companies such as SBD. Essential was to secure control of the cost, i.e. spent time, of the project and to be able to supervise the progress of the development of the DRFM circuit.

The thesis work has been carried out in accordance with the requirements of the Master of Science degree at Linköping University (LiU) in Sweden. The examination has been done by assistant professor Kent Palmkvist at the division of Electronics Systems, a part of the Department of Electrical Engineering at LiU.

1.2 Purpose

The main objective of the project was to develop a DRFM circuit to be used in the ELSI simulator. The DRFM functions should be implemented in an FPGA using VHDL as the hardware description language for programming the logic. The DRFM should be controlled by a computer. The interface was at first chosen by SBD to be a standard VMEbus interface but during the project the interface was changed to be an Ethernet interface instead, see Section 2.12. No requirements regarding the component cost of the FPGA were made.

To be able to fulfill the objectives above, the folowing tasks had to be accom-plished:

• A survey of FPGAs suitable for the project. • Study of the design of the VMEbus.

• Study of the Ethernet standard and a market survey of available Ethernet modules.

• Review of the available development tools at SBD to be able choose the best tools for the development of the circuit.

• Development of the DRFM circuit using VHDL.

1.3 Method

The first task of this project was to establish a time plan for the entire project. The time plan can be found in Appendix A. The time plan was used to estimate the time needed for the different phases of the project.

The second task was to study the documentation of the DRFM circuit used today. After having established an overview of the function and capability of the present circuit a design requirement specification was composed in collaboration with the ELSI staff at SBD. The specification can be viewed in Appendix B.

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1.4 Limitations 3

The third task was to study design alternatives in more detail, i.e. the choice of the FPGA circuit, the layout of the design, the development tools to be used etc. This ended up in a design specification, available as Appendix C.

After the three first steps of the project the actual development started. This included learning the chosen development tools, VHDL programming, behavioral simulation of the design, synthesis, design implementation and testing the design through timing simulation. This step was the major part of the project in terms of time. After the functionality of the design had been verified the circuit was considered complete. No test in hardware was performed, as the hardware platform to be used for the DRFM circuit had not been developed at the time for this thesis project. Hence, hardware tests had not been included in the time plan.

1.4 Limitations

This thesis project was completed in accordance with the regulation of thesis projects at Linköping University. Due to the limitation in time, the goal of this project has been to develop the architecture and functions of the new DRFM circuit. The communication interface and testing of the logic in hardware have not been part of the project.

1.5 Thesis outline

Chapter 2, Technology & Background, is intended to give the reader the back-ground information needed to understand the implementation of the DRFM de-sign.

Chapter 3, Implementation & Testing, describes layout decisions made, the imple-mentation flow used and the implemented design. A discussion is also held around the testing methods.

Chapter 4, Results & Discussion, presents the result of the master’s thesis and a discussion around the difficulties that have come up during the thesis work.

Chapter 5, Conclusions & Future work, discusses the conclusions that can be made and future improvements that can be done.

The appendices contains the time plan, the requirement specification, the design specification and wave forms from simulations of the design.

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Chapter 2

Technology & Background

This chapter is intended to give the reader the background information required to understand the implementation of the DRFM circuit. The chapter starts with a description of the company where this thesis project has been performed. It con-tinues with a short technology background of radar seekers, electronic countermea-sures and the DRFM technology. After that, the simulator ELSI will be described in more detail. In particular the DRFM circuit used today and the requirements of the new architecture will be explained. Furthermore the different technologies and logic blocks needed to implement the design will be described. The chapter ends with a description and a discussion of the communication interface of the DRFM circuit.

2.1 Saab Bofors Dynamics AB

Saab Bofors Dynamics AB (SBD) is a business unit within Saab AB having ap-proximately 1200 employees. The head quarter is located in Karlskoga, but local divisions are also situated in Linköping, Eskilstuna, Gothenburg and Stockholm. SBD develops, markets and produces missile systems and man-portable support weapons. The products are aimed for use at both land, air and above and under water. SBD has customers all over the world, approximately 80% of the company’s turnover comes from export, but the Swedish market is still an important base for the company. SBD participates in a number of international collaborations and has also developed own defense products. Well-know, entirely own-developed, prod-ucts are the anti-ship missile RBS 15, the anti-aircraft missile system BAMSE and the recoilless gun system Carl Gustaf1.

1_{Carl Gustaf is well-known for its appearance in the Steven Spielberg Hollywood movie “War}

of the Worlds” in 2005

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2.2 Radar seekers

In the Electronic Warfare Simulator, ELSI, the accuracy and performance of radar seekers in guided missiles are tested. A guided missile is made up of a series of different parts. These are used in applications such as propulsion, control and guidance. The guidance of the missile is controlled by the guidance computer. It maneuvers the missile during the flight towards the target pointed out by the radar seeker.

A basic radar consists of a radio transmitter, a radio receiver, two antennas and signal-processing circuitry. The radio transmitter sends radio waves, i.e. elec-tromagnetic waves, which radiates from the transmitter antenna. The receiver uses the other antenna to pick up echoes of the waves that have been reflected on, hopefully, the wanted target. These echoes are forwarded to the signal-processing circuitry that calculates for example the distance and the direction to the target. As the radio waves travel at constant speed, the speed of light, the distance is possible to calculate according to the formula in example 2.1.

Example 2.1: Target distance formula.

R = 1 2 T c

R is the target distance in meters T is the round-trip time in seconds c is the speed of light in m/s

[2]

To avoid the transmitter from interfering with the receiver the transmitter usually sends the radio waves in pulses and the receiver is turned off during transmission. The rate at which the transmitter sends pulses is called pulse repetition frequency, PRF.

In practice the radar seeker uses only one antenna for both transmitting and receiving waves. In this case the antenna is shared by time multiplexing.

The antenna concentrates the energy dissipated in a narrow beam to be able to more precisely detect targets. Due to the narrow area of detection, the beam has to be swept over the region of interest to be able to find the wanted targets.[2]

2.3 Electronic countermeasures

To avoid being hit by a missile the target, e.g. a fighter jet, can use electronic countermeasures (ECM) to trick the missile. There is a wide variety of ECM techniques that can be used depending on the situation. The simplest example is when an airborne target deploys chaff in the air to confuse the missile. Chaff are small strips of metal or metal-coated dielectric fibers with an optimal length of half of that of the radar signal wave length. A huge amount of these are deployed in the air and can stay there for a long time producing strong radar echoes hopefully

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2.4 Digital Radio Frequency Memory 7

misleading the missile. Other examples are noise jamming and false targets. Noise jamming is intended to increase the background noise making it more difficult to locate the targets. False targets can be generated in different ways. The simplest way is to use a transponder which receives the pulse, waits for a certain delay, corresponding to the additional target range, and transmits the pulse back to the seeker. The transmitted false target pulse is hopefully interpreted by the radar seeker as target situated on a certain distance from the real target. To produce more realistic false targets a repeater can be used. The repeater is similar to the transponder but is also equipped with a memory. The memory can be used to store the intercepted radar pulses and using them to display multiple and moving targets on different ranges and velocities for the seeker. To be able to fully exploit this principle a digital radio frequency memory (DRFM) could be used.[2]

2.4 Digital Radio Frequency Memory

Digital radio frequency memory, DRFM, is a technique used for storing and recre-ating radio frequency (RF) and microwave signals. The principle of the DRFM was invented in 1974 at EMI Electronics Ltd in Britain. The basic task is to input an RF signal that has been converted to a frequency low enough to be sampled by a high-speed A/D converter (ADC). The sampled signal is stored in a high-speed memory and can be retrieved and converted back to the original signal using a D/A converter (DAC). A simplification of the DRFM function is to see the DRFM as a variable delay line for radio frequency signals. The technique is often used in electronic warfare applications. In particular DRFMs are widely used in ECM products to generate false radar echoes. SBD markets military products using the DRFM technique, but the technique is also used in the Electronic Warfare Simulator at SBD.[3]

2.5 The Electronic Warfare Simulator

The Electronic Warfare Simulator (ELSI) is a hardware-in-the-loop, HWIL,

sim-ulator used to test radar seekers. An HWIL simsim-ulator uses an actual individual of the seeker that is presented with a complete simulated target scenario. This is used to verify and test the radar seeker capabilities against simulated scenarios of targets and countermeasures. By using ELSI, different conditions and properties of the environment can be simulated (e.g. weather conditions, seeker primings, target behavior, ECM)[1]

ELSI is situated in a stand-alone building at the Saab area in Linköping. The test facility was inaugurated in 1994 and the first tests were carried out in 1995 [1]. The simulator consists of an anechoic chamber, an antenna wall, the flight

motion simulator, signal generators and a data and control room, see Figure 2.1.

The anechoic chamber is a room with the dimension of 14 m × 13 m × 10.5 m. The room is electromagnetically shielded and the walls are covered with radar absorbing materials, see Figure 2.2. The material makes the attenuation of the chamber walls at least 50 dB. This is equivalent to reducing a signal to a level 100,000 times

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Figure 2.1. Overview of the Electronic Warfare Simulator.

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2.5 The Electronic Warfare Simulator 9

weaker than its original strength. The high attenuation is a requirement to make the walls invisible to the seeker, instead it just sees the target scenario presented by the simulator.

On one of the walls of the chamber 16 radar antennas and transmitters are situated. These are used by the simulator to simulate and present the target scenario for the seeker. The antenna wall is mounted on a framework which is mounted on a concrete foundation. The antennas are placed on a horizontal row with one degrees spacing on a segment of a circle with a radius of 13 meters. The circle has the origin at the axis intersection of the gimbals of the flight motion simulator which is situated on the opposite wall.

Normally the radar seeker sweeps its radar beam over a certain angle of the horizon. In the simulator, however, this would not be possible because of the limited width of the antenna wall. Widening the antenna wall by installing more antennas are not feasible because of the huge cost associated with filling the room with antennas. Instead the radar seeker is attached to the flight motion simulator, see Figure 2.3, which during simulations moves the seeker at the same rate as the radar beam so that the beam is always centered to the middle of the antenna wall. To make this solution work the whole target scenario presented by the antenna wall also moves, at the same rate as the radar beam. This way of presenting the simulated scenario is called synthetic line of sight, SLOS.

Figure 2.3. The flight motion simulator in ELSI.

The flight motion simulator, weighing approximately 11 tonnes, is attached to a concrete foundation weighing about 500 tonnes, see Figure 2.1. The concrete foundations for both the antenna wall and the flight motion simulator has been placed on geological stable sand to minimize vibrations. The further minimize the vibrations of the flight motion simulator its foundation is in no way in contact with the rest of the building. Minimizing vibrations are essential to have the radar antennas and the seeker perfectly aligned at all times. Otherwise the simulated scenarios presented by the antennas will not be accurate enough.

The control of the simulator and the data collection are handled in the control and data room of the simulator building. The central parts are the two

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Power-Hawk 740 computers developed by the American company Concurrent Computer

Corporation2. The two simulation computers updates the hardware with data in

real-time during test runs.

The last part of ELSI is the signal generators. These contain different equip-ment which handles the transmission of the complete simulation scenario to the antennas. For this master’s thesis the most interesting equipment of the signal generators are the Target Echo Generator (TEG).[1]

2.6 The Target Echo Generator

The TEG is the part of the signal generators that this thesis is all about. More precisely, focus is on the DRFM circuits situated on four circuit boards in the TEG. These circuit boards have two main functions:

1. Store target echoes.

2. Control the delay of the echoes during run-time.

The delays of the echoes are introduced to be able to simulate the distance to a target. Normally the distance to the target can be several kilometers but in the anechoic chamber of ELSI there is merely 13 meters between the seeker and the antennas. Therefore the echoes are delayed to simulate the distance. This is possible since the delay is equivalent to distance according to the formula in example 2.1.

The four DRFM circuit boards are mounted in a VME chassie together with other circuit boards used for generation of different trigger signals. The VME chassie, see Section 2.12.1, has a custom made backplane that has been developed at Saab. The backplane is used for external communication and power.

The DRFM circuit boards consist mainly of a DRFM circuit and an A/D converter. Each of them generates echoes for one target during simulation. Hence, four targets can be displayed at the same time during run-time. The function of the DRFM circuits will be described in more detail in Section 2.7.

The circuit boards are controlled through an interface called High-Speed Data

Enhanced (HSDE) interface. The HSD bus is an industry de facto standard

de-veloped by Encore3. This interface is used to load pulses to the memory in the DRFM circuits and to control the delays during run-time.

2.7 The current DRFM circuit

There are several different architectures that could be used to implement a DRFM chip [3]. The architecture used in the current ELSI DRFM is illustrated in Fig-ure 2.4. It consists of a high-speed memory, DSP logic and an integrated DAC. A

2_{Concurrent Computer Corporation is a company specialized in real-time computer systems}

for industry and government, see http://www.ccur.com

3_{Encore is a real-time computing company which was acquired by Compro in 2002, see}

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2.7 The current DRFM circuit 11

Figure 2.4. A simplified figure showing the layout of the DRFM circuit used in ELSI today.

controller is also contained in the chip. It can is used for control of the behavior during run-time and for the access to the circuit via the HSDE interface.

The basic function of the DRFM circuit is as follows: The original radio signal (RF) is converted to a lower, intermediate frequency (IF) that can be A/D con-verted and stored, temporary, in the high-speed memory in the DRFM chip. The memory is dual-ported so that reading and writing can be done independently and at the same time. Therefore the stored radio signal can be read at the same time as it is recorded. Optional advanced DSP functions can be applied on the output of the memory. The output can also be connected directly to the DAC. The DAC, inside the chip, converts the signal back to the IF. The RF signal is then restored by converting the IF signal to the original frequency. This analog output is used by the signal generators in ELSI to generate the radar echoes sent back to the radar seeker.

The DRFM circuit used in ELSI today is a full custom ASIC design4_developed at Saab in the early 90’s. Several newer versions of the design have been developed. Used today in the TEG is the second version5 _{of the DRFM circuit which was} developed in 1994. In the used DRFM circuit there is also a parameter server which can be used in ECM applications. This parameter server places functionality in the DRFM circuit instead of in the simulation software which makes the DRFM circuit more independent.

2.7.1 The function of the DRFM

The current DRFM circuit can be set to work in three different modes. All three modes will also be available in the new DRFM circuit. The three modes are used in three different contexts. The first mode, trigged mode or mode A, is used when the pulse from the radar seeker is known. The equivalent of the mode described in the previous section is called delay line mode or mode B. The third mode, CW

mode or mode C, is not intended to be used during simulations. Instead it is used

for calibration and testing of equipment.

4_{The manufacturing process used is 0.8 micron BiCMOS process}

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Next follows a more detailed description of the function of each mode:

Mode A, Trigged mode The trigged mode is used when the waveform of the

pulse is known and if the tested radar seeker is able to deliver a trigger signal for every radar pulse it transmits. In Figure 2.5 the trigger signal, PRF, is used as input to the circuit instead of the seeker pulse. When using this mode the pulse is loaded into the memory of the DRFM circuit before the simulation starts. For every trigger signal, the stored pulse is transmitted via RFout after the corresponding delay. The time the wave form is delay after the trigg pulse corresponds to a distance according to example 2.1.

Figure 2.5. A simplified figure showing mode A, trigged mode.

Mode B, Delay line During this mode the DRFM circuit is used as a delay

line, meaning that the radar echo is stored in the memory for a specified time and after that transmitted back. In Figure 2.6 the radar echo is loaded to the memory via the RFin port. The echo is delayed according to the variable delay applied and then transmitted via RFout.

Figure 2.6. A simplified figure showing mode B, delay line.

Mode C, CW mode The third and last mode of the DRFM is used during

test and calibration. This mode is called CW mode, where CW is an acronym for continuous wave. No input is used during this mode, instead a wave form, often a sine wave, is loaded to the memory. During run-time the wave form is transmitted repeatedly again to form a continuous wave that can easily be measured, see Figure 2.7.

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2.8 The new DRFM circuit 13

Figure 2.7. A simplified figure showing mode C, CW mode.

2.8 The new DRFM circuit

The version of the DRFM circuits used today was developed in the middle of the 90’s. Today the design is obsolete and because of this support on the circuits would be very expensive, should any of the circuits fail. This has made SBD taken the decision to develop a new DRFM circuit and, thus, new DRFM circuit boards. In the end the meaning is that the entire TEG, were the circuit boards are situated, shall be replaced with a new one.

Below, the most important reasons for SBD to develop a new circuit and new circuit boards are listed:

• The old design is obsolete.

• The control of the old circuit is too complex.

• Maintenance of the circuit boards are extremely expensive. • No standardized backplane in the TEG.

• A desire to have a design that is easy to upgrade and that is future proof. • New demands on the simulator due to requirements of future test runs:

– Increased maximum target distance.

– Support for up to five digital outputs used for triggering ECM

equip-ment.

– New digital outputs.

The items above resulted in a collection of requirements for the new design. The requirements was put together in a requirement specification, see Appendix B. The requirement specification served as a basis when a design specification was written. In the design specification the layout of the circuit and the functions to be implemented was specified as well as other characteristics of the circuit. The complete design specification can be found in Appendix C, but here follows a short summary of the new design:

• The circuit will be implemented in an FPGA using VHDL code. • The functional modes (A, B and C) will be the same.

• The parameter server will not be implemented, instead this functionality is placed in software in the simulation computers.

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• The communication interface will be an Ethernet interface instead of the HSDE interface.

• The new demands on the simulator, see above, will be fulfilled.

A description of the implementation of the circuit can be found in Section 3.4.

2.9 Field Programmable Gate Array

FPGA is short for Field Programmable Gate Array and is a technology for imple-menting advanced hardware without having to do an expensive and time consum-ing full custom design. An FPGA is a chip which consists of complex logic cells containing e.g. look-up tables (LUTs) and multiplexers. The cells are connected to each other via interconnections. Both the cells and the interconnections are programmable by the designer which makes FPGAs an easy and economic way to implement logic in hardware.[4]

The connection between the logic cells in an FPGA is managed by program-mable switches. These can be based on different technologies. The three most common technologies are RAM-based technology, flash-based technology and

anti-fuse technology. The former two are similar in the way that they are both

repro-grammable whereas the anti-fuse technology has one-time prorepro-grammable switches. The differences between RAM-based and flash-based FPGAs, on the other hand, is that the first is a volatile technology. Volatile means that if power fails to the circuit the content is lost. Therefore, when using RAM based technology a non-volatile memory chip, such as a flash chip, is needed outside the FPGA circuit to store the logic implementation. The content of the non-volatile chip is loaded to the FPGA on power-on which means that some extra start-up time is needed for RAM-based FPGAs. Flash-based FPGAs does not need an external flash chip, as RAM-based FPGAs does. Instead programmable, non-volatile flash cells, which controls the switches, are integrated in the chip. The advantage of this solution, apart from that no external memory chip is needed, is that the circuit is live directly at start-up because of the non-volatile property of the flash cells. The dis-advantage is that the speed of the circuits is lower in comparison to RAM-based FPGAs.

The anti-fuse technology instead uses a dielectric material in the switches. Normally this material has high impedance but when a high enough voltage is applied over the switch the material is altered to have low impedance which means that the switch closes. This process can not be undone but on the other hand no extra circuit or start-up time is needed as with RAM-based FPGAs.[4, 5]

The logic in the FPGA is implemented using a hardware description language (HDL). The two most common languages are VHDL and Verilog. The HDL source code for the implementation is translated to a bit-file using a set of software tools that the FPGA manufacturer supplies. The bit-file is used to program the FPGA according to the HDL design. A more detailed description of the VHDL design flow can be found in Section 3.2.

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2.10 Choosing the FPGA circuit 15

2.10 Choosing the FPGA circuit

The prerequisite of this project was that the design should be possible to implement in an FPGA. This was a demand by SBD and the reason for that was that SBD wanted to be able to more easily change the design if needed in the future. The first task was thus to choose an FPGA for the implementation. The division of SBD where this project has been carried out has a lot of experience of using the Actel FPGAs. Hence it would have been a natural decision to use one of their circuits. The disadvantage with the Actel FPGAs is that Actel uses the anti-fuse switch technology in their FPGAs, a technology that does not match the demand of a design that is easy to update. The author of this report, however, has a lot of experience of Xilinx FPGAs, which has a RAM-based switch technology. Therefore the Xilinx FGPAs were more closely studied to be able to differentiate the FPGA needed. First of all a decision had to be made as of what classification the FPGA should have. There are different circuit classifications which specify the condition of the environment (temperature, radiation etc.) that the circuit can be used in. Due to the fact that the circuit will be used in a computer server room that is air conditioned, no circuit with special classification was needed. That means that all Xilinx FPGAs could be used for the design.

The Xilinx FPGAs are divided into different families depending on the circuit generation they belong to. The latest and most advanced generation is the Virtex-4 family and this was also the family chosen for the project. The choice was based on several facts:

• The Xilinx design flow is well-known by the author of this thesis.

• The Virtex-4 family is state-of-the-art technology, meaning that high perfor-mance can be expected from the design.

• The Virtex-4 family is in the beginning of its life span, meaning that support for the products will be given for a long time.

• The larger circuits in the Virtex-4 family has enough integrated memory to be used for the dual-port memory needed for the design. This means no external memory would be needed.

2.11 The Virtex-4 family

Introduced in 2004 the Virtex-4 family is Xilinx’ latest and most advanced FPGA family. The product family is based on the older generation Virtex-II Pro FPGAs but in contrast to the .13 micron6 _{process used when manufacturing the} Virtex-II circuits a .09 micron process is used for the Virtex-4 family. To better target different segments of the market the family is divided into three platforms: the LX, SX and FX platforms. The three platforms aim at four different application

6_{Micron is another term for a micrometer, i.e. a millionth of a meter. In this case it refers to}

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domains: a logic domain, a DSP domain, a connectivity domain and an embed-ded domain. To meet these domain requirements the platforms are optimized in different ways. The LX platform is optimized towards highest performance and logic density, SX towards highest performance signal processing applications and FX towards Software-on-Chip (SoC) designs and high speed serial connectivity. In total the three platforms consists of 17 circuits.[6][7]

To be able to more easily develop these rather different platforms of FPGAs Xilinx has developed an architecture called Advanced Silicon Modular BLock (ASMBL, pronounced “assemble”). This architecture was developed to address the problem that in the past an FPGA designer could only choose between small or large and slower or faster FPGAs within the same family. Earlier larger FPGAs had more special features and smaller had less of the same features [8]. The new ASMBL architecture makes it possible for Xilinx to develop FPGAs with a mix of the various special features and hardware blocks available that does not depend on the size of the FPGA. Thus the three platforms could become reality.[6][7]

2.11.1 Hardware resources in Virtex-4

This section gives a brief description of the hardware resources, interesting for this project, in the Virtex-4 FPGAs. It starts with a description of the main logic resource, the Configurable Logic Blocks, and a memory resource called BlockRAM. After that the XtremeDSP slice which has been introduced with the Virtex-4 family will be described. All FPGAs also have Digital Clock Managers which is used for managing the different clocks available in the design.

The FX platform, which is aimed at embedded processing and serial connec-tivity, is equipped with another three hardware resources. From the older FPGA generation comes an embedded PowerPC405 core which was introduced with the Virtex-4 successor Virtex-II Pro. New for the Virtex-4 generation is the intro-duction of the integrated tri-mode Ethernet MAC block, for Ethernet capabilities, and the RocketIO transceivers, for fast communication. These FX specific hard-ware resources will not be described in more detail, though, as this thesis will only lightly touch the use of them.[6, 7]

Configurable Logic Blocks

The main logic resource in the Virtex-4 FPGA is the Configurable Logic Blocks (CLBs). The CLBs can be connected to each other via programmable intercon-nections and switching matrices, see Figure 2.8. Each CLB is made up of four slices. There are two different kinds of slices in each CLB. The two kinds are called SLICEM and SLICEL. Common to both of the slices are:

• two function generators (or look-up tables) • two storage elements

• arithmetic logic gates • large multiplexers

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2.11 The Virtex-4 family 17

• fast carry look-ahead chain

Figure 2.8. The figure shows the arrangement of the slices within the CLB. [9]

SLICEM also has the ability to support two additional functions: storing data using distributed RAM and shifting data with 16-bit registers.[9]

BlockRAM

Apart from the Distributed RAM situated in the CLBs the Virtex-4 FPGA also has what Xilinx calls BlockRAM (short BRAM). These are integrated blocks of mem-ory placed in columns over the entire Virtex-4 chips. Each BlockRAM primitive is 16 Kbit (18 Kbit if parity bits are included) and is a true dual-port memory7_{. The} circuits comes with varying amounts of BlockRAM, from 864 Kbits in the smallest one up to 9,936 Kbits in the largest FPGA. The primitives can be combined to-gether to form larger memory areas and can be configured to have different widths and depths. The best and easiest way to combine them is to use Xilinx CORE Generator which is used for customizing hardware resources in the FPGAs, see Section 2.11.3.[9]

XtremeDSP slice

The XtremeDSP slice, or DSP48 slice, was introduced with the Virtex-4 family. This block, as the name indicates, was developed to accelerate DSP designs, a very common application for FPGAs nowadays. The slices are fast enough to be clocked in up to 500 MHz according to Xilinx[9]. The XtremeDSP slice is available in varying quantities in all Virtex-4 circuits, from 32 slices in the smallest

7_{As mentioned in Section 2.7, dual-port means that the memory has two different I/O ports}

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circuits to 512 in the largest FPGA. In short the DSP block can be described as an 18x18 multiplier followed by a 3-input adder with a 48-bit output. The block can be configured to do various common DSP tasks such as add, multiply, MACC (multiply and accumulate) etc, see Figure 2.9.

Figure 2.9. The figure shows a simplified view of the XtremeDSP slice. The A and B inputs are 18 bits wide and the C input is 48 bits wide. PCIN is an input from a cascaded DSP48 slice. The arrows indicates a wire right shift by 17 bits. [10]

Digital Clock Managers

The Digital Clock Managers, DCMs, are advanced logic circuitry for managing clock signals in the design. There are four main features that the DCMs provide in a design:

• Clock Deskew

• Frequency Synthesis

• Phase Shifting

• Dynamic Reconfiguration

For the implementation of the DRFM design the second feature is the most in-teresting one. With the help of the frequency synthesis hardware in the DCM, an external input clock can be used to synthesize a new internal clock. The out-puts from the DCM provide different new clock frequencies derived from the input clock. New frequencies provided is a double frequency, a specified fraction of the

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2.11 The Virtex-4 family 19

frequency and an output frequency that is derived from the input frequency by si-multaneous division and multiplication. The first and last feature are also available as 180◦ phase shifted signals.[9]

SelectIO

SelectIO is the Virtex-4 technology for supporting a wide variety of I/O standards. The FPGAs provides up to 960 user I/Os that can be configured in up to 20 different electrical I/O standards. The SelectIO drivers and receivers are divided into blocks called input/output blocks, IOBs. Each IOB contains both input, output and a 3-state drivers which make them easy to configure for different data directions. The IOB is connected to a pair of logical blocks called ILOGIC and OLOGIC. These blocks provide logical resources for the IOB such as output and input registers.[9]

2.11.2 Intellectual Property blocks

To speed up the development of FPGA designs custom Intellectual Property blocks, IP blocks (also called IP cores), can be used. The IP blocks can be of two different kinds: hard IP blocks and soft IP blocks. Hard IP blocks are physi-cal blocks of logic in the circuit that are designed for specific purposes, for example the Virtex-4 has hard IP blocks for Ethernet communication and DSP operation, se Section 2.11.1 above. Soft IP blocks uses the available logic resources, CLBs, in the FPGA to create logical functions (e.g. adders, counters and accumulators) and system-level building blocks (e.g. bus interfaces and processors).

Next follows a description of the two soft IP blocks interesting for this imple-mentation, a counter and a comparator.

Binary Counter

The binary counter is a soft IP core from Xilinx which can be used to implement an up to 256 bits wide up/down counter. The counter has a load input which can be used to load values. The version used in the project is version 8, which is the first version supporting Virtex-4 FPGAs. This IP core can be customized using Xilinx CORE Generator, see 2.11.3 below.[11]

Comparator

The comparator is also a soft IP core from Xilinx. It can be used to implement efficient comparison logic that can perform the following functions: =, <>, ≤, <, ≥, >. The comparator has two input ports which can be up to 256 bits wide. To improve performance, which was necessary in this design, a pipelined version of the comparator can be implemented. The number of pipeline stages depends on the function to be implemented and the bit width. At the most 4 pipeline stages can be implemented but in the design it was only possible to implement one stage. The output port can both be asynchronous and synchronous. A synchronous output port means one extra latency cycle.[12]

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2.11.3 Xilinx CORE generator

Xilinx CORE generator (Coregen) is used to customize the different hardware resources in the FPGA or to generate IP blocks to be used in the design. Together with Coregen a catalogue of different functions and building blocks (cores) are included. In the Coregen interface, parameters can be specified which controls the behavior of the chosen core, see Figure 2.10. The implementation files needed are then generated by Coregen so that the core easily can be implemented in the design.

Figure 2.10. Screen shot from Coregen showing the interface were the parameters for the resources, in this case a dual-port memory, are specified.

2.12 Communication

The DRFM circuit has to be controlled by the simulation computers through a communication interface during run-time. A requirement of the communication interface was that it has to be fast enough for the control commands to be trans-mitted to the circuit. The simulation updating frequency is 100 Hz which means that the time between every update is 10 ms. Measurements have showed that the time available for sending control commands to the circuit is approximately 5 ms. Another requirement on the interface was that it should be a wide-spread well know standard. This section will describe the two communication alterna-tives, the VMEbus and the Ethernet standard, that have been reviewed during this thesis. After that the Internet protocol suite used in conjunction with the

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2.12 Communication 21

Ethernet standard is described. The section ends with a discussion of the choice of communication interface.

2.12.1 VMEbus

VMEbus is an industry standard defined in 1981 by Motorola, Mostek and Sig-netics. VMEbus is based on the older VERSAbus standard defined by Motorola in 1979. This standard never became popular in Europe. The reason was mainly because of dissatisfaction with the connectors used to connect the board into the backplane and the large form factor boards. The VMEbus, instead, uses the Eu-rocard form factor8 _{which already was popular in Europe at the time of VMEbus} introduction. This is also the origin of the name; VME stands for VersaModule Eurocard even though sometimes the E in VME also is referred to as Europe or European.[13][14]

After the initial version of VMEbus in 1981 several newer and extended ver-sions have emerged which has made it possible for the VMEbus to survive until today. No proprietary rights have been assigned to the standard which makes it possible for anyone to develop VMEbus products without paying any royalty fees or licenses. This property of the VMEbus standard is yet another important factor that made the standard so successful. Nowadays the VMEbus is used in a wide variety of fields such as in military and aerospace applications and in simulators as in ELSI at SBD.[13][14][15]

The VMEbus is an asynchronous bus, which means that it does not have a clock that synchronizes the transfers. Instead this is done by handshaking signals and the signaling speed is set by the slowest module connected to the bus. The VMEbus also has a master-slave architecture. This means that master modules that are connected to the bus is the ones which initiates transfers from other masters or slaves. All transfers are supervised by a special module called the system controller. There can be several masters on the same bus, which is why the VMEbus is called a multi-processing bus. The VMEbus has an address bus and a data bus which both can be up to 64-bit wide and can handle data transfer speeds of up to 80 MB/s.[13]

2.12.2 Ethernet

The Ethernet network system was invented by Bob Metcalfe in 1973 at the Xerox Palo Alto Research Center, PARC, in California. But it was not until 1980 that the original Ethernet standard was published by the DEC-Intel-Xerox vendor con-sortium. This standard is known as the DIX standard (based on the first letter in the company names). The DIX standard was then used as basis by IEEE9 _when the IEEE Local and Metropolitan Networks (LAN/MAN) Standards Committee developed the IEEE 802.3 standard. The 802.3 standard is the official Ethernet standard which has been complemented several times with new media systems and

8_{The Eurocard form factor is a more compact form factor and has better connectors than}

that used by the VERSAbus.

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capabilities to form the Ethernet of today. The Ethernet standard contains, for example, different standards of transfer speeds of which 100 Mbps over twist-pair cables (100BASE-TX) is the most used standard in households and companies to-day. This standard is also the standard interesting for this thesis, hence the focus will be on the 100BASE-TX standard.[16]

To be able to connect to an Ethernet network, an Ethernet interface is needed. The interface is a physical hardware that has all the circuits needed to communi-cate over the network. It can both be free-standing hardware or parts of it could be integrated in another circuit, as the integrated Virtex-4 Ethernet MAC.

Every Ethernet interface has a unique 48-bit address which is hard coded to the physical interface. The 48-bit address is divided into two 24-bit parts. The first half is called the OUI, which stands for Organizationally Unique Identifier. The OUI is a unique 24-bit number assigned by IEEE to every Ethernet vendor. The second half of the 48-bit address is assigned by the vendor and has to be a unique number. The two halves combined makes up the unique 48-bit Ethernet address which every Ethernet interface is equipped with. [16]

Data sent over an Ethernet based network is transmitted in Ethernet frames. A frame is a standardized set of bits used to carry data over the Ethernet system. In short the Ethernet frame consists of a header, a data field and a frame check sequence for error detection. The header is 14 byte long and contains the source address, the destination address and type. The addresses sent in the Ethernet frame are the 48-bit Ethernet addresses. The data to be sent is encapsulated inside the data part of the frame which can be from 46 bytes up to 1500 bytes. The data part must be at least 46 bytes; otherwise padding data is used to make the data field 46 bytes. For a more detailed description of Ethernet and the Ethernet frame see [16].

When wanting to network enable a device using off-the-shelf Ethernet products usually three parts are needed: An Ethernet Media Access Controller, a Physical

Layer Device and a Registered Jack type 45.

Media Access Controller. The sending and receiving of frames is controlled

by the Media Access Control (MAC) protocol (therefore the Ethernet ad-dress, mentioned above, is also called a MAC address). The protocol used by the MAC is called Carrier Sense Multiple Access Collision Detection (CSMA/CD). Carrier sense means that the protocol listens for activity and sends only if there is no activity on the channel used. Multiple access means that multiple nodes can share the same channel. If two nodes are trying to use the channel at the same time it is detected by the collision detection. The mode when using the CSMA/CD protocol is also called half-duplex mode. If two nodes are connected to each other via a dedicated channel full-duplex mode could be used. Dedicated channels are used between, for example, a node and switch. In this case the CSMA/CD protocol is not needed. The benefit of full-duplex mode is that both nodes can send at the same time doubling the transfer speed.[16]

Physical Layer Device. The physical layer device, PHY, is the part of the

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2.12 Communication 23

used, e.g. twisted-pair or fiber cable. The PHY is often called a transceiver. The name comes from that it transmits and receives signals. The EMAC and the PHY are often connected to each other via a Media Independent

Interface (MII). The MII is a standardized interface between the transceiver

and the EMAC used by the 100BASE-TX standard. This makes it possible to connect different media systems to the Ethernet interface.[16]

Registered Jack type 45. The RJ-45 jack is the connector for the twisted-pair

cable mentioned earlier. It is connected to the PHY and can be referred to as the Media Dependent Interface (MDI) in opposite to the MII.

2.12.3 The Internet protocol suite

When using higher level protocols these are carried inside the data field of the Ethernet frame. The protocols interesting for this thesis are the protocols which are parts of the Internet protocol suite. The suite is also often referred to as the TCP/IP protocol suite after the two most important protocols: the Internet

Protocol (IP) and the Transmission Control Protocol (TCP).

The job of the IP protocol is to move packets of data from a source to a destination. To be able to do that, every interface on an IP network, such as the Internet, is identified by a 32-bit binary number called an IP address. IP carries data for several different higher level protocols which are parts of the Internet protocol suite. If reliable transport over the network is needed, the TCP protocol has to be used. Several different functions is included in the TCP protocol to supervise the transport of data packets. For that reason TCP is able to discover lost packets and resend them if needed. Another protocol often used is the User

Datagram Protocol (UDP). UDP sends and receives datagrams10_{but, unlike TCP,}

UDP has no control of reliability11_{. UDP is most often used for sending streaming} media, such as audio and video, were on-time arrival is more important than reliability.

Even though there are a lot more protocols in the Internet protocol suite, the ones previous mentioned are the most interesting one for the DRFM application. Therefore no deeper description of the others will be conducted in this report and the reader is referred to [17] if more information about the protocol suite is wanted.

2.12.4 Choosing communication interface

The most important reason to use the VMEbus for communication was that it is an industry standard and that it already is well-known at SBD. Other important advantages of using the VME interface was the speed, the simplicity and the fact that a VMEbus VHDL IP core already had been developed at SBD. The disadvantage of VMEbus was the high cost of new hardware if the system would have to be increased in size. Furthermore, more DRFM circuit boards in the new system means that the length of the bus had to be increased using so called bus

10_{Units of information.}

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repeaters. Not only does this mean a considerably high cost, it also means that the speed goes down significantly. Therefore a new cheaper, high speed and well-spread communication standard was of interest. The choice fell on the Ethernet interface. Ethernet is a very wide spread industry standard for high speed data communication. The communication protocol to be used in the simulator can be chosen from a variety of protocols, for example, raw Ethernet, UDP or TCP could be used, see Section 2.12.2. The actual choice of protocol is not made during this thesis, instead it is up to the staff at ELSI to decide, depending on resources and the speed required.

2.13 Choosing Ethernet interface

As the needed Ethernet and Internet protocol technology and acronyms have been discussed we are ready to go into the choice of Ethernet interface.

The first alternative to look into was the new Virtex-4 FX family which comes with integrated Ethernet MAC (EMAC) and PowerPC processor cores. The idea was to use the EMAC for communication and to use the PowerPC for handling the TCP/IP stack. A TCP/IP stack for the PowerPC integrated in the Virtex-4 is available from a company called Treck Inc.12_{. The TCP/IP stack from Treck} is designed in cooperation with Xilinx and can be used in the Virtex-4 with the PowerPC processor. When tested on a Virtex-II Pro system a through-put of 785 Mb/s [18] has been achieved which is well enough for the requirements of this project. The disadvantage of this solution is that much more development time would have been needed, time which was assumed not available.

Because of the limitations of the project, that is, only the DRFM function was to be implemented in the FPGA during the given time, a free-standing Ethernet module had to be used. Hence, the second alternative was to scan the market for ready-to-use Ethernet modules. The market scan resulted in a review of the modules found. The review will serve as a future basis for deciding the Ethernet module needed. Before the review, requirements was set up that the module had to fulfill. Five requirements were identified:

• High enough data transfer speed

• Available TCP/IP stack

• Small enough to fit on a circuit board

• Preferably both TP port, PHY and MAC available on the module • Availability on the market

These requirements are used in Section 2.13 to make a preliminary choice of Ethernet module. But first, the module reviews:

12_{Treck Inc. is a company that has been designing real-time embedded internet protocols since}

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2.13 Choosing Ethernet interface 25

Rabbit RCM3200

Rabbit Semiconductors13_{is a fabless semiconductor company that is specialized in} high-performance 8-bit microprocessors. They have also developed several different Ethernet modules that uses their microprocessors. The most interesting module, which best suits this projects requirements, is the Rabbit RCM3200 module. This is a small Ethernet module which consists of a Rabbit 3000 microprocessor, an Ethernet controller, memory and a 10/100 Ethernet port. The Rabbit 3000 is an 8-bit microprocessor and runs at up to 44.2 MHz. It can be programmed using a development system called Dynamic C. Together with the development system comes a royalty-free TCP/IP stack (and the source code). According to the RCM3200 FAQ [19] the current maximum receive speed is approximately 3 Mbps using TCP/IP on the RCM3200.[20]

Netburner Mod5282

Netburner14_{is a company that provides embedded Ethernet for quick network} en-abling of products. The Netburner Mod5282 is a small Ethernet module based on the Coldfire MCF5282 processor from Freescale Semiconductor (former Motorola). The MCF5282 is a 32-bit processor, runs at up to 66 MHz and has a built in 10/100 Ethernet MAC. No throughput information is available for the Mod5282 module. A good guess is that the throughput will be better then the RCM3200 module be-cause of the more powerful processor handling the communication protocols.[21]

Epson S1S60000

The Epson15 S1S60000 is a network controller with built-in TCP/IP protocol (firmware). It is a single chip, thus it has to be complemented with a PHY chip and a RJ-45 port. The controller can be controlled through GPIO’s. According to the manual for the circuit the maximum effective transfer rate (over UDP) is approximately 5.5 Mbps for the S1S60000 circuit [22]. Worth to notice is that a new chip called S1S60020 based on the S1S60000 is under development. The preliminary data sheet for the chip claims that a throughput of 20 Mbps or more could be achieved [23]. The primary reason for the boost in throughput over the older chip is the hard-wiring of some portions of the processing.

WizNet NM7010B

WizNet16_{is a Korean company that has developed completely hard wired TCP/IP} and Ethernet MAC chip. The most recent is called W3150. WIZnet has combined this chip together with a 10/100 Ethernet PHY and an Ethernet port to the NM7010B module. The data sheet for the NM7010B was not available at the WIZnet home page during the writing of this review. Hence no speed informa-tion for the module is available. Informainforma-tion on the home page for the W3150

13_{http://www.rabbitsemiconductor.com}

14

http://www.netburner.com

15_{http://www.epson-electronics.de}

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chip, on the other hand, claims that the throughput of the chip can be up to 11 Mbps depending heavily on the CPU controlling the chip. The real throughput is somewhat unclear due to the fact that the maximum throughput according to the W3150 Brochure is claimed to be up to 25 Mbps [24].

2.13.1 The choice of Ethernet module

The first thing to be said is that no real component selection will be done during this thesis. The final selection will not be done until the DRFM circuit board will be designed. This review and choice of Ethernet module is more of a proposal and serves as basic data for decision-making.

Three important properties of the wanted modules have been identified. The three properties are

• data transfer speed

• the easiness of implementing the interface • the documentation of the interface

Starting with the speed issue a simple estimation of the needed data transfer speed is approximately 4.5 Mbps, see Example 2.2. Except the Netburner module (which has no speed data) and the Rabbit module (having only 3 Mbps receiving speed) the two other modules could live up to the requirement. As always with performance measures of computer products values of speed can not be taken too serious. E.g. it is hard to tell under what conditions the throughput values have been measured and what protocols have been used.

The WIZNet, Netburner and Rabbit modules are all complete with PHY chip and RJ-45 port whereas the Epson chip has to be completed with the PHY chip and port. This makes the first three modules easier to handle and to connect to the DRFM circuit board. All modules except WIZNets has good or very good documentation. The problem with WIZNets documentation is the lack of correct (and understandable) English and the slow and hard navigated home page.

Summing up the properties wanted neither of the modules could live up to all of the requirements. A decision had to be made anyway and the choice fell on the Netburner module. This module has good documentation and is easy to implement in a design. It lacks specification of data transfer speed but as the pro-cessor equipped on the module is rather powerful a good guess is that the speed requirement will be easy to live up to. Another advantage is that the CPU on the module could be used for other calculations and not only for the communication. Hence a development kit for the Mod5282 and an extra Mod5282 has been bought by SBD and speed measurements will be done after this thesis has come to an end.

Example 2.2: Calculation of data transfer speed

This example is intended to give an approximate calculation of the transfer speed needed to update the DRFM circuit with control data during run-time.

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2.13 Choosing Ethernet interface 27

An overestimation is that forty 24 bit commands have to be sent to the Ethernet module every cycle during run-time. This makes a total of

40 × 24 bit = 960 bit

to be sent to every DRFM circuit connected to the Ethernet module. At the most four DRFM circuits will be connected to the same Ethernet module which makes a total of

960 × 4 bit = 3840 bit

that has to be sent every simulation cycle. To be able to calculate the correct data transfer speed the header of the used communication protocols also needs to be taken into account. Different protocols could be used for communication, the final decision of protocol is not made during the work of this thesis, but a good guess is that the UDP or the TCP protocol will be used. Of these two protocols, TCP has the largest header. The TCP header can be up to 60 bytes. The TCP frame is encapsulated inside an IP frame which header also can be up to 60 bytes. This makes a total of

3840

8 bytes + 2 × 60 bytes = 600 bytes

The IP frame in its turn is encapsulated inside the data part of an Ethernet frame. The Ethernet header is always 14 bytes. Therefore totally

600 bytes + 14 bytes = 614 bytes

have to be sent every simulation cycle. The simulator is updated at 100 Hz which makes every cycle 10 ms. Unfortunately the whole cycle cannot be used to send data though. A part of it will be used for other processes on the CPU controlling the DRFM circuits. A low estimation is that 1 ms can be used for sending control data17_{. This finally makes the data transfer speed needed}

614

1 × 10−₃ MB/s = 614 kB/s ≈ 4.9 Mbps [17]

17_{Measurements of the processes have showed that half of the cycle, 5 ms, is available for}

sending control data to the DRFM circuits. In this case, 1 ms is used to approximate the result in the right direction.

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Implementation of a Digital Radio Frequency Memory in a Xilinx Virtex-4 FPGA

Implementation of a Digital Radio Frequency

Memory in a Xilinx Virtex-4 FPGA

Implementation of a Digital Radio Frequency

Memory in a Xilinx Virtex-4 FPGA

Examensarbete utfört i elektroniksystem

vid Tekniska högskolan i Linköping

av

Abstract

Acknowledgements

List of Acronyms

Contents

List of Figures

List of Tables

Chapter 1

Introduction

1.1

Background

1.2

Purpose

1.3

Method

1.4

Limitations

1.5

Thesis outline

Chapter 2

Technology & Background

2.1

Saab Bofors Dynamics AB

2.2

Radar seekers

2.3

Electronic countermeasures

2.4

Digital Radio Frequency Memory

2.5

The Electronic Warfare Simulator

2.6

The Target Echo Generator

2.7

The current DRFM circuit

2.7.1

The function of the DRFM

2.8

The new DRFM circuit

2.9

Field Programmable Gate Array

2.10

Choosing the FPGA circuit

2.11

The Virtex-4 family

2.11.1

Hardware resources in Virtex-4

2.11.2

Intellectual Property blocks

2.11.3

Xilinx CORE generator

2.12

Communication

2.12.1

VMEbus

2.12.2

Ethernet

2.12.3

The Internet protocol suite

2.12.4

Choosing communication interface

2.13

Choosing Ethernet interface

2.13.1

The choice of Ethernet module