Study of Time-Interleaved SAR ADC andImplementation of Comparator for High DefinitionVideo ADC in 65nm CMOS Process

(1)

Institutionen för systemteknik

Department of Electrical Engineering

Examensarbete

Study of Time-Interleaved SAR ADC and

Implementation of Comparator for High Definition

Video ADC in 65nm CMOS Process

Examensarbete utfört i Elektroniksystem vid Tekniska högskolan vid Linköpings universitet

av

Sara Qazi (sarqa372@student.liu.se)

LiTH-ISY-EX--2010/4344--SE

Linköping 2010

(2)

(3)

Study of Time-Interleaved SAR ADC and

Implementation of Comparator for High Definition

Video ADC in 65nm CMOS Process

Examensarbete utfört i Elektroniksystem

vid Tekniska högskolan i Linköping

av

Sara Qazi (sarqa372@student.liu.se)

LiTH-ISY-EX--2010/4344--SE

Handledare: Dr. J. Jacob Wikner

isy, Linköpings Universitet

(4)

(5)

Avdelning, Institution

Division, Department

Division of Electronic Systems Department of Electrical Engineering Linköpings universitet

SE-581 83 Linköping, Sweden

Datum Date 2010-12-21 Språk Language Svenska/Swedish Engelska/English Rapporttyp Report category Licentiatavhandling Examensarbete C-uppsats D-uppsats Övrig rapport

URL för elektronisk version

http://www.systems.isy.liu.se http://www.es.liu.se ISBN — ISRN LiTH-ISY-EX--2010/4344--SE

Serietitel och serienummer

Title of series, numbering

ISSN

—

Titel

Title

Studie av Tidsmultiplexad SAR ADC och Konstruktion av komparator för högup-plöst Video ADC i 65nm CMOS.

Study of Time-Interleaved SAR ADC and Implementation of Comparator for High Definition Video ADC in 65nm CMOS Process

Författare

Author

Sara Qazi (sarqa372@student.liu.se)

Sammanfattning

Abstract

The Analog to Digital Converter (ADC) is an inevitable part of video Analog Front Ends (AFE) found in the electronic displays today. The need to integrate more functionality on a single chip (there by shrinking area), poses great design challenges in terms of achieving low power and desired accuracy.

The thesis initially focuses upon selection of suitable Analog to Digital Con-verter (ADC) architecture for a high definition video analog front end. Successive Approximation Register (SAR) ADC is the selected architecture as it scales down with technology, has very less analog part and has minimal power consumption.

In second phase a mathematical model of a Time-Interleaved Successive Ap-proximation Register (TI-SAR) ADC is developed which emulates the behavior of SAR ADC in Matlab and the errors that are characteristic of the time interleaved structure are modeled.

In the third phase a behavioral model of TI-SAR ADC having 16 channels and 12 bit resolution, is built using the top-down methodology in Cadence simulation tool. All the modules were modeled at behavioral level in Verilog-A. The func-tionality of the model is verified by simulation using signal of 30 MHz and clock frequency of 300 MHz, using a supply voltage of 1.2 V. The desired SNDR (Signal to Noise Distortion ratio) 74 dB is achieved.

In the final phase two architectures of comparators are implemented in 65nm technology at schematic level. Simulation results show that SNDR of 71 dB is achievable with a minimal power consumption of 169.6 µW per comparator running at 300 MHz.

(6)

(7)

Abstract

The Analog to Digital Converter (ADC) is an inevitable part of video Analog Front Ends (AFE) found in the electronic displays today. The need to integrate more functionality on a single chip (there by shrinking area), poses great design challenges in terms of achieving low power and desired accuracy.

The thesis initially focuses upon selection of suitable Analog to Digital Con-verter (ADC) architecture for a high definition video analog front end. Successive Approximation Register (SAR) ADC is the selected architecture as it scales down with technology, has very less analog part and has minimal power consumption.

In second phase a mathematical model of a Time-Interleaved Successive Ap-proximation Register (TI-SAR) ADC is developed which emulates the behavior of SAR ADC in Matlab and the errors that are characteristic of the time interleaved structure are modeled.

In the third phase a behavioral model of TI-SAR ADC having 16 channels and 12 bit resolution, is built using the top-down methodology in Cadence simulation tool. All the modules were modeled at behavioral level in Verilog-A. The func-tionality of the model is verified by simulation using signal of 30 MHz and clock frequency of 300 MHz, using a supply voltage of 1.2 V. The desired SNDR (Signal to Noise Distortion ratio) 74 dB is achieved.

In the final phase two architectures of comparators are implemented in 65nm technology at schematic level. Simulation results show that SNDR of 71 dB is achievable with a minimal power consumption of 169.6 µW per comparator run-ning at 300 MHz.

(8)

(9)

Acknowledgments

First of all I would like to thank Allah “Alhamdulilallah”, for giving me the strength to accomplish this task.

I am extremely grateful to my supervisor J. Jacob Wikner for being a guide, a mentor, an amazing teacher and most of all a critic. I have learned a lot from him and its been great fun especially with the weekly meetings.

I am thankful to Aiysha. A. Khalifa for being a wonderful friend and being a great support throughout my masters studies.

I owe my deepest gratitude to my parents (Ama and Aba) and my family (three sisters) for believing in me and for their love and prayers.

I am very thankful to my husband Fahad for his friendship, love, support, patience and believing in my potential. I can never thank him enough for all he has done for me especially having fruitful technical discussion round the clock even at home (bearing with me).

Lastly, I offer my regards and blessings to all of those who supported me in any respect during the completion of the project.

(10)

(11)

List of Figures

1.1 Block diagram of video Analog Front End IC [4]. . . 10

2.1 Ideal ADC characteristic [8]. Copied from Analog-to-Digital Con-verters Testing by Kent. H. Lundsberg 2002. . . . 14

2.2 Quantization error for an ideal ADC [8]. Copied from Analog-to-Digital Converters Testing by Kent. H. Lundsberg 2002. . . . 14

2.3 Offset and gain errors in ADC [8]. Copied from Analog-to-Digital Converters Testing by Kent. H. Lundsberg 2002 . . . . 15

2.4 Non-linear errors in ADC [8]. Copied from Analog-to-Digital Converters Testing by Kent. H. Lundsberg 2002 . . . . 16

3.1 Block diagram of Flash ADC [9]. . . 20

3.2 Block diagram of Pipelined ADC (12-bit ADC with four 3bit stages and a 4bit flash ADC) [10]. . . 21

3.3 Block diagram of Sigma Delta ADC (1-bit ADC) [11]. . . 22

3.4 Block diagram of SAR ADC [12] . . . 23

4.1 SAR operation [12]. . . 24

4.2 Block diagram showing submodules of Successive Approximation Register ADC [12]. . . 25

4.3 Block diagram of Time-Interleaved ADC. . . 27

5.1 Block diagram of MATLAB Model of Time-Interleaved ADC. . . 29

5.2 Input signal (spectrum and time domain graph). . . . 30

5.3 Channel input signals (time domain graph). . . . 30

5.4 Output signal (spectrum and time domain graph). . . . 31

5.5 Output spectrum with gain errors σa= 0.1. . . . 32

5.6 Output spectrum with offset errors σo= 0.1. . . . 33

5.7 Output spectrum with channel jitter σt= 10ps. . . . 34

5.8 Output spectrum with cycle to cycle jitter σc2c= 0.1ns. . . . 35

5.9 Delta signal in absence of error (spectrum and time domain graph). 36 5.10 Delta signal in the presence of gain error (spectrum and time domain graph). . . . 37

5.11 Delta signal in the presence of offset error (spectrum and time domain graph). . . . 37

5.12 Delta signal in the presence of channel jitter (spectrum and time domain graph). . . . 38

5.13 Delta signal in the presence of long-term/drift jitter (spectrum and time domain graph). . . . 38

(12)

5.14 Delta signal in the presence of cycle-to-cycle jitter (spectrum and

time domain graph). . . . 39

5.15 Standard frame for video display testing. . . 40

5.16 Effect of addition of Additive White Gaussian Noise (AWGN) on frame. . . 40

5.17 Effect of offset error on frame. . . 41

5.18 Effect of gain error on frame. . . 41

5.19 Effect of distortions on frame. . . 42

5.20 Effect of fine quantization (12-bit) on frame. . . 43

5.21 Effect of intermediate level of quantization (8-bit) on frame. . . . 43

5.22 Effect of coarse quantization (1-bit) on frame. . . 44

6.1 The 16 phases and the system clock. . . 49

6.2 Block diagram of 16 channel 12-bit TI-SAR ADC. . . 50

6.3 Block diagram of 16 channel 12-bit TI-ADC (Cadence Block ). . . 51

6.4 Block diagram of channel SAR ADC. . . 52

6.5 SAR ADC internal block diagram (Cadence block ) . . . . 53

6.6 TI-SAR ADC test bench (Cadence block ). . . . 55

6.7 Time domain output of TI-SAR ADC (Cadence block ). . . . 56

7.1 Latch-only comparator operation [15]. . . 61

8.1 Transistor-level schematic of pre-amplifier. . . 64

8.2 Gain of pre-amplifier. . . 65

8.3 Offset of pre-amplifier . . . 65

8.4 Transistor-level schematic of the SR latch. . . 67

8.5 Transistor-level schematic of the comparator1 architecture. . . . 68

8.6 Propagation delay of comparator1. . . 69

8.7 Offset of comparator1. . . 70

8.8 Transistor-level schematic of comparator2 . . . 72

8.9 Propagation delay of comparator2. . . 73

8.10 Offset of comparator2. . . 74

9.1 TI-SAR ADC test bench (Cadence block ) . . . . 77

9.2 Histogram plot of ADC for sinusoidal input. . . 78

9.3 SNDR versus signal amplitude graph for TI-SAR ADC using comparator1. . . 79

9.4 ENOB versus signal amplitude graph for TI-SAR ADC using comparator1. . . 79

9.5 Result of FFT test. Output spectrum of TI-SAR ADC using comparator1 for signal amplitude of 0.25 Vpeak. . . 80

9.6 Result of code density test. Histogram of TI-SAR ADC using comparator1 for signal amplitude of 0.25 Vpeak. . . 81

9.7 SNDR versus signal amplitude graph for TI-SAR ADC using comparator2. . . 82

9.8 ENOB versus signal amplitude graph for TI-SAR ADC using comparator2. . . 83

(13)

A.1 Video signal composition [22]. Copied from Video Signal

Mea-surement and Generation Fundamentals Dec 11, 2009 . . . . 94 A.2 Video levels [22]. Copied from Video Signal Measurement and

Generation Fundamentals Dec 11, 2009 . . . . 95 A.3 Monochrome composite video signal (luma steps from white to

black) [22]. Copied from Video Signal Measurement and

Gener-ation Fundamentals Dec 11, 2009 . . . . 98 A.4 Color information signal for a color bar line (including the color

burst) [22]. Copied from Video Signal Measurement and

Gener-ation Fundamentals Dec 11, 2009 . . . . 98 A.5 Color Composite Video Signal for a Color Bar Line [22]. Copied

from Video Signal Measurement and Generation Fundamentals

(14)

List of Tables

1.1 Video ADC specification (modified from [2]). . . 12

3.1 Comparison of ADC architectures modified from [13]. . . . 23

5.1 SNDR in the presence of errors. . . 36

6.1 Summary of simulation result of the TI-SAR ADC behavioral model. . . 57

8.1 Optimized component values for pre-amplifier. . . 64

8.2 Achieved simulation results of pre-Amplifier. . . 66

8.3 Optimized component values for comparator1. . . 69

8.4 Achieved simulation results of comparator1. . . 71

8.5 Optimized component values of comparator2. . . 73

8.6 Achieved simulation results of comparator2 . . . 75

9.1 Summary of the simulation results of the TI-SAR ADC using comparator1. . . 81

9.2 Summary of the simulation results of the TI-SAR ADC using comparator2. . . 86

9.3 Simulation results of the TI-SAR ADC using comparator1 with ideal pre-amplifier. . . 89

9.4 Simulation results of the TI-SAR ADC using comparator2 with ideal pre-amplifier. . . 91

(15)

7.2.1 Resolution . . . 58 7.2.2 Gain . . . 59 7.2.3 Propagation Delay . . . 59 7.3 Comparator Non-idealities . . . 59 7.3.1 Offset Voltage . . . 60 7.3.2 Kick-back Noise . . . 60 7.3.3 Metastability . . . 60 7.4 Types of Comparators . . . 60 7.4.1 Open-loop Comparator . . . 61 7.4.2 Latch-only Comparator . . . 61

(17)

7.4.3 Latch with Pre-amplifier . . . 62

8 Implementation of High-speed, Low-offset Comparators 63 8.1 Pre-amplifier . . . 63

8.1.1 Architecture of Pre-amplifier . . . 63

8.1.2 Simulation Results of Pre-amplifier . . . 64

8.2 Comparator . . . 66

8.2.1 Architecture of Comparator1 . . . 68

8.2.2 Simulation Results of Comparator1 . . . 68

8.2.3 Architecture of Comparator2 . . . 71

8.2.4 Simulation Results of Comparator2 . . . 72

9 Simulation Results 76 9.1 Simulation Setup . . . 76

9.1.1 FFT Test . . . 78

9.1.2 Code density Test . . . 78

9.2 Simulation using Comparator1 . . . 78

9.3 Simulation using Comparator2 . . . 82

9.4 Simulation using Ideal Pre-amplifier . . . 87

10 Conclusion and Future Work 92 10.1 Conclusion . . . 92

10.2 Future Work . . . 92

A Video Basics Review 93 A.1 Video on Screen . . . 93

A.2 Video Signal . . . 93

A.2.1 Video Levels . . . 95

A.3 Video Resolution . . . 96

A.4 Video Formats . . . 96

A.4.1 Television Video Formats . . . 96

A.4.2 Computer Video Formats . . . 96

A.5 Video Interfaces . . . 98

A.5.1 Composite/CVBS Interface . . . 98

A.5.2 S-video Interface . . . 98

A.5.3 Component Interface . . . 99

(18)

Chapter 1

Introduction

In this chapter the motivation for the thesis is discussed. The working environ-ment for the project, the objectives and scope of the thesis are explained. Lastly contents of the thesis work are summarized.

Note: It is recommended that reader reads appendix A which contains a brief account of video basics, so the discussion in chapter 1 is better understood.

1.1 Motivation

Analog video interfaces are very important parts of digital home and personal entertainment systems. This is due to the fact that they deliver extremely high image quality with minimal power consumption, still maintaining compatibility with most modern and earlier-generation video devices where analog video in-terfaces are the prevalent video interface. Earlier analog video inin-terfaces were implemented using external components. To meet the needs of today’s advanced consumer electronics such as DVD players, digital TVs and set-top boxes, inte-grating high-speed analog interface Intellectual Property (IP) (containing ana-log video interfaces and other multimedia anaana-log and digital interfaces) into Systems on Chip (SoCs) has become difficult to achieve the desired processing power and image quality [3].

Currently available video formats can be divided into the following reso-lution categories: standard TV (PAL, NTSC, etc.), HDTV (e.g., 1080p) and widescreen VGA formats (e.g., 1920x1200) for PC graphics. They demand ab-solutely flawless transmission of color, brightness and synchronism information over a long cable. To meet this, the video transmitter should be able to trans-mit the video signal reliably and independent of the quality of the transmission cable. On the other hand the receiver must be able to accurately receive the sig-nal and decode the synchronism information in order to re-create a high-quality image [3].

Keeping up with today’s consumer electronic products market trend inte-grating increased functionality into the same digital SoC is the only sound choice, which further tightens the requirements in terms of power dissipation, form-factor reduction and ability to handle multiple video sources [3].

(19)

Motivation Introduction

1.1.1 Video Analog Front End IC

The thesis is focused upon Analog to Digital converter (ADC) design for a video Analog Front End (AFE) targeting video digitization in handheld devices like microprojectors and laptops. The goal is to achieve low power consumption with maintained accuracy. The project has the following distinct features.

• High resolution, 12-bit digitizing channel • Conversion rate as high as 300 MHz

• Usage of reduced power supply as low as 1V • 65 nm CMOS process

• All digital PLL and DLL

The video AFE project at the Electronics system division at the department of Electrical Engineering Link¨oping university is unique project following the SCRUM project model. The main project is parsed into different master the-sis works, where all members get together for a weekly meeting, discuss their progress and the supervisor delivers tool oriented talks. Information during the week is mainly shared via email group so all can participate in discussions and learn. The vision is take the modules all the way to the layout and build a state of the art video AFE Integrated Circuit (IC) that will be optimized every year by students and researcher at the division and then eventually taped out.

The detailed block diagram of the video AFE IC is shown in Fig. 1.1. The figure shows that the video AFE consists of two different channels, the time/reference channel and the digitizing channel.

1.1.2 Time-Reference Channel

The time-reference channel consists of the blocks that generate clock signals, synchronization signals and reference voltage and currents for the rest of the chip. The signals generated in this channel are vital to the chip as the digitiz-ing channel functionality is dependent upon them [4]. The function of blocks contained in the channel are briefly explained below.

Slicer

The slicer detects timing information in the input video signal, it might come from the digital domain or an external triggering signal [4].

Multiplexer

The multiplexer selects the correct reference for the current, voltage or time reference [4].

Phase Locked Loop (PLL)

The PLL is designed as an all digital device that aligns its output clock (at a higher frequency) to the input reference. The PLL output frequency can range from 10 to 300 MHz. The PLL is required to achieve a 50% duty cycle, so that the delay chain in the DLL can be implemented with half the number of element [4].

(20)

Motivation Introduction

Figure 1.1: Block diagram of video Analog Front End IC [4]. Delay Locked Loop (DLL)

The DLL will shift the rising edge of the clock in a controlled manner and will then produce an output clock which has the same frequency as the input, but with another phase. It needs to produce a total of 32 equally spaced phases [1, 4].

Oscillator

Oscillator is an ultra low power,RC type wake up-oscillator which maintains a standby mode, unless digitally triggered by some on-screen activity [1, 4]. Bandgap reference

A bandgap reference ensures a supply voltage for all modules that is safe from Process-Voltage-Temperature variations [1, 4].

Regulator

The block is responsible for generating voltages required by the chip compo-nents. It will take in supply voltage and generate regulated supply in the range of 1-1.2 V and reference voltages for the ADC [1, 4].

(21)

ADC Specifications Introduction

1.1.3 Digitizing Channel

The digitizing channel is composed of blocks that accept the video signal, process it and digitize it. Digital blocks that are for correction are also a part of this channel. Some small blocks that generate references for the ADC are also shown. The video AFE IC has five such channels to cover different video standards [1, 4]. Input Multiplexer

The input multiplexer provides an interface with the external world, it should have high linearity around 60 dB and a bandwidth of 500 MHz to meet the requirements of all formats [1, 4].

Clamp circuit

The purpose of the block is DC restoration. This circuit adjusts the clamp level to the correct brightness of the picture during the back porch or the sync tip section of the video signal [1, 4].

Anti-Aliasing Filter

This filter acts like a pre-select filter, to remove aliases (images) formed as a result of Digital to Analog Converter (DAC) and ADC sampling frequency. The use anti-aliasing filter results in significant improvement of image quality [1, 4]. Programmable Gain Amplifier (PGA)

Programmable Gain Amplifier takes multiplexed and filtered video signal from the mux-clamp block and is referenced from a DAC for Sync-tip compensa-tion. The operational transconductance amplifier designed for the PGA is a novel Cascaded Fully Balanced Pseudo Differential OTA with common mode feedforward and inherent common mode feedback detector.

ADC

The ADC is takes the signal from PGA and digitizes it. The architecture se-lected for the video ADC is Time-Interleaved Successive Approximation Register (TI-SAR) ADC. The ADC is a module that mainly decides the quality of the image that is quantized, so it is very important for the correct function of the video AFE IC. (Details about ADC are discussed in later chapters.)

1.2 ADC Specifications

The ADC for the video AFE needs to meet the specifications, given in Table. 1.1. The requirements of the sub modules within the ADC will be dictated by these requirements.

1.3 Objectives

(22)

Thesis Organization Introduction

Table 1.1: Video ADC specification (modified from [2]).

Item Value Unit

Resolution 12 bits Sample Frequency 270 to 330 MHz Video Bandwidth 6 30 MHz Circuit Bandwidth 500 MHz SNDR 74 dB Input Range 0.8 to 1.2 Vpp Supply Voltage (VDD) 1 to 2.5 V Latency 6 20 Clock cycles Power Consumption 6 30 mA

• Select a suitable ADC architecture for a video application, which is low

power, area efficient, scalable with technology, has maintained accuracy and also supports high sampling rates.

• Develop a mathematical model of the selected architecture, modelling

er-ror sources, studying their effect on system performance.

• Develop a fully functional behavioral model of the selected ADC,using

Verilog-ams blocks.

• Design a schematic level circuit of the comparator of ADC, study behavior

and verify it meets the specifications.

• Create layout of the comparator used in the ADC.

The thesis report reflects how various goals are achieved and also interprets the simulation results obtained.

1.4 Thesis Organization

The thesis report is organized into various chapters. A brief summary of the contents of the each chapter is provided in this section. Chapter 2, reviews the

fundamentals of Analog to Digital conversion, also touching upon the static and dynamic performance metrics of ADCs. Chapter 3 provides brief explanation of the contemporary ADC architectures and gives a comparison of the archi-tectures to motivate the selection of a suitable ADC for the AFE. Chapter 4 contains a detail discussion about of SAR ADC. Chapter 5 discusses concisely the mathematically formulation of ADC and errors modelling of error that are characteristic of video and TI-ADCs. Results are used to draw some conclusions. Chapter 6 focuses mainly on the development of a behavioral top level model of TI-ADC and the timing scheme which is very essential for its proper operation. Results are used to draw appropriate conclusions. Chapter 7 is composed of comparator performance metrics, types and some issues of concern while de-signing comparators. Chapter 8 mainly deals with the implementation of the comparator for the ADC. Chapter 9 presents the simulation setup and discusses the obtained results. Chapter 10 concludes the thesis work and discusses the future prospects. Appendix A provides a brief review of video basics.

(23)

Chapter 2

ADC Fundamentals and

Performance Metrics

In this chapter the fundamentals and characterization of Analog to Digital Con-verters are presented.

2.1 Analog to Digital Converter (ADC)

An ADC is a device that takes an analog input and outputs digital codes since it has both analog and digital functions, it is a mixed-signal device. An ADC has an analog reference voltage against which the analog input is compared. The input signal varies between 0 and Full Scale (FS), and it is converted to a digital word of N-bits. The digital output word signifies what fraction of the reference voltage is the input voltage [5].

2.1.1 Resolution

The resolution of an ADC is the distinct analog levels that can be represented by the binary word. for an ideal N-bit ADC there are 2N _{analog levels ad thus}

the resolution is said to be N-bit. The smallest step that can be discriminated by an N-bit ADC is VLSB = VF S/2N, where VF Srepresents the full scale range

of the converter [6]. The size of the LSB compared to the total code range is sometimes also referred to as resolution of the converter so for an N-bit ADC, thus resolution would be 1/2N_.

2.1.2 Quantization Error

The quantization error is introduced due to quantization of an analog (continu-ous) signal to set of discrete values. For ideal ADC it is VLSB/2. It is modelled

as white noise that is uncorrelated to the signal, which is a good estimation for large number of quantization levels [6]. Considering the error as white noise having equal probability lying in the range of ±VLSB/2 the resulting noise power

is given in an equation below.

(24)

Static Performance Metrics ADC Fundamentals and Performance Metrics

Figure 2.1: Ideal ADC characteristic [8]. Copied from Analog-to-Digital

Con-verters Testing by Kent. H. Lundsberg 2002.

Figure 2.2: Quantization error for an ideal ADC [8]. Copied from

Analog-to-Digital Converters Testing by Kent. H. Lundsberg 2002.

2.2 Static Performance Metrics

Static errors are deviation of the converter from the ideal characteristics, they depend only upon the input signal that is being converted. The measures of static performance of an ADC are explained below.

(25)

Static Performance Metrics ADC Fundamentals and Performance Metrics

2.2.1 Offset Error

Offset error is the deviation in the ADC’s behavior at zero. The first transition voltage should be 1/2 LSB above analog ground. Offset error is the deviation of the actual transition voltage from the ideal 1/2 LSB. Offset error can consid-erably reduced by calibration [8]. Fig. 2.3 clearly shows what effect offset error has on the ideal ADC characteristic. (Compare Fig. 2.1 and 2.3.)

2.2.2 Gain Error

Gain error is the deviation in the slope of the line through the ADC’s end points at zero and full scale from the ideal slope of 2N_/V

F S codes-per-volt. The gain

error is easily corrected by calibration [8]. Fig. 2.3 illustrates how the slope of the ideal ADC characteristic changes due to Gain error. (Compare Fig. 2.1 and

2.3.)

Figure 2.3: Offset and gain errors in ADC [8]. Copied from Analog-to-Digital

Converters Testing by Kent. H. Lundsberg 2002

2.2.3 Differential Non-Linearity (DNL)

DNL is the deviation of the code transition widths from the ideal width of 1 LSB. For an ideal ADC, DNL is zero everywhere [8].

2.2.4 Integral Non-Linearity (INL)

INL is the distance of the code centers in the ADC characteristic from the ideal line. If all code centers land on the ideal line, the INL is zero everywhere [8].

(26)

Dynamic Performance Metrics ADC Fundamentals and Performance Metrics

Mathematically INL is best expressed as the sum of DNL for each code [7].

IN Li= k

X

i+=1

DN Li (2.2)

It important to mention here that in applications offset and gain errors are acceptable INL is specified with respect to a best fit line rather than the ideal transfer characteristic.

2.2.5 Missing codes

Missing codes term corresponds to the output digital codes that are not pro-duced for any input voltage, mainly due to large DNL [8]. Wide codes occur as a result of positive DNL while negative DNL results in narrow codes. Fig. 2.4 illustrates narrow, wide and missing codes in an ADC.

Figure 2.4: Non-linear errors in ADC [8]. Copied from Analog-to-Digital

Con-verters Testing by Kent. H. Lundsberg 2002

2.3 Dynamic Performance Metrics

Dynamic performance is judged by applying single or sometimes multitone sinu-soidal input signal and observing the response, important measures are discussed below.

(27)

2.3.1 Signal to Noise Ratio (SNR)

The SNR is the ratio of power of the input signal to the sum of total noise power, within in a certain frequency band. It is expressed in decibels.

SN R = 10 · log10 · Psignal Pnoise ¸ (2.3) where Psignal is the power of the signal

Psignal=

¡

VLSB· 2N −1

¢2

2 (2.4)

where VLSB· 2N −1 is the maximal amplitude of the sinusoidal input. Pnoise

refers to the sum of thermal noise and quantization noise power in the band of interest. putting the value in relation 2.3 from equation 2.4 and equation 2.1

SN R = 10 · log10  ( VLSB·2N −1)2 2 V2 LSB 12   SN R = 10 · log10 £ 1.5 · 22N¤ SN R = 6.02N + 1.76 (2.5) Equation 2.5 presents a linear relation between N i.e., the number of bits and SNR.

2.3.2 Spurious Free Dynamic range (SFDR)

The SFDR is defined as the ratio of the power of the signal to the largest spurious that is the distortion tone within the band of interest.

SF DR = 10log10 · Psignal Pspurious ¸ (2.6)

2.3.3 Total Harmonic Distortion (THD)

The THD is the ratio of the total power of harmonic components to the input signal power [8] and [7].

T HD = P2+ P3+ P4+ P5+ P6· · · + Pn

Psignal (2.7)

where Psignal is the power of the fundamental tone that is the signal, and Pn

is the power of the nth _{harmonic. As the number of harmonic distortions are}

infinite, calculation is restricted to 10 − 20 harmonics, also the power of higher order harmonics is almost negligible.

(28)

2.3.4 Signal to Noise and Distortion Ratio (SNDR)

The SNDR is the ratio of power of the input signal to the sum of noise and distortion power, within in a certain frequency band. It is expressed in decibels.

SN DR = 10 · log10 · Psignal Pnoise+ Pdistortion ¸ (2.8) where Psignal is the power of the signal, Pnoise refers to the sum of thermal

noise and quantization noise power and Pdistortion, represents the power of the

harmonics lying inside the band of interest. It is noteworthy that SNDR is dependent on the input signal frequency and amplitude, degrading at high fre-quency and power.

2.3.5 Effective Number Of Bits (ENOB)

ENOB is simply the signal-to-noise-and-distortion ratio expressed in bits rather than decibels by employing the ideal SNR equation.

EN OB = SN DR − 1.76

6.02 (2.9)

It is one of the important performance metrics for ADC characterization.

2.3.6 Dynamic Range (DR)

Dynamic range is the ratio between the FS signal to the smallest detectable signal [7]. DR = 10 · log10 µ Pmax Pmin ¶ (2.10) where Pmax is the maximum power for full scale input signal and Pmin

corre-sponding to the minimum noise power.

2.3.7 Effective Resolution Bandwidth (ERB)

ERB refers to the input-signal frequency where the SNDR of the ADC has fallen by 3 dB (0.5 bit) from its value for low-frequency input signals [8].

(29)

Chapter 3

ADC Architectures

This chapter briefly reviews the contemporary ADC architectures in terms of speed, resolution, accuracy and applications. Also functionality of each archi-tecture is briefly discussed. The chapter concludes with concise comparison of ADCs to firmly establish the argument behind selection of the proposed architec-ture.

3.1 Flash ADC

Flash ADC are also known as parallel ADC, as the analog to digital conver-sion is done for N-bits in parallel. Flash ADC are have a high converconver-sion rate making them suitable for high speed devices. They are suitable for applications requiring very large bandwidth. The downside of this architecture is the huge power consumption which grows drastically with the increase of resolution of the converter, thus making it a good choice only for low resolution (up till 8 bits) applications. This is a major problem as low power applications requiring high speed and accuracy cannot make use of flash ADC. Flash ADC are suitable for application like data acquisition, satellite communication, radar processing, sampling oscilloscopes, and high-density disk drives [9].

3.1.1 Functionality of Flash ADC

Fig. 3.1 shows a typical block diagram of flash ADC, for an N-bit converter the architecture requires 2N _{− 1 comparators. A resistor ladder circuit consisting of}

2N _{resistors, is used to generate distinct reference voltages for the comparators.}

The reference voltage of each comparator is 1 LSB less than the one preceding it. The comparator performs comparison between the analog input and the reference value if the input is greater it outputs a “1” else a “0”. Considering an input lying between Vx3and Vx4, so the comparators X1to X3 will produce

a “1” while the rest will output a “0”. Note that the converter outputs the whole N-bit digital code corresponding to the analog input in parallel [9].

(30)

Pipelined ADC ADC Architectures

Figure 3.1: Block diagram of Flash ADC [9].

3.2 Pipelined ADC

The pipelined ADC architecture as the name reflects employs the pipelined ap-proach for analog to digital conversion, using m-bit identical stages to achieve N-bit conversion. It provides sample rates up to a few hundred Mega sam-ples and resolution up till 16-bits. Reasonably high speed and resolution with comparatively low power consumption and good dynamic performance make it desirable choice for a wide range of applications like Charge Coupled Device (CCD) imaging, ultrasonic medical imaging, digital receivers, base stations, dig-ital video, xDSL, cable modems, and fast Ethernet [10].

3.2.1 Functionality of Pipelined ADC

The architectural block diagram of a pipelined ADC is shown in Fig. 3.2. It consists of four identical stages of 3-bits (which resolve to 2-bits) and 4-bit flash ADC for the last four bits. The input is vinis held then provided to first stage

that utilizes a 3-bit ADC to convert it into a digital code, which is then fed to a 3-bit DAC which converts it to corresponding voltage level. The vin is

sampled and then the output of DAC is subtracted from it, which generates the residue error. As each stage outputs k = 3 raw bits, the residues is amplified by a factor of 2k−1 _{= 2}2 _{= 4 before it is sent to the next stage. This}

(31)

gained-Sigma Delta ADC ADC Architectures

up residue continues through the pipeline, providing three bits (raw) per stage until it reaches the 4-bit flash ADC, which resolves the last four LSBs. Bits corresponding to the same sample are time-aligned with shift registers before being fed to the digital-error-correction logic because the bits are computed at different time points in different stages. When a stage finishes processing a sample it can move to the next sample received from the internal sample and hold, this pipeline action is the reason behind high throughput [10].

Figure 3.2: Block diagram of Pipelined ADC (12-bit ADC with four 3bit stages and a 4bit flash ADC) [10].

3.3 Sigma Delta ADC

The Sigma-Delta ADC, consisting of a relatively simple analog side and rather complex digital side consisting of filtering and decimation is inexpensive to de-sign. It provides high resolutionand integration at reduced cost. It has a limita-tion that is has a trade-off between speed and resolulimita-tion. Suitable for applicalimita-tion that require high resolution at low bandwidth, like some audio applications.

3.3.1 Functionality of Sigma Delta ADC

This architecture requires that the input signal should be oversampled such that

OSR = fsignal/2·fsample, oversampling has the benefit that it spreads the noise

over a larger bandwidth that is OSR · fsamplethus decreasing the average noise

floor which increases the SNR and the ENOB also increases. The block diagram of a sigma-delta modulator of the first order Fig. 3.3. It includes a difference amplifier, an integrator, and a comparator with feedback loop that contains a 1-bit DAC. The DAC acts like a switch that connects the negative input of the difference amplifier to a positive or a negative reference voltage. DAC serves as the purpose of maintaining the average output of the integrator near the comparator’s reference level. For increasing input the comparator generates more “1” than “0” and for decreasing signal its the opposite. By summing the error voltage, the integrator behaves like a lowpass filter for the input signal and a highpass filter for the quantization noise. Thus oversampling and noise

(32)

Successive Approximation Register (SAR) ADC ADC Architectures

shaping change the noise power distribution pushing the quantization noise into higher frequencies and reducing noise floor. In the digital domain the ADC output is filtered by a digital filter that has a positive effect on the SNR [11].

Figure 3.3: Block diagram of Sigma Delta ADC (1-bit ADC) [11].

3.4 Successive Approximation Register (SAR)

ADC

SAR ADC provide medium resolution at a couple of mega samples speed (below 100) at low power consumption and low cost. IT is well suited for applications, such as portable/batterypowered instruments, pen digitizers, industrial controls, and data/signal acquisition [12].

3.4.1 Functionality of SAR ADC

The Fig. 3.4 shows the architectural block diagram of the ADC. The analog input voltage vin is held using a track/hold. SAR ADC uses binary search

algorithm, thus N-bit SA register is first set to the middle value i.e., 100 · · · 00, where the Most Significant Bit (MSB) is set to“1”. This results in the DAC output VDAC to be VREF₂ , where VREF is the reference voltage provided to

the ADC. The comparator then compares vin and VDAC, if vin = VDAC, the

comparator outputs a“1” and the MSB of the SA Register remains at “1”, otherwise comparator outputs a“0” and MSB is cleared to “0” . The SAR control logic then moves to the next bit down, forces that bit high, and does another comparison. The procedure continues in similar fashion down to the LSB. After this the conversion is complete, and the N-bit digital word is available in the register [12].

3.5 Comparison of the ADC Architectures

Comparison of the ADC architectures in terms of performance and functionality needs to be done so that decision regarding a suitable ADC architecture for the Analog videofront end can be made.

(33)

Selecting the Architecture and Why? ADC Architectures

Figure 3.4: Block diagram of SAR ADC [12]

Table 3.1: Comparison of ADC architectures modified from [13]. Architecture Speed Conversion

Time

Resolution Area Power

Flash ADC High Constant Low (up till 8-bits) Increases exponen-tially with resolution Very high Pipelined ADC medium-high Increases with resolu-tion medium-high (up till 12-bits) Increases linearly with resolution medium Sigma-Delta ADC medium Trade-off with resolu-tion

High (up till 24-bits) constant;no change with increase in resolution medium-low

SAR ADC medium-low

Increases with resolu-tion

High (up till 18-bits) Increases linearly with resolution medium-low

3.6 Selecting the Architecture and Why?

SAR ADC is most suitable for the analog video front end, as it has low power consumption, reasonable resolution and accuracy. The architecture has to be more “digital” rather than “analog”, as the system design should be “scalable” that is it scales with technology, and digital is scalable. SAR ADC meets this requirement, as the comparator is the sole “analog” component in this design, the rest of the modules shrink as the design is implemented in contemporary technologies (low). Due to the digital nature reduced power supply can be used resulting in further power reduction. The sampling speed required is very high and SAR ADC cannot meet that specification but using the Time-Interleaved approach several low power SAR-ADCs can be placed in parallel to achieve a sampling rate around 300M samples/s.

(34)

Chapter 4

Successive Approximation

Register (SAR) ADC

This chapter contains a detailed theoretical review of the SAR ADC. Starting with the explanation of the conversion algorithm employed, the functionality of the components of the SAR ADC is discused. Finally the Time-Interleaved ADC is defined and the merits and demerits of the approach are briefly discussed.

4.1 The Successive Approximation (SA)

Algo-rithm

The SAR architecture converts the analog input signal level to corresponding N-bit code by using the Successive Approximation algorithmic approach. In other words the SAR ADC employs the binary search Algorithm to successive approximate to the correct digital code. One bit is obtained per clock cycle.

Figure 4.1: SAR operation [12].

In order to better understand the working consider an example of a 4-bit ADC as shown in Fig. 4.1. Intially VDAC is set to VREF/2 i. e 10002 and then

(35)

SAR ADC Submodules Successive Approximation Register (SAR) ADC

so the comparison Vin= VDAC is false so the bit3 is cleared to “ 0 ”. Next the

DAC is set to 01002that is, VREF/4 so we are in the lower half now we will be

finding the correct value below the VREF/2 as the first bit was “ 0 ” and the

second comparison is complete, now as Vin> VDAC, bit is set. After this DAC

is set to 01102 ,now as Vin < VDAC, bit is cleared. Finally for the fourth bit

DAC is initialized to 01012 and the comparison is not true again so bit0 is “ 0

”. For a 4-bit ADC, one cycle for sampling the input and four cycles are used for comparison. At the end of 5 cycles the digital code in the SAR is 01002.

4.2 SAR ADC Submodules

A typical SAR ADC architecture consists of the following submodules which are shown in Fig. 4.2:

• Sample and Hold

• Digital to Analog Converter (DAC) • Comparator

• Successive Approximation Register (SAR)

Figure 4.2: Block diagram showing submodules of Successive Approximation Register ADC [12].

4.2.1 Sample and Hold

Sample and hold is actually a misnomer, it tracks an input signal and then holds it, so track and hold is what it actually does. It consists of a sampling switch and a sampling capacitor, at every rising edge of the sample signal it tracks the input for half cycle and then holds the value for the next half of the cycle. The benefit we achieve by having the input held before comparison is that the comparator gets a stable value at its input, which yields correct result of the comparison.

(36)

Time-Interleaved SAR ADC Successive Approximation Register (SAR) ADC

4.2.2 Digital to Analog Converter (DAC)

As the name indicates it is a mixed signal device for performing the reverse operation of that of an ADC. It is used for converting digital bits to a corre-sponding analog value. In the SAR ADC the DAC is present in a sort of a loop, it takes the digital bits in the Successive Approximation Register (SAR) and converts them to the appropriate signal level and provides it to the input of the comparator to compare with the held input. Popular DAC architectures are R-2R ladder DAC ( consisting of resistors) and a C-2C ladder DAC (consisting of capacitors). As the later architecture relies on ratio of capacitors, better matching can be achieved in this way. In contemporary SAR ADCs sometimes a capacitive DAC with an inherent Sample and Hold is used, which is known as a charge re-distribution DAC. It has the benefit of being low power

4.2.3 Comparator

This is the heart of the ADC doing the actual conversion from Analog to digital, as it compares the two analog signals at its input and generates a digital output a “1” or a “0”. The comparator used in SAR ADC is usually a clocked comparator, which compares the held input with the DAC output and yields and output that sets a bit in the SAR, and this procedure continues till the LSB For this particular ADC, the comparator needs to be fast enough to yield the correct output within a clock cycle. Also as the resolution of the ADC is 12-bit, the comparator needs to be robust enough to differentiate between very small values. (Details about comparator design are covered in Chapter 8 )

4.2.4 Successive Approximation Register (SAR)

This is the part from which the architecture gets its name “Successive Approxi-mation Register”. The register contains N-bits, where N is the resolution of the ADC. Each bit can be accessed independently and can be set to “1”, cleared to “0” or retain its value. Intially MSB of the register is set and converted to analog value by DAC, compared with input by the comparator if the input is higher than it MSB remains “1” otherwise it is cleared and same is repeated for the next bit, all the way down to the LSB. At the end of N+1 cycles the SAR ADC contains the correct digital code corresponding to the input.

4.3 Time-Interleaved SAR ADC

SAR ADC is the selected architecture based upon the facts that it has a scalable architecture, burns less power and provides reasonable accuracy but at the same time for the video AFE the required sample rate is 300 MHz which is a lot more than typical SAR ADC can provide, so we adopt time-interleaving to achieve this high speed.

Time-Interleaving is a smart technique to achieve an overall high sample rate by operating low sample rate ADCs in parallel. Thus to achieve an overall sample rate of say FClk we can use M ADCs having a sample rate of FClk/M

each, so the speed requirement for ADCs is relaxed by a factor of M at the same time increasing the number of comparators by M . Luckily the area and

(37)

Time-Interleaved SAR ADC Successive Approximation Register (SAR) ADC

power consumption don’t necessarily scale by a factor of M as there are some modules that can be shared among the M-channels.

Mathematically FClk =

Pn=M

n=1 FClk−ADC(n)

where FClk−ADC(n) is the rate of one of the ADCs.

The concept time-interleaved is illustrated in the Fig. 4.3 given below. The input signal vinis fed to all the channels at the same time as the the Sample and

Hold units of each channel work at FClk/M and for each channel the sample

instant is different, M consecutive samples of input signal are picked up by the Time-interleaved ADC, to speed up the conversion process M times. The result is digitally multiplexed to provide the digital bits.

Figure 4.3: Block diagram of Time-Interleaved ADC.

As good as it sounds time-interleaved ADC is not perfect, its performance is limited by the accuracy of the channel ADCs and also the mismatch between the channels gives rise to gain errors, offset errors and skew errors. Thus the factor

M used for interleaving is also limited by the occurrence of these characteristic

(38)

Chapter 5

Mathematical Model of

Time-Interleaved SAR

ADC

The chapter consists of discussion regarding development of a mathematical model of the TI-SAR ADC. The errors modelling in the tool and effects on the system performance are also observed.

5.1 Introduction and purpose

In order to develop an understanding of the functionality of the ADC, a proto-type in MATLAB is developed. Top-level modelling has the benefit of making the designer identify the inputs and outputs of the system, keeping the im-plementation details aside. A mathematical model is helpful in making one visualize signal as matrices and translate input into output using mathematical equations. A code for an ideal N-bit SAR ADC was written which functionally modelled the behavior of SAR ADC. The model is flexible and allows the user to choose sample frequencyFsample, signal frequencyFsignal, number of channels

or slices of the TI-SAR ADC M and the resolution of the ADC N . Firstly the behavior of the model was observed such that it complies with what we need, next only those errors were modelled that would be difficult to emulate using the Cadence environment. The model can be best explained with the help of a pictorial representation shown in Fig. 5.1.

The model has a coherent sampling unit that ensures that, the input fre-quency is changed such that the criteria for coherent sampling , given below are met.

• There should be integer number of sinusoid cycles in a record.

• The Number of Cycles (N oC) and Number of Samples (N oS) in a record

should have no common factor.

Meeting these conditions guarantees that the samples are distributed uni-formly over 0−2π, in phase. If this is not done, one potential disadvantage is the spectral Leakage, such that the output spectrum acquires a skirt and tends to

(39)

Introduction and purpose Mathematical Model of Time-Interleaved SAR ADC

Figure 5.1: Block diagram of MATLAB Model of Time-Interleaved ADC. leak into neighboring channels. For this model N oS = 216_{, F}

sample= 300M Hz,

Fsignal= 30M Hz

The N oC is computed using the relation

N oC = Fsignal

Fsample · N oS (5.1)

Next look for a prime of N oS that is very close to the computed N oC and then finally substitute in the relation below to compute the new Fsignal

Fsignal= N oC

N oS · Fsample (5.2)

The input signal is generated consisting of N oS points, it is a 1-dimensional matrix [1 × N oS]. The errors are added to the input signal one at a time to study their impact closely. Next the input needs to split up into M separate channels. The input is reshaped into a matrix having dimension [M × L] where

L = N oS/M as for this case M is a multiple of N oS. Each mthrow corresponds

to the signal provided to the mthADC, where m = 1 · · · M . The SAR conversion

code is run M times. This code takes input row by row and also N the number of bits. The output is then merged back from M-channels to one output. Delta signal is plotted, to study how the output differs from input. The SNDR is computed, from the output signal. The output of the MATLAB model at this point demonstrates the normal behavior (in the absence of any sort of error).

(40)

Figure 5.2: Input signal (spectrum and time domain graph).

Figure 5.3: Channel input signals (time domain graph).

Fig. 5.2, 5.3 and 5.4 show the signal that is provided at the input of the system, the channel inputs and the output of the system respectively.

(41)

(42)

Modelling Errors Mathematical Model of Time-Interleaved SAR ADC

5.2 Modelling Errors

The first three errors that are discussed in upcoming sections are characteristic of a TI ADC, the later two are more relevant to video ADCs.

5.2.1 Gain Error

The parallel ADCs may be different and that can result in different channel gains which in turn cause distortion in the output signal. To model this behavior its suitable to consider it as a random process. If the gain in channel m is

am, considering it as normally distributed random variables with mean a and

variance σ2

athe SNDR of the TI ADC, having M channels can be approximated

as shown in 5.3. SN DR = 20 · log10 µ a σa ¶ − 10 · log10 µ 1 − 1 M ¶ (5.3) Equation 5.3 shows that the number of channels will only affect the SNDR only by 3 dB as M increases from 2 to infinity, so M has very less impact on SNDR. While the first term indicates that the value of σa should be very small

to allow a large value of SNDR, for a 12-bit ADC it is approximately 0. 0199%. This is very difficult to achieve so little higher σa is allowed in the design and

some digital correction are made later [7].

Figure 5.5: Output spectrum with gain errors σa = 0.1.

The distortion tones that result due to gain errors are signal dependent they are located at Fsignal+ m · Fsample/M, m = 1 · · · M − 1. The tones can be seen

clearly in Fig. 5.5.

5.2.2 Offset Error

The offset in the different channels can result in corruption of the output signal. Each channel may suffer from different offset and this is best modelled as a random process. If the offset in a certain channel m is om, considering it as

(43)

random variables having a normal distribution with mean zero and variance σ2

o,

then the SNDR in this case is given by the relation given in equation 5.4.

SN DR = 20 · log10 µ 1 σo ¶ (5.4) The expression above indicates that to achieve an SNDR of 74dB for a 12-bit ADC, the value of σoneeds to be as low as 0.04% . This is obviously unrealistic

to achieve so a little margin is given in the design and σo is allowed slightly

higher such that it can be corrected in digital domain [7].

Figure 5.6: Output spectrum with offset errors σo= 0.1.

The distortion tones that result due to offset errors are signal independent they are located at m · Fsample/M, m = 1 · · · M − 1. The tones can be seen

clearly in Fig. 5.6.

5.2.3 Channel Jitter

The time interleaved ADC structure has the parallel ADCs typically working upon different subsequent shifts of the original clock. This error occurs as re-sult of the time differences between the channels due to mismatches. The mis-matches in the clock generator MOS transistor and different capacitive load seen by different outputs, can yield certain phase jitter. Even if they are matched , VT hreshold mismatch in sampling switches can also result in phase skew.

Re-garding the errors as normally distributed random variables with zero mean and

σ2

t, the SNDR can be approximated as shown in 5.5.

SN DR = 20 · log10 µ 1 σt· 2π · Fsignal ¶ − 10 · log10 µ M − 1 M ¶ (5.5) The number of channels in a TI ADC have very less impact on the total SNDR as M goes from 2 to infinity. The value of σt should be around 1 ps, in order

(44)

to get 12-bit resolution at 30 MHz input frequency. This is some what diffi-cult to achieve in a CMOS process. The distortion tones lie at Fsignal+ m ·

Fsample/M, m = 1 · · · M − 1, similar to the gain error spurs [7].

Figure 5.7: Output spectrum with channel jitter σt= 10ps.

5.2.4 Long Term Jitter (LTJ)

Long term jitter is a characteristic error associated with video ADCs, its due to jitter caused by the HSYNC frequency present in the video application. It is also referred to as drift jitter due to its slowly changing nature. The allowed value for our system is 8%/FSample which approximately 267 ps. Simulation

results show that this error does not have an immense adverse impact on the system performance.

5.2.5 Cycle to cycle Jitter (Random Jitter)

The cycle to cycle jitter (random jitter) is due to the jitter in the original clock generated by the DLL, and as the clock phases upon which each of the m channels operate are derived from the system clock, if it is jitter prone, all the phases will inherit it.

The performance of the time interleaved ADC is severely affected by the random jitter, because due to the uncertainty of time at which input is sampled, the converted digital code can be erroneous, thus resulting in a poor quality of video.

Fig. 5.8 indicates that the significant rise in noise floor with introduction of random jitter as compared to Fig. 5.5 and Fig. 5.6.

(45)

(46)

Identifying the killer ... Mathematical Model of Time-Interleaved SAR ADC

5.3 Identifying the killer ...

In the quest to identify the killer of the TI-SAR ADC, the SNDR is used as a measure to gage the effect of the errors on the system performance. Also the delta signal is used determine how much the output deviates from what it should be due to a certain error. The model was simulated for different values of the errors modelled above, each time the SNDR was measured. The simulation results are tabulated in Table. 5.1. (SNDR graphs for the errors are given in

the previous section)

Table 5.1: SNDR in the presence of errors.

Error SNDR

None 74 dB

Gain Error 54 dB

Offset Error 53 dB Channel Jitter 52 dB Long Term Jitter 73 dB Cycle-to-Cycle Jitter 34 dB

The effect of the errors can also be seen by observing the difference between the input and output.

(47)

Figure 5.10: Delta signal in the presence of gain error (spectrum and time

do-main graph).

Figure 5.11: Delta signal in the presence of offset error (spectrum and time

(48)

Figure 5.12: Delta signal in the presence of channel jitter (spectrum and time

domain graph).

Figure 5.13: Delta signal in the presence of long-term/drift jitter (spectrum and

(49)

Demonstration of Errors Mathematical Model of Time-Interleaved SAR ADC

Figure 5.14: Delta signal in the presence of cycle-to-cycle jitter (spectrum and

time domain graph).

Fig. 5.9, 5.10, 5.11, 5.12 and 5.13 show delta signal in the presence of no error, gain error, offset error, channel jitter and long-term jitter respectively. Fig. 5.9 shows that the difference between input and output is very negligible. The Delta signal shown in Fig. 5.10,has a significant value and also forms a distinct noticeable pattern. The Delta signal shown in Fig. 5.11, has a lesser value than in Fig. 5.10. The Delta signal in Fig. 5.12 has a significant value and also repeats in a unique pattern. The Delta signal in Fig. 5.13 has a very small value.

The observation of the spectrum of the delta signal from the point there is no error and then comparing it with the spectrum after introduction of errors. This helps to identify the error that affects the system the most. The delta

signal for gain and channel jitter occurs in a visible pattern. Also it is noticed

that amplitude of the delta signal in time domain is largest for cycle-to-cycle jitter. The simulation results conclude that the cycle to cycle jitter is the worst enemy for our system. It is good to mention here again that this due to the DLL that generates the system clock and the ADC module only inherits the troubles.

5.4 Demonstration of Errors

The errors modelled above can affect the video adversely by creating artifacts that degrade the image quality. In order to demonstrate how video will be degraded by these errors, a standard frame of testing of display is used and errors are added to see the effects.

Lastly it is important to investigate the effect of level of quantization on the quality.

(50)

Figure 5.15: Standard frame for video display testing.

Figure 5.16: Effect of addition of Additive White Gaussian Noise (AWGN) on frame.

(51)

Figure 5.17: Effect of offset error on frame.

(52)

(53)

Figure 5.20: Effect of fine quantization (12-bit) on frame.

(54)

Error Reduction TechniquesMathematical Model of Time-Interleaved SAR ADC

Figure 5.22: Effect of coarse quantization (1-bit) on frame.

Fig. 5.16 shows that addition of Additive White Gaussian Noise (AWGN) can significantly reduced the quality of the video frame. Fig. 5.17 shows how the offset errors can visibly distort the image. A pattern of vertical lines is visible on the screen which is dependent upon the number of ADC channels (slices) used in the time interleaved structure. Fig. 5.18 shows how the gain errors can affect the image. A pattern of lines is visible on the screen which is dependent upon the number of ADC channels (slices) used in the time interleaved structure. Fig. 5.19 demonstrates the effect of distortion on the image, so if distortions are present the picture looks like Fig. 5.19 instead of Fig. 5.15. Comparing Fig. 5.15 and 5.20 there is not any noticeable difference, even Fig. 5.21 doesn’t show much degradation but Fig. 5.22 shows a drastic effect on the picture. So if due to some issues the ADC has a reduction in SNDR and its ENOB drops there can be a noticeable effect on image quality.

5.5 Error Reduction Techniques

Over the course of years several effective techniques have been developed to counter the channel mismatches that limit the performance of time interleaved ADCs. A few of these techniques are discussed below.

5.5.1 Two-Rank Sample and Hold

This is mainly focused on the elimination of the timing mismatch, the channel jitter as mentioned earlier and has no effect on other errors (gain and offset). The idea is to insert a sample and Hold (S/H) at the input, before the input is given to the channels, this removes the phase skew but the obvious disadvantage

(55)

Error Reduction TechniquesMathematical Model of Time-Interleaved SAR ADC

is the operation of the S/H at the maximum sample rate, as it is cumbersome to design S/H at high speed in CMOS technology [7].

5.5.2 Randomization

This technique is focused on reduction of gain and offset and has little effect on the timing errors. If the channel to convert the next sample is randomly chosen as opposed to the sequential way the correlation between the input signal and channel errors is reduced [7]. In [14] it is discussed how randomization can be done at the cost of introduction of additional ADCs and randomly selecting an ADC at each sample instance. The results in [14] show that it can remove the periodicity of errors, thus transformation the spurious distortions to more noise like distortion that is spread uniformly over the whole spectrum. The demerit of the scheme is that all the ADCs must operate at the system clock signal, as the decision regarding which channel samples next is done dynamically, so the benefit of the TI-SAR is almost lost. Also a potential issue is the design com-plexity of the switches that make this randomization possible,which increases with the number of channels.

Study of Time-Interleaved SAR ADC andImplementation of Comparator for High DefinitionVideo ADC in 65nm CMOS Process

Institutionen för systemteknik

Department of Electrical Engineering

Examensarbete

Study of Time-Interleaved SAR ADC and

Implementation of Comparator for High Definition

Video ADC in 65nm CMOS Process

Study of Time-Interleaved SAR ADC and

Implementation of Comparator for High Definition

Video ADC in 65nm CMOS Process

Examensarbete utfört i Elektroniksystem

vid Tekniska högskolan i Linköping

av

Abstract

Acknowledgments

List of Figures

List of Tables

Contents

Chapter 1

Introduction

1.1

Motivation

1.1.1

Video Analog Front End IC

1.1.2

Time-Reference Channel

1.1.3

Digitizing Channel

1.2

ADC Specifications

1.3

Objectives

1.4

Thesis Organization

Chapter 2

ADC Fundamentals and

Performance Metrics

2.1

Analog to Digital Converter (ADC)

2.1.1

Resolution

2.1.2

Quantization Error

2.2

Static Performance Metrics

2.2.1

Offset Error

2.2.2

Gain Error

2.2.3

Differential Non-Linearity (DNL)

2.2.4

Integral Non-Linearity (INL)

2.2.5

Missing codes

2.3

Dynamic Performance Metrics

2.3.1

Signal to Noise Ratio (SNR)

2.3.2

Spurious Free Dynamic range (SFDR)

2.3.3

Total Harmonic Distortion (THD)

2.3.4

Signal to Noise and Distortion Ratio (SNDR)

2.3.5

Effective Number Of Bits (ENOB)

2.3.6

Dynamic Range (DR)

2.3.7

Effective Resolution Bandwidth (ERB)

Chapter 3

ADC Architectures

3.1

Flash ADC

3.1.1

Functionality of Flash ADC

3.2

Pipelined ADC

3.2.1