Development of a Class D Motor Amplifier for a Next-generation Mechanism Control
Electronics
Juan Camilo Garcia Hernandez
Space Engineering, masters level 2016
Luleå University of Technology
Department of Computer Science, Electrical and Space Engineering
Julius-Maximilians-Universit¨ at W¨ urzburg Lule˚ a University of Technology Department of Computer Science
Master Thesis
Publishable Version
submitted in fulfillment of the requirements for the degree of Master of Science
Co-funded by the Erasmus Programme of the European Union
Topic: Development of a Class D motor amplifier for a next-generation mechanism control electronics.
Autor: Juan Camilo Garcia Hernandez
Version from: 3rd October 2016
Tutor from Airbus DS: Mustafa ¨Ozel
Examiner JMUW: Prof. Dr. Sergio Montenegro Examiner LTU: Prof. Dr. Annita Enmark
This version of the Master Thesis deviates from the formal orig- inal submitted for examination in order not to disclose confidential information of Airbus DS GmbH. All positions in the document, where additional information was removed are properly identified.
This document can be published according to the general rules of the Julius-Maximilians-Universit¨ at W¨ urzburg and the Lule˚ a Uni- versity of Technology.
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Para mis padres, que en la distancia siempre me han apoyado y de quienes aprend´ı que los logros llegan con esfuerzo.
Los llevo en mi coraz´on.
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Preface
At this point in my career, where my main phase of studies comes to an end, the amount of people I would like to thank for their support or help is too much and this thesis would be twice as long. Nonetheless I am specially grateful with my professors from the SpaceMaster, Prof. Anita Enmark and Prof. Sergio Montenegro who agreed to be my examiners for this thesis. Special thanks go also to Prof. Eveline Gottzein who put me in contact with Airbus Defence and Space where I obtained my thesis contract. In a related matter, I would like to mention Mr. Daniel Ruf who made possible this thesis in his department of Power Electronics. My tutor at the company, Mr. Mustafa ¨Ozel deserves also to be thanked for all his support and orientation. Also thanks to all the colleagues at the department who were there to answer all my questions and help me when needed.
The European Union and their Erasmus+ program have also all my gratitude as it was thanks to their support not only through the obtained scholarships but also through my admission to the SpaceMaster that I am not about to finish my studies and that way continue my life in this beautiful country.
In a more personal matter, the biggest thank you goes to my parents who always have been there for my then I needed them and have supported me al the way through my studies and who made possible not only my successful bachelor degree in Germany, but also my soon to be obtained Master degree.
To my friends not only in Germany but also in Colombia and those scattered around the world who helped to keep me sane during all this time: thank you!
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Hinweis zum Urheberschutz
Diese Arbeit einschließlich aller ihre Teile ist urheberrechtlich gesch¨utzt. Jede Verwer- tung außerhalb der engen Grenzen des Urheberrechtsgesetzes ist ohne Zustimmung des Verfassers unzul¨assig.
Insbesondere enth¨alt sie betriebsinterne Daten des Unternehmens Airbus DS GmbH. Eine Weitergabe an Dritte sowie die Ver¨offentlichung oder Verwendung der betriebsinternen Daten ist nur mit ausdr¨ucklicher vorheriger Zustimmung des Unternehmens Airbus DS GmbH. gestattet.
Notice of copyright protection
This Thesis including all its parts is copyrighted. Any utilization outside of the strict limits of the copyright law is illegitimate without the permission of the editor.
This thesis particularly contains internal data of the company Airbus DS GmbH. A transmission to a third party as well as the publication or utilization of internal data is only allowed with the prior explicit consent of the company Airbus DS GmbH.
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Statement of Authorship
Statement
I hereby declare that the paper presented is my own work and that I have not called upon the help of a third party. In addition, I affirm that neither I nor anybody else has submitted this paper or parts of it to obtain credits elsewhere before. I have clearly marked and acknowledged all quotations or references that have been taken from the works of others. All secondary literature and other sources are marked and listed in the bibliography. The same applies to all charts, diagrams and illustrations as well as to all Internet sources.
Signature : P lace, Date :
C ONTENTS
Chapter 1 – Introduction 1
1.1 Motivation . . . 1
1.2 Overview of the thesis . . . 2
Chapter 2 – Basics 3 2.1 Brushless DC (BLDC) Motors and 2 Phase Step-Motors . . . 3
2.2 Candidate Topologies . . . 4
2.2.1 Full-Bridge . . . 5
2.2.2 Half-Bridge . . . 6
Chapter 3 – Current Version of the Power Amplifier 8 Chapter 4 – Available Resources/Technology 11 4.1 MOSFET Gate Drivers . . . 11
4.1.1 First design by Fehrle . . . 12
4.1.2 Second version by Kollewe . . . 12
4.1.3 Corrections of the MOSFET protection by Mayer . . . 12
4.1.4 Suggestions by Rapp . . . 13
4.2 Delta-Sigma (∆Σ) Analog/Digital Converter . . . 13
4.3 Prototyping and Test Board . . . 13
Chapter 5 – Trade-off and Simulations 14 5.1 Criteria . . . 14
5.2 Simulations . . . 16
5.2.1 MOSFET Drivers . . . 17
5.2.2 MOSFET Protection . . . 19
5.3 Comparison . . . 21
5.4 Improvements . . . 23
5.5 Detailed Simulations of the Final Topology . . . 24
Chapter 6 – Hardware Design 35 6.1 Component Selection . . . 35
6.1.1 Power Transistors . . . 35
6.1.2 Operational Amplifiers . . . 37
6.1.3 Analog to Digital Converter (ADC) . . . 37
6.1.4 Other components . . . 38
6.2 Design of the Printed Circuit Board (PCB) . . . 38
6.2.1 Layouting of the Demonstrator . . . 39
Chapter 7 – Test Preparations 43
7.1 Considered PWM Generators . . . 43
7.1.1 Logic Gates Circuit . . . 43
7.1.2 Real-Time Target Machine . . . 43
7.2 Setup of the Target Machine for testing . . . 44
7.2.1 Implementation of a PWM generator . . . 46
Chapter 8 – Hardware Implementation and Testing 50 8.1 First Hardware Tests and Solution of Errors . . . 50
8.2 Implementation of a PID Controller and Further Testing . . . 54
8.2.1 3-Phase Implementation of the Demonstrator . . . 60
Chapter 9 – Conclusions 63
Appendix A – Available Circuit Toppologies 65
Appendix B – Demonstrator Schematic 66
Appendix C – Layout Design Rules 67
Appendix D – Demonstrator Layout 72
Appendix E – VHDL Block for PWM Generation 73
VII
List of Figures
2.1 Basic construction of a BLDC motor. [13] . . . 4
2.2 Wye connection of a 3-Phase BLDC Motor from the OrCad Capture MIX- MISC library . . . 5
2.3 Reference Signals for the BLDC Motor control . . . 6
2.4 Simplified1H-Bridge. . . 6
2.5 Variation of the H-Bridge. . . 6
2.6 Simplified Half-Bridge topology. . . 7
3.1 Block diagram of the previous version of the amplification circuit. . . 8
3.2 Simulation of the full bridge circuit. . . 9
3.3 Measurements of the real circuit with a reference signal of 58 Hz. In green and lila are the sinusoidal currents through a 2-phase step motor. . . 10
5.1 The four PWM signals fed to the MOSFET drivers. . . 17
5.2 Two PWMs are used to control each gate driver. . . 18
5.3 Output voltage of the halfbridge without MOSFET protections at d = 25%. (In green is Fehrle’s circuit, Kollewe’s in red, Mayer’s in blue and Rapp’s in yellow) . . . 19
5.4 Output voltage of the halfbridge without MOSFET protections at d = 50%. (In green is Fehrle’s circuit, Kollewe’s in red, Mayer’s in blue and Rapp’s in yellow) . . . 20
5.5 Output voltage of the halfbridge without MOSFET protections at d = 75%. (In green is Fehrle’s circuit, Kollewe’s in red, Mayer’s in blue and Rapp’s in yellow) . . . 21
5.6 Output voltage of the halfbridge without MOSFET protections at d = 75% over several periods of the PWM. (In green is Fehrle’s circuit, Kollewe’s in red, Mayer’s in blue and Rapp’s in yellow) . . . 22
5.7 MOSFET power loss for each circuit with its original protection circuit. (In green is Fehrle’s circuit, Kollewe’s in red, Mayer’s in blue and Rapp’s in yellow) . . . 23
5.8 Falling and rising flanks from the output signal of the circuits with original protection. (In green is Fehrle’s circuit, Kollewe’s in red, Mayer’s in blue and Rapp’s in yellow) . . . 24
5.9 Power loss at the MOSFETS with the selected protection circuit. . . 25 5.10 Power loss at the MOSFETS in the final topology. In blue is the circuit
previously selected and in red the circuit with the suggested modifications. 26
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5.11 Falling and Rising flanks of the final topology (red) vs the previously
selected circuit (green). . . 26
5.12 Comparator used for the generation of a PWM from a sinusoidal wave. . 27
5.13 Signals at the input and output of the PWM generator. . . 27
5.14 Circuit used for the generation of the On-Signals. . . 28
5.15 Feedback circuit featuring the LT1014 Quad precision amplifier. . . 28
5.16 Low pass LC filter. . . 29
5.17 Low pass LC filter. . . 29
5.18 Low pass LC filter with motor phase. . . 30
5.19 Magnitude Bode diagram of the low pass LC filter. . . 30
5.20 Low pass LCR filter with motor phase. . . 31
5.21 Magnitude Bode diagram of the low pass LCR filter with motor phase. . 32
5.22 Filtered sinusoidal PWM with LC filter. . . 32
5.23 Filtered sinusoidal PWM with LCR filter. . . 33
5.24 Non controlled simulation of a 50 Hz signal. . . 33
5.25 PI controlled simulation of a 50 Hz signal. . . 34
6.1 Area allocation for each section of one phase. . . 40
6.2 Layout of the first phase. Names and values not shown for readability purposes. . . 40
6.3 Final design of the demonstrator. . . 42
7.1 Simulink model for testing the communication with the xPC. . . 45
7.2 Results of the communication test. Scope 5 shows a zero value as expected. 45 7.3 State machine for PWM generation. . . 47
7.4 Simulink model of the PWM generator. . . 48
7.5 Time to bit conversion block. . . 48
7.6 Contents of the FPGA block. . . 49
7.7 PWMs generated from the FPGA with duty cycle of 50% and pulse period of 50 µs. . . 49
8.1 Overshoot due to error in diode connection. . . 51
8.2 Comparison between simulation and Eagle schematics . . . 51
8.3 Simulation of the diode connection error. . . 52
8.4 Output PWM with implemented diode correction. . . 52
8.5 Error output with negative duty . . . 54
8.6 Resistors replaced for proper signal amplification. . . 54
8.7 Sinusoidal current with no control . . . 55
8.8 Simulink model for PID controll of the demonstrator. . . 56
8.9 Output current with a 10 Hz 300 mA reference signal without control. . . 57
8.10 Output current with a 10 Hz 300 mA reference signal with the implemen- tation of a PID control. . . 58
8.11 Output current with a 50 Hz 300 mA reference signal with PID control. . 58
8.12 Saturation reached with a reference signal of 600 mA peak value. . . 59
8.13 Simulink model for 3 phase control of the demonstrator. . . 60
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8.14 Three phases of the demonstrator working at the same time with the motor
connected to ground. . . 61
8.15 Demonstrator controlling three phases connected in wye. . . 62
C.1 Layer design rules of the demonstrator. . . 67
C.2 Clearance design rules of the demonstrator. . . 68
C.3 Distance design rules of the demonstrator. . . 68
C.4 Size design rules of the demonstrator. . . 69
C.5 Restring design rules of the demonstrator. . . 69
C.6 Shapes design rules of the demonstrator. . . 70
C.7 Supply design rules of the demonstrator. . . 70
C.8 Mask design rules of the demonstrator. . . 71
C.9 Misc design rules of the demonstrator. . . 71
D.1 Top layer. . . 72
D.2 GND layer. . . 72
D.3 Pwr layer. . . 72
D.4 Bottom layer. . . 72
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List of Tables
6.1 List of Hi-Rel radiation hardened Power MOSFETs from STMicroelectronics 36 6.2 Used commercial power MOSFETs . . . 37 7.1 Input an output variables for the PWM VHDL block . . . 46 8.1 My caption . . . 56
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Nomenclature
ACL Airbus DS Component List ADC Analog Digital Converter BJT Bipolar Junction Transistor BLDC Motor Brushless DC Motor DC Direct Current
DIP Dual Inline Package EMF Electromotive Force
EMI Electromagnetic Interference FP Flat Pack
FPGA Field Programmable Gate Array GUI Graphical User Interphase
Hi-Rel High Reliability
ITAR International Traffic in Arms Regulation LP Low pass
LSB Least Significant Bit
LVTTL Low Voltage Transistor-Transistor Logic MOSFET Metal Oxide Field Effect Transistor NMOS N-Channel MOSFET
PCB Printed Circuit Board
PCI Peripheral Component Interconnect PID Proportional-Integral-Derivative
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PMOS P-Channel Mosfet PWM Pulse Width Modulation
RDS(on) Drain to Source Impedance during the ON state SMD Surfce-Mounted Device
SOIC Small Outline Integrated Circuit TSSOP Thin Shrink Small Outline Package VDS Dain to Source Voltage
VHDL Very High Integrated Circuit Hardware Description Language
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C HAPTER 1 Introduction
1.1 Motivation
In the last couple of decades, technology has advanced at a very high speed with every year producing a large amount of new developments in all fields. In some cases however, the rate of that advance may not seem as high due to different constraints. In the space industry it is not uncommon to still use relatively old designs or components that are not necessarily state of the art. One reason for this is that space systems need to be constructed in a way that they must survive the harsh environment of space for many years (ideally) without a single failure as there is no possibility for physical maintenance and if a critical subsystem fails the satellite is usually condemned and the investment lost. This has led in some cases to the application of the rule ”if it isn’t broken, don’t fix it”. Nonetheless as technology advances and new components are approved for space use their introduction in the space market either renders these old designs useless or opens the possibility for improvements.
Such is the case of the currently used power amplification system for motors in satellite mechanisms. The previous design, though still usable, has certain disadvantages that convert it in a non-ideal candidate for missions that require the use of newer generations of motors with extra precision, higher speeds or altogether smoother rotation of the motor’s shaft.
For this reason a new project was opened which aims to develop a new generation of the power amplification system for motors in satellite mechanisms. The final objective is to produce a modular, digitally controllable system which is capable of operating in different power ratings and provide different types of motors with power with just slight changes in the circuit. Previous work in this project has already suggested the main topology to be evaluated with different versions of it. This topology is that of a Class D amplifier which converts the signal to be amplified into a PWM that is used to switch two power MOSFET transistors in an Half-Bridge configuration which amplifies the PWM signal which is then filtered to recover the original analog signal at a higher power rating. The main objective of this Master Thesis is to compare the different versions of the topology
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1.2. Overview of the thesis 2 and improve it where needed to finally produce a demonstrator circuit aiming for a small PCB size and to test it and evaluate its output signals as well as to suggest options of Hi-Rel components to be taken into account for flight models of the circuit in accordance to their status in the Airbus DS Component List (ACL). After this Master Thesis is done, more work is to come to implement other developments such as a digital PID control together with the final product of this thesis.
1.2 Overview of the thesis
The following chapters describe and show the process that led to the final implementa- tion of the demonstrator starting with chapter 2 which presents the basics of BLDC and 2-Phase Step motors and the two main topologies for power amplification for motors.
Next, chapter 3 shortly describes the currently used power amplifier and its characteris- tics. Following, chapter 4 talks about previous developments for the project and how they relate with the current thesis. Chapter 5 begins the main work of this master thesis and shows the simulations of the topologies and provides the main criteria to be taken into account for the trade-off and finally selects a candidate topology offering some improve- ments. Next,chapter 6 describes the design process of the demonstrator as well as the selection of the main components and suggest Hi-Rel candidates for future stages of the project. Chapter 7 shows the process of test preparation as the demonstrator required very accurate control signals and opens the possibility of implementing a digital PID control. Afterwards, chapter 8 shows the implementation of the demonstrator including the solving of encountered issues and testing under different conditions. Finally chapter 9 offers the conclusions of this Master Thesis and suggest areas of further development for the project.
C HAPTER 2 Basics
2.1 Brushless DC (BLDC) Motors and 2 Phase Step- Motors
The developed circuit must be able to handle mainly two types of motors: Brushless DC (BLDC) Motors and 2-Phase Step Motors. Although their working principle is similar, they are optimized for two different types of operation. BLDC Motors are designed to provide smooth torque between steps so that an applied current generates maximum torque, providing a way to control output torque by increasing or deducing the current through the motor. They are also mainly used for continuous operation instead of posi- tion. Step Motors on the other hand, are designed to provide maximum holding torque while energized, having the ability to hold mechanical loads at the same position.
The construction and working method for both types of motors is basically the same.
The rotor is made of permanent magnets which vary in quantity (from two to eight pole pairs in BLDC to 12 pairs in Permanent Magnet step motors) [7]. The stator consists on a number of windings (for this work only step motors with two windings and BLDC motors with three windings will be considered). Each winding consists of one or several coils distributed spatially in the stator to form a pair number of poles [18]. As the different phases of the motor are sequentially powered, they induce a magnetic field inside the motor, the rotor then tries to align its south pole to a north pole of the stator (following the magnetic principle of opposite poles attracting each other). Through a series of commutations movement of the rotor can be achieved. This commutation must be done in sequence to provide a smooth rotation of the magnetic field in the stator. Figure 2.1 from [13] shows the basic construction of a BLDC Motor.
The typical signal to control both types of motors consists of a series of trapezoidal functions which are commutated to make the motor rotate as desired. In this case however the signals to be applied to the motors will be sinusoidal currents which eliminate undesired torque ripples that can produce mechanical disturbances on the satellite. For
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2.2. Candidate Topologies 4
Figure 2.1: Basic construction of a BLDC motor. [13]
this reason signal accuracy is a big concern as with the previous power amplifier the output current looses quality at higher frequencies (i.e. higher rotational speeds).
In the case of a two-phase stepper motor the reference signals that are given to the controller are two sines with a phase of 90° between them (a sine and a cosine). As for the three-phase BLDC motor, depending on it, the reference can be three trapezoidal signals or three sines with a phase of 120° between them as it is depicted in figure 2.3.
This phase difference for the BLDC motor is due to the ”wye” (Y) or star connection between windings (figure 2.2) that is to be used and this arrangement of signals ensures that the sum of currents at the node is equal to zero.
If a sensor-less control is to be used with the BLDC motor, i.e. without the use of hall sensors or encoders to measure the position of the shaft in order to control the commutation sequence, the most used technique is sensing the back-electromotive force (Back EMF). In this case, two of the motor windings are powered while the induced voltage at the third one is measured and analyzed by the controller for feedback. [6]
2.2 Candidate Topologies
Class-D power amplification presents mainly two topologies: Full and Half Bridge. Both have the same basic working principle: a slow changing and low power reference signal is compared with a much faster triangular function in order to generate a PWM which is then fed to a Full or Half Bridge that consists of power MOSFETs which are switched in accordance to the PWM and amplify it. This amplified PWM goes then to a low pass filter which eliminates the high frequency components and feds the load with a high power version of the reference signal. [9]
2.2. Candidate Topologies 5
Figure 2.2: Wye connection of a 3-Phase BLDC Motor from the OrCad Capture MIX- MISC library
2.2.1 Full-Bridge
One important topology to be considered is the Full-Bridge Amplifier, also known as H- Bridge. In this case four MOSFETS are connected as seen in figure 2.4. Technically, all transistors can be switched on independently, however the switching must be controlled in a way that avoids simultaneous turn-on of Q1 and Q2, or Q3 and Q4 as this would generate a short circuit between the source and ground. By switching on Q1 and Q4 or Q2 and Q3, the direction of the current flow through the load (R1) can be controlled.
The amount of current flow can be controlled in two possible ways using a PWM. One way is to apply PWM controlling signals to the gates of the transistors and thus control the on-time of them. The other way is to add an extra MOSFET as seen in figure 2.5 to control with a single PWM signal and Q1 to Q4 being turned on and off in order to control the direction of the current.
1Referred to as ”simplified” due to the lack of MOSFET drivers and protection compared to schemat- ics to be analyzed late on.
2.2. Candidate Topologies 6
Figure 2.3: Reference Signals for the BLDC Motor control
Figure 2.4: Simplified1H-Bridge. Figure 2.5: Variation of the H-Bridge.
2.2.2 Half-Bridge
The other important topology to be evaluated is the Half-Bridge (figure 2.6). In this case, only two MOSFETs are used and the load is connected to the central point of the circuit and to ground. This circuit uses half the components as the full-bridge (hence the name) and also half the controlling signals.
Different variations of this topology will be simulated and compared. These variations will include the addition of diodes at MOSFET outputs to avoid reverse current flowing,
2.2. Candidate Topologies 7 among other additions to the circuit to determine how the half-bridge behaves, like different versions of the MOSFET drivers and protections.
Figure 2.6: Simplified Half-Bridge topology.
C HAPTER 3
Current Version of the Power Amplifier
The current version of the amplification circuit was developed over 15 years ago and its flight model hast been used on many satellites throughout the years. Figure 3.1 shows the overall block diagram of the circuit. An analog PI controller receives a positive half sinus reference signal and the amplified shunt voltage that represents the current flowing through the motor. The controlling signal coming out of the PI block is then compared to a fast triangular wave to generate a small signal (0 to 5 V ) PWM that controls a N-Channel MOSFET which amplifies the voltage of the PWM up to +24 V . This signal is then sent to a low pass filter that eliminates the high frequency components so that only the slow half sinus wave passes to the full bridge. The bridge is then controlled in a way that the motor receives a complete sinusoidal wave with peak voltages of ±24 V .
Figure 3.1: Block diagram of the previous version of the amplification circuit.
There are two main reasons why this circuit requires a replacement or update. First, its analog control makes it more susceptible to component failures and errors as well as
8
9 less flexible in the type of controller that can be used. And second, as the frequency of the reference sinus increases the error at the zero crossing also increases and generates undesired noise in the output torque of the motor as well as in its speed and position.
Figure 3.2 shows the error generated at the output of the simulated circuit. This simu- lated signal does not present a big error due to the ideal components and approximations used by the simulation program. If a real measurement of the current through the motor is observed as in figure 3.3 it becomes clear that the output signal is distorted to a high degree. The reference signal for this circuit is a discrete half sinusoidal wave generated by the FPGA that controls the switching of the full bridge. One of the objectives of this Master Thesis is to determine whether the new version of the amplification circuit produces such amount of distortion at frequencies in the vicinity of 50 Hz.
Figure 3.2: Simulation of the full bridge circuit.
This distortion begs an update and, if needed, replacement of the power amplification circuit for this kind of motors. A new modular circuit that improves the signal quality, has the possibility of being digitally controlled, ideally uses non export-restricted components and can be used for different types of motors was to be designed. This thesis will work upon previously developed test circuits to find the best suitable topology and where there is room, improve it. The demonstrator circuit to be designed and built must ideally have as a small footprint as possible taking into account the modularization objective of the whole power amplification system but also being able to fit up to three phases of the circuit in order to control BLDC motors as well as 2-phase step motors.
10
Figure 3.3: Measurements of the real circuit with a reference signal of 58 Hz. In green and lila are the sinusoidal currents through a 2-phase step motor.
C HAPTER 4
Available Resources/Technology
This Master Thesis should take into account technology previously developed by other students and employees at the company. This developments range from the drivers of the power transistors to the way the output current is measured and fed into a digital controller. The following sections depict some of the developments that are to be tested and given the case, used in the final demonstrator developed in this thesis project.
4.1 MOSFET Gate Drivers
In order to control power MOSFETs as switches using PWM signals, the use of gate drivers is in most cases mandatory as the controller cannot give enough output current to drive the gate capacitance of the power MOSFET [2]. Driver circuits ensure the power MOSFET receives enough current and the correct voltage levels to power on or off in a reasonable amount of time.
From previous designs there is a working driver topology which is to be used for the final circuit taking into account the different versions of it. These versions have only slight variations between them in component number, placement or value. All these are to be simulated and compared. The following subsections will show the available drivers and highlight their subtle differences. The versions are presented in order of publication or development. It is to take into account that two of them were presented in internal documents of the company ([12] and [17]). The complete schematics with the gate-drivers, the half bridge, original filter and the model of once phase of the motor can be found (for readability purposes) in appendix A where the four versions of the circuit that were simulated in section 5.2 are presented.
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4.1. MOSFET Gate Drivers 12
4.1.1 First design by Fehrle
The first available version of the MOSFET drivers was developed by Fehrle in his Bachelor Thesis. This circuit is the one on which all other three are based.
The circuit is designed to receive low voltage signals (3.3 V and 5 V) which are amplified to higher voltages to achieve the required levels for turning on and off the power MOSFET.
The current through the BJT transistor is also amplified so that the capacitances of MOSFET are charged as fast as possible.
A total of four logic level PWM signals must be fed to the circuit, two of them will turn on the the MOSFETs (one signal for each power transistor) and the other two will turn them off (having priority the ”turn-off” signal). A detailed explanation (in German) of how the circuit works can be found in [4]. For simulation purposes, a low pass filter and model of one phase of a step motor (depicted as a resistor in series with an inductor) were added at the output of the half bridge.
4.1.2 Second version by Kollewe
The next version of the circuit comes from an internal Airbus Defence and Space docu- ment by Kollewe. All transistors remained the same and some resistors were fine tuned.
The diodes however were changed, for example the 1N4148 was replaced by the 1N6642 diode, which is a military and space qualified version of the other. The changes in the topology are the elimination of the 1 kΩ resistor at the collectors of the ”on” buffer tran- sistors, the addition of a resistor and a diode between the driving BJT transistors and the gates of the power MOSFETs to modify how the gate capacitance charges and dis- charges. Finally, the protection against overvoltages and counter currents between drain and source of the MOSFETs have been changed. The consequences of these changes will be discussed in section 5.2 via simulations.
4.1.3 Corrections of the MOSFET protection by Mayer
During his Master Thesis, while working with the circuit version from Kollewe, Mayer encountered two possibilities of improvement. First, as the circuit is to be controlled (at some point) with an FPGA that only generates 2.5 V PWM signals but had a power source of 3.3 V and this same power source is used to provide a reference level in the driver of the N-Channel MOSFET, he added a diode at the emitters of the PNP transistors that receive the signals from the FPGA in order to reduce by 0.7 V the reference voltage, leaving it closer to the signal level [15]. The second, to this thesis relevant, improvement was in the protection of the power MOSFETS as the previous circuit had the problem of generating an over current at the N-Channel MOSFET up to the point that it burned during tests. The solution was to eliminate the diodes that were in parallel with a resistor in the RC protection of the MOSFETs and replaced it with a Schottky diode between drain and source which was in charge of reducing the current flowing through the transistor while discharging. A detailed explanation of both changes can be found in [15].
4.2. Delta-Sigma (∆Σ) Analog/Digital Converter 13
4.1.4 Suggestions by Rapp
Finally in an internal document Rapp suggested the re-incorporation of the 1 kΩ resistor between the collector of the buffers transistors and the rest of the circuit. This change will also be addressed during the simulation phase.
4.2 Delta-Sigma (∆Σ) Analog/Digital Converter
Among the previous work developed by interns to be taken into account for this Master Thesis is the development made by Eckstein of a Delta-Sigma Analog to Digital Con- verter. This type of ADC samples slow signals at a very high frequency giving at its output an bit-stream who’s average value is the averaged value of the input signal. The main advantages of the ∆Σ Converter are its high resolution and the fact that it shapes the quantization noise (generated by every ADC) to frequency ranges far away from the original signal frequency as it can be seen in [3] and [10].
4.3 Prototyping and Test Board
In order to reduce development times and costs of the power electronic systems for satel- lite mechanisms a modular test and development system needs to be designed. Radlinger focused his Bachelor Thesis on the development of the computing unit of this test sys- tem. The objective is to have a large carrying PCB that will support several power amplification modules (like the one to be developed in this Master Thesis) and one of these processing units as well as to provide mechanical stability to them and electrical connections and sensing capabilities to the whole system. Once the carrying board has been designed, hardware tests of the complete system can be carried on. [16]
C HAPTER 5 Trade-off and Simulations
Before selecting a final topology for the power amplifier. All possible circuits must be simulated and compared in different aspects in order to make the best possible decision.
This chapter presents the different criteria taken into account for the trade-off between the evaluated circuits and shows the selection of the final topology that will be used for the demonstrator and tests with motors.
5.1 Criteria
Several aspects of the circuits must be evaluated, weighted and compared before the selection of the best candidate for the new power amplification for satellite mechanisms can be conducted. Following, the different criteria will be discussed and given a level of priority representing their weight for the final decision.
• Signal Accuracy As one of the goals for this project is to improve the accuracy of the output signal with respect to the input signal, this aspect will be given a high priority. This is of importance since differences between the controlling signal and the output signal can lead to bad positioning of the mechanism, bad measurements of the instruments and even generate undesired disturbances for the attitude control system. However, due to the impossibility of simulating the digital control (which will be run on an FPGA) in the circuit simulation software, the simulation of the whole system is not possible. Therefore in this case the criteria will compare the change of state of the circuits, as this is important for how the output signal behaves. Once a demonstrator is constructed, laboratory tests will be conducted to compare the efficiency of the demonstrator versus the available Full-Bridge circuit.
• Power Loss Power loss on electronics can be a big problem in space. First because it is difficult to generate and store that power for it to be wasted and secondly be- cause of the heat dissipation. As there is no atmosphere in space, the only way to
14
5.1. Criteria 15 eliminate undesired generated heat by electronic components is to transfer it to the satellite’s structure and radiate it.
Therefore Power loss will be given a high priority in the trade-off criteria for select- ing the final topology.
• Number of Components One other item in which optimization is desired is the number of components in the circuit or the total foot print area. Increased power loss can in part be caused by a large number of components in the circuit.
Another advantage of having the lowest possible number of components is that the size and weight of the circuit board to be used on the satellites will be reduced, helping this way to reduce launch costs. As the circuit elements must be space graded, they are highly expensive and an increased number of parts has for conse- quent larger costs for the subsystem.
However, the efficiency, security and accuracy of the circuit must not be compro- mised by the design, therefore the priority for this criteria will be of a medium level.
• Component Availability for Space Applications and Space Suitability of the topology The final work environment of the developed circuit will be space, special care must be taken when designing the circuit and selecting the components, topologies and technologies. The high radiation of space can generate error on solid state devices or even completely destroy them For this reason, the circuit must use components that are less susceptible to fail due to radiation and the topology must be developed in a way that it helps avoid single component failure. Even though shielding could be a possibility for protecting the circuits, it is not a viable option as it would greatly increase the weight of the system as well as it’s cost.
Another important point when selecting space graded components is that all ITAR restricted elements should be avoided for their export restrictions.
This criteria will have therefore a high priority level when analyzing the different topologies.
• Electro-Magnetic Interference (EMI) Due to the switching characteristic of this type of power amplifier Electromagnetic Interference (also known as EMI) can be a concern [5], specially inside a satellite where EMI can cause disturbances to antennas and other sensing equipment. EMI generation must be avoided as much as possible and therefore this selection criteria will be given a medium priority.
• Flexibility The final product of this master thesis must be as universal as possible, being able to support dual and single power sources with different ranges of input voltages. The circuit must also be compatible with control signals of 2.5V , 3.3V and 5V and be able to supply different types of motors like step and brushless DC motors.
This selection criteria will have a medium/high priority in the Trade-Off.
• Control Complexity The way of controlling the circuit will also play a role in the selection process as it should have ideally as less control signals as possible while
5.2. Simulations 16 maintaining a good performance and fidelity. The priority however will be low as this item should not be a ”deal breaker” in the selection process.
Once the comparison criteria has been set, up the different candidates for the power amplifier can be identified. For this several topologies with different technologies will be presented for later simulation and comparison.
5.2 Simulations
This section shows the different simulations that were run using the programs OrCAD Capture and PSpice AD of the four versions of the power amplifier circuit previously discussed in chapter 2. The models used for the different components were from the OrCad libraries or when needed from online sources like the manufacturers of the device.
It must be taken into account that these simulations use many approximations and may not consider all possible characteristics of the elements of the circuit. Therefore, there may be differences between the simulated results and real measurements. The following subsections will shortly describe the tests that were run in the simulations in order to give a comparison basis between the different versions of the gate drivers and MOSFET protections provided by Fehrle, Kollewe, Mayer and Rapp.
Simulation conditions
The following lines describe how the simulation parameters and characteristics of the involved signals are set up in the simulation environment.
The control signals come from a total of four pulse generators that give the PWM sig- nals to turn on or off the transistors. These PWMs have a frequency of 32 kHz and a variable duty cycle. Figure 5.1 shows the signals fed to the drivers, it is to note that while the Top P-Channel MOSFET is high active, the Bottom N-Channel MOSFET is low active. TP ulse (for both ”On” signals) is the minimum pulse duration needed to turn on the power MOSFET, in the simulations TP ulse will be of 1.5 µs. TDuty represents the Duty Cycle of the PWM that outputs the Half-Bridge, this is also the pulse duration of both ”Off” signals, these are in charge of turning each of the MOSFETs off and keeping them that way while the other MOSFET is switched on. TDead is of big importance, as this ”dead” time is used to ensure the MOSFET that was just turned off is, indeed, turned off, as this take some short time. Once TDead has passed, the other MOSFET can be safely turned on. Should TDead be too short or non-existent, high currents would flow through the transistors, as for a short time (while one turns off and the other on) there would be a low ohmic path between V+ and V−, this high current could damage or even destroy the power MOSFETs. For the simulations V+ and V− will be of +25 V and
−25 V respectively while VSource will be of 2.5 V , this supply is used to give a positive reference for the NMOS driver and the control signals will be of 2.5 V high and 0 V low.
Figure 5.2 shows to which driver the PWM signals are assigned.
5.2. Simulations 17
The half bridge will be loaded with a low-pass LC filter whose parameters were taken (for simulation purposes) from previous work, the inductor of the filter will be of 380 µH and the capacitance will be of 4.7 µf , this filter will be either calculated or empirically determined once the demonstrator is built. After the filter, a simple model of a motor’s phase will be added. In this case, the motor modeled will be the APM Motor and the values for it’s internal resistance and inductance were taken from it’s Datasheet (22 Ω and 24 mH respectively).
Figure 5.1: The four PWM signals fed to the MOSFET drivers.
5.2.1 MOSFET Drivers
The first simulation is intended to differentiate the behavior of the four versions of the MOSFET drivers. As previously said in section 4.1, the circuits vary only slightly, so to avoid influences on the output signals, the MOSFET protections were removed. This way, the output signal will be driven only by how the drivers turn on and off the transistors.
Three simulations have been run at duty cycles (d) of 25%, 50% and 75%. The output signal of the half bridge, that is before the low pass filter, will be compared.
Duty Cycle of 25%
A duty cycle of 25% means the top MOSFET will be turned on only that percent of the time while the bottom MOSFET is switched on the remaining 75%. Figure 5.3 shows a zoom up of the falling and rising edge of the output PWM. It is to note that the Mayer version of the circuit is slightly slower in response than the others, while Fehrle’s is slightly faster. Both the rising and the falling flanks have overshots when they get
5.2. Simulations 18
Figure 5.2: Two PWMs are used to control each gate driver.
close to their final value, these overshots are of 1.6 V and 0.5 V respectively. In the case of the falling edge, the voltages present also a bump of about 1.3 V just before it starts dropping. The rising flank takes about 130 ns to reach its final value (not taking into account the length of the overshot), on the other hand, the falling flank takes almost 700 ns to reach its final value. Both rising and falling times were similar between circuits.
Duty Cycle of 50%
When the duty cycle is of 50%, waveforms are similar to those at 25%. The main difference is that there is no bump in the voltage right before the falling flank. Fehrle’s circuit is still slightly faster than the others and Mayer’s has a slower response. The rising edge for all circuits takes again 130 ns while the falling edge is faster than before with 200 ns falling time. Figure 5.4 shows the associated waveforms from this test.
Duty Cycle of 75%
With the duty cycle being equal to 75% the waves behave similar as before, with the difference that there is not bump before the rising flank as it could have been expected.
This time however the rising edge takes 250 ns and the falling edge requires 200 ns to reach its final value. Finally, figure 5.6 shows several periods of output signal with a duty cycle of 75%. In this image, the overshots at the end of the rising and falling flanks can be clearly seen. This overshots may increase the EMI production of the circuit and therefore it is desirable to eliminate them.
Up to this point, there are no big differences between the versions of the drivers. One
5.2. Simulations 19
Figure 5.3: Output voltage of the halfbridge without MOSFET protections at d = 25%.
(In green is Fehrle’s circuit, Kollewe’s in red, Mayer’s in blue and Rapp’s in yellow)
of them however is slightly faster in response. The next step is to simulate the circuits with their MOSFET protections.
5.2.2 MOSFET Protection
In order to smoothen the square signal at the middle point of the half bridge, and to eliminate the overshots seen before, but also to protect the MOSFET against counter currents, a small protection circuit was added in the previous work. By Fehrle, the pro- tection consisted of a single 1N5806 diode connected in parallel to the transistor’s source and drain terminals. Then, in the circuit revised by Kollewe the protection consisted of an RC circuit with a diode in parallel to the resistor, this circuit however presented a design failure that overlasted the PMOS increasing its temperature and also destroyed one of the NMOS during tests as explained by Mayer in his thesis. Mayer presented then an improved version of the protection circuit.
Simulations were then conducted with duty cycles varying from 10% to 90% with steps of 5% and the average power loss over one PWM cycle calculated in PSpice and plotted
5.2. Simulations 20
Figure 5.4: Output voltage of the halfbridge without MOSFET protections at d = 50%.
(In green is Fehrle’s circuit, Kollewe’s in red, Mayer’s in blue and Rapp’s in yellow)
(using a line smoothing function) in MatLAB. The results of this simulation can be seen in figure 5.7. From the figure it can be taken that Mayer’s solution improved the power loss at the PMOS for high duty cycles, but increased by over a watt the loses at the NMOS for very low duty cycle, the loss is also higher at cycles close to 50%. However, when the voltage signals are looked at, the protection designed by Mayer eliminates the undesired overshots from the signals as it can be seen in figure 5.8. Although this cir- cuit increases the rising and falling times up to almost 2 µs, the protection from Mayer reduces the risk of overloading the MOSFETs with undesired current peaks. Therefore this will be the selected MOSFET protection circuit to be used in the demonstrator.
After confirming that Mayer’s approach was the best solution for the smoothness of the signal and protection of the MOSFETs, a new simulation was run under the same con- ditions, this time with all circuits having the selected protection in order tho see how it would influence the output signals. Figure 5.9 shows that Fehrle’s circuit has less power loss when the selected protection is applied to it’s MOSFETs, specially in the case of the NMOS, where the power loss is over half a Watt less than in Mayer’s circuit. The voltage signals remain similar to that of Mayer’s from figure 5.7.
5.3. Comparison 21
Figure 5.5: Output voltage of the halfbridge without MOSFET protections at d = 75%.
(In green is Fehrle’s circuit, Kollewe’s in red, Mayer’s in blue and Rapp’s in yellow)
5.3 Comparison
In order to make a final decision the criteria from section 5.1 must be taken into account.
However due to simulation constraints some of it, like signal accuracy, must be left for the final conclusions of this work when the selected and built circuit is compared to the full-bridge version of the power amplified being currently used in satellites.
As previously described, Mayer’s approach to the protection circuit offers not only higher smoothness of the output PWM signal, but also decreases the power loss at the MOS- FETs and therefore the possibility of them being overloaded to a point of risking a destruction of the transistors. For the gate drivers, Fehrle’s design will be used as it is slightly faster than the others, but mainly because it reduces even further the power losses at the transistors.
The number of components although important, remains fairly similar among the differ- ent topologies, but there is still an advantage with respect to the full bridge amplifier as the number of components is reduced to about the half.
The elements used in the simulations have space graded and radiation hardened versions.
5.3. Comparison 22
Figure 5.6: Output voltage of the halfbridge without MOSFET protections at d = 75%
over several periods of the PWM. (In green is Fehrle’s circuit, Kollewe’s in red, Mayer’s in blue and Rapp’s in yellow)
However some of them, specially in the case of the PMOS, as the ones being considered may have ITAR restriction. Further research must be carried in order to find ideally European made replacements.
It is not possible to completely eliminate EMI produced by type D power amplifiers, however the protection circuit selected and the LP filter (placed as close as possible to the power MOSFETs) should reduce the amount of EMI generated.
The simulations were all carried out with control signals that had a 2.5 V high level, other simulations carried out at different signal levels (3.3 V and 5 V ) were also success- ful confirming the flexibility of the circuit for different types of input signals.
The number of control signals remains almost the same as with the full bridge circuit, having the half bridge four (two for each MOSFET) and the full bridge five (one for each of the four bridge MOSFETS and one to turn off the MOSFET in charge of generating the PWM). Therefore the half bridge remains as an improvement in this matter even though this is a low priority criteria.
With all this into consideration, it is decided that the main focus of the demonstrator will be testing the capabilities of the gate divers designed by Fehrle with the MOSFET protection given by Mayer. At this point, the development of final schematic will begin, however wherever possible, components will be placed in the design (but not necessar- ily will be implemented in the demonstrator) in order to conduct further comparisons between the different versions of the circuit.
5.4. Improvements 23
Figure 5.7: MOSFET power loss for each circuit with its original protection circuit. (In green is Fehrle’s circuit, Kollewe’s in red, Mayer’s in blue and Rapp’s in yellow)
5.4 Improvements
Once the trade-off was done and a circuit was selected, it was carefully analyzed in order to find any possible room for improvement.
Here was found that the overshot present after the falling and rising flanks of the output PWM were due to the fact that the schottky diode that is in parallel with the power MOSFETs turned on faster than them and after some time the transistor would com- pletely turn on and take over the conduction of current. Therefore, these overshot are not necessarily bad as they do not affect much the filtered signal and they ensure a faster transition of states. Furthermore, the RC circuit protection suggested by Mayer moved the power losses from the MOSFETs to the RC circuit, protecting the transistors but without addressing the issue of the counter currents generated due to the turn-off of the diodes at the MOSFETs. To address this issue, the RC circuit was removed leaving only the Schottky diode in parallel to the transistor and two diodes were added in series with the output of the power transistors to prevent the flow of any counter current. Finally, as it will later described, a 10Ω resistor was added in series to the filter capacitor in order to eliminate the overshot of the step response of the circuit.
With these changes, the power loss at the transistors was lowered from almost one Watt
5.5. Detailed Simulations of the Final Topology 24
Figure 5.8: Falling and rising flanks from the output signal of the circuits with original protection. (In green is Fehrle’s circuit, Kollewe’s in red, Mayer’s in blue and Rapp’s in yellow)
(at 10% or 90% duty cycles) to 0.3 W or less as it can be seen on figure 5.10.
Finally, from figure 5.11 it can be taken that the reduced power loss comes also from the much faster High to Low and Low to High transitions of the output signal, meaning that the transistors spend less time letting current pass through them during the flanks.
For the feedback line of the system a Delta-Sigma ADC was originally considered mainly due to the fact that the ADC in integrated circuit form initially desired for the project was ITAR restricted. It was however recently released from the export restriction list so in order to reduce the number of components but also increase the speed of the measure- ments, the ADC128S102 from Texas Instruments will be used. This ADC has a total of eight channels (from which only three will initially be used), it has a speed from 500-ksps to 1-Msps and uses a 12 bit converter. The output data is read via a serial interface. For this reason, no simulations will be ran using the Delta-Sigma ADC.
5.5 Detailed Simulations of the Final Topology
Once the final topology was decided new simulations were run, this time focusing on how the circuit behaves with a variable duty cycle in a way that a sinusoidal current flows through the motor phase.
The first step for this was to generate in PSpice a PWM whose duty cycle was dependent
5.5. Detailed Simulations of the Final Topology 25
Figure 5.9: Power loss at the MOSFETS with the selected protection circuit.
on the value of the reference sinusoidal signal. This can be done by comparing the slow sinus with a much faster triangular wave, the frequency of this is the same as the desired frequency of the PWM. For the comparison, an ideal operational amplifier (op-amp) was used as it can be seen in figure 5.12.
Figure 5.13 shows the sinusoidal wave that is compared to the triangular signal. It is to note that the peak (high and low) values of the sinusoidal wave must not be the same or bigger than those of the triangular wave (that is, the sinus must be completely contained in the triangular signal), this is to avoid duty cycles close or equal to 0% and 100%. For illustration purposes, the frequency of the simulated sinus is of 1k Hz, for the motor amplifier circuit the sinus will be of less than 100 Hz. This PWM however does not suffice to control the amplification circuit since as previously described in section 5.2.1, each MOSFET requires two control signals: one for turning on and one for turning off.
The PWM generated from the sinus can be used as Off-Signal for both transistors. Using a series of NAND Schmitt triggers with resistors and capacitors for delay and NOR gates a circuit was designed to generate the remaining two On-Signals, this way the dead time after the Off-Signal changes state is ensured as well as the short duration of the pulses (in each case of approximately 1.5 µs). The resulting circuit can be seen in figure 5.14.
Since the circuit is to be controlled by a digital PID controller, a way to measure the output current has to be integrated into the circuit. For this a shunt resistor of 0.5 Ω is to be placed in series with each phase of the motor, but as in the case of a wye connected
5.5. Detailed Simulations of the Final Topology 26
Figure 5.10: Power loss at the MOSFETS in the final topology. In blue is the circuit previously selected and in red the circuit with the suggested modifications.
Figure 5.11: Falling and Rising flanks of the final topology (red) vs the previously selected circuit (green).
BLCD motor the phases are not connected to ground, the shunt resistor must be placed after the low pass filter and before the motor. Then, using a series of operational ampli- fiers the differential voltage across the shunt resistor will be measured and amplified to have a peak to peak value of maximum 5 V (i.e. a sinusoidal wave with ±2.5 V peaks).
This circuit also provides an offset of +2.5 V so that the output voltage is always positive
5.5. Detailed Simulations of the Final Topology 27
Figure 5.12: Comparator used for the generation of a PWM from a sinusoidal wave.
Figure 5.13: Signals at the input and output of the PWM generator.
and the hole measuring range of the ADC128S102 can be used. The selected operational amplifier for this part of the circuit is the LT1014 which is a quad precision Op-Amp with a space graded version in an FP14 (Flat Pack) package with a 2B (Standard Component) ACL Status and no ITAR restriction. The final circuit can be seen in figure 5.15. The first stage is a differential amplifier that measures the voltage across the shunt resistor and feeds it to a second stage that consists of an inverter amplifier. This stage feeds the amplified signal to a third and last stage consisting of a differential amplifier who’s main task it to add the +2.5 V offset from a reference voltage. Equation (5.1) shows the complete transfer function of the feedback circuit. The multiplication term of 2 comes from the fist stage, this arrange must be carefully chosen in order to reduce the voltage level at the input of the fist op-amp as it could have values higher than the absolute maximum voltage tolerated by the op-amp. The gain of 5.49 comes from the second stage and is used to bring the peak values to the desired level. It is to note that with this values a limited maximum current output can be controlled. This is due to the fact that
5.5. Detailed Simulations of the Final Topology 28
Figure 5.14: Circuit used for the generation of the On-Signals.
as more current flows to the motor, the voltage drop across the shunt resistor is higher and this will be amplified and the output signal of the feedback section can drop below 0 V and also go above 5 V which would saturate the maximum values of the ADC and therefore feeding wrong values to the PID controller. In order to avoid this, the resis- tor values should be adjusted to provide less amplification when high currents are desired.
Vout= 2.5 + 5.49 ∗ 2 ∗ VShunt (5.1)
A final consideration must be done to the filtering circuit needed to eliminate the high Figure deleted due to confidentiality concerns.
Figure 5.15: Feedback circuit featuring the LT1014 Quad precision amplifier.
frequency components of the square signal leaving only the smooth sinusoidal wave that controls the motor. The previous versions of the circuit used a LC low pass filter for this function with an inductor of 380 mH and capacitor of approximately 4.7 to 5 µf (this approximation is due to the low accuracy of the capacitors used, for calculations, a capacitance of 5 µf will be used). In the practice, such a high capacitance had to be achieved by connecting five capacitors of 1 µf in parallel. Figure 5.16 shows the schematic of the LC filter an equation (5.2) it’s transfer function. The −3 dB point of this filter takes place at 5.68 kHz presenting resonance at 3.651 kHz (see figure 5.17)
Vout Vin
= 1
C1L1S2+ 1 (5.2)
5.5. Detailed Simulations of the Final Topology 29
Figure 5.16: Low pass LC filter.
Figure 5.17: Low pass LC filter.
However as the inductance of the motor is much higher than that of the filter, it also influences the signal flowing through it and must be taken into account at the moment of analyzing the dynamics of the signal. From figure 5.18 the output variable is the voltage at the resistor of the motor’s model. Equation (5.3) shows the new transfer function and
5.5. Detailed Simulations of the Final Topology 30 figure 5.19 its bode diagram. From this it can be seen that the −3 dB point is at 144 Hz but still presenting a peak at the resonance frequency.
Vout
Vin = Rm
C1L1LmS3+ C1L1RmS2+ (L1+ Lm)S + Rm (5.3)
Figure 5.18: Low pass LC filter with motor phase.
Figure 5.19: Magnitude Bode diagram of the low pass LC filter.
5.5. Detailed Simulations of the Final Topology 31 In order to eliminate the resonance peak a 10 Ω resistor (R1) was placed between C1 and ground. Equation (5.4) shows the resulting transfer function and the circuit can be seen in figure 5.20.
Vout
Vin = Rm(R1S + C1
1)
L1LmS3+ (L1R1+ LmR1+ L1Rm)S2+ (RmR1+ LC1
1 +LCm
1)S + RCm
1
(5.4)
Figure 5.20: Low pass LCR filter with motor phase.
With this correction, the cut-off frequency remains at the same position but the res- onance is completely attenuated as it can be seen in figure 5.21.
Finally a sinusoidal PWM was generated in Matlab and using the system analysis tool it was fed to both transfer functions presented in equations (5.3) and (5.4). The results can be seen in figures 5.22 and 5.23. In this case it can be noted that a high frequency component is still present in the signal filtered with the LC circuit but not present when the resistor is added to the filter.
Once the filter has been confirmed to work and be of the right magnitude, the whole am- plification circuit can be simulated in Orcad PSpice. A sinusoidal signal with a frequency of 50 Hz will be fed to the circuit and the current through the motor will be measured as well as the output of the feedback circuit. The results can be seen in figure 5.24. It must be taken into account that at this point, the power supply of the half bridge is of ±12 V , this is due to the fact that both selected power MOSFETs that are space qualified have a VDS of maximum ±100 V so due to the de-rating requirements of the space regulations a power supply of ±25 V would be too close to the de-rated maximum voltage. Chapter 6
5.5. Detailed Simulations of the Final Topology 32
Figure 5.21: Magnitude Bode diagram of the low pass LCR filter with motor phase.
Figure 5.22: Filtered sinusoidal PWM with LC filter.
will explain more in detail the selection of components and design of the circuit board.
From figure 5.24 it can be taken that the simulated circuit performs well at relatively high frequency (it is to remember that the currently used full-bridge circuit presents a high level of distortion when the reference sinus approaches frequencies of 50 Hz). The
5.5. Detailed Simulations of the Final Topology 33
Figure 5.23: Filtered sinusoidal PWM with LCR filter.
Figure 5.24: Non controlled simulation of a 50 Hz signal.
sinusoidal wave at the output of the circuit presents a small phase shift that is to be expected as the simulation ran does not have any sort of control. The current through the motor peaks at about ±270 mA and has the form of a smooth sinusoidal signal without a large amount of distortion. If an analog PI controller is added, the accuracy of the signal improves as it can be seen in figure 5.25. This PI controller was made with ideal operational amplifiers whose parameters were adjusted in order to provide controlling signals in the right magnitude to the amplification circuit. However, as the
5.5. Detailed Simulations of the Final Topology 34 control system of this circuit is to be made in further work on a digital way using an FPGA, no further simulations will be performed using the analog PI control. Nonetheless this simulation proves the capabilities of this circuit at higher frequencies in comparison to the full-bridge version currently used.
At this point the design of the schematic can be considered as finished and it can be
Figure 5.25: PI controlled simulation of a 50 Hz signal.
proceeded with the next step which consists in the selection of components (where still needed) and design of the printed circuit board.
C HAPTER 6 Hardware Design
Once the topology has been selected, the design of the circuit board can begin. This chapter describes the selection of the main components (most of them selected during the simulation stages) as well as the design and soldering of the PCB.
6.1 Component Selection
The suggestion of Hi-Rel parts should take into account the Airbus DS Component List (ACL). In this list, the parts used by the company receive a status which indicates their level of preference, being Status 1 the best option as those components are used in higher quantities and may be even found in stock. Next the second level is subdivided in 2A (preferred component), 2B (Standard Component) and 2C (Specific component). Level 3 is for new parts for future use. The other categories are: A for Project specific, B for Obsolete component, C for Forbidden component and Z for not categorized parts.
6.1.1 Power Transistors
The most important component of the Half-Bridge topology are the power MOSFETs as they act as the switches that allow the flow of current to the load. They are required to withstand a high voltage drop across them in the off state and a high current flow and low voltage drop during the on state. Apart from this, there should be a space qualified version of the transistor, ideally from an European manufacturer or in the case of an USA component, free of export regulations.
After a survey on European semiconductor manufacturers two of them offer Hi-Rel radiation hardened power MOSFETs being STMicroelectronics and Infineon. However the last offers only N-Channel power MOSFETs and this design requires one N-Channel and one P-Channel transistor. In the case of STMicroelectronics the devices shown on table 6.1 are offered.
From table 6.1 the only two available PMOS are the STRH12P10 and STRH40P10.
35
