Echo cancellation in ADSL modems

Johan Överby

Echo cancellation in ADSL modems

2001:292

MASTER'S THESIS

Civilingenjörsprogrammet Elektroteknik

Institutionen för Systemteknik

Avdelningen för Signalbehandling

Echo cancellation in ADSL modems

Johan ¨ Overby

1st November 2001

Abstract

This Master Thesis report presents a way of enhancing the performance of an ADSL

system by canceling out transmitter echoes that occur in the coupling between the AFE

and the phone lines. This new way of canceling the transmit echoes applies to all systems where the transmitted signal can be modeled by a random noise signal. The idea is to cancel out the transmit echoes in the analog domain before the ADC

in order to increase the sensitivity of the receiver. With this echo canceling method the echo suppression of the transmitted signal can come close to what is theoretically possible.

The development and simulations are done using a Matlab model of the AFE. To verify the model and show that the performance expectations were fulfilled the echo canceller was implemented in a real time system based on four ADSP-21160 DSPs

from ADI

. The issues involved with a migration from a simulation model to real systems are also considered.

1Asymmetric Digital Subscriber Line

2Analog Front End

3Analog Digital Converter

4Digital Signal Processor

5Analog Devices

Acknowledgements

This thesis was researched and written at Voyan Technology in Santa Clara, USA. The thesis work started in April of 2001 and kept on going thorough the summer and fall of 2001.

First I want to thank my supervisor James P. LeBlanc in Lulea for helping me finding a master thesis project in USA.

I also want to thank Jim Waite, Michail Tsatsanis and Mark Erickson at Voyan for their support and ideas.

I also want to thank John DeCelles and Vivek Subramanian at LSI Logic for their help in the development of the analog design.

Last I want to thank Texas Instruments for their excellent component samples that they

provided me within a day after ordering.

CONTENTS CONTENTS

Contents

1 Introduction 6

1.1 Scope . . . . 6

1.2 Background . . . . 6

1.2.1 Design solutions . . . . 7

2 Hardware 9 2.1 AFE . . . . 9

2.2 Digital interface . . . . 9

2.3 Analog modifications . . . . 9

2.3.1 DAC quantization noise reduction . . . 10

2.4 AFE noise . . . 13

3 Algorithm analysis 15 3.1 System identification . . . 15

3.2 Adaptive algorithms . . . 16

3.3 Regular LMS . . . 17

3.4 Applied LMS filtering . . . 18

4 Software 24 4.1 Simulation interface . . . 24

4.2 Real time system . . . 25

4.2.1 DSP 1 . . . 26

4.2.2 DSP 2 . . . 26

4.2.3 DSP 4 . . . 27

5 Results 29 5.1 Future . . . 30

6 Acronyms 31

APPENDIX 33

A-1 ADSL . . . 33

LIST OF TABLES LIST OF FIGURES

List of Figures

1 Two line solution . . . . 7

2 Digital echo canceller . . . . 8

3 Hybrid matching echo canceller . . . . 8

4 Two DAC echo canceller . . . . 8

5 Digital interface circuit between Hammerhead and AFE . . . 10

6 The original AFE-board design . . . 10

7 The complete circuit for summing and quantization noise suppression . . . 11

8 Second order Chebychev LP-filter . . . 11

9 Small signal circuit for analysis . . . 12

10 Frequency response for noise suppressing filter . . . 12

11 Frequency response of HP-filter on AFE input . . . 13

12 PSD of the noise in the original and the new design . . . 14

13 Block diagram of the analog components . . . 15

14 PSD from echo and transmitter paths . . . 16

15 Impulse response for the transmitter path through the hybrid . . . 17

16 Impulse response for the echo path . . . 18

17 AFE theoretical system model . . . 18

18 AFE system model with echo filter . . . 19

19 Theoretically modified system model . . . 19

20 System model with echo path estimator . . . 20

21 Optimal vs Desired solution . . . 22

22 Transfer function H

. . . 22

23 Desired (H

) vs Calculated (H

∗ W ) impulse response . . . 23

24 Optimal impulse response W . . . 23

25 Synchronization scheme for the serial interface . . . 24

26 Diagram of the test system used to capture and send data . . . 25

27 The communication channels used for the implementation . . . 26

28 Cycle consumption compared to block size . . . 27

29 Flow and algorithm overview of DSP1 . . . 27

30 Flowchart and algorithm overview of DSP2 . . . 28

31 PSD of the output from the echo canceller vs hybrid rejector . . . 29

32 ADSL reference model . . . 33

33 FDM ADSL . . . 34

34 ECH ADSL . . . 35

List of Tables 1 Complexity diagram of different adaptive algorithms[5] . . . 17

2 Link port interconnections in the DSP cluster . . . 25

1 INTRODUCTION

1 Introduction

In the last two decades, developments in the home computer industry have grown rapidly.

The computing power that only governments and large cooperations once had has come into everyone’s homes. Computers are also often used in networks to ease the sharing of data.

In homes there are often a limited number of computers which increases the need for a connection to a larger network like the internet. In the beginning these modem connections had a transfer rate of about 300 baud or coax cable baseband connections with transfer rates of 512kbit and up. These baseband connections are very expensive but since the consumers have fast computers they also want fast connections. As a result the demand for cheap high speed internet connections grew. Service providers needed to find new ways of distributing services in a cheaper way. Data connection services to consumers started with low speed modems and ISDN. But as the demand for high speed connections grew, new ways of connecting houses were developed.

The techniques used to transfer data are rapidly getting more and more complex. Eventu- ally the concept of using the IFFT and FFT algorithms to transfer data was discovered. This method is called OFDM or DMT. It is frame based and a very efficient way of transferring data between two points. ADSL is one of the first standards that uses DMT (see appendix A-1). It makes the presumption that the normal person does not use the same bandwidth

for upload and download of data. Generally the demand for bandwidth in the upload link is lower than for downloads. Hence ADSL modem have a has lower transfer rate for upload then downloads.

In this thesis a way of canceling echoes in the analog domain is presented. This method is applicable on all systems where the transmitted signal can be modeled by a random signal.

Which are generally the most difficult signals to handle. In the rest of this thesis a modified ADSL board is used for testing the analog system. In ADSL systems generally there is no need for echo cancellation. But in the ECH implementation echo cancellation is used (see appendix A-1).

Removal of the transmitted signal in this way makes it ideally possible to fully overlap the transmit band by the receive band, thereby increasing the bandwidth of the up- and down stream data.

1.1 Scope

The main project was to derive an echo canceller that cancels the transmitter echoes in the analog domain. This includes development of the extra hardware and software needed to prove the concept.

Since the ADSL that is used for testing has a transmit bandwidth of 237kHz the simulations and the tests will be limited by this frequency. This do not have any significant impact on the design since the low frequencies are harder to cancel out then the high.

There are also nonlinearities in the AFE which decreases the performance of the echo canceller. A lot of research have been made to compensate for these nonlinearities. It is however out of the scope of this thesis.

1.2 Background

In ADSL standard there are two ways of dividing the up- and down-stream bands. Either they are completely separated or overlapped (see appendix A-1). Even when they are separated problems occur because the up- and down-stream bands are close and they can interfere with each other.

Generally some receiver gain is needed to compensate for the damping in the lines. When the receiver gain increases the transmit echo will also increased such that the echo can saturate the receiver and destroy the received signal. To avoid this the dynamic range on the receiver can be increased but this is expensive. An other way of solving the problem is to remove the transmitted signal before the receiver ADC. Several ways to do this are discussed in section 1.2.1.

6Transfer rate

1 INTRODUCTION 1.2 Background

In all ADSL modems the transmitter and receiver paths are coupled to the phone-line through a hybrid. Ideally this hybrid would be constructed such that the transmitted and received signals are completely separated. But due to the fact that it is close to impossible to make a perfect hybrid the echoes will typically be reduced by 30-40dB. To achieve high enough sensitivity on the receiver it is essential to remove all the echoes from the received signal.

1.2.1 Design solutions

There are two ways of implementing the up and down stream in the ADSL standard. One is to separate the up and down stream bands completely by using a HP-filter to filter out the transmitter echo. In the other case the up and downstream overlap each other and the separation is done by an echo canceller. The most common of the two ADSL designs is the one with analog filtered up and down streams. Since it is hard to construct an analog representation of ideal HP filter, there will be a degradation of SNR in the lower frequencies of the downstream (see appendix A-1 for more details on ADSL). Because the frequency response of the transmission channel

is attenuated at higher frequencies, the lower frequencies can carry more data than the higher. But when using a HP-filter, the SNR on the lower frequencies of the received signal is decreased since the HP-filter has a role-off region at the cut-off frequency. This directly affects the number of bits that is possible to load.

If the high pass filter can be bypassed then the low frequency part of the receiver will get a higher SNR which means that the lower frequencies can carry more data. But the transmitter echo needs to be removed to avoid the saturation of the receiver ADC. There are a number of different ways to remove this echo signal or suppress the effect of it. Some of these are:

1. Cancel the echo in the digital domain (after the ADC).

2. More precise matching of the hybrid.

3. Add the inverse of the transmitted signal before the receiver DAC.

4. Use two separate lines for the transmitter and receiver.

There are advantages and disadvantages with all of these. The most effective echo suppression is the case with two lines to the AFE (see figure 1)(i.e., no echo only crosstalk between the lines). This solution is however a waste of resources. With a digital domain canceller (see figure 2) it is fairly easy to cancel out most of the echo but the dynamic range of the receiver must be high enough to handle the remaining echo from the hybrid. There is also an issue with long impulse responses that the fixed subtraction of the transmitted signal creates which increases the complexity of the echo canceller. This type is often used in the symmetric DSL standards like SHDSL with a typical filter length of about 250 − 300µs. A different approach

Line 1

DAC

ADC

Figure 1: Two line solution

to handle the echo is to match the hybrid (see figure 3). There are some products that uses this method of echo cancellation. One of these products comes from Siemens Semiconductor Group [7]. They have made an integrated hybrid matching circuit that reduces the echo by approximately 30dB for frequencies over 50kHz.

The last way of handling the echo is to add an inverse of the transmitted signal convolved with the echo channel prior to the ADC (see figure 4). In this solution the AFE needs an additional DAC. To effectively implement this method, the additional DAC needs to be as good as or better than the transmitter DAC in a bandwidth and resolution sense. The echo

7The twisted pair that connects the houses and the CO

1 INTRODUCTION 1.2 Background

ADC

Line

Rx Tx

DAC Hybrid

W

Figure 2: Digital echo canceller

Hybrid

DAC

ADC

Matching contol

Figure 3: Hybrid matching echo canceller

output must therefore be able to generate echo cancellation signals that have high enough accuracy, such that the addition of the echo signal does not introduce more noise to the receiver input.

Hybrid

DAC DAC

ADC W

Rx Tx

Figure 4: Two DAC echo canceller

2 HARDWARE

2 Hardware

The hardware used in this project consists of one computer with a DSP PCI board and an ADSL AFE board.

2.1 AFE

The AFE board has the ADSL AFE-chip Farallon (LSI Logic DPS8101), filters and a VCXO for the clock generation. The AFE-board is a development board with many different jumpers such that all the data paths can be disconnected or rerouted.

The control of the AFE is done by a serial port that interfaces to the computer. The Farallon has many features and all of them can be controlled by software provided by LSI Logic. The different features are power control to the primary analog parts of the chip, gains, filter cut off frequencies and digital output format.

2.2 Digital interface

To model and evaluate the echo canceller a hardware interface between the AFE and the DSP board in the computer is needed. The AFE has a one to four bit wide 3.3V synchronous serial interface to each of the DACs and the ADC which is clocked at approximately 17MHz. The objective is to implement the software for the echo canceller in real time in a DSP platform.

The DSP platform available was the Bittware Hammerhead board (model number HHPC-46- 08). It is a PCI board with four DSPs from Analog Devices (ADSP-21160). The board also has four different types of external interfaces:

• Link ports

• Serial ports

• RS-232

• PMC slots

The RS-232 interface is a 5-12 volt dual voltage asynchronous serial port which is not com- patible with the AFE synchronous serial port interface. The PMC-slot needs a PCI-controller chip and a lot of additional hardware, and it was not realistic for the purpose of this project to design a new AFE board with a PMC interface. This leaves the Link-ports and serial ports.

The link-ports need flow control and cannot use an external clock at the bit rates used for the AFE. This leaves the serial ports. They are synchronous and can theoretically be clocked at 40MHz (up to half the CPU rate of 80MHz). The serial port can also use external bit and a word clock.

The AFE has only one clock signal available and it is the master clock at 35MHz which is twice the bit clock. This frequency needs to be divided down or handled by software. The specifications on the serial interface of the AFE and ADSP-21160 did not exactly match (the timing was off by a few nanoseconds). This was also confirmed when capturing data with the 35MHz clock. The DSP could not keep the correct word sync and bit errors occurred.

To surmount this problem the clock rate must be divided by two. The ADSP-21160 has an internal clock divider but it can only divide internally generated clock frequencies so an external divider is needed.

There are many ways to divide a digital signal by two using logical circuits. One way is to use a D-type Flip-Flop where the inverting output is connected to the input and the divided clock rate can be read either on the inverting output or the noninverting output. I choose the D-type Flip-Flop SN74AC74 from TI to realize the divider. The schematic of the digital interface is shown in figure 5

2.3 Analog modifications

The AFE board was mainly developed to use FDM ADSL

with a HP-filter in the receiver chain to cancel out the echo from the transmitter. The board also has a hybrid rejection circuit that suppresses some of the echo before the filter. The HP-filter is a high-order analog

8For more information see A-1

2 HARDWARE 2.3 Analog modifications

3.3V

SN74AC74 3

1

2

4

5

CLK 6

CLR

D PRE Q Q

MCLK−35MHz

Rx

Tx

Ex

Rx

Tx

Ex

WCLK WCLK

WCLK BCLK−17.5MHz BCLK−17.5MHz

SPORT1 Hammerhead−PCI AFE

SPORT2

Figure 5: Digital interface circuit between Hammerhead and AFE

filter that separate the up- and down-stream frequency bands, and suppresses the rests of the transmitter echo (see figure 6).

ADSL−modem

ADC

AFE development board AFE

Rx

Tx Hybrid

LP−filter LP−filter DAC

HP−filter

Line

Figure 6: The original AFE-board design

The AFE has a secondary transmitter path or the echo path. Although present on the AFE board, this path was not active and therefore available for development work by Voyan.

The idea is to use this path to lower the HP-filter cutoff frequency ideally to just above the voice band. To accomplish this a signal is sent through the echo path that cancels out the echo from the transmitter through an analog summing circuit. The circuit for adding the echo signal to the received signal as well as the circuits needed to bypass the original HP-filter had to be designed and built.

2.3.1 DAC quantization noise reduction

In the specification of the AFE it is clearly stated that the internal filters for quantization

noise suppression are not to be relied on. To suppress the quantization noise a second order

Chebychev LP-filter was added in the echo path before echo cancellation signal is added to

the received signal. The filter is an active filter with multiple feedback that the engineers at

2 HARDWARE 2.3 Analog modifications

LSI Logic suggested. The schematic of the low pass filter and the summing circuit can be seen in figure 7.

To verify the suggested design the transfer function needs to be derived. The problem can be reduced from a differential to a single input problem since the frequency response does not change. The equivalent circuit can then be drawn as in figure 8 and the small signal circuit model as in figure 9. Then by using Kirchhoff’s current and voltage laws the following equations can be derived. In figure 9 the different “round trips” are shown.

2:nd order Chebychev LP at 200kHz

Summer with hybrid gain 0.5 and echo gain of 4

HP−filter at 15.7kHz ECL

ECR

From Hybrid From Hybrid

RXR RXL

0 ^{Vee 5V}

Vcc 5V

0 Vee

−

−5v

Vcc 5V

0 Vee −5v Vee −5V Vcc 5V

Vcc 5V R7

2k

R2 24.9

R12 4k R7

500 C3

82

k 2 0 1 R F

n 0 1 6 C

F p 0 2 8

2 C

0 0 5 6 R F

p 0 2 1 4 C

k 2 1 R

F n 7 4 8 C

+V−V

− +

T U O

84

6 5

1 2 6 0 6 S H T

A 5 1 U

+V−V

− +

T U O

84

6 5

1 2 6 0 6 S H T

A 5 1 U F

n 0 1 5

C 4k

1 1

R 2k

9 R

+V−V

−

+ T U O

84

2

3 1

2 1 0 6 S H T

A 1 U

k 2 6 R

k 2 8 R

F n 7 4 7 C

9 . 4 2

2 R

k 2 5 R

3 3 3

3 1 R

k 2 3 R

+V−V

−

+ T U O

84

2

3 1

2 1 0 6 S H T

A 1 U

F p 0 2 1 1 C F

p 0

Figure 7: The complete circuit for summing and quantization noise suppression

0 0

Vee −5v Vcc 5V R2

2k

C2 820pF C3

10nF

R3

2k

R4 24.9

C1

120pF

THS6012 1 3

2

48

OUT +

−

V−V+

R1

2k

V

V

OUT

Figure 8: Second order Chebychev LP-filter

i

− i

− i

− i

= 0 (1)

V

− i

sC

− R

i

− i

sC

= 0 (2)

R

i

− i

sC

= 0 (3)

V

+ i

R

− i

sC

= 0 (4)

V

+ i

³ ₁ sC

+ R

´

− i

sC

= 0 (5)

By solving the equation system with the equations 2,3,4 and 5, the equations for i

become

i

= C

s(C

R

V

s + V

)

C

R

s + 1 (6)

2 HARDWARE 2.3 Analog modifications

0 0

0

2k

C2 820pF C3

10nF

R3

2k

R4 24.9

C1

120pF

3 2

+ +

−

− R1

2k _OUT

V

i 2 i3

i 4

V

Figure 9: Small signal circuit for analysis

i

= −C

R

V

s − V

R

(7)

i

= −C

sV

(8)

i

= −C

C

s

R

V

(9)

Then by using equation 1 with 6,7,8 and 9 the transfer function can be written as V

V

= − R

sC

à s

C

C

C

R

R

R

+

s

C

(C

R

R

+ C

(R

(R

+ R

)) + R

R

)+

s(C

(R

+ R

) + C

R

) + 1

! ⁽¹⁰⁾

The suggested quantization noise filter results in the frequency response depicted in figure 10.

From the frequency response and the schematic it is evident that the circuit has both a LP

0 1 2 3 4 5 6

x 10⁵

−20

−15

−10

−5 0 5

20*log10 (VOUT/VIN) [dB]

Frequency [Hz]

Figure 10: Frequency response for noise suppressing filter

characteristic as well as a HP part. The HP characteristic removes all the DC and some of the

2 HARDWARE 2.4 AFE noise

lower frequencies by virtue of the capacitor C

. The low frequency breakpoint of the filter is approximately at 4590Hz and the high frequency breakpoint is at 367kHz. These frequencies are for the ideal circuit but the frequency response does not change significantly when adding the input and output resistances to the model (see figure 9) (verified in PSpice).

For the filter to work well with low noise and high bandwidth the THS6062 from TI was used. This is a ADSL receiver OP-amp which has better performance than the ADSL driver OP-amps if the load is not too great. The bandwidth of the OP-amp is 100M Hz and slew rate 100V /µs. The distortion in the pass-band of the filter is less then -80dBc with a 300Ω load [4]. To reduce the low frequency content of the received signal a simple RC HP-filter was added to the output of the summer. The cutoff frequency of this filter can be calculated through voltage division using formula 12. The effect from the AFEs input resistance falls within the error margins of the resistors and therefore are neglected in the calculations.

V

= R

R

+

7

V

(11)

V

V

= R

R

+

7

(12)

= R

sC

R

sC

+ 1 (13)

= 333iπf 47 · 10

333iπf 47 · 10

+ 1 (14)

The transfer function 14 is then plotted in figure 11

0 1 2 3 4 5 6

x 10⁵

−25

−20

−15

−10

−5 0

20*log10 (VOUT/VIN) [dB]

Frequency [Hz]

Figure 11: Frequency response of HP-filter on AFE input

The entire analog design is laid out on a small double sided PCB with the summer on one side and the LP quantization filter on the other. The OP-amps are decoupled by two capacitors, one 6.8µF and the other at 100nF .

2.4 AFE noise

To get an idea of how much noise the new design adds to the received signal the output from

the AFE is investigated. The test is done by sending zeros to the DACs while capturing the

received data. It turns out that in the original design the noise level is lower than the new

with the adder. Figure 12 shows the noise in the original design versus the design with the

2 HARDWARE 2.4 AFE noise

echo path connected are shown. There are many factors why the new design has a higher noise level than the old. In the new design the circuits are mounted on a board that is manually routed and not optimal in a noise sense. The matching between the driver circuit on the AFE board and the summer has been changed. The HP-filter has a resistance of 100Ω but the summer has an input resistance of 4kΩ that can create some differences in the noise spectrum.

0 1 2 3 4 5 6

x 10⁵

−5 0 5 10 15 20 25 30 35

Frequency (Hz)

Power Spectrum Magnitude (dB)

With analog summer With HP−filter

Figure 12: PSD of the noise in the original and the new design

3 ALGORITHM ANALYSIS

3 Algorithm analysis

The echo cancelling filter algorithm should work as a predictor that predicts and cancels the transmitted echo signal at a certain time. This filter will optimally remove all of the trans- mitted signal from the received. But since there are some differences in the two transmitter paths total suppression of the received signal can not be accomplished. Instead some addi- tional digital filtering is needed. The different factors that affect how successfully the filtering can be done are

• Frequency response of the transmitter and echo paths.

• The channel length of the transmitter path versus the echo path.

• Limitations in number of filter taps that are needed versus the maximum number that can be used in the DSP system.

• Non linearities in the system.

There are also significant physical limitations in the system that affect the result of the echo cancellation. These are

• Computational power.

• Dynamic range of the ADC/DAC.

3.1 System identification

To determine the system transfer functions, all frequencies need to be excited over the band- width of interest [1]. This can be accomplished by sending white noise through the two channel inputs (see figure 13) one at a time. Then the frequency responses and channels can be calculated from the received data.

The first step to evaluate if the echo cancellation can successfully be accomplished is to examine the PSDs of the output from the two different paths. This tells if the echo path can produce a signal that covers all of the transmit frequencies. In figure 14 the PSD for the both channels are plotted and it is noted that the echo response covers the transmitter response almost completely. The only exception to this is at frequencies below 20kHz.

Test system

ADC

Echo path Transmitter path AFE

Rx Ex

Tx Hybrid

LP−filter LP−filter LP−filter

DAC DAC

Figure 13: Block diagram of the analog components

The next step is to calculate the impulse response of the channels. The two channels are modulated one at a time (meaning that data is only transmitted in either the transmitter or the echo path), and the response captured to memory. Then by using the Wiener filter solution the impulse response can be calculated as follows (where x is the input vector, y

the output at time k and w is the impulse response)[5]

R = E{xx

} (15)

p = E{xy

} (16)

w = R

p (17)

To get an accurate value of w the matrix R and the vector p are averaged before w is

calculated.

3 ALGORITHM ANALYSIS 3.2 Adaptive algorithms

0 1 2 3 4 5 6

x 10⁵

−140

−130

−120

−110

−100

−90

−80

−70

−60

−50

−40

Frequency (Hz)

Power Spectrum Magnitude (dB)

Echo path Transmitter path

Figure 14: PSD from echo and transmitter paths

The resulting impulse responses are shown in figure 15 and figure 16. These impulse responses were used in the model shown in figure 17. With this model the entire analog system could be modeled in Matlab.

Before any algorithm development it is good to know what the real system can do. If the sample rate of the DACs and ADCs is 1.104M Hz [2] and the DSP has a clock rate of 80M Hz [3] then the DSP has only

80 ∗ 10

1.104 ∗ 10

= 72 (18)

cycles to generate the output of the next echo sample. Since the DSP theoretically can make two MAC operations in one cycle the maximum FIR-filter length between the t

and the e

path (see figure 19) can be only 72 ∗ 2 − 1 = 143. Since the DSP needs time to set up registers, handle interrupts, do the tap update, and transfer data this number will decrease significantly.

3.2 Adaptive algorithms

ADSL systems are usually always connected and running continuously and this makes the systems very close to stationary since the only changes that occur are thermal. There are some special cases where the change is more drastic, such as would be the case when a temporary but strong noise source impairs the ADSL line. This may require a retrain of the ADSL modem, including a re-initialization of the echo algorithm.

The fact that there are differences in the incoming lines between different locations makes it hard to design a static digital FIR filter that performs well. Thus arises the need for an adaptive filter solution. There are a number of different types of adaptive filters, all with their own advantages and disadvantages. Almost all of the adaptive filters have the objective to minimize the mean square error, either by using some kind of Steepest decent algorithm or Kalman filter to come as close to the Wiener solution as possible. Because of the limited computational power in the DSP it is necessary to choose an algorithm that has a low computational complexity. In table 1 the complexity of some of the most commonly used adaptive algorithms is shown. The Regular LMS algorithm has the lowest computational complexity. But on the other hand it has the slowest convergence rate of the three algorithms.

Because of the limitations in computational power the regular LMS algorithm is best suitable

for the echo canceller even given the slow convergence speed. As stated earlier this has no

major impact on the performance since it is almost a static system.

3 ALGORITHM ANALYSIS 3.3 Regular LMS

0 50 100 150 200 250 300

−4

−2 0 2 4 6 8 10 12 14x 10⁻³

Tap number

Figure 15: Impulse response for the transmitter path through the hybrid Algorithm Complexity

Regular LMS O(N ) LMS Newton O(N

) Regular RLS O(N

)

Table 1: Complexity diagram of different adaptive algorithms[5]

3.3 Regular LMS

The LMS filter is one of the more commonly used adaptive filters. The filter uses an adaptive algorithm to update the taps in a FIR. The tap update in the LMS is very simple and it can be derived from the Wiener solution stated in equation 17.

A good estimate of correlation matrix R of the input (denoted ˆ R

) and the cross correla- tion between input and output vector p (denoted ˆ p

) can be made by taking the instantaneous values of the input and the output. Then a steepest-decent-based algorithm can be used to search for the Wiener solution of equation 19 using the gradient method.

w

= w

− µˆ g

(19)

= w

+ 2µ(ˆ p

− ˆ R

w

) (20)

To calculate the estimates ˆ R and ˆ p the instantaneous estimates are used as follows

R ˆ

= x

x

(21)

ˆ

p

= d

x

(22)

then the resulting gradient ˆ g

can then be written as ˆ

g

= −2d

x

+ 2x

x

w

= 2x

¡ −d

+ x

w

¢

= −2e

x

(23)

Note that if the objective function is replaced with the instantaneous squared error e

instead

3 ALGORITHM ANALYSIS 3.4 Applied LMS filtering

0 50 100 150

−1.5

−1

−0.5 0 0.5 1 1.5 2

Tap number

Figure 16: Impulse response for the echo path

H +

H ex

rx t x

ex

nx

+ rx

Figure 17: AFE theoretical system model

of the MSE, the gradient estimate above represents the true gradient vector [5] since

∂e

∂w

=

· 2e

∂e

∂w

2e

∂e

∂w

...2e

∂e

∂w

¸

= −2e

x

= ˆ g

(24)

The resulting gradient based tap update function that minimizes the MSE then becomes

w

= w

+ 2µe

x

(25)

which is the LMS tap update function.

3.4 Applied LMS filtering

In the system shown in figure 13 all the analog blocks can (as stated in section 3.1) be reduced to the system in figure 17. This is the model used to develop the echo canceller. When the echo suppression filter is added to the model the system becomes as shown in figure 18.

Unfortunately the only signals that are accessible in the algorithm are the ones in the digital

domain, i.e. t

,e

and r

.

3 ALGORITHM ANALYSIS 3.4 Applied LMS filtering

W ex

tx

rx

Hex H +

+ tx

nx

Figure 18: AFE system model with echo filter

If the filter update function uses the input t

as well as the r

values for the tap update, then the most straightforward way of deriving the function from equation 25 would look like equation 26.

w

= w

+ 2µe

x

x

= t

e

= r

w

= w

+ 2µr

t

(26)

To verify that this solution converges to the right solution the update equation 26 is studied.

If equation 23 is modified to match this update equation the gradient becomes ˆ

g

= −2d

x

+ 2x

x

w

(27)

= −2dt

+ 2t

t

(w

∗ h

) (28)

= 2t

(−r + t

(w

∗ h

) ⇒ (29) w

= w

+ 2µt

(−d + t

(w

∗ h

)) (30)

6= w

+ 2µr

t

(31)

which is not the desired update equation. The update of the filter is incorrect due to the fact that the transfer function h

changes the gradient. This in turn results in that the filter will not converge to the right w. It turns out that if h

is one i.e. a δ function, the update equation 30 reduces to equation 26. Then the system can be reduced to the system shown in figure 2.

The filter update functions obviously need some change in order for them to converge to the right solution. If the system in figure 18 is changed to the one in figure 19 the update function could be derived as follows

W

nx

ex tx

rx

H rx +

+ Hex

Figure 19: Theoretically modified system model

w

= w

+ 2µe

x

3 ALGORITHM ANALYSIS 3.4 Applied LMS filtering

x

= e

e

= r

w

= w

+ 2µr

e

(32)

this system works since t

6= e

but it is not possible to change the order of the adaptive filter W and the echo path filter H

. In a series of LTI-filters the order of the filters can be changed without affecting the resulting output. So if the update equation (32) could be used in the system in figure 18 it would converge. But the tap update equation (32) is dependent on the output of the adaptive filter itself (see figure 18) which is not available. If on the other hand suppose an estimate of the H

filter were used to create an estimated input vector ˆ e

. This then would be used instead of the original one to update the filter W (see figure 20).

The update equations for this new system are derived as the previous ones where the function 33 is the filtration of the t

input through the estimated filter ˆ H

(equation 28).

^ ^ W

x t x

ex

nx

+ x

+

e Hex

Hrx

H ex

r

Figure 20: System model with echo path estimator

w

= w

+ 2µe

x

x

= X

i=0

t

h ˆ

(33)

e

= r

w

= w

+ 2µr

Ã

X

i=0

t

ˆh

!

(34)

Even if this solution works the echo path impulse response is unknown. The echo path needs to be estimated for the equation to be successful.

There are different ways to estimate the echo path. The safest and as it turned out the most reliable way to get a stable system is to send data through the echo output and then digitally adapt a filter to cancel out the received signal in the same manner as in figure 2. Then when the estimation has converged, stop updating and start the real system with this fixed estimation. One other possible solution is to let both the W and the echo path estimation filter ˆ H

filters adapt at the same time. This requires that the initial values of the filters are not equal to zero. Unfortunately it is hard to get a guaranteed stable filter convergence which rules out this solution. Yet another way of doing it could be to first let the estimate H ˆ

converge, and then adapt the filter W with fixed ˆ H

. After the W filter has converged, H ˆ

can be updated with a small µ to compensate for thermal or other slow changes in the system.

To determine how well the filters can perform the optimal solution needs to be calculated.

By studying figure 18 it is clear that the echo path must be equal to the transmitter path.

Meaning that

h

= h

∗ w (35)

3 ALGORITHM ANALYSIS 3.4 Applied LMS filtering

If equation 35 is rewritten to matrix form using the following convolution matrices

H

=



 

 

 

 

 

 

 

 

 



h

0 ... 0

h

h

0 ... 0

.. . . .. .. .

h

... h

0 ... 0

0 h

... h

0 ... 0

.. . . .. .. .

0 ... 0 h

h

0 ... 0 h



 

 

 

 

 

 

 

 

 



(36)

W =



 

 

 

 

  w

w

.. . w

0 .. . 0



 

 

 

 

 

(37)

the convolution can be written as

H

= H

W (38)

and the optimal solution can then be written as follows

W = H

H

(39)

However this operation turns out to be an illposed problem since the matrix H

is not of full rank. This can be rectified by adding noise to the system, i.e. by adding a small number to the main diagonal of H

. The equation then becomes

W = (H

+ δI)

H

(40)

This solution does not give the exact solution but if δ is carefully chosen the solution is close to optimal. Equation 40 is used to calculate the optimal solution from the impulse responses that are shown in figure 15,16. The solution then is compared with H

and the square difference between them is about -27dB (see figure 21). It also turns out that the required impulse response length of W that is needed to solve this problem is about 1200 taps which is not feasible.

The problem is that the transmitter echo path is too long to be able to solve the problem

in this manner. If however the length of the transmitter echo impulse response could be

decreased the problem would be simpler. It turns out that the analog hybrid rejection circuit

that reduces the echo is the sole reason why the impulse response is as long as it is. When the

hybrid rejection circuit is removed the echo response magnitude increases by several dB but

the channel length becomes much smaller. In figure 22 the new transmit impulse response is

plotted. Then by using equation 40 with δ = 0 the squared error between the desired and the

resulting impulse responses becomes -62dB and the plot looks like figure 23. The echo filter

then results in an impulse response with a length of about 200 taps and the main changes in

the response is taking place in a window of 50 taps see figure 24.

3 ALGORITHM ANALYSIS 3.4 Applied LMS filtering

0 200 400 600 800 1000 1200 1400 1600

−4

−2 0 2 4 6 8 10 12 14x 10⁻³

Taps

Calculated responce Desired responce

Figure 21: Optimal vs Desired solution

0 50 100 150 200 250 300

−1

−0.8

−0.6

−0.4

−0.2 0 0.2 0.4

Taps

Figure 22: Transfer function H

3 ALGORITHM ANALYSIS 3.4 Applied LMS filtering

0 200 400 600 800 1000 1200 1400 1600

−1

−0.8

−0.6

−0.4

−0.2 0 0.2 0.4

Taps

Calculated responce Desired responce

Figure 23: Desired (H

) vs Calculated (H

∗ W ) impulse response

150 200 250 300 350 400 450 500 550

−0.3

−0.25

−0.2

−0.15

−0.1

−0.05 0 0.05

Taps

Figure 24: Optimal impulse response W

4 SOFTWARE

4 Software

To be able to develop the algorithms in section 3 a simulation model of the AFE needs to be developed for both the the transmitter and the echo path (see figure 17). To simplify modeling it is convenient to let Matlab control data generation and capturing. However there are no specific Matlab functions to interface to the Hammerhead card, although Bittware

supplied a number of c-libraries. These libraries can instead be used in Matlab MEX functions that can handle the data transactions needed for system modeling.

4.1 Simulation interface

The Matlab interface needed for capturing data for modeling the system consists of two parts

• MEX function on pc.

• DSP program

The mex function takes two arguments: one is the transmit vector and the other is the echo vector. The function returns the received vector with the same size as the transmitted ones. The maximum size of the vector is limited by the size of the internal memory on the DSP. In this case the limit is 48kW

but to also fit the received vector the maximum size of the transmit and receive is therefore 24kW.

The MEX function loads the DSP executable and the two input vectors on to DSP1 and DSP2. Then starts both DSPs and waits until the DSPs are finished sending and receiving the data. Then it fetches the received vector from DSP1 and dumps it to Matlab.

The DSP code assumes that all the data is loaded. It will start by initializing the serial ports and synchronizing them. The synchronization scheme is needed since the AFE sends data continuously and the DSP serial port only reads the word clock (see figure 5) during the first bit of each word

. Therefore if the transfer is activated during word clock high

the words will always start at that position. To avoid this phenomena the word-length is set to a value smaller than the actual word length and then a fixed number of words are read. This operation will make the word start change after each received word until the start reaches the correct position. When the word start reaches its correct position the word length is changed to the correct length and the serial transfer is in sync. After this initialization the DSP will start sending and receiving data. In figure 25 the synchronization scheme is shown for a word length of 7 bits. The sampling is done at the rising edge.

After sync

Word sampling Word sampling

Word sampling

Word sampling Word sampling Word sampling

Word length 5bit Sync operation

Word sampling Word sampling Word sampling Word sampling

Bit clock Word clock

Word length:7bit

With no sync

Word sampling

Figure 25: Synchronization scheme for the serial interface

Before the data can be sent it needs to be converted to the right format. The normal binary representation of numbers is two’s complement and the data from the ADC arrives in that format. The DAC wants offset-binary which is two’s complement with inverted sign bit.

After sending the converted data the DSP will signal the host that the received vector is filled up. In figure 26 the flow diagram over the test system is shown.

9The manufacture of the DSP board

10kilo Words (32bit)

1116 bit

12Depends on if set to active high or active low

4 SOFTWARE 4.2 Real time system

MATLAB

two’s comp −> bin offset two’s comp −> bin offset

DSP−lib

DSP1 DSP2

AFE MEX function

Figure 26: Diagram of the test system used to capture and send data DSP1 DSP2 DSP3 DSP4 PMC External

DSP1 x 2-4,3-5 1-2,5-3 0 4

DSP2 4-2,5-3 x 2-4,3-5 0 1

DSP3 4-2,5-3 x 2-4,3-5 0 1

DSP4 2-1,3-5 4-2,5-3 x 0 1

PMC 0 0 0 0 x

External 4 1 1 1 x

Table 2: Link port interconnections in the DSP cluster

4.2 Real time system

In the full echo canceller system the Visual Debugger from Analog devices was used since it is easier to simulate a real time system in a debugger. There are however some down sides in using the debugger for the simulations, generally related to software bugs. For instance it is not possible to plot buffers of arbitrary length.

The real time echo canceller consists of a system with three DSPs because the topology of the processor cluster is such the third processor is not used. The DSPs have different ways of communicating with each other. Some of these are:

• Cluster Bus

• Link port

• Flags/Interrupts

The Link ports are bidirectional and operate at half the clock speed of the DSP with a bus width of 8 bits. There is a fixed topology of Link port interconnections in the cluster. This topology is shown in table 2 where the Link port numbers are (Row DSP link port)-(Column DSP link port).

The cluster bus is a shared medium between all of the DSPs and runs at half the DSP clock rate. It is a 64bit wide bus that also connects to the SDRAM and the SharkFIN ASIC interface chip. This is a fast medium to communicate between the DSPs but only one DSP can transfer data at the same time. The transfers to SDRAM are slower than transfers between the DSPs so memory transfers can slow down or halt transfers between the DSPs.

Flags and interrupts are a useful medium to distribute signals throughout the system.

There are two flags and two hardware interrupts connected to the SharkFIN ASIC from

each DSP. The SharkFIN can route any flag to any interrupt on any DSP or the PMC/PCI

interface. It is however not possible to transfer data through the interrupts or Flags.

4 SOFTWARE 4.2 Real time system

The reason that the echo canceller is divided into three different DSPs is due to the fact that only one external serial port (with one transmit and one receive wire) exists on each DSP. An extra serial port is needed for the additional echo path which in turn means one more DSP. The DSPs themselves have two serial ports but one of them is used internally on the Hammerhead board. In figure 27 the whole flowchart of the dsp system is shown.

SPORT AFE

DSP2 DSP4 DSP1

RAM

CLUSTER

CLUSTER LINE

ADSP−21160 ADSP−21160 ADSP−21160

IRQ

LPORT LPORT

LPORT

SPORT

Figure 27: The communication channels used for the implementation

4.2.1 DSP 1

The main task of DSP1 is to calculate the different filter outputs and adapting the adaptive filters. There are two stages in the program: initialization where the echo-path adaptation is taking place and secondly the show-time stage where the real echo cancellation is taking place.

The first thing that the DSP does is to synchronize the serial ports. This is done in the same way as described in section 4.1. To synchronize the transmissions between DSP1 and DSP2, DSP1 sets off an interrupt on DSP2 to start synchronization. Right after the start DSP1 sends data from DSP4 to DSP2. The update of the echo path estimation is then taking place on every received word. Equation 41 is used for calculating the cycle consumption N of the initialization phase, where N

is the block size and N

is the estimation filter length.

N = 18 + (N

− N

+ 1)(16 + N

) (41) After the echo path estimation has converged the DSP goes into show time.

In the show time mode the DSP receives data from DSP4 and then filters the received data with the adaptive echo canceller filter before sending it to DSP2. The data from DSP4 is also converted to offset-binary and transmitted through the serial port. The tap update operation consists of two steps. First the transmit vector is filtered through the echo estimation filter H ˆ

before being used as input vector to the tap update. To be able to fit all the operations the tap update algorithm is only performed once on every block of data. In equation 42 the cycle count for the entire set of operations is shown, where N

is the block size, N

is the estimation filter length, and N

is the echo canceller filter length.

N = 38 + N

2 + N

(8 + N

) + N

(9 + N

) (42) For a filter with 10 tap estimator and a 50 tap echo canceller the size of the blocks can be plotted as a function of the number of cycles needed. The available number of cycles are also plotted as in figure 28. Is is evident that the block size needs to be greater than 72 for the system to work. A figure of the general implementation can be seen in figure 29.

4.2.2 DSP 2

DSP2 has one main objective and that is to receive data from DSP1 and convert it to the output format and then send it to the AFE. There are also two stages in this DSP, one for initialization and one for show-time. The serial initialization is triggered by DSP1 and works exactly as the one in DSP1 (to keep them synchronized).

During the initialization stage the data from DSP1 is represented as integers in two’s com-

plement representation. At show-time the received data changes to float after the transition is

signaled from DSP1 with a flag in DSP2 memory. Both conversions takes less then 72 cycles