Surfaces and interfaces of low dimensional III-V semiconductor devices
YEN-PO LIU
DEPARTMENT OF PHYSICS | FACULTY OF SCIENCE | LUND UNIVERSITY
Surfaces and interfaces of low dimensional
III-V semiconductor devices
Yen-Po Liu
DOCTORAL DISSERTATION
Doctoral dissertation for the degree of Doctor of Philosophy (PhD) at the Faculty of Science at Lund University to be publicly defended on 28th of October at 13:15
in the Rydberg lecture Hall, Department of Physics Faculty opponent
Professor Bruno Grandidier, Institute of Microelectronics, Electronics and Nanotechnology (IEMN-CNRS) and Institut Supérieur d’Electronique et du
Numérique (JUNIA-ISEN)
Organization
LUND UNIVERSITY Document name
Doctoral thesis Division of Synchrotron Radiation Research
Department of Physics, Box118 S-22100 Lund
Date of issue 2022-10-28 Author:
Yen-Po Liu Sponsoring organization
Title and subtitle
Surfaces and interfaces of low dimensional III-V semiconductor devices Abstract
The demand for fast and energy efficient (opto-)electronic applications needs high mobility semiconductor materials, such as InAs with a very high electron mobility and GaSb with a very high hole mobility. Beyond the material itself, also an innovative device geometry is needed, for example, the gate-all-around geometry that provides higher efficiency and electrostatic control for computational units. Vertically or laterally grown nanowires and nanosheets are excellent candidates for realizing such beneficial device geometries. The logic operations and charge transport could be realized in different device architectures, such as the concepts of tunnelFETs instead of classical FETs or new neuromorphic hardware instead of complementary metal-oxide-semiconductor (CMOS).
With both the excellent functional properties of III-V materials and the flexibility of nanostructuring into 1D nanowires and 2D nanosheets, III-V semiconductors could be the stars for next-generation applications. For example, lateral grown InxGa1−xAs nanowires have a high spin-orbit coupling and moderate bandgap promising for quantum computing devices. GaSb nanowires are excellent high-speed p-channels for III-V CMOS, and InAs/InP nanowires have an energy barrier in the axial direction which can be used for photovoltaic and sensor applications. Due to the high surface-to-bulk ratio of nanowires and nanosheets, their surface condition becomes the key to the device performance. In this work, III-V nanowire and nanosheet devices are studied with an emphasis on surfaces and interfaces, using a wide range of characterization methods. The dissertation explores the fabrication of novel nano- devices and the characterization of their surface chemistry, topography, electronic properties, electrical transport and interaction with photons.
The characterization techniques include scanning tunneling microscopy/spectroscopy (STM/S) for atomic level topography and electronic properties. Development of a Scanning gate microscopy (SGM) system with additional single-mode focused lasers for simultaniously probing influence of static and optical fields. Synchrotron based X- ray techniques, mainly X-ray photoelectron spectroscopy (XPS) is used for evaluating surface chemistry. Surface treatment processes, e.g., ultra-high vacuum (UHV) annealing, digital etchants, atomic hydrogen cleaning, and atomic layer deposition (ALD), are applied and the resulting surface chemistry, structure and electronic properties measured. Beyond studying the surface properties, we also investigate the device efficiency and performance down to the nanometer scale. Therefore, we perform measurements to monitor the device while the local gate and/or a focused light interact with the device.
In conclusion, in this thesis the surfaces and interfaces of low-dimensional materials for future device applications are studied using many different characterization methods. It is the hope that the thesis will assist in the progress toward novel devices and improve the energy efficiency and performance of devices. Both the method development and the results give relevant contributions opening for future quantum technologies and (opto)electronics.
Key words
III-V semiconductor, nanowires, nanosheet, nano-device fabrication, STM, AFM, SGM, OBIC, XPS Classification system and/or index terms (if any)
Supplementary bibliographical information Language
English
ISSN and key title ISBN
978-91-8039-399-7 (electronic) 978-91-8039-400-0 (print)
Recipient’s notes Number of pages 150 Price
Security classification
I, the undersigned, being the copyright owner of the abstract of the above-mentioned dissertation, hereby grant to all reference sources permission to publish and disseminate the abstract of the above-mentioned dissertation.
Surfaces and interfaces of low dimensional
III-V semiconductor devices
Yen-Po Liu
Front cover:
SEM images of vertically grown InAs nanowires (upper, top view), InAs nanosheets (lower, side view), and transferring the nano-materials to pre- patterned electrodes for devices using micro-probe in the SEM chamber.
Back cover:
SEM image of long GaAs NWs.
Copyright pp i-96 Yen-Po Liu
Paper I © Licensed under CC-BY 4.0 published by AIP Publishing LLC.
Paper II © The Authors.
Paper III © Licensed under CC-BY 4.0 published by American Chemical Society.
Paper IV © Licensed under CC-BY 4.0 published by Elsevier.
Paper V © Licensed under CC-BY 4.0 published by American Chemical Society.
Paper VI © The Authors.
Division of Synchrotron Radiation Research Department of Physics, Faculty of Science Lund University
ISBN 978-91-8039-399-7 (electronic) 978-91-8039-400-0 (print)
Printed in Sweden by Media-Tryck, Lund University, Lund 2022
Crystals are like people; it is the defects in them which tend to make them interesting!
- Colin Humphreys.
Table of Content
Abstract ... xi
Popular science ... xiii
List of Papers ...xv
Acknowledgements ... xix
Abbreviations and symbols ... xxi
Chapter 1: Introduction ...1
Chapter 2: Low-dimensional Semiconductor Materials ...9
2.1 Semiconductor materials and their structure ...9
2.2 Low-dimensional semiconductors and their surfaces...11
2.3 III-V semiconductor nanowires and nanosheets ...14
2.3.1 Indium Arsenide (InAs) ...15
2.3.2 Indium Gallium Arsenide (InxGa1-xAs) ...16
2.3.3 Indium Arsenide and Indium Phosphide heterojunction (InAs/InP) ...17
2.3.4 Gallium Antimonide (GaSb) ...18
Chapter 3: Nano-device Fabrication and Surface Control ...21
3.1 Pattern design ...23
3.2 Surface cleaning and Spin coating ...24
3.3 Electron beam lithography & plasma cleaning ...25
3.4 Contact material deposition ...26
3.5 Nano-material transferring ...27
3.6 Atomic hydrogen cleaning ...28
3.7 ALD passivation ...29
3.8 Other sample fabrication examples ...31
3.8.1 OBIC SGM devices ...31
3.8.2 Hard X-ray nano beam combined conductive AFM samples ...32
3.8.3 Navigation patterns for synchrotron measurements ...33
3.8.4 Au 111 surface ...33
Chapter 4: Scanning Tunneling Microscopy and Spectroscopy ...35
4.1 Scanning Tunneling Microscopy...36
4.2 Scanning Tunneling Spectroscopy ...40
4.3 Instrument description ...43
4.4 STM on nano-devices ...46
Chapter 5: Combining Laser Excitation and Scanning Gate Microscopy ...49
5.1 Atomic Force Microscopy ...49
5.2 Scanning Gate Microscopy ...52
5.3 Optical Beam Induced Current ...53
5.4 Combining Lasers illumination with SPM ...54
Chapter 6: Synchrotron based X-ray Photoelectron Spectroscopy ...57
6.1 Synchrotron X-ray sources ...57
6.2 X-ray Photoelectron Spectroscopy ...58
6.3 XPS spectrum analysis ...60
6.4 Examples of XPS studies ...61
6.4.1 XPS on GaSb NWs ...61
6.4.2 Hard XPS on ferroelectric devices ...62
Chapter 7: Summary of Results ...65
7.1 InxGa1-xAs lateral nanowires studies with LT-STM/S...65
7.2 InAs/InP NW device studied with the combined laser and SGM system ...69
7.3 GaSb NWs studied with XPS ...74
7.4 A hybrid material system of 1D InAs NWs and 2D graphene ...79
7.5 Single suspended InAs nanosheet devices ...82
Chapter 8: Conclusion and Outlook ...87
References ...91
Abstract
The demand for fast and energy efficient (opto-)electronic applications needs high mobility semiconductor materials, such as InAs with a very high electron mobility and GaSb with a very high hole mobility. Beyond the material itself, also an innovative device geometry is needed, for example, the gate-all-around geometry that provides higher efficiency and electrostatic control for computational units.
Vertically or laterally grown nanowires and nanosheets are excellent candidates for realizing such beneficial device geometries. The logic operations and charge transport could be realized in different device architectures, such as the concepts of tunnel FETs instead of classical FETs or new neuromorphic hardware instead of complementary metal-oxide-semiconductor (CMOS).
With both the excellent functional properties of III-V materials and the flexibility of nanostructuring into 1D nanowires and 2D nanosheets, III-V semiconductors could be the stars for next-generation applications. For example, lateral grown InxGa1−xAs nanowires have a high spin-orbit coupling and moderate bandgap promising for quantum computing devices. GaSb nanowires are excellent high- speed p-channels for III-V CMOS, and InAs/InP nanowires have an energy barrier in the axial direction which can be used for photovoltaic and sensor applications.
Due to the high surface-to-bulk ratio of nanowires and nanosheets, their surface condition becomes the key to the device performance. In this work, III-V nanowire and nanosheet devices are studied with an emphasis on surfaces and interfaces, using a wide range of characterization methods. The dissertation explores the fabrication of novel nano-devices and the characterization of their surface chemistry, topography, electronic properties, electrical transport and interaction with photons.
The characterization techniques include scanning tunneling microscopy/
spectroscopy (STM/S) for atomic level topography and electronic properties.
Development of a Scanning gate microscopy (SGM) system with additional single- mode focused lasers for simultaniously probing influence of static and optical fields.
Synchrotron based X-ray techniques, mainly X-ray photoelectron spectroscopy (XPS) is used for evaluating surface chemistry. Surface treatment processes, e.g., ultra-high vacuum (UHV) annealing, digital etchants, atomic hydrogen cleaning, and atomic layer deposition (ALD), are applied and the resulting surface chemistry,
structure and electronic properties measured. Beyond studying the surface properties, we also investigate the device efficiency and performance down to the nanometer scale. Therefore, we perform measurements to monitor the device while the local gate and/or a focused light interact with the device.
In conclusion, in this thesis the surfaces and interfaces of low-dimensional materials for future device applications are studied using many different characterization methods. It is the hope that the thesis will assist in the progress toward novel devices and improve the energy efficiency and performance of devices. Both the method development and the results give relevant contributions opening for future quantum technologies and (opto)electronics.
Popular science
In the classic movies, watching people during world war II struggle to send letter or telegram to their family, I realized how much a video call could have helped them.
I can still remember how my dad had a huge Motorola mobile phone when I was 5- year old, a manual antenna was a fashion essential. A much simpler way of connecting people is present everywhere nowadays, due to the development and revolution of the semiconductor technology. A self-driving / auto-pilot car was also something hard to imagine when I was young, but it is realistic now thanks to new technologies. The future world will be a new adventure with new ideas everywhere, and we are taking part in it by prototyping new device concepts and novel material applications.
Semiconductor devices, like transistor and memory, are the basic functioning unit for electronic applications. Silicon is so far the most common semiconductor material and has the most developed supply chain, but the III-V semiconductors are the better candidates to high-end applications, for instance, 6G high-frequency communication and quantum computing. Furthermore, a smaller device can scale down the applications and save energies. Low dimensional nano-materials are able to confine the spatial freedom for charge carriers. For example, a one-dimensional material, e.g., nanowire (NW), can limit the electrons moving only forward or backward, which avoids electron collisions during transport that cause heat waste.
Once the device shrinks to a size in nanometer range, the surface to bulk ratio becomes very high. Therefore, the surface starts to influence the material behavior significantly, so the surfaces and interfaces of the low-dimensional material play a critical role to the device performance. In my dissertation, fabricating new type of devices and characterizing the chemical, structural, and electronic properties with synchrotron techniques and scanning probe microscopy (SPM) down to the atomic level is the main goals. This can lead to an improved understanding of the surfaces and interfaces of III-V semiconductor nanowire/nanosheet devices in relation to their function and help improve the nano-devices for a better performance.
Three main achievements of this thesis toward high technology and green future are these: I. reporting the surface morphology and electrical properties of the novel 1D III-V semiconductor device down to atomic-scale using STM/S to further solve the
interface difficulty for building quantum devices. II. Combined with synchrotron techniques for the surface components and its chemical states on the nanomaterials, we demonstrated the full oxide removal on GaSb NWs and correspondingly improved device performance of vertical GaSb NW MOSFET by surface control.
III. Energy harvesting devices are extremely important for limiting global warming and instead providing sustainable energy sources. In order to study photovoltaic devices for energetically higher efficiency, we built a high resolution laser combined scanning probe microscopy (SPM) system for studying and engineering the electrical transport properties by coherent laser light and precise local static electrical fields that can be used to study a wide-range photovoltaic devices.
By implementing different advanced characterizing techniques for developing new types of novel III-V nanomaterial devices, efforts in this thesis on the device fabrications and device characterization methods are for higher end technology, lower energy consumption, and a greener environment.
List of Papers
This doctoral thesis is based on the following papers, which will be referred to in the text by their Roman numerals.
I. Low temperature scanning tunneling microscopy and spectroscopy on laterally grown InxGa1−xAs nanowire devices
Yen-Po Liu, Lasse Södergren, S Fatemeh Mousavi, Yi Liu, Fredrik Lindelöw, Erik Lind, Rainer Timm, Anders Mikkelsen.
Applied Physics Letters, 117(16), p163101 (2020)
In this paper we present the geometric and electronic surface structures of InxGa1-xAs laterally grown nanowires and contacts using LT-STM/S.
I was the main responsible for planning of the experiment, performing the measurements, analyzing the data, and writing the manuscript.
II. Combined light excitation and Scanning Gate Microscopy on Heterostructure Nanowire Photovoltaic Devices
Yen-Po Liu, Jonatan Fast, Zhe Ren, Yang Chen, Adam Burker, Rainer Timm, Heiner Linke, Anders Mikkelsen.
In manuscript.
In this paper we present the electrical transport on a InAs/InP axial barrier NW device using LED and laser sources in combination with SGM.
I was the main responsible for planning of the experiment, building the setup, performing the measurements, analyzing the data, and writing the manuscript.
III. Optical-beam induced current in InAs/InP nanowires for hot-carrier photovoltaics
Jonatan Fast*, Yen-Po Liu*, Yang Chen, Lars Samuelson, Adam Burke, Heiner Linke, Anders Mikkelsen.
*J.F. and Y.-P.L. contributed equally.
ACS Applied Energy Materials.2022,5,7728−7734 (2022)
In this paper we present the hot carrier extraction on the InAs/InP barrier NW device using OBIC.
I was the main responsible for building the experimental setup and perform the measurements. I took part in the data analysis and writing of the manuscript.
IV. Hydrogen plasma enhanced oxide removal of GaSb surfaces and nanowires for transport device
Yen-Po Liu, Sofie Yngman, Andrea Troian, Giulio D’Acunto, Adam Jönsson, Johannes Svensson, Anders Mikkelsen, Lars-Erik Wernersson, Rainer Timm.
Applied Surface Science, 593, 153336 (2022)
In this paper we present full oxide removal from GaSb NW surfaces using effective hydrogen plasma cleaning in UHV and in ALD, as a protective high-k layer, environment studied in-situ by XPS.
I took part in the experiment planning, sample preparation and the XPS beamtime. I did the data analysis and I was the main responsible for writing the manuscript.
V. Improved Electrostatics through Digital Etch Schemes in Vertical GaSb Nanowire p-MOSFETs on Si
Zhongyunshen Zhu, Adam Jönsson, Yen-Po Liu, Johannes Svensson, Rainer Timm, and Lars-Erik Wernersson.
ACS Applied Electronic Materials. 2022, 4, 1, 531–538 (2022).
In this paper we present improved electrostatics of vertical GaSb nanowire p-channel MOSFETs by employing robust digital etch schemes, prior to high-κ deposition.
I took part and contributed to the XPS experiment and analysis, and I joined the discussion of the manuscript.
VI. Interface and Morphology Control of Graphene on InAs Surfaces and Nanowires by Annealing in Atomic Hydrogen
S. Fatemeh Mousavi, Yen-Po Liu, Giulio D’Acunto, Andrea Troian, José M. Caridad, Yuran Niu, Lin Zhu, Asmita Jash, Vidar Flodgren, Sebastian Lehmann, Kimberly A. Dick, Alexei Zakharov, Rainer Timm, Anders Mikkelsen.
Submitted to ACS Applied Nano Materials.
In this paper we present high quality morphological and chemical control of the hybrid material system of graphene and InAs NW.
I took significant part in the planning of the experiment, making the samples, joining the AFM, PEEM and XPS measurements, and discussing
Publications to which I have contributed, but are not included in this thesis:
VII. GaN Nanowires as Probes for High Resolution Atomic Force and Scanning Tunneling Microscopy
Sofie Yngman, Filip Lenrick, Yen-Po Liu, Zhe Ren, Maryam Khalilian, Lars Samuelson, Jonas Ohlsson, Dan Hessman, Rainer Timm, Anders Mikkelsen.
Review of Scientific Instruments, 90(10), p103703. (2019).
VIII. Few-cycle lightwave-driven currents in a semiconductor at high repetition rate
Fabian Langer, Yen-Po Liu, Zhe Ren, Vidar Flodgren, Chen Guo, Jan Vogelsang, Sara Mikaelsson, Ivan Sytcevich, Jan Ahrens, Anne L’Huillier, Cord L Arnold, Anders Mikkelsen.
Optica, 7(4), 276-279 (2020).
IX. Atomic Layer Deposition of Hafnium Oxide on InAs: Insight from Time-Resolved in Situ Studies
Giulio D’Acunto, Andrea Troian, Esko Kokkonen, Foqia Rehman, Yen- Po Liu, Sofie Yngman, Zhihua Yong, Sarah R McKibbin, Tamires Gallo, Erik Lind, Joachim Schnadt, Rainer Timm.
ACS Applied Electronic Materials, 2(12), p 3915-3922 (2020) X. Bismuth surface alloying on 2D InAs nanoplatelets
Sandra Benter, Yi Liu, Lassi Linnala, Chin Shen Ong, Dong Pan, Austin Irish, Yen-Po Liu, Renan Da Paixao Maciel, Jianhua Zhao, Hongqi Xu, Olle Eriksson, Rainer Timm, Anders Mikkelsen.
In manuscript.
XI. Bismuth-oxide nanoparticles: study in a beam and as deposited M.-H. Mikkelä, M.Marnauza, C. J. D. Hetherington, R. Wallenberg, E.
Mårsell, Yen-Po Liu, A. Mikkelsen, O. Björneholm, M.Tchaplyguine.
In manuscript.
Acknowledgements
The PhD life in Sweden is the best time in my life so far, and my PhD work is done with great support both technically and mentally from everyone who participated in my life. To begin with my sincere appreciation, most importantly, I am grateful for my supervisors, Anders Mikkelsen and Rainer Timm, who chose me five years ago to come to Lund and to work with great people in the very international division.
I would like to thank Anders, you are the best supervisor ever! You gave me so much freedom to do whatever experiments I enjoyed doing, and you have such adequate funding that allows me to build many lab equipments without worrying about the cost. I admire your broad knowledge, broad connections, open-minded thinking, and the way interacting with people! Talking and meeting with you always broaden my mind. For example, the non-typical annoying trapping states on InAs nanowires can be a temporal memory for neuron calculation applications. The most amazing thing is that you can turn my unexpected data into an interesting story.
Most importantly, I appreciate so much for your support in everything.
My dear co-supervisor, Rainer Timm, is not just a supervisor or a colleague; you are also my close friend that I like to share everything about my life with. Further, you are the first one I met after I came to Sweden! Traveling with you for beamtime always has many fun talks and good stories. Your trust in me since the beginning of my PhD makes me flattered, and your way of talking always makes people feel warm and pleasant. I really hope to work much more with you, not just because you helped me improve but also because you make me feel like I am important. Thanks for your well support on good science, careful reading and polishing, and even helping me search for future jobs. My gratitude for the last five years is beyond what words can describe.
My PhD cannot be done this well without my lovely colleagues. I performed my first experiment with Zhe Ren, and you are very professional in explaining everything about the Unisoku and pump-probe laser system to me. I would like to thank Yi, Andrea, Sarah, Estephania, Sofie, and Filip for working with me since the beginning of my PhD. You made me enjoy life in Sweden since then. Also for people who joined the great group after and had a good time with, Fatemeh, Austin, Vidar, and Rohit, we have very good organization and communication in our group,
you really helped me a lot. There are many people in the division that I don’t take you as colleagues, sorry, you are my best friends: Giulio, Sanna, Virgi, Sandra, Hanna, Lukas, Alfred, Stefano, Nils, Nelia, Foqia… Literally everyone in the division! Lukas, thank you for building the greenest and coziest office with me in the last five years, and you are my best badminton teammate! Besides, I want to tell Jesper that I appreciate your efficiency at work and that you can always get to the point immediately. Further, there are some essential people in the division who brought fun and make the environment relaxing; Patrik, without you I probably cannot get all the reimbursements back. I am very proud and happy to be in SLJUS.
One thing I really like about working in SLJUS is that we have so much cooperation that broadens my view. The people in EIT make the most advanced devices in the world! Johannes, Adam, Lasse, Erik, Saketh, Zhongyunshen, and Lars-Erik, the experience working with you on the big kT/q project is amazing and valuable. Also, it is quite a pleasant experience working with the solid state physics people, Heiner, Jonatan, Yang, Claes and Dan. You have the ability to dig a physics phenomenon very deeply and then make it clear.
Friends around during my PhD are very important as well! I really appreciate everyone around talking about everything, hanging out, cooking, and drinking.
These are really good memories of my life! There is a special one who joined my life from the very last part of my PhD, but make a big influence, Annika. Thank you for bringing me so unique experiences and lifestyle and taking the time to understand me.
Last but most important, my family, especially my parents and Da-Mei group, support me by holding welcoming parties with fantastic food every time when I come back and letting me feel proud of what I am doing.
Abbreviations and symbols
1D, 2D, 3D One-, two-, and three-dimensional
III–V Compound composed of one group III-element and one group V- element
AFM Atomic force microscopy ALD Atomic layer deposition CB Conduction band CCD Charge-coupled device
CMOS Complementary metal-oxide-semiconductor CPU Central processing unit
DOS Density of states
EBL Electron beam lithography EF Fermi energy
Eg Bandgap
FET Field-effect transistor FIB Focused-ion-beam
FWHM Full width at half maximum GAA Gate-all-around
HSQ Hydrogen silsesquioxane ICs Integrated circuits Iset Setpoint tunnel current LDOS Local density of states LED Light-emitting diode MBE Molecular beam epitaxy
MOSFET Metal-oxide-semiconductor field-effect transistor MOVPE Metal-organic vapor phase epitaxy
NPC Negative photo-conductance
NW Nanowire
OBIC Optical beam induced current PL Photoluminescence
PPC Positive photo-conductance
QD Quantum dot
QW Quantum well
RAM Random access memory SEM Scanning electron microscopy SGM Scanning gate microscopy
SPCM Scanning photo-current microscopy SPM Scanning probe microscopy
SPEM Scanning photoelectron microscopy STM Scanning tunneling microscopy STS Scanning tunneling spectroscopy TEM Transmission electron microscopy TFET Tunneling field-effect transistor UHV Ultra high vacuum
VB Valence band
WZ Wurtzite
XPS X-ray photoelectron spectroscopy ZB Zinc-blende
Chapter 1:
Introduction
Since the discovery of semiconductor material properties in the early 19th century, semiconductor devices have been developed, and the technology for electronics emerged in all aspects, enabling advances in communications, computing, medical healthcare, clean energy, and many other applications. In modern times, electronics are an essential part of our lives as a daily necessity, and COVID-19 pandemic made the use of information technology even bigger. Semiconductor electronic devices for information processing, usually referred to as integrated circuits (ICs) or microchips, are mainly based on silicon and produced in a mature industry. Due to the needs of modern applications for higher response frequency, efficiency, and optoelectronic applications, compound semiconductors, that is, III-V based semiconductor materials, have become of importance.
In the 1940s, the first solid state transistors were invented. These transistors have kept becoming smaller and significantly increasing the numbers on a single chip.
Moore’s law, suggested by Gordon Moore in 1965 from his perception, predicts that the number of transistors in a microchip doubles about every two years. For a long time, the industrial trend followed the law well, as shown in Figure 1-1. The process node size of a metal-oxide-semiconductor field-effect transistor (MOSFET) was 10 μm in 1971, while the most advanced manufacturing nowadays is 3 nm by TSMC in September 2022. [1] Around 2014, when the MOSFETs were down-scaled below 20 nm, the slope for Moore's law curve flattened, when thermal issues and quantum tunneling leaking started to interfere with the transport process.
Figure 1-1. Moore’s law diagram from 1970 to 2020 showing how the number of transistors doubles every other year.
Every point represents the highest transistor number in a chip die of the year. Figure courtesy from [2].
To continue the miniaturization of transistors, the geometry of transistors has changed from planar structure, as seen in Figure 1-2 (a, b), to the FinFET geometry (also called tri-gate transistor due to the triple gate sides around the channel) as shown in Figure 1-2 (c, d). FinFET took the transistor to its third dimension and extended Moore’s law. The enhanced FinFET was improved from a single-Fin structure to multiple-Fin channels, as shown in Figure 1-2 (e, f). This technique facilitates the transistor technology developed from sub-20 nm to nowadays state- of-the-art 5 nm process. In order to have even lower working bias, less thermal perturbation and higher efficiency, the gate-all-around (GAA) field-effect transistor with high-k passivation seems to further continue Moore's prediction in silicon- based electronics. The GAA geometry, as shown in Figure 1-3, increased the gate sides around the channel from three (FinFET) to four, which gain the gate field more effective.
Figure 1-2. The developing of field-effect-transistor (a) 3D image of a plain FET (b) cross-section of a plain FET (c) 3D image of a FinFET (d) cross-section of a FinFET (e) 3D image of a multiple FinFET (f) cross-section of a multiple FinFET. (a)(c)(e) are courtesy from [3].
III-V semiconductors generally have a direct bandgap, and the properties of higher electron/hole carrier mobilities and lower thermal conductivity compared to Silicon make them a great candidate for radio frequency and opto-electronic applications.
For example, it is already difficult for Si based semiconductors to support 5G communication at high radio frequency (spectrum band in the range of 1 to 6 GHz) due to the comparably lower electron mobility of Si. The needs for next generation technology require a much higher responding frequency and high-power efficiency;
therefore, a replacement of silicon is pressing. Now it is reversed, GaAs is used in the 5G RF signal receiver due to its higher electron mobility. Some III-V semiconductors have much high electron mobility to fulfill the demands for next generation communication, such as the 6G communication band in a frequency range of 100 GHz. The III–V semiconductors consist of materials from group III (e.g. In and Ga) and group V (e.g. As and P) on the periodic table. Compared to Si (the most used industrial semiconductor material), most of the III–V materials have advantages of higher electron/hole mobility, tunable bandgap sizes, customized crystal structure and strong spin-orbit coupling. [4]
Figure 1-3. Gate-all-around (GAA) field effect transistor (a) the channel structure for GAA: nanowires vs. nanosheets.
Figure courtesy from [5] (b) sketch of GAA device cross-section (c) SEM image of the cross-section of a demonstration GAA-FET. Figure courtesy from [6].
The III-V semiconductors, particularly in nanowire (NW) and nanosheet structures, have drawn most of the attention and they have the highest potential for promising future nanometer-scale applications owing to the great properties of III-V semiconductors and the well-defined crystal structure. NWs are crystallized nano- rods with diameters from less than 10 to hundreds of nanometers and lengths usually in the micrometer range. Due to the one-dimensional nano-shaped structure, confinements of electron and photon occur, which leads to unique (opto-)electric transport and thermoelectric behaviors. Therefore, the research in NWs with promising candidates, for example, III-V materials, has become a hot spot. These properties make III–V NWs optimal for high-performance electronics[7], photonics[8][9], and energy harvesting[10][11]. Not only in research, but also in industry it is urgent to develop the GAA-FET, which channels require the material to be in the form of nanowires or nanosheets. In this dissertation, these III-V nano- structured semiconductors are studied in the transistors and photovoltaics device geometry with various techniques from synchrotron based XPS to low-temperature STM to discover the surface and electrical properties and further improve their performance.
To investigate and develop the function of these excellent semiconductors, I fabricated the devices made of these nano-materials, like transistors or opto- electronic components. The fundamental concept for semiconductor devices is to control the conductivity with an external potential; for example, the FET uses a gate electrode to apply a local electric field on the channel material. Hence the current flowing through the channel depends on the gate voltage, bit 1 (current) and 0 (no current), which is how the binary unit forms. Furthermore, light with moderate photon energy (above the bandgap) has the ability to control the semiconductor as well, such as photo-detector, solar cell, and other photovoltaic products.
Semiconductor engineering includes doping to create extra states within the bandgap, material heterojunctions for building customized band engineered devices, e.g., p-n junction or potential barrier, in both axially and radially directions, mixing different material concentration for bandgap engineering and many other technical methods. Once the nano-structure can be well defined and grown in the precision of atomic layers for specific applications, (e.g. a 25 nm InP segment in a few micrometer InAs NW) the precise gate position of the device determines the device functionality and performance.
Not only the semiconductor material structure engineering, but also the interface and surface structure can play an important role, especially when the materials are scaled down and the impact from the surface gets higher. As a consequence of low- dimensional geometry, NWs and nanosheets have a considerably higher surface-to- bulk ratio, making them much more sensitive to surface effects compared to larger- scale components. Research shows that the NW device properties are greatly influenced both electronically and optically by the surface conditions[12], [13].
Therefore, the surface morphology, surface defects, surface states, and possible oxidation of the NW facets play an important role. Once the NW comes to the device fabrication steps, the surface will turn into an interface to other materials, which increases the complexity since they may vary depending on the material of the NW and the combination of the NW and the other material, for example, Al2O3, HfO2, Ti, or Al.
The surface of the nano-device plays a determinant role in the device performance.
As nano-device development become more complex with the technology demands, the fundamental understanding and characterization of the nano-materials are essential. However, the understanding of the correlation between electronic and morphologic properties of NW surfaces is inadequate, and the characterization of the surface of the NW itself and in its device geometry is not straight forward.
Advanced characterization methods can in principle characterize semiconductors, including e.g., transmission electron microscopy (TEM), scanning tunneling microscope (STM) scanning tunneling spectroscopy (STS), photoluminescence
(PL), and X-ray photoelectron spectroscopy (XPS). But they are limited regarding nano-structure dimension, surface contribution, or device geometry. The STM/S is limited to scan only on a conducting surface while all the nano-devices need an insulating substrate, the X-ray techniques are limited to beam sizes larger than the NW itself, the TEM measurement needs to have thin samples in a hundred nanometer scale for transmission which is challenging for operando devices, and the PL results show the properties contributed mainly from the bulk.
The primary goal of this work is to come beyond the obstacles, for instance, STM/S measurement of the transistor device geometry, in characterizing the surfaces of III–
V NWs and nanosheet devices in electronic, morphologic, and structural properties down to the atomic scale. In this respect, I have fabricated suspended single NW/nanosheet devices where the materials used for the top surface are all conductive, optimized for STM/S measurements of both electrical and morphologic aspects. The same technique was used to observe the lateral NWs used in quantum devices. Further, I developed the laser combined scanning gate microscopy (SGM) to study hot electron dynamics and electrical transport of InAs/InP NW devices with mobile gate precision down to the nanometer scale. The chemical composition of NW surfaces was studied using X-ray photoelectron spectroscopy (XPS) and scanning photoelectron microscopy (SPEM), which are capable of detecting elements and chemical compounds for homogeneous surfaces and nanometer scale structures, respectively.
Outline of the thesis
This dissertation includes the core topics of novel nano-material, NW, and nanosheet based devices. It covers the III-V NWs for next generation GAA MOSFET, ALD for high-k passivation around the FET channel, and other scientific issues for future electronics. We investigated electrical devices during operation down to atomic scale at low-temperature, studied the electrical transport under the mobile local gate combined with laser/LED illumination, and characterized its surface chemistry. In Chapter 2, the semiconductor materials, their surface crystal structure, and the nano-structure will be introduced. These novel nano-materials need to be fabricated into devices to make them functioning. The fabrication process and details for different characterization techniques will be described in Chapter 3.
Since the materials are scaled down to one-dimensional (1D, NW) or two- dimensional (2D, nanosheet and graphene) structures, the surface-to-bulk ratio becomes tremendous. To see the surface with high resolution, we use STM to investigate the surface down to the atomic scale and use STS to study the local surface electrical properties. The STM and STS techniques are presented in Chapter 4. While operating devices are sensitive to electric fields and the light conditions,
electron studies. The system and its abilities are introduced in Chapter 5. Apart from the atomic scale topography and the surface band structure, also the surface chemistry, which is still missing, has high impact on the device performance.
Therefore, we use synchrotron-based XPS to probe into the issue, as presented in Chapter 6. Data from the semiconductor nano-materials and devices measured by the above mentioned techniques will be shown in Chapter 7.
The results of this dissertation show the surface morphology, the effectiveness of the cleaning, and the elemental composition along the NW resulting in local bandgap changes of lateral InxGa1−xAs NWs using low-temperature STM/S in Paper I. The surface of GaSb NWs and different treatments to improve their interface quality, on the other hand, were studied by XPS. Here we demonstrate full oxide removal on the GaSb surfaces in UHV and that the NWs are cleaned faster and more efficiently than planar substrates. Cleaning suggestions with pre-treatment and surface protection for scalable fabrication are suggested. (Paper IV) The relevance of surface treatments also became relevant for vertical GaSb NW MOSFETs, which after improved removal of the Sb-oxides, proved by XPS, reach an improved state- of-the-art subthreshold swing value. (Paper V)
In order to study carrier transport in devices with nanometer precision heterojunctions, characterization techniques with especially high spatial resolution are required. InAs/InP NW photovoltaic devices include such nm-scale heterojunctions, where OBIC demonstrates hot-electron extraction across the InP segment, thus generating electrical power. (Paper III) With the SGM combined with LED/laser excitation, setup, interactive effects of photon-excitation and local band alignment contributing to the device electron transport are studied. The demonstrated setup has significant advantages to study optoelectronics. (Paper II) New types of future devices may require hybrid integration of one-dimensional, i.e., III-V NWs, and two-dimensional, i.e., graphene, nanostructures, combining their excellent complementary properties. Paper VI affirms high quality morphological and chemical control of this hybrid material system.
Chapter 2:
Low-dimensional
Semiconductor Materials
As technology develops, the size of electronics scales down and new semiconductor materials could be introduced. The material and the structure of semiconductors to the atomic scale become central for future technology. In this chapter, semiconductor materials and their structure are introduced in section 2.1. The geometry of low dimensional semiconductors and their surfaces are discussed in section 2.2, and the semiconductor materials used in this dissertation are presented in section 2.3.
2.1 Semiconductor materials and their structure
A semiconductor is a material with electrical properties between a conductor and an insulator with a moderate bandgap, which is the area between the bottom of the unoccupied conduction band and the top of the occupied valence band where there are no electronic states. Thanks to the appropriate bandgap, the semiconductor conductivity can be controlled by introduction of impurities, doping, and devices operated with some assistance from a small external electrical field, gating. Thus one can control the transport properties of the materials for various applications.
The bandgap of semiconductors makes it possible to interact with photons of specific energies, both emitting and absorbing in the visible range. Usually, the semiconductor is defined with a bandgap larger than 0eV and below 3 eV. For instance, the bandgap energies of the most common semiconductors are 1.1 eV for silicon, 0.4 eV for InAs, and 1.3 eV for InP at room temperature. [14] An exception is Nitride semiconductors with a high bandgap, for example, GaN with a 3.49 eV bandgap is classified as a semiconductor, and it is famous for high power communication devices and blue LEDs.
The most common semiconductor in our daily used technologies is silicon. It is earth abundant, and the fabrication procedure is very well-developed in industry.
Commercial electronics, like the central processing unit (CPU) of a computer consisting of billions of transistors (there are 16 billion transistors on Apple M1 chip[15]), random access memory (RAM), and sensors, are silicon-based. Since Si is a group IV material, it is convenient to process with doping for p-n junction for wide range applications. However, higher operational speed and higher efficiency/power are needed as technology develops, and the properties of many III- V semiconductors fit the requirements. Most III-V semiconductors have a direct bandgap which is needed for optoelectronics, and some have strong spin-orbit coupling needed for quantum technologies. The III-V semiconductor materials are important in both research and industry due to the need for high speed and low consumption for modern electronics.
Applications in broad fields can be achieved by engineering of the electrical properties, such as p/n-doping and heterojunctions, and the fabrication geometry of semiconductors can be engineered. Doping variation in the semiconductors grants the material with spatial defined heterostructures structures, for example, p-n junctions. The fundamental of doping is to intentionally introduce specific impurities into a semiconductor crystal to modify the conductivity caused by externally implemented electrons or holes. Doping is a very matured and widely used process in the silicon-based semiconductor industry, for example, B, In, and Ga are used as p-type dopants; while P, As, Sb and Li are used as p-type dopants, for products, like CMOS, photodetector, LED and solar cell. The doping techniques can be well applied to the growth of III-V NWs, creating the functions in the nanometer scale.
Figure 2-1. The unit cell schematic views of InAs in (a) ZB and (b) WZ crystals using software VESTA. The difference in stacking sequence (ABC or AB) is seen for both structures. The purple spheres represent for group III atoms, i.e. In, and the green ones, i.e. As, denote for group V-atoms.
The structure of the semiconductor nanomaterials has impact on their band structures and, therefore, varies their optical and electronic properties. Most III-V materials, except the nitrides, occur naturally only in the cubic zinc-blende (ZB) crystal structure, which has a stacking …ABCABC… of hexagonal layers along the crystal [111] direction, as shown in Figure 2-1 (a). The hexagonal wurtzite (WZ) structure, with stacking of …ABABAB… as shown in Figure 2-1 (b), has instead been found more often in NWs[16]. The low-dimensional materials have large surface-to-bulk ratio, and different surface facets could result in a different surface status, e.g., surface oxidation and surface reconstruction. The surface, incorporating differently with other materials, would be an interface in device geometries affecting the device properties, and will be discussed in the next section.
2.2 Low-dimensional semiconductors and their surfaces
Nano-material science has been developed for several decades. The low dimensional materials, like one-dimensional NWs or two-dimensional nanosheets, have unique and different properties as compared to the bulk. For example, monolayer graphene shows Dirac points in its band structure and has extraordinary mechanical and electrical properties, but not in multi-layer graphene or bulk graphite.[17], [18] Due to the confined and guided photon and electron transport, the low-dimensional semiconductor materials have also helped extending the understanding of fundamental optical, structural, or electrical properties.
NWs define their transport function in large part due to the confinement of electrons and holes in space. The significant control in two dimensions benefits the future electronic devices, for instance, GAA transistors. The size and geometry of the NWs can be customized by the growth mechanism and parameters, which allows for band structure engineering by combining different materials and crystal structures, axially or radially. One of the large advantages of NWs is that they have minimal effects from strain so that a rather large lattice constant mismatch without dislocations is possible, due to their small footprint. This for example allow the growth of III-V NWs on silicon or integration of very lattice strained combinations III-V materials. Further, III-V NWs can be grown in crystal structures that were previously unavailable in bulk, such as the hexagonal WZ structure. In this thesis, all the nano-materials studied are either NWs (30-100 nm diameter for III-V semiconductors with length a couple of micrometers) or nanosheets (10 nm thickness for InAs with an area of around 3 μm2).
There are two distinct types of III-V NWs studied in this dissertation: vertically grown NWs or laterally grown. The vertically grown NWs in this thesis are grown in the ZB structure with side facets typically {110} or {111}A/B twin plane facets, or WZ structure with typically {112�0}side facet.[4], [19]–[21]For laterally grown NWs, the top facet of the NW is in surface direction (001), comparable to the side facet of vertically grown NWs. The angle between the NW (001) top facet and its side facets amounts to ~45 degrees, indicating that the side facets consist of {011}
surface planes.
The III-V NWs in this thesis are mostly grown epitaxially on crystalline substrates using Au particles, except for the laterally grown InxGa1-xAs NWs of Paper I. The epitaxially grown III-V NWs have been found to prefer to grow in the [111�����]
direction and are usually grown on (111)B substrates so that they grow perpendicular to the growth substrate. Here is an example of the growth procedure:
We first expose the desired size for Au seeds using electron beam lithography (EBL) on a growth substrate and then deposit Au, Figure 2-2 (a). After lift-off, the substrate with Au particles is inserted into a metal-organic vapor phase epitaxy (MOVPE) growth chamber. Second, the temperature is increased under group V precursor flow in order to alloy the Au-particle with the substrate and to remove oxide residues and contaminants on the substrate, see Figure 2-2 (b). To initiate the growth, the temperature is reduced so that nucleation only occurs under the Au-particle (and not on the substrate), typically to 400-600 °C. The group III material is then thought to enter the Au-particle and supersaturate it, see Figure 2-2 (c). At the interface in between the vapor, the Au-group-III alloy, and the substrate, growth material precipitates into a nucleus which rapidly grows and forms a new layer of crystal directly beneath the Au-particle. A single crystalline NW with diameter set by the Au-particle and the length corresponding to the growth time would then be grown, as shown in Figure 2-2 (d). The growth of NWs is an epitaxial process, meaning that the crystal structure of the growth substrate continues into the NW.
Figure 2-2. Epitaxial III-V NW growth. (a) Size selected Au particles are deposited on a growth substrate using EBL.
(b) The sample is annealed under group-V flow to allow the Au-particle to alloy with the substrate and for removal of surface oxides/contaminants. (c) Temperature is lowered and group III-precursor is introduced. III–V materials precipitate directly under the Au-particle. (d) After growth the vertical NW still resides with the Au-alloy on top.
Like the crystal structures discussed above, also the surfaces differ depending on the facet terminations. NW growth control to achieve different surface facets is possible, as an example of a WZ-ZB InAs NW in Figure 2-3, and the surface facets have an impact on the band structure. [19], [22]. The electronic structure of a material can be altered by the surface states around the Fermi level. Surface states located within the fundamental bandgap can be detrimental to the performance of semiconductor devices where they can act as unwanted recombination centers for charge carriers or change band alignment at a heterojunction via Fermi level pinning[23]. The surface states within the bandgap can be seen in the STS measurements, as will be discussed later. In the case of GaAs and InAs NWs, there are no intrinsic surface states located within the bandgap for non-polar {110} and {11-20} surface facets[23]. However, recent publications show that the surface states in the conduction band can trap the free carriers, thus also influencing the device performance[19,20], and it has been proven that the trapped electrons are possible to be de-trapped back into the NW again as free electrons to improve the conductivity.[20], [25] This effect is observed on both plain InAs NW and nanosheet[26] devices under laser and LED lamp illuminations. The surface state trapping situation can be complex giving either positive photo-conductance (PPC) or negative photo-conductance (NPC) depending on the light intensity. More discussions will be in Chapter 7. Further, surface oxides and defects, such as vacancies, atomic steps, adsorbates, and material interfaces, can potentially cause surface states; therefore, the surface condition and proper surface passivation[27]
play important roles in device properties.
Figure 2-3. STM results on a WZ-ZB InAs NW from Reference [19]. (a) Overview image of a {11-20}-{110}-type WZ- ZB interface on a NW. Vsample = -1.0 V, IT = 50 pA. (b) Micrograph depicting As atoms on part of a rotationally twinned {110} facet. Vsample = -2.2 V, IT = 100 pA. (c) Atomic arrangement on the {11-20} facet. Vsample = -2.3 V, IT = 160 pA. (d) Atomically sharp interface between {110} and {11-20} facets. Vsample = -2.5 V, IT = 100 pA.
2.3 III-V semiconductor nanowires and nanosheets
III-V semiconductors are the compounds made of group-III materials (with 3 valence electrons), e.g. Ga and In, and group-V materials, e.g. P, As, and Sb, on the periodic table. They are relevant for the next generation semiconductor technology because of the higher flexibility in engineering the crystal structure and its electrical properties compared to the most popular semiconductor nowadays, silicon. III–V semiconductor NWs have demonstrated significant promise for applications in (opto)electronics and quantum computing. The properties for nanostructured III-V can be quite different to the bulk material, for example, the InAs NWs have superb electrical conductivity in contrast to the bulk substrate due to the free electrons at the surface caused by surface band bending.
In the following sections, the main III-V materials used in this work will be introduced starting from the high electron mobility material InAs for n-channel in section 2.4.1 to high hole mobility GaSb for p-channel in section 2.4.4. Also, the lateral InxGa1-xAs NW for quantum computing will be presented in section 2.4.2 while Indium Arsenide and Indium Phosphide heterojunction (InAs/InP) NW for photovoltaic applications in section 2.4.3. The NW growth is supported by our cooperators in Lund.
2.3.1 Indium Arsenide (InAs)
InAs promotes superior device performance due to its high electron mobility and direct bandgap of 0.35 eV at room temperature[28], and it is widely researched in the fields of transistors[29]–[33], photovoltaics[34], and terahertz laser[35], [36].
Quantum dots and quantum computing bits are demonstrated with low-dimensional InAs materials.[37] Devices such as gate-all-around (GAA) NW metal-oxide- semiconductor capacitors and field-effect transistors (FET) have been realized for InAs and InGaAs NWs. In this dissertation, both InAs NWs and nanosheets are used for single suspended nano-devices, as shown in Figure 2-4 (a) and (b), respectively.
The device fabrication and its geometry are described in chapter 3.
The InAs NWs, used in Paper VI, are grown using low pressure MOVPE on InAs
<111>B substrates with Au aerosol particles with diameters around 30 nm acting as seeds for the growth of the NWs. A close coupled showerhead AIXTRON 3x2"
system was used. The growth process was initiated by annealing the aerosol-covered growth substrate for 10 minutes in an AsH3/H2 at 550°C. After setting a growth temperature of 470°C, a short stem and alternating WZ and ZB segments were grown. NW growth was terminated by cutting the precusors supply and cooling under the same AsH3/H2 ambience as used for the annealing down to 300°C. The diameter for the used NWs is 30 nm with a length of around 2 μm, as shown in Figure 2-4 (a), consisting of both WZ and ZB segments.
The InAs nanosheets used in this work were grown on p-type Si (111) substrates in a molecular-beam epitaxy (MBE) system using silver as seed particles. The quality of the nanosheets is highly dependent on the growth temperature[38], and high quality samples are grown at a relatively high temperature at 525 °C for 40 min with the V/III beam equivalent pressure ratio being set at 6.3 to achieve a reasonable density for the micro-manipulator to pick up a single nanosheet at once – a process which will be discussed in section 3.5. The indium flux here determines the dimensional tunability to be 1D or 2D structure. As soon as the indium-rich growth condition was reached, the silver−indium alloy droplets start segregation, and the morphology of InAs evolved from 1D NW to 2D nanosheet gradually due to the anisotropical growth caused by catalyst alloy segregation. Due to the high indium flux, high-density and large-size free-standing 2D InAs nanosheets were acquired and the structure is mixed with WZ and ZB phases[26].
Figure 2-4. (a) InAs NWs of growth run number 3110 CCS with a diameter of 30 nm on the growth substrate. The white scale bar is 1 um. (b) InAs nanosheets on growth sample. The orange scale bar is 2 μm.
2.3.2 Indium Gallium Arsenide (In
xGa
1-xAs)
As for InAs, an alloy of InAs with gallium arsenide (GaAs) forms indium gallium arsenide (InxGa1-xAs) - a material with a bandgap dependent on the concentration ratio of the In/Ga components. The bulk lattice constants of InAs and GaAs are 6.06 Å and 5.65 Å, respectively, which is within the lattice mismatch tolerance and close enough to form an alloy. The bandgap of the InxGa1-xAs almost linearly changes from that of InAs, around 0.35 eV at room temperature, to that of GaAs, about 1.4 eV, according to the In/Ga ratio.[39]
The laterally grown InxGa1-xAs NWs, which are described in Paper I, are relevant for radio frequency and quantum computing applications. The InxGa1-xAs NW devices were selectively grown in a lateral growth approach on a semi-insulating InP:Fe (001) substrate by MOVPE. The process starts from electron beam lithography (EBL) to define hydrogen silsesquioxane (HSQ) lines aligned to [100]
with a spacing of 50 nm, which ultimately would be the width of the NWs. After defining the HSQ patterns by EBL, a 13 nm In0.63Ga0.37As is grown on all areas that are not covered by HSQ. The NW facets are defined by [001] top-surface and {011}
sidewalls. The composition and thickness of the 2D layer were confirmed by X-ray diffraction, however, due to different growth kinetics close to the small feature of the HSQ mask, the NWs are expected to have a lower Ga content[40]. After the growth of the 2D layer including the lateral NWs, a following process for forming the contacts begins with a second HSQ exposure with lines aligned in the [110]
direction, covering the NWs. A second growth step of ~25 nm Sn doped In0.63Ga0.37As contacts (ND = 5x1019 cm-3) was then performed. Due to the 45°
rotation relative to the NWs, the contacts are defined by {111}B facets. With such a specialized sample, we aim to understand the surface morphology and electrical
Figure 2-5. Lateral InxGa1-xAs NW device schematics: (a) SEM image of the laterally grown NW sample with Ti markers for STM navigation. The length of the white scale bar is 200 μm. The inset shows the zoomed in image from the yellow rectangle, where the NWs are grown. The length of the pink scale bar is 500 nm. (b) Top view illustration of the NW sample design and material. x=0.63 for the composition of the contact material, while x is higher in the NW material.
(c) Cross-sectional schematic of the NWs and contacts. The dashed lines show where the NWs end.
2.3.3 Indium Arsenide and Indium Phosphide heterojunction (InAs/InP)
Heterostructures consisting of InAs NW s with InP segments have shown to produce a photocurrent under optical illumination with a higher open circuit voltage than the Shockley-Queisser limit for a corresponding bulk InAs photovoltaic device.[41]
The observed high photovoltage is believed to be generated by hot electrons diffusing over the InP energy barrier with a higher bandgap. An InAs NW with a diameter of about 50 nm and a length of 2 µm, embedded with an InP segment located roughly at the center in axial direction, was studied. The length of the InP segment is chosen to be long enough to rule out tunneling but shorter than expected relaxation lengths, and it is around 25 nm. It results in a potential barrier of 0.56 eV and 0.38 eV in the conduction and valence band, respectively, as shown in Figure 2-6 (b). Growth is done by chemical beam epitaxy using gold seed particles deposited on an InAs (111)B surface; all segments are of WZ crystal structure. High crystalline quality with few defects is expected, except for some stacking faults in the growth direction, and the samples are weakly n-type.
Figure 2-6. (a) SEM image of an InAs NW with an InP segment in a device configuration. (b)The graphic sketch and the band diagram of the InAs/InP NW are labeled with its dimension.
2.3.4 Gallium Antimonide (GaSb)
In contrast to the high electron mobility material InAs, the high hole mobility material GaSb makes the material of choice for p-channel conductivity. Fully NW- based complementary metal-oxide-semiconductor (CMOS) transistors have been realized using InAs and GaSb NWs monolithically integrated on Si[42]. Another highly promising approach towards novel NW-based devices consists of InAs-GaSb NW tunneling field-effect transistors (TFET)[43], which recently have demonstrated steep slope behavior and high current densities for 10 nm thin NWs[43].
The growth of the GaSb NWs starts with the same procedure as described in section 2.2, using EBL to pattern arrays of Au particles as seeds for the NW growth on Si(111) substrates with a 250 nm highly doped InAs layer on top. Then, InAs-GaSb NWs were grown from the Au seeds using MOVPE in an Aixtron CCS reactor. A short InAs segment was grown first, and this InAs stem is required because the nucleation of GaSb directly on the substrate surface is challenging[44]. The GaSb segment was grown on top of the InAs stem. The NWs grown by our cooperators obtain a diameter of about 50 nm and a length of around 1.55 µm.
Figure 2-7.(a) SEM image of the NW growth sample. The white scale bar is 500 nm. (b) A schematic diagram of the grown GaSb NW.
Chapter 3:
Nano-device Fabrication and Surface Control
Nanoscale semiconductor fabrication is the key to advancements in modern technology, e.g., self-driving cars, 6G communications, and artificial intelligence.
A transistor is the fundamental device used in the logic and calculating, and its dimension has been scaled down following Moore's Law in the past decades. In the most advanced modern foundries, companies like Intel handles both advanced IC design and manufacturing, Taiwan semiconductor manufacturing company (TSMC) currently produces 92% of the world’s most advanced chips (5 nm node technology) in 2021[45], [46], [47], and Samsung leads in the dynamic random access memory (DRAM) industry[48]. Furthermore, new types of devices are released from the latest research; for instance, Microsoft is developing quantum computers with combined fabrication techniques of semiconductors and superconductors[49], in which the new and advanced fabrication methods play an important role.
The present work is centered on low dimensional nano-devices, including 2D InAs nanosheets and 1D III-V NWs, investigating the surfaces, interfaces, and electrical and optical properties with the long term aim for applications such as transistors, quantum computers and photovoltaic devices. The device fabrications typically include basic procedures, like material transfer, layout design, chemical processes, lithography, metal deposition, and lift-off. The specific processing methods and order of these can be different depending on the type of sample desired. Among many fabrication procedures used, I would like to emphasize on the devices for STM measurement which display many of the involved methods. For this type of device, the sample has to be conductive everywhere on the top over the whole sample, as shown in Fig 3-1, to allow the STM scanning (as will be discussed in Chapter 4.1).
In this case, the nanomaterials are suspended across the two contact electrodes, which can rule out the interface effects between the material surface and the substrate. It is worth mentioning that not many experimental methods can characterize and observe the surface of operating semiconductor devices down to the atomic scale. For example, TEM gives averaging atomic resolution along a
crystal direction but not surface information, also, it requires a nanometer thin sample to let the transmitting electron pass through. Further processing, such as, focused ion beam (FIB) cutting, could thin down or give a cross section of the devices, but it would also change the pristine status of the sample surface and make the devices non-functioning.
The entire fabrication procedures of the STM devices follow pattern design, surface cleaning, photoresist spin coating, electron beam lithography, plasma cleaning, contact material deposition, and material transfer. The illustrations of the whole procedure are shown below in Fig 3-2.
Figure 3-1. Sketch graph of the single suspended NW device for STM measurement (a) top view of the device showing that the whole surface of the sample can be conductive (b) a 3D view of the device showing that the SiO2 underneath the metal contacts isolates the device from the Si substrate.
Figure 3-2. The device fabrication procedure for STM measurement (a) cleaning the Si wafer with IPA and acetone in an ultrasonic bath (b) spin-coating the photoresist, PMMA, on (c) exposing the designed pattern layout by electron beam lithography (d) developing the exposed PMMA in MIBK:IPA (methyl isobutyl ketone:isopropanol)=1:3 (e) depositing
3.1 Pattern design
The software Klayout is used to design a lithographic mask pattern. It has integrated functions for layout patterns and supports numerous image files, includingGDSII;
which is the primary file format used by Raith, the lithography software used in the EBL systems in the lab. For a semiconductor device, at least two electrical contacts are needed for the source and drain. Each set of contact patterns, as shown in Figure 3-4(a), contains two large pads for wire bonding (for external contacts) and long horizontal lines toward the fine structure gap, where the center of Figure 3-3(b) or Figure 3-4(c) is, for placing the material. Some small features as markers, i.e., stripes with width of two hundred nanometers and length of a few micrometers (see Figure 3-3(a)) are patterned to provide us the actual position of the tip related to the device, which makes the navigation before the STM measurement easier. In my design as shown in Figure 3-4(a), the long horizontal lines have different widths, for example, the initial width of the horizontal electrodes nearest to the bond pads is 20 μm, which tapers off to a width of 10 μm when it is 100 μm away from the gap for the nanomaterial in the x-axis, which might still be visible by the microscope to the CCD camera. The width of the finest horizontal line is only 5 μm, which is within the maximum STM scanning range. The width differences can benefit for the STM navigation. Once we come to the end of the horizontal contact, the opposite side to the bonding pad, the vertical contacts are leading to where the nano-material is placed, with width from 4 μm at the connection to the horizontal contact smoothly shrinking to 2 um wide at the trench. Hence, one can tell the direction to the nano- material by the width change. The nano-material would be there at the trench, so then we are at the device. The descriptions above are for one set of the device electrodes, and I usually put 5 sets of the electrode on one substrate, as shown in Figure 3-4 (a) and (b), so if one device failed, I don’t need to take everything out from the UHV chamber, wire-bond new devices, pump to UHV and clean the surface again.
It is worth mentioning that all the surfaces features must be able to conduct a current, in order to scan/navigate with the STM tip. Otherwise, the STM cannot detect the tunneling current, and then the feedback loop would push the tip crashing into the sample. There is a failure example in Figure 3-3 (a), a thin stripe aside the contact electrode could give a hint that the tip is on the top electrode to the material. Vice versa, if one sees two stripes on the sides in STM image, the tip at the bottom part of the nanomaterial. However, the nicely-looking thin fingers for navigation cannot be biased, since they are not connected to any electrical pad. That means the potential of the stripes is floating and they cannot create a current loop for tunneling mechanism. As a result, the tip would scratch through the thin features if they are scanned over, instead of telling a relative position. The SEM image of the device
