Micro-Power Inverter-Based Continuous-Time Sigma-Delta Modulator for Biosensor Applications

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IN

STOCKHOLM, SWEDEN 2014

Micro-Power Inverter-Based Continuous-Time Sigma-Delta

Modulator for Biosensor Applications

JIAZUO CHI

KTH ROYAL INSTITUTE OF TECHNOLOGY

INFORMATION AND COMMUNICAION TECHNOLOGY

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Micro-Power Inverter-Based

Continuous-Time Sigma-Delta Modulator for Biosensor Applications

JIAZUO CHI

Stockholm 2014 Master Thesis

School of Information and Communication Technology

Kungliga Tekniska H¨ ogskolan

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Abstract

Biosensor applications have made promising progress during the last decade, presenting potentials and challenges at the same time. Meanwhile, digital signal processing (DSP) has become even more powerful than before, due to Moore’s Law. Bridging the biosensor applications and the digital circuits, analog-to- digital converters (ADCs) are a critical block that influences the performance of the entire system, in terms of speed, accuracy and power. Particularly, incremental Σ∆ (IΣ∆) ADCs have recently received increasing research interest because of their high-resolution feature and the ability to time-multiplex different channels of input signals, making them especially suitable for neuroscience studies and brain-computer-interface (BCI). However, IΣ∆ ADCs are less power-efficient than traditional Σ∆ ADCs.

To improve the power efficiency and reduce the chip size, an inverter-based continuous-time (CT) Sigma-Delta (Σ∆) modulator is proposed, to be inte- grated in a two-step I(Σ∆) ADC previously designed. Inverter-based operational transconductance amplifiers (OTA) have recently demonstrated their high power efficiency in multiple Σ∆ modulators, most of which are discrete- time (DT) implementation. CT implementation is investigated in this thesis for the possibility to further reduce power consumption, due to its more relaxed requirements on bandwidth and settling compared to the DT counterpart. In the circuit implementation of the modulator, fully-differential topology is used in inverter-based CT Σ∆ ADCs for the first time. Compared to pseudo-differential topology, fully-differential topology has more precise control on the operating point and the quiescent power.

The post-layout simulation result shows that the modulator achieves a peak SNDR of 58.1 dB, and a dynamic range of 65.9 dB. The entire modulator consumes 1.28 µW from a 1.2 V supply voltage, on a chip area of only 0.07 mm². This corresponds to a FoM of 243 fJ/(conv. step).

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Acknowledgment

First of all, I would like to thank my supervisor and examiner, Prof. Ana Rusu, for providing me with an opportunity to work on this research project. As a beginner, such an opportunity is all one can hope for, and would be deeply cher- ished by me. I appreciate your guidance and supervision, and have benefited a lot from the countless useful feedbacks that you gave me. The two courses that you offered have helped me so much during this thesis.

Next, I would like to express my sincere gratitude to Ms. Sha Tao, my daily supervisor, who has guided me through the entire project. Thank you for your kind assistance and patient explanation on your design, from system-level down to its circuit implementation. Thank you for the discussion with me on my circuits, for the technical supports and for helping me write this thesis. Thanks to you, I have learned a lot during my thesis.

I wish to thank all other group members as well, Dr. Saul Rodriguesz Due- nas, Ms. Tingsu Chen, Mr. Janko Katic, Dr. Ayobami Iji, Mr. Nikola Ivanisevic, and Mr. Mohammad Waqar Hussain. Thank you for providing generous help throughout my thesis. I couldn’t have done it without you.

A big thanks goes to my colleagues and friends at ICT school, particularly, Mr. Babak Taghavi, Mr. Jia Mao, Mr. Saleh Kargarrazi, Mr. Ye Tian, Mr. Maziar Naiini, Ms. Gunilla Gabrielsson, and Ms. May-Britt Eklund Lars- son. I would also like to express my gratitude towards my friends who sup- ported me a lot during my thesis, Mr. Ruitong Wang, Ms. Wen ”Sharon” Sun, Mr. Yang Yu, Mr. Peiyue Zhao, Mr. Chang Gao, Mrs. Xia Xin, Mr. Kenji Kjellsson, Ms. Sandra Trankell, Ms. Ulrika ”Ullis” Rangmark, Mr. Tianshu ”B”

Gu, Mr. Yiting Xu, Mr. Chang Liu, Mr. Chencheng Zhang, Mr. Chao Wang, Mr. Ke Ma, Ms. Anja Djuric, Mr. Weiyan Shao, Mr. Wei Zhang, Mr. Jiabing Guo, Mr. Jiannan Guo, Mr. Yongchao Wu, and a lot more friends, whose names will not be mentioned here, but whose help and support is deeply appreciated. A special thanks goes to Mr. Jianbo ”Double Happiness” Zhang, who has helped me a lot in understanding Σ∆ ADCs and taught me so much more.

Last but certainly not the least, I would like to thank my family for their love and affection that keep me warm not only during this thesis, but throughout my entire humble life. To my mother, without your unconditional love and support, I would have no idea who I am right now. Thank you for molding my character, paving my path, correcting my direction, and encouraging me to pursue my dream.

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List of Figures

1.1 ADC Performance Survey 1997-2014 [1] . . . . 1

1.2 A simplified diagram of BCI . . . . 2

2.1 Oversampling ADC with noise-shaping (Σ∆ ADC) . . . . 10

2.2 Σ∆ ADC linear model block diagram . . . . 10

2.3 Two-step CT IΣ∆ ADC for multi-channel applications . . . . 13

2.4 2nd-order CT Σ∆ modulator in CIFF topology . . . . 14

3.1 An inverter-based OTA . . . . 15

3.2 VTC of an inverter with 1.2 V and 0.8V supply voltages, respectively . . . . 16

3.3 Integrator with inverter-based OTA biased using auto-zeroing . . 19

3.4 Sampling phase of SC integrator with inverter-based OTA . . . . 19

3.5 Transfer phase of SC integrator with inverter-based OTA . . . . 20

3.6 Inverter-based OTA with LDO-defined supply voltage . . . . 21

3.7 A bulk-input amplifier with gate used for CMFB . . . . 22

3.8 Integrator with negative resistance to boost DC-gain . . . . 23

4.1 Current mirror biased fully-differential inverter-based OTA . . . 26

4.2 RC integrator with a finite DC gain OpAmp . . . . 27

4.3 Bode plots for non-ideal and ideal integrators . . . . 28

4.4 CT CMFB circuit with capacitive input impedance . . . . 32

4.5 Low-supply-voltage current mirror . . . . 34

4.6 Layout of the 2nd-order CT Σ∆ modulator . . . . 36

5.1 Bode plot of the inverter-based OTA biased with 0.5 µA . . . . . 37

5.2 2nd-order Σ∆ with distortion induced by two stages . . . . 39

5.3 Noise simulation result on the first integrator . . . . 40

5.4 Input-referred noise spectral density of the first integrator . . . . 41

5.5 PSD plot for -5 dBFS input at 1 kHz . . . . 42

5.6 SNDR versus input signal amplitude at 1 kHz . . . . 42

5.7 Monte-Carlo simulation result with post-layout extraction . . . . 43

vii

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List of Tables

1.1 Specifications for an inverter-based 2nd-order CT Σ∆ ADC . . . 3 2.1 Coefficients values for 2nd-order modulator in Figure 2.4 . . . . . 14 5.1 Performance metrics of the inverter-based OTA . . . . 38 5.2 Performance comparison with state-of-the-art inverter-based de-

signs . . . . 43 5.3 Monte-Carlo simulation result with post-layout extraction . . . . 43

ix

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Acronyms

Σ∆ Sigma-Delta

ADC analog-to-digital converter BCI brain-computer interface

CIFF cascade-of-integrators feedforward CMFB common-mode feedback

CMOS complementary metal-oxide-silicon CT continuous-time

DAC digital-to-analog converter DSP digital signal processing

dB decibel

dBFS dB relative to full-scale input DR dynamic range

DT discrete-time ECoG electrocorticography EEG electroencephalography ENOB effective number of bits FoM figure of merit

GBW gain-bandwidth product IΣ∆ incremental Σ∆

IBN in-band noise

IIT impulse invariant transformation LDO low-dropout regulator

NTF noise transfer function OpAmp operational amplifier OSR oversampling ratio

OTA operational transconductance amplifier PSD power spectral density

RMS root mean square SC switch capacitor

SNDR signal-to-noise and distortion ratio SQNR signal-to-quantization noise ratio

SR slew rate

STF signal transfer function VTC voltage transfer curve

xi

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Chapter 1

Introduction

1.1 Background

Recently, biosensor applications have emerged as a tool for quick and convenient detection of human health condition [2], and even a complex system to help people with devastating conditions to restore their ability to see [3], smell [4], and act [5]. The fast advancement of these applications goes hand-in-hand with the powerful digital signal processing (DSP), which directly benefit from the scaling of modern semiconductor technology [6]. In such systems, analog-to-digital converter (ADC) is a critical constituent of virtually all biosensor applications, and significantly influences the precision, speed and power of the overall systems. The state-of-the-art of ADCs is shown in Figure 1.1. It can be seen that designing power-efficient ADCs with a bandwidth of several kilohertz that suits biosensor applications remains a challenging research topic.

5.E-01 5.E+00 5.E+01 5.E+02 5.E+03 5.E+04

1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 1.E+10 1.E+11 FOMW,hf[fJ/conv-step]

f_snyq[Hz]

ISSCC 2014 VLSI 2014 ISSCC 1997-2013 VLSI 1997-2013 Envelope

Figure 1.1: ADC Performance Survey 1997-2014 [1]

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2 Introduction

A particular interesting biosensor application is brain-computer-interface (BCI), also referred to as brain-machine-interface (BMI), which enables humans or animals to control external actuators through their brains, as illustrated in Figure 1.2. BCI researches aim not only to help some people to rebuild a con- nection to their lost senses and motion abilities, but also to provide valuable insight into how microscopic neurons interact with each other to initiate macro- scopic human behaviors [7].

Feedback Electrode recording

Extraction algorithm

Actuator

Figure 1.2: A simplified diagram of BCI

BCI starts with recording neural activities through electrode arrays. The recording can either be carried out through electroencephalography (EEG), which is a noninvasive method that place the electrode arrays directly on the scalp, or through electrocorticography (ECoG), which places the arrays on the cortical surface and requires a surgery [9]. ECoG is particularly attractive because it has better temporal and spatial resolution than EEG. Another reason is that ECoG method is able to cover the high-gamma band (60-120 Hz), which contains information about motor and cognitive task [8], and proves useful for studying neuroscience. Since brain is a very complex system, simultaneous multichannel recording of neural signals provides much more information than that contained in a single channel. ECoG signals are typically confined to 200 Hz in bandwidth and 10 to 5000 µV in amplitude [9]. Therefore, for simultaneous recording of 16 channels, a multichannel ADC with at least 9-bits¹and 3.2 kHz is required for this application. Moreover, biosensor applications generally have stringent requirements on the battery life and the physical size of chip, in order to achieve longer durability and more portability.

To sum up, the analog-to-digital conversion of ECoG signals requires an ADC that has high precision, moderate bandwidth, and supports multiplexing

1Generally, the resolution of the ADC depends on the front-end circuit. 9-bit is the minimum number to assure no overflow of data in the digital domain, because 10 × 2⁹ = 5120 >

5000, 10 × 2⁸= 2560 < 5000.

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1.2 Motivation and Objectives 3

inputs from different channels. The power consumption and chip size of the ADC should be as small as possible for practical usage.

1.2 Motivation and Objectives

Utilizing oversampling and noise-shaping, Sigma-Delta (Σ∆) ADCs are a suitable solution to high-precision analog-to-digital conversion, as required in BCI applications. The trend illustrated by recent publications shows the dominance of Σ∆ ADCs in high-resolution applications. However, traditional Σ∆ ADCs cannot be used in multichannel applications, because the outputs do not have a sample-to-sample mapping with the inputs and therefore cannot be used to process time-multiplexed multichannel inputs, as will be discussed in detail in 2.3.

Incremental Σ∆ (IΣ∆) ADCs, on the other hand, can handle multichannel inputs, and provide high-resolution analog-to-digital conversion at the same time, and is thus a viable solution for multichannel applications. A two-step continuous-time (CT) incremental Σ∆ ADC has been proposed [10] for multichannel biosensor applications, to achieve a better tradeoff between the resolution and conversion speed. Since it has been demonstrated that the design specifications of the second stage in the two-step ADC are quite relaxed as compared to the first stage, it is worthwhile to explore the potential to use an inverter-based operational transconductance amplifier (OTA) to replace the original OTA in order to achieve a lower power consumption and a smaller chip area. Due to more relaxed requirements on settling and bandwidth, continuous- time implementation is investigated in this design to potentially further improve the power-efficiency.

The proposed design specifications for the Σ∆ ADC in the second stage are given in Table 1.1.

SNDR 55 dB

BW 4 kHz

supply voltage 1.2 V differential input range 0.667 Vpp

technology 180nm CMOS

Table 1.1: Specifications for an inverter-based 2nd-order CT Σ∆ ADC Although no explicit specification is made on the power consumption, the target of this design is to restrict it in µW range to achieve a state-of-the-art FoM.

1.3 Contribution

The author has designed and implemented a 2nd-order CT Σ∆ modulator using inverter-based amplifiers, which meets all the design specifications shown in Ta-

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4 Introduction

ble 1.1. The entire modulator, including the biasing circuit, consumes 1.064 µA from 1.2 V supply voltage, and occupies a chip area of 0.07 mm², featuring a very power-efficient (243 fJ/(conv.step)) and compact design.

Moreover, this thesis is the first attempt to use fully-differential implementation of inverter-based CT Σ∆ modulators. As will be discussed in detail in section 3.1, the fully-differential topology enables precise control on the operating point and quiescent power of the circuit. It also provides better control on important small-signal circuit parameters, such as the DC-gain, gain-bandwidth product (GBW), and the slew rate (SR) of the inverter-based amplifier. The control on these aspects results in a very robust design, which in turn lowers design requirements for the common-mode feedback (CMFB) circuit, leading to a high power efficiency.

This design provides an alternative to implement inverter-based CT Σ∆

ADCs. In this area only one publicated design [30] exists, to the author’s knowledge. Unlike [30] which targets high-frequency applications, this thesis illustrates the ability to achieve micro-power consumption with inverter-based CT Σ∆ ADCs, providing a competitive solution to low-power biosensor applications. It has also shown potential in two-step implementation of incremental Σ∆ ADCs by cascading compact modulators, to achieve higher power efficiency while maintaining high-resolution feature, than traditional incremental Σ∆ ADC designs.

1.4 Thesis Organization

This thesis work is targeting the implementation of the two-step CT IΣ∆ ADC proposed in [10] using inverter-based Σ∆ modulators. It focuses on implementing the second-order Σ∆ modulator at circuit level, to decrease the power consumption, and therefore improving the figure-of-merit (FoM) of the entire system.

Chapter 2 provides a short overview of the fundamentals of ADCs. Subse- quently, Σ∆ ADCs are introduced and the advantages of CT implementation are discussed. In particular, incremental Σ∆ ADCs are described and shown to suit multichannel biosensor applications.

Chapter 3 gives a detailed analysis on inverter-based OTAs. The working principle of inverter-based amplifier is introduced first. Next, some of the state- of-the-art designs using inverter-based OTAs are presented to show some novel methods to compensate for the cons. These methods are also evaluated for whether they suit CT implementation.

In Chapter 4, the circuit-level implementation is presented. This chapter is divided into five parts, each describing in detail a component in the overall design, with the last part presenting the layout of the entire modulator. This chapter also presents why fully-differential structure is used in this design rather than pseudo-differential structure.

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1.4 Thesis Organization 5

The simulation results are shown in Chapter 5, first for individual circuit components, and then for the entire modulator. This chapter concludes with a Monte-Carlo simulation to demonstrate the circuit robustness of this design.

Chapter 6 concludes the thesis, and proposes possible future work to improve the design presented in this thesis.

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Chapter 2

CT Σ∆ Analog-to-Digital Conversion

Connecting the real world and the ever-growing digital network, analog-to- digital converters are an integral part in almost all electronic systems. With the constant-changing applications and evolving semiconductor technologies, it is worthwhile to investigate novel approaches that could potentially lead to better performance, in terms of precision, speed, and power. This chapter will start with a brief overview of the fundamentals of ADCs, and proceed on to the description of a two-step CT incremental Σ∆ ADC, from which a more power- efficient design using inverter-based CT Σ∆ modulator is proposed.

2.1 Overview of ADCs

Analog-to-digital conversion is the process of converting an analog input signal into its corresponding digital output. It can be divided into two operations, sampling and quantization.

During sampling, the input analog signal x(t) is converted into a sequence of discrete-time values. The n^th output value, x_s[n], satisfies x_s[n] = x(nT_s), where T_s is the sampling period¹. Sampling turns a signal continuous in time domain into a sequence of discrete-time samples. The output sequence from sampling process still has analog amplitudes.

The quantization process converts the discrete-time sequence from sampling into discrete levels. The circuit that performs the quantization process is called a quantizer. The difference between any two consecutive quantization levels is the quantization step (usually denoted as ∆).

The quantization process induces an error in approximating infinite analog levels with finite levels of discrete signals. This error is called the quantization

1Only uniform sampling is considered in this project.

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8 CT Σ∆ Analog-to-Digital Conversion

error. It can be fully determined with the input and quantizer specified.

Quantization is a nonlinear process, and makes linear circuit theory not applicable to the analysis of ADCs. However, if the input signal varies large enough from sample to sample, the spectrum of the quantization error is ap- proximately white [11]. Therefore, linear analysis can be carried out on ADCs, if the quantization process is approximated as adding a white noise to the input of the quantizer. The quantization error is therefore also referred to as quantization noise ². The total power of this approximated white noise is shown to be ^∆₁₂² [12], where ∆ is the quantization step. According to the assumption that the quantization noise has a white spectrum, the spectral density of the quantization noise is _12f^∆²

s, with fs being the sampling frequency.

If only quantization noise is considered, by ignoring all other forms of noise, the ratio between the RMS value of the input signal, and that of the quantization noise, is defined as the signal-to-quantization noise ratio (SQNR), usually expressed in units of dB.

SQN R = Psignal

Pquantization noise

(2.1)

In actual circuit implementation, the quantization noise, together with other forms of noise, such as thermal noise and flicker noise, constitutes the total noise in the ADC circuit. The total noise sets a lower bound on the dynamic range of the ADC. Signal-to-noise ratio (SNR) is defined as the ratio between the RMS value of signal power to the power of total noise, i.e.,

SN R = P_signal

Pquantization noise+ Pcircuitnoise

(2.2)

Signal-to-noise plus distortion ration (SNDR) is defined as the ratio between the signal power and the power of the total noise and distortion, usually expressed in dB. It is the standard measure of the resolution of an ADC.

SN DR = P_signal

Pquantization noise+ Pcircuit noise+ Pdistortion

(2.3)

Effective number of bits (ENOB) is an equivalent metric regarding resolution, and can be calculated as

EN OB = SN DR [dB] − 1.76

6.02 (2.4)

2In fact, it is neither a noise nor white.

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2.2 Σ∆ ADCs 9

Power, bandwidth (BW) and resolution are the three key performance metrics of an ADC. A standard method to compare ADCs across various applications that have different design requirements is to use a figure-of-merit (FoM).

The FoM used in this thesis is given by [13]

F oMW = P ower

2 × BW × 2^{EN OB} (2.5)

2.2 Σ∆ ADCs

Since its first appearance in literature in 1962 [14], Σ∆ ADCs have received intense research interest and wide range of application in commercial products.

Making use of oversampling and noise-shaping techniques, Σ∆ ADCs are widely used in applications featuring medium to high resolution and moderate speed.

2.2.1 Oversampling ADCs

The Nyquist-Shannon sampling theorem states that for a signal band-limited to fB, a sampling frequency of at least 2fBis needed so that the sampled signal can be effectively reconstructed. Nyquist-rate ADCs sample the input at a rate equal to or slightly larger than the Nyquist frequency of the input f_{N yquist} = 2f_B. Oversampling ADCs, on the other hand, use a clock frequency much larger than the Nyquist rate. As a result, the total in-band noise (IBN) powers of Nyquist- rate ADCs and oversampling ADCs are listed below for comparison.

For Nyquist-rate ADCs, i.e., fs= 2fB,

IBNN yquist= Z fB

−fB

∆²

12f_sdf = ∆² 12

2fB

f_s = ∆²

12 (2.6)

For oversampling ADCs, i.e., fs> 2fB,

IBNoversampling= Z fB

−f_B

∆² 12fs

df = ∆² 12

2f_B fs

= ∆²

12 · OSR (2.7) where OSR is the oversampling ratio, defined as the ratio between the sampling frequency and the Nyquist frequency, i.e.,

OSR = fS

2f_B (2.8)

From equations (2.6) and (2.7), it can be seen that oversampling reduces IBN by a ratio of OSR, through spreading the noise power in a larger bandwidth and using a filter to reject noise outside the bandwidth of interest, i.e.,

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fB. The resulting SQNR is improved by 10 · log₁₀OSR (dB). As a result, oversampling ADCs are able to trade higher SQNR with larger power consumption due to the faster sampling process.

2.2.2 Oversampling ADCs with Noise-Shaping

As introduced in subsection 2.2.1, oversampling improves the SQNR by uni- formly spreading the quantization noise over a frequency band much larger than the bandwidth of interest. Combined with the noise-shaping technique, oversampling can further reduced the IBN and thus improve SQNR.

Essentially, noise-shaping technique uses a loop filter to suppress IBN. The out-of-band noise, on the other hand, generally grows as a result of noise- shaping. However, a digital filter will be employed at the output of the ADC to filter out the out-of-band noise.

DAC

X(z) Y(z) V(z)

Integrator DACQ

Figure 2.1: Oversampling ADC with noise-shaping (Σ∆ ADC)

Noise-shaping is implemented by embedding the quantizer in a feedback loop, as shown in Figure 2.1. This configuration is commonly-known as Sigma-Delta (Σ∆) ADC.

Figure 2.2: Σ∆ ADC linear model block diagram

The filter represented by H(z) in Figure 2.1 is used to shape the noise so that IBN is reduced and effectively ”shifted” to frequencies out of the band of interest. Linear circuit theory can be applied to analyze Σ∆ ADCs by using its linear model where quantization error has been replaced by the white noise source, as shown in Figure 2.2. The signal transfer function (STF) and noise

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2.2 Σ∆ ADCs 11

transfer function (NTF) can be derived from

V (z) = H(z) · (X(z) − V (z)) + E(z) (2.9)

Therefore,

ST F = V (z) X(z) _E(z)=0

= H(z)

1 + H(z) (2.10)

N T F = V (z) E(z) _X(z)=0

= 1

1 + H(z) (2.11)

And by applying superposition, the output is given by

V (z) = ST F · X(z) + N T F · E(z) (2.12)

According to equations (2.10) and (2.11), by designing the zeros and poles of H(z), STF and NTF can be chosen to have the desired frequency selection properties. Particularly, for frequencies where |H(z)| is large, ST F .

= 1 and N T F .

= 0 satisfy, therefore these frequency components get passed from input to output. Conversely, for frequencies where |H(z)| .

= 0, ST F .

= 0 and N T F .

= 1 satisfy, and these frequencies get rejected by the loop. Note that ST F + N T F = 1 for all frequencies. Therefore, the frequency components passed by STF is rejected by NTF, and vice versa.

2.2.3 CT Σ∆ ADCs

Although the analysis in subsection 2.2.2 is carried out in DT domain for a more straightforward understanding of its operation, Σ∆ ADCs can also be implemented in CT domain. Essentially, CT implementation of Σ∆ ADCs moves the sampling process into the loop, and replaces the discrete-time (DT) filter H(z) with its continuous-time (CT) counterpart Hc(s). Hc(s), the CT equivalent of H(s), can be found by performing an impulse-invariant transformation (IIT) as shown in equation (2.13).

H(z) = Z( [L⁻¹(Hc(s))]

_t=nT

s) (2.13)

in which Z and L denote the Z-transform and Laplace-transform, respectively.

Utilizing equation (2.13), the design of CT Σ∆ ADCs can be carried out in DT domain first, and then transformed to the CT counterpart. Alternatively, the design of the loop filter can be carried out in CT domain directly [15].

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Although the publications on inverter-based Σ∆ ADC is mostly DT imple- mentations, CT implementation has some advantages over its DT counterpart.

Since sampling is moved into the loop, any non-idealities induced by sampling get noise-shaped by the loop filter. Moreover, the requirements on settling and gain-bandwidth product (GBW) are more relaxed, which generally means a more power-efficient solution could satisfy the design requirements. Inherent anti-aliasing filtering is also a feature unique to CT Σ∆ ADCs. On the other hand, increased sensitivity to jitter and excess loop delay (ELD), and larger coefficient variation in the loop filter are the main drawbacks of CT implementation.

2.2.4 A Short Summary on Σ∆ ADCs

Utilizing oversampling and noise-shaping, Σ∆ ADCs are able to reduce the IBN and obtain a higher SQNR. Therefore, Σ∆ ADCs are a popular solution in applications that require high resolution. Compared to other types of ADCs, Σ∆

ADCs scale better with advancing semiconductor technology. With the down- scaling of supply voltage, the available dynamic range (DR) decreases, because noise power does not scale with the supply voltage. Oversampling and noise- shaping are able to suppress the noise to compensate for smaller DR, which is not available for other types of ADCs.

Another reason why Σ∆ ADCs are popular is that they have less stringent requirements on the circuit components used for their implementation, because non-idealities, such as component mismatch, are shaped by the loop filter.

One point to notice before leaving this subsection is that any noise that is added directly to X(z) or the feedback path from DAC is unshaped, such as the input X(z). Since these components are not noise-shaped by the loop, they can be more influential than other noise components.

2.3 Incremental Σ∆ ADCs

2.3.1 Σ∆ ADCs for Multichannel Applications

Despite the merits introduced in section 2.2, traditional Σ∆ ADCs are not suitable for multi-channel applications, because each digital output depends not only on the present input but also on the previous inputs stored in memory elements.

IΣ∆ ADCs were introduced for instrumentation applications requiring high accuracy but low speed [16]. By sample-and-holding an input signal during each conversion and resetting memory elements afterwards, IΣ∆ ADCs are able to make use of the high-resolution property of Σ∆ ADCs, and apply it to signals from multiple channels.

The IΣ∆ ADC presented in [16] has a first-order architecture, and is ex- tremely slow in conversion speed. To solve the low-speed drawback of first-order

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2.3 Incremental Σ∆ ADCs 13

Dout

MUX

f_s U(s) SH1

V_in,1 V_in,2

Vin,16

channel selection

2^nd order CT IΣΔM

Digital Filter^opt

SH2

reset

M·fs

Master clock reset

Digital Filter

N1 N₂

N=N1+N2

D1(z) D2(z) U(z)

V1(z)

U2(z)

f_s Φ1 f_s Φ2

Stage-1 Stage-2

V_res1 sample

Z^-1

Figure 2.3: Two-step CT IΣ∆ ADC for multi-channel applications

IΣ∆ ADCs, higher-order IΣ∆ ADCs were investigated to improve the conversion speed while conserving a high output resolution [17]. Due to reduced number of cycles per conversion, higher-order architectures also offer an opportunity to reduce the power consumption compared to first-order counterparts [18].

Partially due to mature design methodologies in switch-capacitor (SC) implementation, all high-order IΣ∆ ADCs had been implemented in discrete-time domain before [19]. In [19], the first CT implementation of higher-order IΣ∆

has demonstrated the potential to reduce the power consumption due to more relaxed requirement on settling and bandwidth of the amplifiers inside the modulator.

2.3.2 Two-Step CT IΣ∆ ADC

In [10], a two-step CT IΣ∆ ADC, is proposed as an alternative to achieve high resolution with short conversion time. Compared to higher-order IΣ∆, coefficient-scaling can be less aggressive, leading to an improved power efficiency.

Therefore, the two-step architecture provides a competitive solution to low- power multi-channel analog-to-digital conversion, required in brain-computer interfaces.

Another advantage of two-step IΣ∆ ADCs compared to higher-order IΣ∆

ADCs is that the requirement on circuit implementation in each conversion step is quite relaxed. As a result, simple circuits, such as inverter-based OTA, can be used in the implementation, potentially leading to a reduced overall power consumption.

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Through intensive system-level simulation, it has been demonstrated that the second-step conversion benefits more from the relaxation on specifications in multi-step operation. Therefore, it is worthwhile to investigate the possibility of implementing the converter in the second stage using an inverter-based CT Σ∆ modulator in the proposed system in [10], to further improve the power efficiency. As will be discussed in the next chapter, inverter-based designs have demonstrated the merit of low power consumption, compared to traditional OpAmp/OTA designs.

The proposed design specifications for the inverter-based 2nd-order CT Σ∆

modulator are listed in Table 1.1 (section 1.2). A major goal of this thesis is to achieve micro-power consumption while meeting the specifications.

The proposed 2nd-order CT Σ∆ modulator is shown in Figure 2.4.

DAC(s) d2

reset

M·fs

fs

d1

a1

c1 c2

b₁

X₁(t) X₂(t)

v(n) u(n)

z(t)

Vref

Vres

Figure 2.4: 2nd-order CT Σ∆ modulator in CIFF topology

Cascade-of-integrators feedforward (CIFF) topology is selected to reduce the signal swings at each of the integrator outputs. As a result, nonlinearity of the inverter-based OTA is minimized by the reduced swing. Due to low DC-gain and small input range of inverter-based OTA, this nonlinearity can easily become the limiting factor of the overall linearity requirement of the system. The detailed analysis is shown in subsection 4.1.4.

The coefficients are listed below in Table 2.1.

a₁ 1 b₁ 1 c₁ 0.4

c2 0.8 d1 3.125 d2 1.5625

Table 2.1: Coefficients values for 2nd-order modulator in Figure 2.4

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Chapter 3

Overview of Inverter-Based OTA

In this chapter, the working principles of inverters as amplifiers is presented first, serving as a ground that further discussion of relevant circuit techniques base on. Next, some novel design examples are presented regarding the short- comings of inverter-based OTAs mentioned in the first section. These solutions are analyzed for the feasibility to be used in this project.

3.1 Voltage Transfer Curve of Inverter

V

_in

M_p1

M_n1

V

_out

V

DD

Figure 3.1: An inverter-based OTA

The working principle of inverters as amplifiers can be understood by look- ing at its voltage transfer curve (VTC). The VTC of an inverter shows the variance of its output as its input changes. Important design parameters can be derived from the VTC, such as the trip point (defined as the voltage where the input equals the output), the small-signal DC gain and the maximum input range, outside of which the small-signal gain starts to drop rapidly. Two typ-

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16 Overview of Inverter-Based OTA

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

0 0.2 0.4 0.6 0.8 1 1.2

Voltage Transfer Curve with 1.2V Supply

Input voltage/V

Ouput voltage/V

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

Voltage Transfer Curve with 0.8V Supply

Input voltage/V

Output voltage/V

Figure 3.2: VTC of an inverter with 1.2 V and 0.8V supply voltages, respectively

ical VTCs for an inverter under different supply voltage conditions are shown in Figure 3.2. It is shown in the following paragraph that the supply voltage can be used to set the operation regions of the PMOS and NMOS in the inverter.

The operation regions of the PMOS and NMOS in an inverter depend on the relation between the supply voltage, V_DD, and the sum of the threshold voltages of the PMOS and NMOS transistors, |Vtp| + Vtn. If VDD> |Vtp| + Vtn, both PMOS and NMOS operate in strong inversion region at the trip point, as shown in the upper half of the plot in Figure 3.2. If VDD < |Vtp| + Vtn, both PMOS and NMOS operate in subthreshold region at the trip point, as shown in the lower half of plot in Figure 3.2. It can be seen that the inverter operating in subthreshold region has a larger DC=gain and a smaller input signal range.

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3.1 Voltage Transfer Curve of Inverter 17

For low-voltage low-power designs, it is favorable to bias the inverter in subthreshold region, which features low quiescent current and high transconductance efficiency gm/ID [20]. In this region, the transconductance is proportional to the biasing current, with a constant factor nVT. Since the quiescent power consumption PDC= VsupplyIbiasand the gain-bandwidth GBW = gm/C are proportional to Ibias and gm, respectively, GBW and PDCgrows or shrinks proportionally with respect to each other, under the condition that the load capacitance C stays constant. It suggests that the lowest possible GBW should be used in the design to obtain the minimum quiescent power consumption.

Furthermore, small load capacitance values would help to increase GBW under a certain bias current. This property will be exploited in the design shown in Chapter 4.

An important constraint in the design is summarized in the lemma shown below.

Lemma: The bias current ID and gate-to-source voltage VGS cannot be determined at the same time before the chip is measured, due to process variations.

This is proved as the following. It is shown in [20] that for MOS transistors working in subthreshold region, its current-voltage relation is

ID= IS· exp[VGS− VT H

nV_T ] · {1 − exp[−VDS

V_T ]} (3.1)

where VT H is the threshold voltage, and VT is the thermal voltage VT = kT /q .

= 25.9 mV . If VDS > 4VT, then exp[−^V_V^DS

T ] << 1, and therefore equation (3.1) simplifies to

ID= IS· exp[VGS− VT

nV_T ] (3.2)

If the condition above is satisfied, the transistor is operating in the saturation in subthreshold region [20].

IS, the specific current [21], given by IS = 2 · n · β · V_T², depends on ^W_L and mobility of the charge carrier (electrons for NMOS, and holes for PMOS) [20], and is thus subject to process variation. Moreover, the threshold voltage VTH

can vary from 10% to 15% from the nominal value in the range from 0.35 V to 0.45 V. According to equation (3.2), the drain current ID can vary more than three times in magnitude with a constant gate-to-source voltage VGS. There- fore, only one of the two parameters, ID and VGS, can be determined during design process. This lemma will be used extensively in later sections to show its effects on the biasing scheme of inverter-based OTAs.

The trip point of the inverter Vtp, i.e., the voltage level where Vin = Vout, is often considered as the optimum operating point [22][23][24], because the small-signal DC gain is maximized at this point. However, Vtpis also a process

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variant, due to the variation of threshold voltages in the inverter.

The small-signal DC gain at low frequency of the inverter can be calculated as

A_DC = g_mR_out (3.3)

where Rout denotes the equivalent output resistance of the inverter.

From equation (3.3), it can be easily seen that either the transconductance gmor the output resistance Routhas to be increased to achieve a larger DC-gain.

Since a larger gm indicates a larger power consumption, as analyzed earlier in this section, increasing Rout is a more power-efficient way to obtain a larger DC-gain.

Another concern is the slew rate (SR) of this circuit. If SR is too small, the circuit might experience nonlinear (dis)charging in its step response, and therefore degrade the system performance due to nonlinearity. The SR of a circuit is

SR = I

C (3.4)

where C is the equivalent capacitance at the output, and I is the maximum current available to charge this capacitance. SR is reduced due to low quiescent current when the inverter is operated in subthreshold region. Nonetheless, whether slewing happens depends on the clock rate of the Σ∆ ADC as well as SR. It is shown in Chapter 4 that for applications with slow switching speed, slewing usually does not happen.

The power-supply-rejection-ration (PSRR) of a simple inverter-based OTA is only roughly 6dB. PSRR of inverter-based amplifiers can be improved by utilizing differential structure, instead of single-ended structure. Moreover, the noise from power supply gets noise-shaped by the loop filter. As long as the noise level stays below the noise floor, its effect can be neglected. This can be guaranteed by using separate digital and analog power supplies and grounds.

In summary, it is shown in this section that the biasing current of inverter- based OTA, i.e. ID, affects not only the quiescent power consumption, but also slew rate and small-signal parameters such as DC-gain and GBW. Therefore, the biasing scheme of inverter-based OTA should be carefully chosen to satisfy the design requirement specified in section 1.2, while minimizing the power consumption.

3.2 Case Study

In this section, some state-of-the-art designs using inverter-based OTAs are presented and analyzed. Methods of setting the DC operating point, increasing SR and improving DC-gain are discussed after describing each of the state-of-the- art designs.

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3.2 Case Study 19

3.2.1 Auto-Zeroing Biasing

One obstacle of using inverter-based OTA instead of traditional OTA is that inverter-based OTA cannot provide a virtual ground terminal because it has only one input. The ground level is required because the any signal level is defined with respect to it. In [22], a method to define a well-established small-signal ground is proposed, together with an offset canceling scheme using auto-zeroing.

C

I

C

_C

C

_S

φ1

φ2 φ1

φ2

φ₁

V

_in

V

out

Figure 3.3: Integrator with inverter-based OTA biased using auto-zeroing As shown in Figure 3.3, the operation of the integrator consists of two steps, sampling (φ1 phase) and transfer (φ2phase). During φ1 phase shown in Figure 3.4, a close loop is formed around the inverter, and thus forcing it to operate at its trip point V_tp. This voltage level is stored onto capacitor C_C. At the same time, the input voltage is sampled by capacitor C_S.

C

S

V

in

V

tp

V

out

Figure 3.4: Sampling phase of SC integrator with inverter-based OTA During the transfer phase shown in Figure 3.5, the voltage at the input of the inverter is −V_in+ V_tp. Therefore, the inverter is operating away from its biasing point V_tp, and the equivalent small-signal input level is −V_in. The charge on capacitor C_Sstarts being transferred to capacitor C_I, until the input to the inverter is restored to its biasing point Vtp. As a result, the node Vvg

is established as the virtual ground point, because the voltage across capacitor CCis equal in magnitude and opposite in sign with the equilibrium input level of the inverter.

In [22], it is also shown that if the inverter is operated as a class-C amplifier, the input sample can bias the inverter in the transfer phase in such a way that

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C

I

C

S

V

O

V

vg

Figure 3.5: Transfer phase of SC integrator with inverter-based OTA

one and only one of the PMOS-NMOS pair in the inverter is operating in strong inversion, and the other is in cut-off. This feature effectively improves the SR, while keeping the quiescent power low for the inverter-based OTA.

The Σ∆ modulator presented in [22] is implemented with class-C inverter- based OTA, and achieves a state-of-the-art FoM of 98fJ/(conv. step). As attractive as this method is, it does not suit CT implementation, due to the inherent sampling process in the integrator. Moreover, since the optimum operating point of class-C inverter-based OTAs happens when VDD

= |V. tp| + Vtn [22], it is difficult to guarantee its performance across different fabricated chips, when a predefined constant supply voltage is used, because V_tpand V_tnare subject to process variations¹. Furthermore, as analyzed in section 3.1, the bias current of the inverter-based OTA would be undefined in this case, making the estimation of quiescent power difficult.

3.2.2 LDO Biasing

In order to address the problem of undefined biasing current, an on-chip low- dropout regulator (LDO) has been proposed in [25] to provide local supply voltage to the inverter-based OTAs [25], as shown in Figure 3.6.

An OpAmp is used to force the gate-to-source voltages of transistors Mn2

and Mn2to be roughly the same. Therefore, the current in transistor Mn2, i.e., Ibias, is copied to transistor Mn2, with a proportion defined by their relative sizes. Since the current through transistor M2n2 is the same as the current through the transistor Mp2, the output voltage of the OpAmp will be established to provide a local supply voltage Vlocal equal to the sums of absolute values of the gate-to-source voltages of the inverter consisting of Mp2 and Mn2. This voltage Vlocal is then used to provide supply to all inverter-based OTAs used in the design.

This method provides better control over the quiescent current of the inverter, and a better PSRR [23]. However, this design also presents some issues

110%-20% according to UMC 180nm design kit.

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3.2 Case Study 21

V

_in

Mp1

Mn1

V

_out

Mp2

Mn2 +

Mn3

V

_DD

-

V

_local

I

_bias

Figure 3.6: Inverter-based OTA with LDO-defined supply voltage

in CT implementation.

First, the design requirement of the OpAmp is demanding. Its DC-gain needs to be high enough such that the difference between the gate-to-source voltages of transistors M_n2 and M_n3 is sufficiently small for a precise copying of the bias current I_bias. A small difference in the gate-to-source voltages could lead to a significant error in the biasing currents, especially when the transistor are working in subthreshold region, where the current depends exponentially on the gate-to-source voltage, as shown in equation (3.2). Moreover, the SR of the OpAmp should be as high as the sum of the SRs of all inverters that it supplies.

The OpAmp in this design also induces additional noise and power consumption.

In terms of power consumption, this method is less efficient because the OpAmp consumes additional power. Besides, the inverter consisting of transistors Mn2 and Mp2 is not used for processing input signals, but consumes the same amount of quiescent current as the one used for signal processing, i.e.

transistors Mn2and Mp2. The power consumed by the OpAmp and transistors Mn2and Mp2should be small compared to other forms of power consumption, in order not to be considered as a significant overhead. These requirements make the design of this OpAmp very challenging, especially when all inverters are working in subthreshold region.

Second, the CM level of input Vinshould be the same as the gate-to-source voltage of transistor Mn2, which is a process variant when its current is determined, according to the analysis in 3.1. In [23], correlated double sampling (CDS) is used to compensate the difference between this voltage level and the actual input CM level. The inherent sampling process in CDS would also pre- vent the entire modulator to benefit from the merits of CT Σ∆ implementation mentioned in subsection 2.2.3

Micro-Power Inverter-Based Continuous-Time Sigma-Delta Modulator for Biosensor Applications

Micro-Power Inverter-Based Continuous-Time Sigma-Delta

Modulator for Biosensor Applications

Micro-Power Inverter-Based

Continuous-Time Sigma-Delta Modulator for Biosensor Applications

JIAZUO CHI

Stockholm 2014 Master Thesis

School of Information and Communication Technology

Kungliga Tekniska H¨ ogskolan

Acknowledgment

Contents

List of Figures

List of Tables

Acronyms

Chapter 1

Introduction

1.1 Background

1.2 Motivation and Objectives

1.3 Contribution

1.4 Thesis Organization

Chapter 2

CT Σ∆ Analog-to-Digital Conversion

2.1 Overview of ADCs

2.2 Σ∆ ADCs

2.3 Incremental Σ∆ ADCs

Chapter 3

Overview of Inverter-Based OTA

3.1 Voltage Transfer Curve of Inverter

V

V

V

3.2 Case Study

C

C

C

V

V

C

C

V

V

V

C

C

C

V

V

V

V

V

V

I