Institutionen för systemteknik
Department of Electrical Engineering
Examensarbete
Performance Evaluation of
Medium-Power Voltage Inverters
Examensarbete utfört i Elektroteknik vid Tekniska högskolan vid Linköpings universitet
av Emil Häger
LiTH-ISY-EX--15/4828--SE
Linköping 2015
Department of Electrical Engineering Linköpings tekniska högskola
Linköpings universitet Linköpings universitet
Performance Evaluation of
Medium-Power Voltage Inverters
Examensarbete utfört i Elektroteknik
vid Tekniska högskolan vid Linköpings universitet
av
Emil Häger
LiTH-ISY-EX--15/4828--SE
Handledare: Martin Nielsen Lönn
isy, Linköpings universitet
Examinator: Atila Alvandpour
isy, Linköpings universitet
Avdelning, Institution Division, Department
Institutionen för systemteknik Department of Electrical Engineering SE-581 83 Linköping Datum Date 2015-03-24 Språk Language Svenska/Swedish Engelska/English Rapporttyp Report category Licentiatavhandling Examensarbete C-uppsats D-uppsats Övrig rapport
URL för elektronisk version
http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-118568
ISBN — ISRN
LiTH-ISY-EX--15/4828--SE Serietitel och serienummer Title of series, numbering
ISSN —
Titel
Title Performance Evaluation of Medium-Power Voltage Inverters
Författare Author
Emil Häger
Sammanfattning Abstract
Power inverters, used to convert DC power to AC, are often used in e.g. solar power applica-tions. However, they tend to be impractically large and expensive; as such, power miniatur-ization is an active research area. In this thesis, several classes of modern power inverters are evaluated and compared with regards to size, efficiency and output quality in order to iden-tify areas of potential improvement. Methods for estimation of THD, power losses and input ripple are created and verified against a simulation of a five-level neutral-point-clamped in-verter with SPWM control. Finally, this design is implemented physically and is found to achieve 94.5% efficiency and 7% THD under low voltage laboratory conditions, while re-maining smaller than an average textbook.
Nyckelord
Keywords Inverter, neutral-point clamped, SPWM, switching losses, input ripple, total harmonic dis-tortion
Abstract
Power inverters, used to convert DC power to AC, are often used in e.g. solar power applications. However, they tend to be impractically large and expensive; as such, power miniaturization is an active research area. In this thesis, several classes of modern power inverters are evaluated and compared with regards to size, efficiency and output quality in order to identify areas of potential improve-ment. Methods for estimation of THD, power losses and input ripple are created and verified against a simulation of a five-level neutral-point-clamped inverter with SPWM control. Finally, this design is implemented physically and is found to achieve 94.5% efficiency and 7% THD under low voltage laboratory conditions, while remaining smaller than an average textbook.
Acknowledgments
Many thanks to my supervisor Martin, who patiently suffered through my many questions without complaint. Likewise, thanks to my examiner Atila, without whose infectious enthusiasm this would never have been done.
Finally, my brother: for offering motivation whether he knew it or not.
Linköping, Mars 2015 Emil Häger
Contents
Notation ix 1 Introduction 1 1.1 Background . . . 1 1.2 Problem Specification . . . 1 1.2.1 Limitations . . . 2 1.2.2 Method . . . 2 2 Theory of Operation 3 2.1 Switching Strategies . . . 3 2.1.1 Pulse-width Modulation . . . 3 2.1.2 Multilevel . . . 6 2.1.3 Multilevel PWM . . . 8 2.2 Topologies . . . 10 2.2.1 H-bridge . . . 10 2.2.2 Diode-clamped . . . 11 2.2.3 Capacitor-clamped . . . 13 2.2.4 Switched-capacitor . . . 15 2.2.5 Switched-inductor . . . 15 2.2.6 Comparison . . . 16 3 Practical Considerations 17 3.1 Filter Selection . . . 17 3.2 Conduction Losses . . . 19 3.3 Switching Losses . . . 20 3.3.1 Gate charge . . . 20 3.3.2 Switch-conduction . . . 20 4 Implemented Architecture 23 4.1 Schematic . . . 23 4.1.1 Inverter . . . 24 4.1.2 Gate Drivers . . . 25 4.1.3 Control . . . 26 viiviii Contents 4.1.4 Filter . . . 27 4.2 Expected Results . . . 29 4.2.1 Ripple . . . 29 4.2.2 THD . . . 30 4.2.3 Efficiency . . . 30 4.3 Simulation Results . . . 32 5 Results 35 5.1 Physical Implementation . . . 35 5.1.1 Control . . . 36 5.2 Output Behaviour . . . 37 6 Conclusions 41 6.1 Discussion . . . 41 6.2 Future Work . . . 43 A Component List 47
B Little Box Requirements 49
Notation
Abbreviations
Abbreviation Meaning
AC alternating current
DC Direct current
EMI Electromagnetic interference
LBC Little Box Challenge
NPC Neutral-point clamped
PWM Pulse-width modulation
RMS Root mean square
SC Switched-capacitor
SL Switched-inductor
SHEPWM Selective harmonic elimination pulse-width
modula-tion
SPWM Sinusiodal pulse-width-modulation
SVM Space vector modulation
THD Total harmonic distortion
ZCS Zero-current switching
ZVS Zero-voltage switching
x Notation
Symbols
Symbol Meaning
CDC Total DC-link capacitance
Ciss MOSFET input capacitance
fc Filter cutoff frequency
fo Inverter output frequency
fs Swithing frequency
Iin Inverter input current
IL Inverter load current (RMS)
m Number of levels in a multilevel inverter
ma Amplitude modulation index
mf Frequency modulation index (fs/fo)
Pin Inverter input power
Pload Inverter output power
Pon Switch conduction loss
Psw Switching power
Rin Internal resistance of input DC source, or total
resis-tance between DC source and inverter
Ron MOSFET on-state resistance
ri Input current ripple factor
rv Input voltage ripple factor
Sn The n-th harmonic of a signal S
VDC DC supply voltage
Vin Inverter input voltage
1
Introduction
1.1
Background
Power inverters are used to convert electric power from DC to AC. They can be used to e.g. run AC-powered household appliances on DC sources such as bat-teries or solar panels, provide variable-frequency AC for electric motors, or as an intermediate step in DC-DC conversion.
Medium-to-high power (kW-scale) inverters tend to be large and bulky, which also makes them expensive and impractical. The need for improvement coupled with the slow pace of innovation led Google to offer a million-dollar price (the Little Box Challenge) to whoever could design a 2 kVA inverter. The technical specifications for this contest (appendix B) are used throughout this thesis as a reference point for what constitutes a high-quality inverter.
1.2
Problem Specification
The aim of this thesis is to evaluate modern power inverter technologies with regard to size, efficiency and output quality. Several classes of inverter are simu-lated and the results compared and generalized to higher-level inverters. Particu-lar attention is paid to the power loss problem, and an architecture-independent analytical model is developed to provide quick efficiency estimates without the need for a full simulation.
Finally, the models and simulations are checked against reality by implement-ing one architecture on a prototype board and testimplement-ing it under low-voltage labo-ratory conditions.
2 1 Introduction
1.2.1
Limitations
Only single-phase inverters are considered; while three-phase inverters are com-mon, they are mostly used for industrial rather than household applications. While most of the thesis applies to modified sine wave inverters, the focus is on pure sine wave inverters.
The quality metrics of temperature and EMI (electromagnetic interference) are ignored, as they are not relevant at low power and do not appear in SPICE simulations.
In addition, resonant-switch converters are not considered since they gener-ally need a highly inductive load to function properly [1, 2].
1.2.2
Method
First, the basics of power inverters are reviewed, and several topologies are con-sidered for implementation. Based on the requirements in appendix B, a suitable architecture is chosen.
Analytical expressions are derived for various performance metrics, and the complete inverter is simulated in SPICE. Finally, the inverter is implemented physically and its performance evaluated based on measurements.
2
Theory of Operation
2.1
Switching Strategies
Inverters have a fixed number of discrete output voltage levels. Since the desired output is an ideal sine wave, it is desirable to switch between these levels in a way that reduces total harmonic distortion (THD) as much as possible. THD for a signal S is calculated as
rms(S − S1)
rms(S1)
. (2.1)
Where S1 is the fundamental frequency component of the signal. THD is
usually measured for both voltage and current, but for a pure sine wave inverter with a mostly resistive load composed of only passive components, these values are close enough that listing them both would be redundant. Unless otherwise specified, THD values given are for the output voltage.
There are two major switching strategies: pulse-width modulation (PWM) and multilevel. PWM switches rapidly between a small number of output levels, while multilevel inverters switch less frequently between a larger amount of out-put levels. These methods can also be combined to get some of the benefits of both.
As long as an inverter can produce the right number of voltage levels, output quality is largely independent of the specific architecture used. The switching pattern is what matters most, with higher switching frequencies and more output levels generally giving lower THD.
2.1.1
Pulse-width Modulation
With PWM, the output signal is "chopped" along the time axis, as seen in Fig. 2.1. Output switches between positive and negative input voltage, with nothing in
4 2 Theory of Operation
between (bipolar switching). The major downsides of this type of control are the switching losses and electromagnetic interference (EMI) created by the large
dV /dt. 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 −200 −150 −100 −50 0 50 100 150 200 Time (s) Vo (V)
Figure 2.1: Output of a PWM-controlled inverter at a low switching
fre-quency.
Sinusoidal PWM
The control signals for a PWM inverter can be generated by comparing a triangle
wave Vcat the desired switching frequency fs and a sine wave Vm at the output
frequency fo (see Fig. 2.2). While the sine is greater than the triangle, the
in-verter output is positive; otherwise it is negative. This control method is called sinusoidal PWM (SPWM). 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 −1 −0.8 −0.6 −0.4 −0.2 0 0.2 0.4 0.6 0.8 1 Time (s) Vc, Vm (V)
Figure 2.2:Generation of PWM control signals.
The ratio of the sine amplitude to the triangle amplitude is called amplitude
modulation ratio and is denoted by ma. With an ideal voltage source at the input,
the peak of the output voltage ˆVoat the fundamental frequency is amaVDC, where
a is an architecture-specific constant, usually 1 or 0.5. This means the output can
be regulated by changing the amplitude of the sine wave.
If the DC source is not ideal, or there is significant resistance between it and the inverter, the input voltage becomes
2.1 Switching Strategies 5
Vin= VDC−IinRin (2.2)
where VDC is the nominal voltage of the DC source, Rinis its internal
resis-tance plus resisresis-tance between it and the inverter, and Iin is the input current.
The voltage drop over Rinmeans mamust vary with the load to maintain a fixed
amplitude of the output voltage.
Assuming 100% efficiency (Pin= Pout), the input current is
Iin= VDC 2Rin ± s RinPout−VDC2 R2in (2.3)
which gives the input voltage
Vin= VDC−
VDC
2 ∓
q
RinPout−VDC2 (2.4)
from which the desired macan be determined using ˆVo= amaVin≡ma=
ˆ
Vo aVin.
Some variations on SPWM involves using different carriers, but for most pur-poses the in-phase triangle waves are sufficient [3].
Other switching methods, such as selective harmonic elimination (SHEPWM) can give lower THD by completely eliminating harmonics. However, these
meth-ods give the switching angles as a function of maand require solving large sets
of nonlinear equations [4], which makes them too computationally intensive for on-line use.
Solving for a few different values of maand storing the results in lookup tables
is a possible, though somewhat inflexible, workaround.
Harmonics
While SPWM does not eliminate any harmonics, it does have the benefit of push-ing them to higher frequencies. This means a smaller filter can be used at the output to achieve acceptable (< 5%) THD. The magnitude of the harmonics is independent of the switching frequency used. Only the modulation method mat-ters [2]. 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 20 25 30 35 40 45 50 55 Ma THD (%) Figure 2.3:THD as a function of ma.
6 2 Theory of Operation
The total harmonic content is dependent on ma, illustrated in Fig. 2.3. When
ma> 1, the output starts to degenerate into a square wave.
0 2 4 6 8 10 12 14 16 18 20 0 10 20 30 40 50 60 70 80 90 100 Frequency (kHz) Fundamental (60Hz) = 324.2 , THD= 105.95% Mag (% of Fundamental)
Figure 2.4: Harmonic content of a PWM inverter with ma = 0.97 and fs =
6060 H z.
The location of the harmonics depends on the switching frequency: as seen in
Fig. 2.4, the first harmonics appear around fs, the second set around 2fs, etc.
2.1.2
Multilevel
Multilevel inverters "chop" the signal along the amplitude axis (Fig. 2.5). Having more voltage levels requires a greater amount of hardware in the inverter, but it also makes the voltage jumps smaller and gives a better approximation of a sine wave; each level added eliminates another harmonic [2].
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 −400 −300 −200 −100 0 100 200 300 400 Time (s) Vout (V)
2.1 Switching Strategies 7
However, the switching will occur at or near the fundamental frequency, rather than at large multiples of it. The time switches spend in the on-state far exceeds the switching period, so conduction losses will be far greater than switching losses.
Since the ma parameter can not be used for control in multilevel inverters,
they require a controllable buck- or boost converter (depending on the architec-ture used) at the input in order to regulate the output voltage.
Control Signal Generation
In order to eliminate the greatest number of harmonics, a multilevel inverter needs to switch at precise angles.
The half-height method from [1] finds the ideal switching angles to be halfway between the angles where a sine wave would reach the available voltage levels, i.e
αi = sin −12i − 1 m − 1 , i ∈ 1, 2 ... m − 1 2 (2.5) where m is the number of output levels in the inverter.
Using a microcontroller with a lookup table of the ideal switching angles is a simple and effective way to achieve the desired control. Due to the sine function’s quarter-wave symmetry, only (m − 1)/2 angles need to be stored.
Harmonics
Unlike the PWM inverter, multilevel inverters do not push their harmonics to higher frequencies. While the THD is lower, the harmonics are located at rela-tively low frequencies, requiring a larger filter to eliminate completely. Achiev-ing acceptable THD without a filter is possible (table 2.1) but requries many out-put levels. As seen in Fig. 2.6, a 5-level inverter at 60 Hz outout-put has harmonics starting at 420 Hz. Levels Achievable THD 3 29.0% 5 16.4% 7 11.5% 9 8.9% 11 7.3% 13 6.1% 15 5.3% 17 4.7% 19 4.2% 21 3.8%
8 2 Theory of Operation
Purely multilevel strategies are thus not a great choice for low-frequency ap-plications. At higher fundamental frequencies, each eliminated harmonic gives greater relaxation on the requirements of the output filter cutoff frequency.
0 100 200 300 400 500 600 700 800 900 1000 0 10 20 30 40 50 60 70 80 90 100 Frequency (Hz) Fundamental (60Hz) = 434.2 , THD= 17.75% Mag (% of Fundamental)
Figure 2.6:Harmonic content of a 5-level inverter.
2.1.3
Multilevel PWM
By utilizing PWM control in a multilevel inverter, some of the benefits from both methods can be gained: smaller voltage jumps, high-frequency harmonics, and
control by changing ma. The output of such an inverter is shown in Fig. 2.7.
Figure 2.7:Voltage output of a 5-level PWM inverter.
Control Signal Generation
Unfortunately, harmonic elimination in multilevel PWM is a difficult task. The
optimal switching angles depend on ma, and as with SHEPWM, solving for them
in real-time is not feasible on a microcontroller.
However, SPWM is easily adapted for more voltage levels by using multiple triangle waves as shown in Fig. 2.8. While the sine is greater than the upper triangle wave, output is at positive maximum; in between it is neutral; and below the lower triangle wave it is at negative maximum. The switching frequency for
2.1 Switching Strategies 9
Figure 2.8:Control signal generation for a 3-level PWM inverter.
The modulation ratio is determined in the same way as for bipolar PWM in-verters.
Harmonics
Despite the multiple voltage levels, no harmonic elimination occurs with basic SPWM control; only the amplitude of the harmonics is affected. The THD lies somewhere between the multilevel and bipolar PWM, with the harmonics located around the switching frequency.
The reduced harmonics are illustrated in Fig. 2.9.
0 10 20 30 40 50 60 70 80 90 100 0 20 40 60 80 100 Frequency (kHz) Mag (% of fundamental)
Figure 2.9: Harmonics of a 5-level PWM inverter. ma = 0.754 and fs =
10 2 Theory of Operation
2.2
Topologies
Many inverter topologies exist and can be used to get the voltage levels needed by any given switching strategy. Several classes of these (from [1]) are discussed below, with some advantages and disadvantages listed for each.
2.2.1
H-bridge
The most basic inverter is the H-bridge (Fig. 2.10), also called full-bridge. It consists of 4 switches with antiparallel diodes. It is capable of negating the input
voltage or blocking it entirely, giving it three output levels: VDC, −VDC, and 0.
+
-AC DC+
DC-Figure 2.10:An H-bridge inverter.
By connecting several H-bridges in series (Fig. 2.11), more output levels can be achieved; however, this requires a separate DC source for each cell.
2.2 Topologies 11 H-bridge H-bridge H-bridge Vo1 Vo2 + − + − + − Vdc Vdc Vdc
Figure 2.11:A seven-level multicell inverter made of several H-bridges.
This type of structure also gives a long conduction path of 2(m − 1) switches, which reduces the device efficiency.
2.2.2
Diode-clamped
The diode-clamped (also called neutral-point clamped, or NPC) class of inverters, as the name implies, uses DC-link capacitors and diodes to clamp the voltage level at parts of the circuit to desired levels. In this way, each phase leg of the
inverter can output between −VDC/2 and VDC/2 relative to the designated neutral
12 2 Theory of Operation AC + -DC+ DC-S1 S2 S3 S4
Figure 2.12:A three-level diode-clamped inverter with a single phase leg.
The switches in Fig. 2.12 make up two complementary pairs: (S1, S3) and
(S2, S4), so the inverter has four possible states. The state where the outer switches
S1and S4are open is unused, since it would give a floating output.
Five-level inverters (Fig. 2.13) and higher have similar pairs. Disallowing the states that give a floating output or a DC-to-ground short always leaves m switch states; thus, NPC inverters have only one viable switch combination for each output level.
AC+ -DC+
2.2 Topologies 13
For an m-level inverter, the switches are required to block a voltage of VDC/(m−
1). Current flows through up to m − 1 switches and one diode, increasing the po-tential conduction losses when more levels are used. The clamping diodes are
also subject to a great deal of stress. They are required to block up to VDC, unless
several smaller series diodes are used.
While the average diode current is less than the inverter output current, the peaks are many times greater.
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 50 100 150 200 Time (s) C1 voltage (V) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 50 100 150 200 Time (s) C2 voltage (V) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 50 100 150 200 Time (s) C3 voltage (V) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 50 100 150 200 Time (s) C4 voltage (V)
Figure 2.14:Voltage over the DC-link capacitors in a five-level NPC inverter.
When m > 3, the DC-link capacitors will suffer a charge imbalance (Fig. 2.14). More current is drawn from the inner capacitors, and the output waveform will eventually decay into three levels, as the charge is located entirely on the top and bottom capacitors. Therefore, this architecture is rarely used without some corrective measures [5].
Balancing methods based on switching patterns only work for low modulation indices [6], so balancing methods often involve additional circuitry [7] or else only work under certain circumstances [8], making NPC inverters generally less attractive from a practical standpoint.
2.2.3
Capacitor-clamped
Using capacitors to clamp the voltage to desired levels gives a topology similar
to the diode-clamped one. Switches are still required to block VDC/(m − 1), but
there is no need for high-performance clamping diodes. Instead, it uses m − 2 capacitors. This means there are no large peak currents in the device.
14 2 Theory of Operation AC + -DC+
DC-Figure 2.15: A three-level capacitor-clamped inverter with a single phase
leg. AC + -DC+
2.2 Topologies 15
As with the diode-clamped topology, capacitor charge imbalance is a prob-lem. However, it occurs in the clamping capacitors rather than the DC-link ones. Fortunately, each voltage level can be synthesized with several switching vectors; careful selection of these can eliminate the charge imbalance.
2.2.4
Switched-capacitor
The switched-capacitor (SC) inverter and its cousin the switched-inductor (SL) inverter offer some advantages over the traditional clamping varieties. They re-quire only a small number of components for each added output level, and offer significant voltage boost capabilities.
Fig. 2.17 shows an SC inverter. Note that if m ≤ 3, there would be no capac-itors and only an H-bridge would remain.The capaccapac-itors are charged in parallel
while the main switch Smis closed, and discharged in series when it is open and
the secondary switches are closed. As a result, the output voltage peak is up to
(m − 1)/2 times the input voltage, with a step size of VDC. This is a downside
in cases where the AC voltage should have a lower peak than VDC; additional
circuitry would be needed to bring down the voltage to the desired level.
AC + -DC+ DC-Sm S1 S2 S3
Figure 2.17:A 9-level switched-capacitor inverter.
The SC inverter also suffers from a charge imbalance issue; the larger the load, the smaller the average charge is on the capacitor, as it is reduced by the output current. At high loads, the capacitors are fully drained each period, giving a three-level output no matter how many levels the inverter is built for.
2.2.5
Switched-inductor
The switched-inductor (SL) inverter uses an inductor to charge series capacitors, as shown in Fig. 2.18. The duty ratio of the inductor switch can be changed to control the capacitor charge, and thus the output voltage.
While the inductor is charging, there is effectively a short across the DC input. Unless the inductor is very large or the duty ratio of the switch very low, this
16 2 Theory of Operation
leads to extremely large currents through the main switch; extensive paralleling of devices is needed to make this design functional, and the power losses through the main switch will be considerable.
AC +
-DC+
DC-Figure 2.18:A 9-level switched-inductor inverter.
Unfortunately, the charge imbalance issue seen in the SC inverter is also present here, for the same reasons.
2.2.6
Comparison
The number of power electronic components needed for each topology is shown in table 2.2.
Topology Switches Diodes Capacitors Switch blocking voltage
Diode-clamped 2(m − 1) 4m − 5 m − 1 VDC m−1 Capacitor-clamped 2(m − 1) 2(m − 1) m VDC m−1 Switched-capacitor 4 + m m − 4 m−32 VDC Switched-inductor 5 +m−12 1 m−32 VDC
3
Practical Considerations
3.1
Filter Selection
Since the output is going to be strongly distorted, a low-pass filter is required to eliminate the unwanted harmonics. These harmonics are a considerable pro-portion (> 30%) of the overall signal energy, so a purely reactive filter is used to minimize losses.
Figure 3.1: A T-section low-pass filter made from two inductors and a
ca-pacitor.
Since this is a resonant circuit, care must be taken to ensure that no harmonics are close to the resonant frequency. In practice, this is easily accomplished for
PWM inverters by making the cutoff frequency fc sufficiently low compared to
the switching frequency.
18 3 Practical Considerations 2,000 3,000 4,000 5,000 6,000 7,000 8,000 9,000 10,000 11,000 12,000 13,000 14,000 15,000 16,000 17,000 18,0000 5 10 15 20 25 30 35 Switching frequency (Hz) THD (%)
Figure 3.2:THD of a five-level PWM inverter at different switching
frequen-cies when using a low-pass LC filter with a cutoff frequency of 2.25 kHz.
Fig. 3.2 shows a rapid decrease in distortion around fs = 2fc, and Fig. 3.3
shows similar results.
20000 3000 4000 5000 6000 7000 8000 9000 10000 11000 2 4 6 8 10 12 14 16 18 20 Cutoff Frequency (Hz) THD (%)
Figure 3.3: THD of a five-level PWM inverter at different cutoff frequencies
with a switching frequency of 12120 Hz.
All third-order filters of this type have a slope of −18 dB per octave, so a
cutoff frequency Fc ≈ Fs/4 will put the inverter well below the 5% THD mark
while keeping the filter’s resonant frequency away from any of the frequencies present on the output.
3.2 Conduction Losses 19
3.2
Conduction Losses
The first major source of power loss is the on-state conduction losses of the MOS-FET switches. Switching strategy has no effect on these losses, since the total
current through the inverter is ILfor both multilevel and PWM switching.
For both NPC and flying-capacitor inverters, the current passes through a maximum of m − 1 switches at a time. The total conduction loss can therefore be estimated as
Pon≤IL2Ron(m − 1). (3.1)
For switched-capacitor inverters, current goes through at most 3 + (m − 3)/2 switches, giving Pon ≤IL2Ron 3 +m − 3 2 . (3.2)
Switched-inductor inverters have 3 series switches regardless of the number of levels; however, a very large current will pass through the main switch while the inductor is being charged, resulting in very high power losses. This needs to be mitigated somehow for the design to be practically workable.
20 3 Practical Considerations
3.3
Switching Losses
One of the primary sources of parasitic power consumption in PWM inverters is switching losses. While these losses occur in pure multilevel inverters as well,
the switching frequency there is relatively low: fs = (m + 1)fo. At the relevant
voltage levels (hundreds of volts), switching losses therefore become negligible next to on-state conduction losses.
For PWM inverters, the switching losses become a major design consideration. A tradeoff must be made between switching losses, filter size, and output quality. Switching loss has two major sources: gate charge and conduction during the switching period.
3.3.1
Gate charge
The gate charge energy is simply the energy stored on the switch’s input
capaci-tance, Ciss. For power MOSFETs, this value is usually around 1-5 nF1, although
it may vary depending on the blocking voltage of the device. Energy stored on this capacitance will be
Eiss=
CissVDC2
2 . (3.3)
This portion of the switching energy is load-independent, and must be taken into account even if the device is idle (i.e not conducting).
3.3.2
Switch-conduction
The precise switching behaviour of a MOSFET is highly dependent on the oper-ating conditions as well as the specific device used. However, an approximation
can be found by using a linear model. Assuming Vgs= Vthgives
Vds = Vd−(Vg −Vth). (3.4)
Assuming the drain current Idrises linearly with gate voltage and reaches its
maximum when Vds= 0 gives
Id = IL
Vg−Vth
Vd
, (3.5)
where ILis the load current, Vg is the gate-to-neutral voltage, Vdis the (fixed)
drain voltage and Vthis the threshold voltage. This model is only valid in the
triode region (0 < Vg < Vd + Vth), but it is a decent approximation within that
interval (see Fig. 3.4). Since the device will always be in the triode region during switching, this limitation is not a problem.
3.3 Switching Losses 21 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 2 4 6 8 Time (us) Id 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 20 40 60 80 Time (us) Vgs
Figure 3.4:Comparison of the linear model (solid) with results from a SPICE
simulation (dashed).
With this model, power dissipation in the transistor is given by
Psw = IdVds= IL Vg −Vth−(Vg −Vth)2 Vd . (3.6)
Fig. 3.5 shows how the instantaneous power consumption rises during the switching period. 0 0.5 1 1.5 2 0 20 40 60 80 Time (us) Vg 0 0.5 1 1.5 2 0 2 4 6 8 Time (us) Id 0 0.5 1 1.5 2 0 20 40 60 Time (us) Vds 0 0.5 1 1.5 2 0 50 100 Time (us) Power (W)
22 3 Practical Considerations
Approximating the gate voltage as rising linearly, the total turn-on energy is
Esw= Ciss(VDC+ Vth)2 2 + IL t2 Z t1 VDCt t2−t1 −Vth− (VDCt) 2 VDC(t2−t1)2 dt. (3.7)
Taking the input capacitance Ciss and drive circuit resistance Rdrv into
ac-count, the total turn-on energy is
Esw= CissVDC2 2 + IL t2 Z t1 VDC(1 − e − t Rdrv Ciss) − Vth−(VDC(1 − e − t Rdrv Ciss) − Vth)2 VDC dt. (3.8)
where t1and t2are the times when the gate voltage reaches 10% and 90% of
its final value, respectively.
By symmetry, the turn-off losses are equal. The total switching power (for a
single switch) becomes 2Eswfs.
In a real application, the current being switched is nowhere near constant, due to stray inductances, non-unity power factor of the load, etc. This model is therefore only an order-of-magnitude estimation of the switching losses.
4
Implemented Architecture
4.1
Schematic
The chosen architecture is a 5-level PWM inverter with a 60 Hz output. It achieves low dV /dt and THD with a small number of components and a switching fre-quency of up to a few kHz. A complete list of the specific components used for the physical implementation can be found in appendix A.
Figure 4.1:Inverter block connections.
The gate driver, filter, controller and main inverter blocks are connected as
24 4 Implemented Architecture
shown in Fig. 4.1.
4.1.1
Inverter
The inverter uses two three-level diode-clamped phase legs (Fig. 4.2). In this configuration, five output levels can be achieved without concern for charge bal-ancing on the DC-link capacitors.
Figure 4.2:The proposed architecture, main part.
As discussed in section 2.2, each phase leg outputs ±VDC/2 or 0 V. If they are
controlled with SPWM using complementary sine waves (Fig. 4.3), the output
4.1 Schematic 25 0 2 4 6 8 10 12 14 16 −1 −0.5 0 0.5 1 Time (ms) Vc, Vm
Carrier and reference signals
0 5 10 15 0 0.5 1 Time (ms) Vo1 Phase leg 1 0 5 10 15 0 0.5 1 Time (ms) Vo2 Phase leg 2 0 2 4 6 8 10 12 14 16 −1 −0.5 0 0.5 1 Time (ms) Vo1−Vo2 Output
Figure 4.3:PWM generation for a two-legged inverter.
Using complementary legs in this way effectively doubles the switching
fre-quency; fs= 2ftwhere ftis the triangle wave frequency.
4.1.2
Gate Drivers
All switches used are N-channel MOSFETs; in order to turn them on, the
gate-source voltage Vgsmust exceed the threshold voltage Vth, typically around 2 V.
This poses a problem, since the upper source nodes will be at VDC when the
26 4 Implemented Architecture
+
−
Vdd
Vb
Vb2
Vb3
Vdc
Vs
Vs2
Vs3
Cb3
Cb2
Cb1
S4
S3
S2
S1
Figure 4.4:Connection of bootstrap capacitors.
To reach the higher voltages needed, a series of bootstrap capacitors are used
(Fig. 4.4). When the bottom switch S4is on, Cb3is charged through the diode to
Vdd; when S4is off and S3 is on, Cb2 is charged from Cb3. Cb1 is charged from
Cb2in the same way.
The bootstrap capacitors must be sized so that they are large enough to charge both the gate it drives and the bootstrap capacitors higher up in the chain [9].
In the case of a three-level diode-clamped circuit, the two upper switches
will need to be charged fs/2fo times during the half-period where the bottom
bootstrap capacitor is not charged from Vdd. It needs to hold enough charge
to do this without its voltage falling below Vth. With a MOSFET gate charge
Qg ≈ 70 nC, a drive supply voltage Vdd = 10 V, and fs = 6060 Hz, this gives
Cb1≥0.7 µF.
Since there is no functional downside to oversizing these capacitors, nor any
appreciable difference in cost or size, the sizes Cb1 = 10 µF, Cb2 = 22 µF and
Cb3 = 47 µF are chosen, allowing the device to operate over a wide range of
switching frequencies. More energy is needed to charge these large capacitors the first time, but the voltage drop during each discharge cycle will be smaller as well; the difference in bootstrap charging power is negligible.
4.1.3
Control
The PWM signals can be generated with a combination of comparators, tri-wave generators and sine generators. However, this approach would require hardware changes to test different output frequencies and control schemes. Due to this inflexibility, a microprocessor is used instead.
For the sake of simplicity, the microprocessor runs off a separate DC source rather than a stepped-down main input (as would be the case in an inverter with
4.1 Schematic 27 only one input). This should not notably affect the efficiency rating, as the micro-processor only consumes a few milliwatts.
The amplitude modulation is controlled either manually by an external con-trol mechanism, or automatically using the microconcon-troller’s built-in analog-to-digital converter. Fig. 4.5 shows how a voltage divider at the input can be used
to sense Vin; since there is a linear relationship between ma, Vin and Vout, this
allows voltage regulation with a simple P-control algorithm.
+5V
Vdd
A/D
Vss
Out
Inverter
DC+
DC-8
+
−
225V
Rin
Rdiv1
Rdiv2
Figure 4.5:Microprocessor connections.
Fig. 4.5 shows the connections to the microprocessor, using the voltage divider setup.
The switching frequency can be chosen almost arbitrarily by tweaking the con-trol program, as long as it is significantly smaller than the operating frequency
of the microprocessor. If fs is set too high, the waveform cannot be synthesized
properly.
4.1.4
Filter
As per section 3.1, a reactive filter is placed at the output. Choosing component sizes 0.56 mH and 22 µF gives a filter with the frequency response shown in Fig. 4.6.
28 4 Implemented Architecture
Figure 4.6: Frequency response of a T-section LC lowpass filter with C =
23 µF and L = 0.56 mH at low load. fc≈2 kHz.
Using fs= 12120 Hz, the first set of harmonics (near fs) should be dampened
by around 50 dB. The third harmonic (180 Hz) is not completely eliminated due to input ripple and imprecise switching, and will be slightly amplified by the filter. This amplification is less than 1 dB however, and should not affect device performance to a noticable degree.
4.2 Expected Results 29
4.2
Expected Results
To verify the accuracy of the models from section 3.2 and section 3.3, the be-haviour of the proposed architecture is predicted before it is simulated and im-plemented.
4.2.1
Ripple
With a sinusoidal output, the instantaneous power draw of the inverter will not be constant. More power is drawn during the peaks, as illustrated in Fig. 4.7.
Since VDCis constant, Iinmust increase when Pindoes, and vice versa.
0 2 4 6 8 10 12 14 16 −200 0 200 Time (ms) Vo 0 2 4 6 8 10 12 14 16 −5 0 5 Time (ms) IL 0 2 4 6 8 10 12 14 16 0 200 400 Time (ms) Pin
Figure 4.7: Instantaneous power draw of inverter, assuming unity power
factor and 100% efficiency.
This waveform has a fundamental frequency of 2fo = 120 H z. Since greater
power draw means a higher input current, this ripple appears on both Iinand Vin
(due to voltage drop over Rin). We define the input current ripple factor as
ri =
Iin,max−Iin,min
Iin,average
(4.1) and the input voltage ripple factor as
rv=
Vin,max−Vin,min
Vin,average
30 4 Implemented Architecture
The input current minimum is always 0 A, and since it is sinusoidal the
maxi-mum is twice the average value. Thus, ri = 200%.
Vin will never exceed VDC, and the minimum depends on the load and the
input resistance. With VDC = 225 V and Pload= 500 W, the average input current
will be 2.5 A. The input voltage minimum becomes
Vin,min= VDC−2RinIin,average= 225 V − 50 V = 175 V (4.3)
which gives rv = 25%.
However, the input resistance Rinand the DC-link capacitors form a low-pass
RC filter. With Rin= 10Ω and CDC = 250 µF, the 120 Hz oscillations are
damp-ened by about 50%. Higher frequency components of the ripple are almost com-pletely filtered out, and do not contribute meaningfully to the ripple factor.
We can expect a current ripple ri ≈100 % and voltage ripple rv .12.5 %.
4.2.2
THD
With the filter from section 4.1.4, the harmonics caused by the high-frequency switching are almost completely eliminated. Thus, the only remaining harmonics are those caused by non-ideal devices and input ripple. These distortions are difficult to model analytically since they depend on the interaction between the controller, the switches, and the rest of the circuit, but some estimations can be made. First, the distortions caused by inexact switching (due to propagation delay, rise/fall times, etc.) are unlikely to have a significant impact, as they will
be of very high frequencies ( fs) and thus filtered out.
The input voltage ripple is a 120 Hz sinusoid. Since the output voltage is directly proportional to the input, taking the input ripple into account gives us an output of:
Vo,ripple = Vo
rvsin (120 × 2π) + 1
2 . (4.4)
This adds an unwanted third harmonic (as well as some irrelevant high-frequency ones). The value of this harmonic relative to the fundamental will be
S3= S1
rv/2
1 + rv/2
. (4.5)
Assuming 10% voltage ripple, the THD of Vo will be approximately 4.7%.
4.2.3
Efficiency
Using the approximations from section 3.2 and section 3.3, the efficiency of the inverter can be estimated. The switches used for the 225 V-450 V inverter have an
on-state resistance Ron ≈0.5Ω, input capacitance Ciss≈1.6 nF and a threshold
voltage Vth ≈ 3.9 V. Each device blocks VDC/2 and has an effective switching
4.2 Expected Results 31
The outer switches conduct ILwhile switching; the inner switches conduct IL
during the half-period where they are held in the on-state. While switching, the drain current is small and the switch-conduction losses can be neglected.
Plugging these numbers into eq. (3.1) and eq. (3.8) gives the efficiency esti-mates in table 4.1.
VDC Pload Estimated efficiency
450 V 2000 W 93.3%
450 V 1000 W 96.3%
450 V 500 W 97.8%
225 V 500 W 93.3%
225 V 250 W 96.4%
Table 4.1:Efficiency estimates.
At the frequency used, switching losses account for 3-8% of the total losses. Efficiency appears to improve as the load decreases, but this effect is likely lim-ited. The gate charge portion of switching losses does not scale with the load, and puts minimum energy requirement on the inverter even when driving no load.
32 4 Implemented Architecture
4.3
Simulation Results
The proposed architecture was tested in National Instruments MultiSim with a few different loads. The results are shown in table 4.2. The output was 240 V and 120 V for inputs of 450 V and 225 V, respectively.
Load Power Factor VDC THD Efficiency Ripple (I) Ripple (V)
< 1 W 1 450 V 3.92% 0.38% 1584% 2.43% 500 W 1 450 V 3.05% 93.13% 128% 3.60 % 1000 W 1 450 V 2.83% 94.46% 104% 6.01% 2000 W 1 450 V 4.04% 93.01% 96% 12.59% 2000 VA 0.7 450 V 3.94% 92.87% 114% 9.90% < 1 W 1 225 V 3.44% 0.23% 932% 2.41% 250 W 1 225 V 2.71% 93.17% 103% 6.04% 500 W 1 225 V 3.86% 92.41% 95% 12.56%
Table 4.2:Simulation results.
Table 4.2 shows the inverter performance under various operating conditions. When checked against the requirements in appendix B, THD is acceptable while efficiency falls just short of the desired 95%. Losses may be reduced i.e. by par-allelling switches, so the ripple factor is the most severe point of failure. Simply increasing the size of the DC-link capacitors would work, though the physical size of the inverter would increase dramatically.
At low loads, the switching losses are dominant; since they do not scale with the load current, this results in very low efficiency. At < 1 W this is not a cause for concern, however. The extremely large input current ripple factor at low loads is not unexpected, given that the absolute value of the current is so small.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0 1 2 3 4 5 6 7 8 9 10 Harmonic Magnitude (% of fundamental)
Figure 4.8: Harmonic spectrum of simulation output at 225 V, 500 W,
zoomed to make the smaller harmonics visible.
4.3 Simulation Results 33
section 4.2; the models used appear to be accurate. Fig. 4.8 shows that the third harmonic (caused by input ripple) is the largest, as expected.
The efficiency estimates, on the other hand, were less reliable. While seem-ingly accurate at maximum load (predicting 93.3% in both cases), accuracy drops off as the load is reduced. This is likely because the filter is connected, causing the inverter to "see" its power factor rather than that of the load. Hence, the currents being switched are not as predictable as assumed, and the estimates are off.
5
Results
5.1
Physical Implementation
The final implementation (minus the output filter) fits on a 10x16 cm prototype
board (Fig. 5.1). The filter (fc≈2 kHz), consisting of two 0.56 mH inductor coils
and one 22 µF film capacitor, takes up slightly less than half of an identical board.
Figure 5.1:Physical implementation of a power inverter.
Roughly half the board is occupied by the control and drive ICs. The DC-link
36 5 Results
capacitors take up a hefty portion of the rest; to improve matching between the top and bottom DC-link capacitance, five parallel capacitors are used instead of a single large one.
Since the microcontroller and gate drivers run on different voltages (5 V and 10 V, respectively), level shifters are used between the microprocessor output and the gate driver logic input.
5.1.1
Control
The control signals are generated from an 8-bit 8 MHz Atmel CPU. The reference sine wave is taken from a lookup table with 1024 samples; the triangle wave has
16 samples per period. This gives ft = 64fo ≡ fs = 128fo. For this prototype,
fo= 61.8 Hz, so fs = 7910 Hz.
The automatic voltage regulation was not implemented, and mais fixed at 1.0.
This is because the internal resistance of the lab voltage source is too small to cause any noticeable voltage drop before the inverter input. For the same reason,
5.2 Output Behaviour 37
5.2
Output Behaviour
Due to equipment availability and safety reasons, the physical implementation was not tested under (or built for) the full-load conditions of 225 V DC input and
120 V RMS output. It was instead tested under low-power conditions: VDC =
20 V DC and Vo = 14.1 V RMS AC.
The unfiltered output and its spectrum are shown in Fig. 5.2 and Fig. 5.3.
0 5 10 15 20 25 30 −50 0 50 Time (ms) Vo 32.36% THD, 14.76 V RMS
Figure 5.2:Unfiltered voltage output, no load.
0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 Frequency (kHz) Magnitude (V)
Figure 5.3:Unfiltered voltage frequency spectrum, no load.
The five-level waveform is correctly synthesized, though the PWM is difficult to see in the figure due to the overshoot that occurs when switching. THD is slightly larger than it would be with ideal switching (Fig. 6.1), but this is not especially surprising.
Connecting the filter, but not a load resistor, gives the output shown in Fig. 5.4 and Fig. 5.5.
38 5 Results 0 5 10 15 20 25 30 −30 −20 −10 0 10 20 30 Time (ms) Vo 6.71% THD, 13.92 V RMS
Figure 5.4:Filtered voltage output, no load. The dashed line shows the
fun-damental frequency component.
0 1 2 3 4 5 6 7 8 9 10 0 2 4 6 8 10 12 14 16 18 20 Frequency (kHz) Magnitude (V)
Figure 5.5:Filtered voltage frequency spectrum, no load.
While THD is a bit greater than preferred, it is still low enough for most non-sensitive applications. Most distortions are located below 2 kHz, since that is the cutoff frequency of the output filter. The "switching spikes" are still present, but are much smaller.
Fig. 5.6 shows the filtered output voltage when a 30Ω resistor is connected
at the output. Since there is now an actual current through the switches, THD is increased and there is some power lost. The location of the distortions is un-changed.
5.2 Output Behaviour 39 0 5 10 15 20 25 30 −30 −20 −10 0 10 20 30 Time (ms) Vo 7.02% THD, 13.04 V RMS
Figure 5.6: Filtered voltage output, 30Ω load. The dashed line shows the
fundamental frequency component.
The input current was just below 0.3 A, so Pin≈6 W. Vo = 13.04 V RMS, so
we have Pout Pin = 13.04 2V 30Ω × 6 W ≈94.5%. (5.1)
A small amount of power also goes to the microprocessor, level shifter, and microprocessor circuits, which were connected to separate DC sources. This is only a few milliwatts, however, and does not scale with the load. Hence, this term can be safely disregarded in the efficiency calculations.
6
Conclusions
6.1
Discussion
Of the examinded topologies, the NPC and flying capacitor inverters were found to have the best tradeoff between performance, cost and size; while the SC and SL topologies could be implemented with fewer total components, the charge imbalance issue renders them impractical.
For the implemented prototype, the low voltage rating of the power MOSFETs is the largest limitation of the device as-is. Exchanging those should allow it to work at DC-link voltages of at least 225 V, as simulated.
Estimation Simulation Measurement
THD 4.7% 3.85% 7.04%
Efficiency 93.3% 92.41% 94.5%
Table 6.1:Comparison between estimation, simulation and measurement.
Table 6.1 summarizes the differences between estimates, simulation results, and measurements on the prototype.
Efficiency matches the simulations well, though it is likely to be reduced at higher power levels as the components get hotter and have higher resistance.
Due to the discretization of the control signals, the inverter output is slightly more distorted than expected. The third harmonic caused by input ripple is miss-ing entirely; the low-frequency distortions that remain are caused by non-ideal components and parasitic inductances in the circuit.
Fig. 6.1 shows that while the quantization of the control signals only adds about 2% extra THD, these extra distortions are spread evenly throughout the spectrum and will not be completely filtered out.
42 6 Conclusions 0 2 4 6 8 10 12 14 16 18 20 0 20 40 60 80 100 Quantized: 29.01% THD Frequency (kHz) Mag (% of fundamental) 0 2 4 6 8 10 12 14 16 18 20 0 20 40 60 80 100 Ideal: 26.96% THD Frequency (kHz) Mag (% of fundamental)
Figure 6.1: Frequency spectrum of SPWM with quantized and ideal
refer-ence signals.
Because of the lack of ripple and the quantization distortions, the THD es-timates from section 4.2.2 are not accurate for this device. Some improvement could be made by tweaking the filter, since the majority of the remaining distor-tions are below the cutoff frequency.
Implementing the automatic voltage control algorithm would likely require a different microprocessor, since the one used has barely enough time to generate the control signals during each period. Adding a few more multiplications to the loop would require further quantization of the control signals, which would further reduce the output quality.
6.2 Future Work 43
6.2
Future Work
While several modulation methods have been discussed in this thesis, only one was implemented. With a better microcontroller, the prototype that was built could be used to compare several different switching methods on a physical cir-cuit, e.g. the 5-level SHEPWM introduced in [10] or the space-vector modulation method from [11].
Another natural progression would be to complete the prototype to work un-der the Little Box conditions and seeing how this affects performance.
A more thorough evaluation of the topologies that were not used for this the-sis is also in order; in particular, a switched-capacitor inverter could feasibly be constructed with enough output levels to eliminate the need for an output filter. The impact of the necessary voltage balancing circuits would need to be evalu-ated.
Lastly, resonant-switch converters made for resistive loads as in [12] can offer significant efficiency improvements if adapted to multilevel inverters.
A
Component List
Name Purpose # used
EEU-ED2C101 DC-link capacitor, 100 µF 10
ECA1VAM470X Bootstrap capacitor, 47 µF 2
EEUFM1H220 Bootstrap capacitor, 22 µF 2
25ML10MEFC4X5 Bootstrap/decoupling capacitor, 10 µF 3
R60IR52205000K Filter film capacitor, 22 µF 1
MCAP115018077A-561LU Filter inductor, 0.56 mH 2
ATMEGA328-PU Microcontroller 1
IR2117PBF High side gate driver 4
IR2110PBF High/low side gate driver 2
CD40109BE Logic signal level shifter 2
IRF3708PBF Main switching device 8
MUR820 Clamping diode 4
STPS1150RL Bootstrap diode 6
B
Little Box Requirements
Parameter Requirement
Maximum load 2 kVA
Load power factor 0.7 − 1, leading and lagging
Volume < 655.3 cm3
Rectangular dimensions > 1.27 cm, < 50.8 cm
Voltage input 450 V DC in series with 10Ω
Voltage output 240 ± 12 V RMS, single phase
Output frequency 60 ± 0.3 Hz
Output THD (voltage) < 5%
Output THD (current) < 5%
Efficiency > 95%
Input ripple (voltage) < 3%
Input ripple (current) < 20%
Outside temperature < 60◦C
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