MOSFET Packaging for Low Voltage DC/DC Converter : Comparing embedded PCB packaging to newly developed packaging

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Master of Science Thesis in Electrical Engineering

Department of Electrical Engineering, Linköping University, 2020

MOSFET packaging for low

voltage DC/DC converter

Comparing embedded PCB packaging to

newly developed packaging

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Master of Science Thesis in Electrical Engineering

MOSFET packaging for low voltage DC/DC converter: Comparing embedded PCB packaging to newly developed packaging

Emil Dahl

LiTH-ISY-EX--20/5275--SE Supervisor: Tomas Uno Jonsson

isy_{, Linköping University}

Magnus Karlsson

Flex Power Modules

Mikael Appelberg

Flex Power Modules

Examiner: Mark Vesterbacka

isy_{, Linköping University}

Division of Integrated Circuits and Systems Department of Electrical Engineering

Linköping University SE-581 83 Linköping, Sweden

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Abstract

This thesis studies the options of using PCB embedding bare die power MOSFET and new packaging of MOSFET to increase the power density in a PCB. This is to decrease the winding losses in an isolated DC/DC converter which, according to "Flex Power Modules", can be done by improving the interleaving between the layers of the transformer and/or decreasing the AC loop. To test the MOSFET packaging two layout are made from a reference PCB, one using embedded MOS-FET and the other using the new packaging. The leakage induction and winding losses are simulated and if they are lower compared to the reference PCB proto-types are manufactured. The simulated result is that PCB embedded MOSFET decrease the leakage induction but the winding loss is higher. With the new packaging the leakage induction is higher and the winding loss has linear char-acteristics. Only the PCB with the new MOSFET packaging is made because the MOSFET die gate pad is too small for the PCB manufacturer to make a via connec-tion to it. The PCB is tested that it operates as a DC/DC converter with a 40-60 V input and a 12 V output. The PCB is put on a test board in a wind-tunnel to test its characteristics under different wind speeds, input voltage and loads. The result is that the PCB has a higher efficiency than the reference PCB but it has worse thermal resistance. Further development of the design needs to be made to improve the thermal resistance. Using new packaging is a way to continue the development of power converter with lower efficiency but embedding MOSFET needs a less complicated manufacturing process before there is any widespread usage.

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Acknowledgments

I would like to thank my supervisors who have helped me during this thesis work. Linköping, April 2020

E D

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3 Theory 9 3.1 Transformer loss . . . 9 3.1.1 Leakage inductance . . . 9 3.1.2 Core loss . . . 10 3.1.3 Winding DC loss . . . 11 3.1.4 Skin depth . . . 11 3.1.5 Proximity effect . . . 12 3.2 Isolated DC/DC converter . . . 15 3.3 Thermal resistance . . . 16 4 Method 19 4.1 Layout . . . 19 4.2 Simulation . . . 22 4.2.1 DC simulation . . . 22 4.2.2 Electromagnetic simulation . . . 22 vii

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viii Contents

4.2.3 Small-signal simulation . . . 25

4.2.4 Thermal simulation . . . 25

4.3 Output induction simulation . . . 26

4.4 Measurement . . . 27 4.4.1 Electrical verification . . . 27 4.4.2 Quality verification . . . 28 5 Result 29 5.1 Layout . . . 29 5.2 DC-simulation . . . 30 5.3 Electromagnetic simulation . . . 30 5.3.1 Current distribution . . . 30 5.3.2 Winding loss . . . 31 5.3.3 Leakage inductance . . . 33 5.4 SPICE simulation . . . 34 5.5 Thermal simulation . . . 35 5.6 Inductor simulation . . . 36 5.7 Manufacturing . . . 38 5.8 Measurements . . . 38 5.8.1 Electrical verification . . . 39 5.8.2 Wind tunnel . . . 39 6 Discussion 41 6.1 Leakage inductance . . . 41 6.2 Winding loss . . . 42 6.3 Thermal simulation . . . 42 6.4 Current distribution . . . 43 6.5 Manufacturing of embedded PCB . . . 43 6.6 Measurements on new PCB . . . 43 7 Closing comment 45

A Thermal performance of new PCB 49

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List of Figures

2.1 A MOSFET packaging with copper clip. . . 6

2.2 A manufacturing process for embedded components. . . 7

2.3 A manufacturing process for embedded components. . . 7

3.1 Transformer model with leakage inductance L1and L2 . . . 10

3.2 Transformer . . . 12

3.3 Interleaved transformer. . . 14

3.4 MMF diagram for the interleaved transformer. . . 14

3.5 Two phase full bridge isolated DC/DC . . . 15

4.1 Schematic for the rectifier. . . 20

4.2 Stackup of the layout. . . 21

4.3 Schematic model for "Comsol Multiphysic" simulation for winding loss. . . 23

4.4 Schematic model for "Comsol" simulation for leakage inductance in phase A. . . 24

4.5 Schematic model for "Comsol" simulation for leakage inductance in phase B. . . 24

4.6 Schematic of the AC resistance in the winding. . . 25

4.7 H-B characteristic of the ferrite material used. . . 27

4.8 Wind tunnel used for stress test. . . 28

5.1 Primary side winding loss. . . 31

5.2 Secondary side winding loss. . . 32

5.3 Total winding loss. . . 32

5.4 Leakage inductance phase A. . . 33

5.5 Leakage inductance phase B. . . 33

5.6 Temperature distribution over the PCB. . . 36

5.7 Current density in the output inductor winding . . . 37

5.8 Magnetic flux density inside the core . . . 37

5.9 Picture of the manufactured PCB. . . 38

5.10 Efficiency of module at a temperature of 23±5◦ C. . . 39

5.11 Efficiency of module in wind tunnel. . . 40

5.12 Thermal resistance of the module with heat sink and test board. . 40

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x LIST OF FIGURES

A.1 Thermal resistance of the module with heat sink excluding pins. . 49 A.2 Thermal resistance of the test board. . . 50 A.3 Thermal footprint of the module with test-board and heat-sink. . . 50

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List of Tables

5.1 Drain current for MOSFETs (TXXX) at different frequencies. . . . 30 5.2 Drain current for MOSFETs (TXXX) at different frequencies. . . . 31 5.3 Power losses from SPICE simulation. . . 34 5.4 Simulated temperatures in reference PCB. . . 35 5.5 Simulated temperatures in embedded PCB. . . 35

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Notation

Abbreviations

Abbreviation Meaning

ac _{Alternating Current}

cte Coefficient of Thermal Expansion dc Direct Current

dosa Distributed-power Open Standards Alliance emi Electromagnetic Interference

fem Finite Element Method

igbt Isolated Gate Bipolar Transistor mmf Magnetomotive Force

mosfet Metal-Oxide Semiconductor Field Effect Transistor nda _{None Disclosure Agreement}

pcb _{Printed Circuit Board} pth _{Plated Trough Hole} rms _{Rote Mean Square}

smps _{Switching Mode Power Supply}

spice _{Simulation Program with Integrated Circuit Emphasis} wbg Wide Band Gap

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1

Introduction

With the increasing need for smaller feature size in electronics the interest for Printed Circuit Board, PCB, embedded components have increased [2]. An em-bedded component is a component that has been inserted between the metal lay-ers inside a PCB. This frees up space on the surface of a PCB and the embedded component has less parasitic compared to a corresponding surface mounted com-ponent. This thesis studies the option of embedding power Metal Oxide Semi-conductor Field Effect Transistors, MOSFETs, used as a rectifier in an isolated DC/DC converter and comparing it to using surface mounted MOSFETs with a package that uses a clip for connection.

1.1 Motivation

An isolated Direct Current, DC, to DC converter with a 40 to 60 V input and a 12 V output was designed by "Flex Power Modules" on a PCB with the Distributed-power Open Standards Alliance, DOSA, quarter brick standard for isolated Distributed-power modules [1]. The converter is galvanic isolated using a planar PCB transformer and the secondary side rectifier is an active H bridge rectifier where each group of transistors consist of four MOSFETs in parallel to decrease the drain source on resistance. Simulation of the transformer’s winding loss showed that it becomes smaller if the Alternating Current, AC, loop to the rectifier is shorten and the in-terleaving between the primary and secondary side are improved. To have a short AC loop the MOSFETs for the rectifier should be put as compact as possible.

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2 1 Introduction

The MOSFETs can be put more compactly if the number of MOSFETs in parallel decreases. But this has the disadvantage of increasing the on resistance. "Flex Power Modules" have recently got a new MOSFET that has a lower on resistance. Using this MOSFET in the rectifier the number of transistors in parallel can be decreased while not increasing the on resistance. One added benefit of using less MOSFETs in parallel is that the parasitic capacitance decreases which lowers the rise and fall time. What needs to be evaluated is how much this decreases the winding loss and if it has any added benefit in the converter.

Using another kind of MOSFET packaging is not the only option for shortening the AC loop. In recent time the development of embedded components for power electronic have increased [2]. By paralleling embedded bare die MOSFETs in the PCB and surface mounted MOSFETs the second side rectifier can be stacked in different layer of the PCB which increases the high-power density and frees up surface space on the PCB.

The issue with embedded component is that the manufacturing process is not as well developed compared to surface mounted components [9]. Embedded com-ponent increases the power density inside the PCB and the prepreg that is used to separate the PCB’s metal layers have a low thermal dissipation increasing the dif-ficult of extracting the heat from the MOSFETs which can lower their efficiency. Embedded component is also exposed to more mechanical stress than the sur-face mounted component. For sursur-face mounted component the pressure from the difference in Coefficient of Thermal Expansion, CTE, between the packaged MOSFET and the PCB is only on one side of the component. The CTE effects the solder pads that the MOSFET is soldered onto and over time, with changing cur-rent and heat, cracks will start to accumulate in the solder and the resistance will increase lowering the efficiency. In an embedded component the pressure from difference in CTE is from all direction, increasing the pressure it is exposed to and possible breaking the MOSFET die. The pressure also effects the connection the bare die has to the layers.

Embedded bare die components are uncommon in power electronics because of these issues. A comparison between embedded bare die and surface mounted component needs to be made to evaluate the benefits and disadvantage of using them in power electronics.

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1.2 Purpose 3

1.2 Purpose

The purpose of this thesis is to study how the winding loss in a transformer for a low voltage isolated DC/DC converter changes with a shorter AC loop by either using embedded FETs or another type of packaging for the FETs. The thesis also studies if embedded component can be used today in power electronics and what challenges there is to use them.

1.3 Problem definition

The questions this report is going to answer is:

• Can embedded or new packaging of MOSFETs be used to reduce the wind-ing loss and leakage inductance of a transformer in a low voltage isolated DC/DC converter?

• Does embedded MOSFETs reduce the mechanical reliability of a power module?

• Can embedded or new packaging MOSFETs in a low voltage isolated DC/DC converter improve the efficiency?

• Should a PCB with embedded bare die MOSFET be designed and manufac-tured or should there be a push to improve packaging of surface mounted MOSFET?

1.4 Delimitation

This paper focus on MOSFETs for a second side rectifier in a low voltage isolated DC/DC converter, the result can therefore not be applied to every power module or small-signal electronics. The focus is on how the winding loss and leakage inductance changes in a transformer and how embedded MOSFETs changes the reliability of the module. In low voltage power module the creepage and the clearance is not of high importance [20].

The MOSFET with a new packaging that "Flex Power Modules" have acquired is under Non-Disclosure Agreement, NDA, and there will be no detailed descrip-tion of its specificadescrip-tion or footprint. This thesis only studies how the power mod-ule where it is used performs.

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2

Related work

With the need for higher switching frequency and power density the packaging of the MOSFET is important to get low parasitic, low power loss and small size. One solution is PCB embedded 3-d MOSFETs. Development has been done on embed-ding MOSFETs and what effects it has on the component [2], written about in this chapter. There is also some discussion on vias which is connections between PCB metal layers. There are different categories for vias. Micro vias are solid with copper and only connects two layers. Buried vias are connected to multiple layers except for the surface ones and are copper plated and filled with prepreg. Plated-Through Holes, PTH, vias connect all layers and are copper plated. PTH vias are also in this thesis always copper plated on the top and bottom to be able to add solder pads directly over them and is filled with prepreg.

2.1 Embedded components

There have been a lot of work done on embedding component in PCB including resistors, inductors, capacitors and active components like transistors. There are two types of embedded components. The first is to insert a finished component into the PCB during the manufacturing process. The other type is making the component while making the PCB, for instant changing the material for a trac-ing to increase the resistance [2]. This is called inserted component and formed component respectably. Embedded resistors are a well-established technology and embedded inductor, capacitors and transistors are being developed. Unlike embedded inductor and capacitors that have been able to handle power up to a few watts, embedded transistors have been shown to handle power up to

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6 2 Related work

sands of watts. This section describes some of the results from having transistors embedded in the PCB and what challenges there is.

2.1.1 Embedded MOSFETs

With the ever-increasing need for compact power electronics and the introduc-tion of Wide Band Gap, WBG, components the packaging that enclose the MOS-FETs have become a bottleneck. Some common package technology used are wire-bonding out of aluminum, copper clip (see figure 2.1), and flip-chip connec-tion.

Figure 2.1:A MOSFET packaging with copper clip.

The package is soldered onto the surface of a PCB using solder pads. Both the connection method and the solder increase the resistance and parasitic compo-nents of the MOSFET which is detrimental for WBG that requires low parasitic to work optimally and the package increase the size of the components [11]. Us-ing a 3-d embedded MOSFET that is put between the metal layers of the PCB and connected with micro vias can both free up space and have a lower resistance and parasitic. They have been used in small-signal electronics but is uncommon in power electronics because of difficult in thermal management.[2]

There are different ways of manufacturing PCB with embedded MOSFET. One way is to solder the bottom side of the MOSFET die onto a copper layer and add laminate through vacuum heating [14]. The laminate encapsulates the MOSFET and acts as the case. For making the vias connecting to the top side of the die the prepreg is laser drilled and filled with copper through an electroplating process before the copper layer above is added. See figure 2.2 for a description of the manufacturing.

Another way of manufacturing is to start by enclose the MOSFET die on the side with laminate and add prepreg on the top and bottom side. Micro vias are formed by using laser drilling and copper filling from both the top and bottom side. The prepreg with the embedded MOSFET die is then attached to a copper layer and another is added on top, see figure 2.3 [12].

The development of embedded components have mostly been done in Europe and Japan [2]. The European project lead by "Empower", a part of "AT&S", is

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de-2.1 Embedded components 7

Figure 2.2:A manufacturing process for embedded components.

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8 2 Related work

veloping embedded MOSFET, Isolated Gate Bipolar Transistor, IGBT, and power diodes. In their demonstration they showed that the design could handle 500 temperature cycles and had a thickness of 0.5 mm [16]. There next goal is to make embedded components for 500 W.

2.1.2 Embedded MOSFETs and CTE

The prepreg that encapsulate the embedded component have bad heat transfer making it hard to use embedded component in high power modules where tem-peratures can get high. A good heat transfer is important for embedded compo-nent because of to the difference in CTE of the different materials. When the temperature rises the materials in the PCB expands differently which increase the pressure on embedded components which can break them. Micro vias can also degrade from the strain. A 2D simulation showed the strain in an embedded die with micro via connections when the temperature was cycled between 125◦C and -55◦C [3]. The result showed that most of the strain is in the corners of the die and the outer micro vias. The lifetime estimate of the micro vias was 2200 cycles which was greater than the estimate for a solder joint, 260 cycles.

The heat transfer can be improved by adding vias connection to the surface layers of the PCB where the cooling is [11]. The thermal resistance from ambient to junction can be lowered with 10 % if vias with a thermal conductivity of 401 W/mK is used. Another way is to embed heat pipes in the PCB that can transfer the heat [6]. Heat pipes are copper pipes that contains a liquid. When the PCB is heated up the liquid in the pipes evaporates and start to move to a part of the pipe that is cooler. There it condenses back into liquid and through the capillary effect the liquid is transported back to where it evaporated creating a cooling mechanics for that point in the PCB.

Simulation and measurement on the thermal resistance of a three phase inverter bridge with embedded MOSFET and the same power module but with surface mounted MOSFET found that there were no greater changes in the thermal resis-tance between the two modules [17].

2.2 Parasitic and packaging

In power electronics it is better to have as high switching frequency as possible to be able to shrink the core for inductor and transformer without saturate them. But with higher switching frequency the power loss from the parasitic induction increases. It also creates voltage spikes that can shorten the lifetime of the compo-nent [20]. The packaging of the MOSFET should therefore add as little parasitic inductance as possible. To lower the parasitic inductance the general guideline when designing a PCB is to have wide and short connection to the die.

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3

Theory

This chapter starts with transformer theory and the reasons behind transformer power loss and how it can be lowered. Second part is dedicated to explaining the design of the isolated DC/DC converter used in this thesis and what benefits and disadvantages there is to it.

3.1 Transformer loss

A transformer is a passive electric component that transform alternating current on the primary side into a magnetic flux which induce an alternating current on the secondary side [8]. The ratio between the current on the secondary and primary side is equal to the ratio between the number of turns on the primary side and secondary side. With the transformer a DC/DC converter input and output can be electrical isolated which increase the safety of the component and lowers the Electric Magnetic Interference, EMI. In an ideal transformer the power loss should be zero but from different effects there is always an efficiency less than one.

3.1.1 Leakage inductance

In all transformers some of the magnetic flux does not get converted back into current in the secondary winding but is instead leaked into the air resulting in a power loss [8]. The leaked flux can be model with an inductor in series with an ideal transformer, see figure 3.1. The lower the inductance the more ideal is the transformer.

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10 3 Theory

L1

LM

L2

Figure 3.1:Transformer model with leakage inductance L1and L2

A transformer with very high turn ratio will have a high leakage inductance [5]. The leakage inductance will also increase the voltage and current spikes which lowers the reliability and lifetime of the module it is used in.

3.1.2 Core loss

In the core of the transformer some of the power is lost as heat [8]. The energy in a transformer’s winding per cycle can be calculated using 3.1. Using Ampere’s and Faraday’s law the equation can be written as 3.2.

W = Z one cycle v(t)i(t)dt (3.1) W = Z one cycle (nAc dB(t) dt )( H(t)lm n )dt = Aclm Z one cycle H dB (3.2)

The power loss in the core is equal to the energy loss per cycle 3.2 times the frequency of the current. This power loss is called hysteresis loss.

PH= f Aclm

Z

one cycle

H dB (3.3)

Hysteresis loss is not the only loss in the core [8]. From the alternating mag-netic flux that passes the core eddy current is induced, circulation in the core and energy is lost as heat. With higher frequencies the eddy current increases and therefore the power loss also increases. The eddy current in the core can be

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low-3.1 Transformer loss 11

ered by using a material that has a high resistance. The problem is that material with a high resistance has a low saturation flux density. The core then needs to increase in volume or the frequency of the current in the transformer needs to in-crease both of which inin-creases the power loss. What material to use for the core depend on the situation the core is going to be used in.

In power converters the cores most used are powder cores made of ferromagnetic particles bound using an insulated material [8]. They are suited for power con-verters because of the insulated material lower the power loss which is important in high power because of cooling. The saturation flux density is between 0.3 and 0.5 T which means that the operating frequency needs to be 100 kHz or higher for powder cores to be effective. Usually the goal in designing Switching Mode Power Supply, SMPS, is to have as high of switching frequency as possible to be able to decrease the size of the cores and in that way increase the power density.

3.1.3 Winding DC loss

The winding in the transformer is an electrical wire and like most wires there is a DC resistance to them that depends on the used materials resistivity ρ, the length of the wire lband the area the current pass through Aw[8]. The DC resistance is

calculated with equation 3.4.

RDC = ρ

lb

Aw

(3.4)

The material resistivity changes with the temperature. For copper wire the resis-tivity is 1.724 µΩ-cm at room temperature and 2.3 µΩ-cm at 100◦

C.

3.1.4 Skin depth

In the winding the alternating current creates a time varying magnetic flux that induce eddy current in the wire [8]. The eddy current reduces the current in the center of the wire and increases it at the outer edges of the wire. The measure-ment of how deep the current is in the wire is measured in skin depth δ and is calculated using equation 3.5. From the equation the skin depth can increase by lowering the frequency or having a material with high resistivity and low perme-ability µ.

δ = r

ρ

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12 3 Theory

At room temperature the function for the skin depth of copper is approximately

δ = 5.2

pf cm (3.6)

At 100◦C it is:

δ = 7.5

pf cm (3.7)

If the frequency is put to 100 kHz the skin depth is about 24 mm at 100◦C.

3.1.5 Proximity effect

A large part of the power loss happens because of the proximity effect [8]. The phenomenon is explained using an example. A transformer has two layers on the primary side and two layers on the secondary side, see figure 3.2. The current that passes in layer one i(t) creates an eddy current in layer 2 that circulate in that layer. Because layer one and layer two are in series the total current in layer two needs to be the same as in layer one. The currents in layer two is then 2i(t) going in one direction and i(t) going in the opposite direction.

i(t)

Primary side Secondary side layer 1 layer 2 layer 2 layer 1

Figure 3.2:Transformer

If the Root Mean Squire, RMS, of i(t) is I and the resistance in all layer is R the power loss in layer one is P1 = I2R. For layer two the power loss is P2 =

I2R + (2I)2R = 5I R = 5P1, five times larger than in layer one. The same process

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3.1 Transformer loss 13

The equation used to calculate the power loss in each layer 3.8 is derived from Maxwell’s equation. The I is RMS of the current in the layer, Rdc is the dc

resis-tance and φ is the ratio between the width of the layer and the skin depth.

P = I2RdcφQ 0 (φ, m) (3.8) The function Q0(φ, m) is Q0(φ, m) = (2m2−_{2m + 1)G}₁_{(φ) − 4m(m − 1)G}₂_(φ) _(3.9) G1(φ) and G2(φ) are G1(φ) = sinh(2φ) + sin(2φ) cosh(2φ) − cos(2φ) (3.10) G2(φ) =

sinh(φ) cos(φ) + cosh(φ) sin(φ)

cosh(2φ) − cos(2φ) (3.11)

The constant m is the ratio in Magnetomotive Force, MMF, (F) to the layer ampere-turns and can be calculated for each layer using equation 3.12 where F(0) is the MMF in one side of the layer and F(h) is the MMF on the other side of the layer. The side of layer that F(h) correspond to is always the side with the greatest mag-nitude.

m = F(h)

F(h) − F(0) (3.12)

The way to compensate for the proximity effect is to interleave the primary and the secondary layers [8]. The current in the secondary layers is in the opposite direction of the primary layer. The MMF is then counteracted between the layers. For an example figure 3.4 shows the MMF for the interleaved transformer 3.3. The ratio between the primary and secondary layers are 2:1, the current in the secondary layer is therefore 2i(t) if the current in the primary layer is i(t).

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14 3 Theory

i(t) i(t) 2i(t) 2i(t) i(t) i(t)

m =1 m =2 m =2 m =2 m =2 m =1 Figure 3.3:Interleaved transformer.

−₂ −₁ 1 2 x F(x)

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3.2 Isolated DC/DC converter 15

3.2 Isolated DC/DC converter

There are many designs for DC/DC converters dependent on the situation they are used in [8]. In high power system like the electric grid or server centers it is important to isolate the input and output to increase safety and lower EMI. It is also required in power adapters etc. according to International Electrotechni-cal Commission, IEC [19]. Isolation have been done using inductance-coupling, capacitive coupling and optical solutions. This chapter is focused on describing a full bridge DC/DC converter that uses inductive coupling. The benefits of us-ing this converter is its low mass compared other isolated converters that uses inductive-coupling and moderate efficiency in high power applications [15]. Figure 3.5 shows a design for a two phase full bridge DC/DC converter. When it is operating as a buck converter the transistors Q1 and Q4are switched together

and the same is for transistors Q2and Q3[7]. No control for the MOSFETs on the

secondary side is need because of the diode creates a rectifier but they should be switched to work as a rectifier to lower the resistance over the transistors.

− + _V in Q1 Q2 Q3 Q4 L C ₋+ Vout

Figure 3.5:Two phase full bridge isolated DC/DC

The cycle starts by having Q1 and Q4 on and the rest of the transistors off the

voltage over the transformers secondary side is 3.13 which leads to the inductor having the voltage 3.14.

vts=

n2

n1

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16 3 Theory

vL=

n2

n1

Vin−Vout (3.14)

The transistors are turned off the voltage over the inductor is −Vout. After that

Q2and Q3is turned on and the voltage over the inductor is turned back to 3.14.

The cycle ends by having all transistors turned off again. Because the inductor is in steady state the current should always go back to the same value. The integral over one cycle is therefore zero and the ratio between output and input voltage can be calculated using equation 3.15 where D is the duty cycle for the transistors. The duty cycle is less than 0.5 but because of switching delays in the transistors the duty cycle should be less than 0.45 to avoid short circuiting the converter.

Vout Vin = 2Dn2 n1 (3.15)

3.3 Thermal resistance

Thermal resistance is a measurement on a materials ability to transfer heat and is calculated by taking the difference in temperature between two points and dividing it with the thermal power loss 3.16 [8].

Rth=

Tj−Ta

Pthermal

(3.16)

Much like electrical resistance thermal resistance can be put in series where the total thermal resistance is Rtot = Rth1+ Rth2or in parallel where the total thermal

resistance can be calculated using equation 3.17.

Rtot= Rth1Rth2

Rth1+ Rth2

(3.17)

In a PCB manufacturing the most common laminate used for electrical isolation is FR-4 which is flame retardant but has a high thermal resistance making a bad material to transfer heat [4]. To improve the heat conductivity in a PCB vias can be added between the copper layers. They have their own thermal resistance

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3.3 Thermal resistance 17

dependent on their diameter and adding vias in parallel adds a thermal resistance in parallel. The heat needs to be transferred to the surrounding and a heat sink can greatly improve the thermal conductivity of the PCB to the surrounding air.

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4

Method

This chapter describes the method for analyzing and comparing the different iso-lated DC/DC converters. It is split between design of the PCBs and simulation of DC, electromagnetic, AC and thermal effects. An explanation of the measure-ments on the manufactured prototype modules are made.

In this thesis the MOSFET that "Flex Power Modules" have acquired will be called "new MOSFET" and the PCB that uses them "new PCB". The PCB with embedded MOSFET will be called "embedded PCB" and when it is written "embedded MOS-FET" it means embedded bare die MOSFETs. Both modules will be compared to an older module that uses the same MOSFETs as the ones in embedded PCB but with surface mounted package only and will be called "reference PCB" or "reference module".

4.1 Layout

A layout of an existing isolated DC/DC converter module is used as a reference layout in all simulations and as a starting layout that is modified to use embedded MOSFETs or the new MOSFETs. It has 16 MOSFETs for a H bridge rectifier on the secondary side of the transformer, four MOSFETs in parallel for each group and 14 copper layers. Figure 4.1 shows a schematic for the rectifier. The input voltage on the primary side is 40 to 60 V and the output is 12 V. The converter should be able to handle a nominal power of 1300 W and a peak power of 1600 W for 2 ms.

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20 4 Method *4 *4 *4 *4 4:1 +Out -Out

Figure 4.1:Schematic for the rectifier.

For the layout of embedded PCB, the reference module is changed to have two MOSFETs from each group of the rectifier embedded inside the PCB. In the man-ufacturing process the micro vias can only be made connecting to a thin copper layer (70 µm). To be able to create micro via connections to the embedded MOS-FETs two more layers with a height of 70 µm where added in the middle of the PCB increasing the number of layers to 16. In the reference module the MOSFET connected to the positive output are put on the top side and the ones connected to the negative output are put on the bottom side. To make the wiring easy and shorten the AC loop the embedded MOSFETs that is going to be connected to the positive side where put in between layer 7 and 8 while the ones connected to the ground put in between layer 9 and 10. The vias that existed in the reference layout was through hole, buried via between layer 2 and 13 and micro vias as blind vias. Buried vias that connect the embedded MOSFET directly to the layer under the surface where added to make the wiring easy and improve the ther-mal distribution to the surface even though they increase the number of steps in the manufacturing process. To lower the winding loss the MOSFETs are put as compact as possible and close to the transformer making the AC loop small. A stackup of the layout and the position of the embedded MOSFETs in the copper layers can be seen in figure 4.2. Copper is orange, prepreg is green and MOSFETs are blue. The thick copper layers are 175 µm and the thin are 70 µm. The thick prepreg layers are 150 µm and the thin are 100 µm. The embedded MOSFETs were put in the middle layers of the PCB because it would be minimum twist in the MOSFETs and lower the chance of breaking them. The heat dissipation is also decent in the middle layers. There are two different types of embedded MOSFETs. One that are soldered on directly to the under-laying copper layer and connection

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4.1 Layout 21

with vias to the copper layer above. Another is that there is connection with vias on both sides. Here the connection is chosen to be soldered directly on the copper layer because it is thought to be the connection with the lowest resistance and the highest thermal dissipation.

Figure 4.2:Stackup of the layout.

To manufacture the PCB with embedded MOSFET the manufacturing process is planned to involve four steps. First layer 2-7 and 10-15 are made separately to make the buried vias from layer 2 to 7 and 10 to 15. Then the layers for the embedded MOSFETs are made (8 and 9). The two halves are joined with prepreg and buried vias between layer 2 and 15 are made. Lastly the top and bottom layers are made.

The second layout that uses the new MOSFETs is made having 14 layers, same as the reference PCB. The new MOSFETs have a resistance lower than the resistance of the old MOSFETs. Three of the new MOSFETS can therefore be in parallel while still having less on resistance than the four MOSFETs in parallel in the reference PCB. The lower number of transistors frees up space and lowers the AC loop. To lower the AC loop even further the core of the transformer is made thinner to have the MOSFETs closer to the transformer. To compensate for the volume loss in the ferrite core, it is made larger in height. With the extra space that it created the output inductor is made bigger than in the reference to have a smaller power loss in it.

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22 4 Method

The transformer is a 4:1 planar transformer meaning that the PCB copper inlays is used for the wiring of the transformer. Planar transformer is used because of the low height, good thermal dissipation and low leakage inductance [21]. The output inductor has also the PCB copper as the wiring. The PCB is cut to insert ferrite cores made of laminated ferrite powder. The core has a good isolation, but the maximum flux density is low meaning that the switching frequency needs to be high to not saturate them.

In both the PCBs the MMF is lowered by having the primary and secondary layers interleave each other. The layers alternate between primary and secondary except for the two middle layer and layer one, two, fifteen and sixteen. Doing an analysis of the MMF ratio between the layers shows that the highest ratio will happen in the second layer and will have a ratio of 2.

4.2 Simulation

Simulations on the PCBs is made to quickly get an understanding on the perfor-mance and behavior of the PCBs instead of only doing measurement on a proto-type. The simulation can give an insight in which part of the PCBs is the critical ones.

4.2.1 DC simulation

The simulation tool "Sigrity" from "Cadence" is used to make a DC simulation of the layout. The simulation is made by having a current source of 25 A on the input pin and having two MOSFETs on and two off creating a current path through the transformers primary side. The same is done on the output pins but the current is 100 A and two groups of transistors are on and two are off creating a current path on the transformers secondary side. The DC simulation is used to check for spots of high current density that can be lowered by changing the layout. Other simulations do give a more realistic simulation of the current path and density, but the DC simulation is a lot quicker and using any other simulation to lower the current density in the layout would take too much time.

4.2.2 Electromagnetic simulation

The electromagnetic effects of the layout are simulated with Finite Element Method, FEM, using "Multiphysical" from "Comsol" and it is used to simulate the winding loss and leakage inductance. The result from the simulation is used to set the AC resistance for the transformer in a small signal simulation using PSPICE. To make the "Comsol" model a XML file from the layout program is imported. A 3d-model of the transformer core is also made and imported. The electromagnetic simulation is very time consuming. To save on simulation time the model is sim-plified by removing all components except for the transistors and transformer

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4.2 Simulation 23

and removing parts of the copper that is uninteresting in this simulation. By sim-plifying the model, a smaller mesh can be made improving the error rate in the part we are interested in while still keeping an acceptable simulation time. It also lowers the chance that the simulation diverges. The mesh size is put to have an error of less than 4 %. For comparing the embedded and surface mounted MOSFET a 3-d model for each is made.

To measure the winding loss in the "Comsol" model a current source of 25 A is inserted on the primary side and two of the transistors are short circuited and two are turned off. On the secondary side a current source of 100 A is inserted between the positive output and ground and two groups of transistors are turned on to close the circuit. The rest of the transistors are turned off. The measured frequencies are between 100 kHz and 20 MHz. A schematic model for the sim-ulation is shown in figure 4.3. For the embedded PCB the on resistance for the surface mounted MOSFETs is set to 1.1 mΩ and for the embedded MOSFETs it is set to 0.7 mΩ. The resistance is also set for the new MOSFET but it can not be disclosed due to NDA. To measure the winding loss in higher frequencies than 1 MHz, Kelvin effect needs to be considered. To have a low error rate simulated depth that the current can travel in is set to four times the skin depth for the frequencies 1, 3, 5 and 10 MHz [18]. For 20 MHz it is put to three times the skin depth.

+Out

100 sin ωt A

-Out 25 sin ωt A

Figure 4.3:Schematic model for "Comsol Multiphysic" simulation for wind-ing loss.

The leakage induction is measured similarly in the same model but the transistors that are on are connected first to the negative output while the ones connected to the positive side are off. This is called phase A, see figure 4.4. To simulate the leakage inductance over the positive side of the rectifier the transistors are turned on and off opposite to phase A. This is called phase B, see figure 4.5.

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24 4 Method -Out +Out − + 0.01

Figure 4.4:Schematic model for "Comsol" simulation for leakage inductance in phase A. +Out -Out − + 0.01

Figure 4.5:Schematic model for "Comsol" simulation for leakage inductance in phase B.

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4.2 Simulation 25

A low frequency sinusoidal voltage source with an amplitude of 0.01 V is inserted on the primary side. The leakage inductance is calculated by measuring the RMS current on the primary side, I, and using 4.1 where V is the RMS voltage of the voltage source, f is the frequency of the voltage source and Lleakis the total

leak-age inductance from both the primary and secondary side.

Lleak= Im ( V j2πfI ) (4.1)

4.2.3 Small-signal simulation

A PSPICE model is designed and used for small signal AC simulations. The model for the winding resistance of the transformer is shown in figure 4.6. At low frequencies the inductors short circuits the resistors except for the DC resis-tance R0. When the frequency increases the impedance in the inductors is going

to increase which increases the total resistance. At higher frequencies resistance will start to saturate to the sum of the resistance of the resistors. To calculate the value of the resistors and inductors the winding loss from the electromagnetic simulation is used. The induced current is a sine wave with an amplitude of 100 A. Using the relation between current and power P = I2R the resistance at different frequencies is calculated. An expression for the AC resistance is made and resistance and inductance are set to different values to only give a maximum of 5 % difference from the simulated AC resistance. The PSPICE model for the transistors comes from the manufacturer and for the embedded they are edited to remove the resistance from the case. From the PSPICE simulation power loss in each component and in the winding are taken, which is used to simulate the thermal dissipation in the PCBs.

R0 R1 R2 R3 R4

L0 L1 L2 L3

Figure 4.6:Schematic of the AC resistance in the winding.

4.2.4 Thermal simulation

Heat from the embedded MOSFETs will dissipate through the PCB material. A thermal simulation is done to compare the temperature difference between the PCB with the embedded MOSFETs and the reference PCB. "Multiphysics" from "Comsol" is used for the thermal simulations. The surface of the PCBs are set to a fixed temperature of 60◦C and the pins 70 ◦C. The MOSFETs and the wind-ing are set to be heat sources. Because the simulation only is for comparwind-ing the

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26 4 Method

temperature and thermal resistance between the PCBs and not to give any real value of the temperature the PCB models can be simplified by removing all pas-sive component and the cores. In the PSPICE model the winding loss and the power loss in the MOSFET is simulated during an operation with an input of 25 A, an output of 100 A and a switching frequency of 200 kHz. These values for the power loss are used for the heat sources in the thermal simulation. The tem-perature from the simulation and the CTE of the different materials can be used to give an idea of how large the mechanical stress is going to be on the embedded MOSFETs. From the junction temperature in the component (Tj), the ambient

temperature (Tamb) and the power loss (Ploss) the thermal resistance (Rth) can be

calculated using equation 4.2. The ambient temperature in this case is the same as the surface of the PCB 60◦C.

Rth=

Tj−Tamb

Ploss

(4.2)

No thermal simulation for the new PCB was made to save time. The new PCB is like the reference PCB with it using surface mounted component and the goal with the thermal simulation is to check if there are any changes in temperature when MOSFETs are embedded.

4.3 Output induction simulation

For the new PCB the design of the output inductor core is changed to fit a wider winding in it. The inductor is built to have an output inductance of 280 nH with a maximum difference of 25 %. To make sure that the inductance is correct with the new design the inductor is simulated using "Comsol". The ferrite core consists of material 3C92 from "FQ" and it is modeled in "Comsol" with its B-H characteristics, see figure 4.7.

The simulation is done by having a current passing through the inductor and measure the induction. The current mostly consist of DC current with a small sinusoidal current added. In the simulation a DC current of 10 A is used and the added AC current is set to a low frequency of 1 kHz to avoid effects in high frequency like the skin effect.

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4.4 Measurement 27

Figure 4.7:H-B characteristic of the ferrite material used.

4.4 Measurement

Simulation usually have a margin of error and the only way to get an accurate measurement is to measure on a real module. If the simulation of the designed PCBs shows any improvement in power loss or at least not any larger power loss a prototype module is made that measurement can be done on. The PCBs are manufactured by "SCC".

4.4.1 Electrical verification

To make sure that the manufactured prototypes work as DC/DC converters and that they can handle 1300 W the modules goes through an electrical verification. For the modules to work the control circuits needs to be loaded with the software developed by "Flex Power Modules" and it is the same used in the reference PCB. To test a module, it is put on a test board and tested with a bias voltage, input voltage and nominal load to see if it can operate as a DC/DC converter. The drain source voltage is also checked to test the avalanche effect.

If the module can transform the electrical power, the module and the test board is inserted into a temperature chamber. The module is connected to a power supply at the input and a variable load at the output. In set intervals the power supply applies a voltage of 54 V and the variable load steps though several loads going from high to low. The input and output power are measured and from that the efficiency of the module is calculated and how the power varies with the current. After each step of different loads, the power supply is turned off and the temperature chamber sets the temperature of the module to a set value of 23±5

◦

C before the module is turned on again and a new load is tested. This is to test how the module behave without considering the thermal dissipation.

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28 4 Method

4.4.2 Quality verification

To measure the efficiency and thermal resistance during air cooling a prototype module is put in a wind tunnel on a test board. The module is tested under different loads and wind speeds. The load is set for the input power to be between 200 W and 1300 W and the wind speeds 4, 3, 2 and 1 m/s are used. See figure 4.8 for an image of the wind tunnel used in this measurement.

Figure 4.8:Wind tunnel used for stress test.

The temperature is measured in spot that is of interest like the winding and the MOSFETs on the primary and secondary side. The output power is measured over different loads and the efficiency is calculated. From this a value of the thermal resistance at different wind speeds and power losses can be calculated.

To measure the thermal resistance of the module the thermal resistance of the test board needs to be accounted for. This is done by running multiple test with different configuration. The first is to test with open frame. The module is then only connected to the test board and the temperature only dissipate through the air and test board. Secondly is to test with a base plate and heatsink on top of the module. They are only connected thermally through the pins and screws. This is to be able to calculate the thermal resistance of the test board. Lastly the top of the module is thermally connected to the heatsink.

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5

Result

Using the methods from chapter 4 the behavior of the isolated DC/DC convert-ers could be documented. This chapter describes the difficulties in the layout and the result from the simulations and measurements. The gate pad on the MOSFET die is too small for the manufacture to make a connection to when it is embed-ded. There is therefore no measurements on a manufactured PCB with embedded component only on the new surface mounted MOSFETs.

5.1 Layout

One of the marketed benefits for using embedded MOSFETs is that they can free up space on the surface of the PCB. Comparing the module that has embedded MOSFETs and the reference PCB the free space that is created is partly taken up by big connections between the layers to lower the current density between them. The freed-up space is therefore not as big as removing the transistors entirely from the surface but still adequate. The transformer winding was widened to get better interleaving.

In the layout with new MOSFET the idea was to align the MOSFETs with the output pin to direct the current more efficiently and lower the maximum current density. This took some space from the winding of the transformer and the in-creased size of the output inductor made the wiring uneven in the transformer.

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30 5 Result

5.2 DC-simulation

The DC-simulation shows that the current splitting between the surface mounted and embedded MOSFETs are about the same with small difference. The embed-ded MOSFETs have a lower resistance than the surface mounted MOSFETs. The current in the embedded MOSFETs should therefore be larger than in surface mounted MOSFETs. Because the current is about the in all MOSFETs the resis-tance from the winding to the MOSFETs must level it out. There is an increase in the current density inside the PCB when embedding MOSFETs.

5.3 Electromagnetic simulation

The electromagnetic simulation that is done using "Multiphysics" from "Comsol" and shows the current distribution, winding loss and leakage inductance for the different PCBs.

5.3.1 Current distribution

Table 5.1 shows the current distribution between the MOSFETs. The MOSFETs named T4XX is surface mounted and T7XX is embedded. T701 and T702 are embedded between layer 7 and 8 and T731 and T732 between layer 9 and 10. Embedded MOSFETs have a lower inductance than surface mounted MOSFET meaning that with increased frequency the drain current should increase in the embedded MOSFETs and the current on the surface mounted MOSFETs decreases which the table shows.

Table 5.1:Drain current for MOSFETs (TXXX) at different frequencies.

Freq [kHz] 100 200 400 600 1000 T401 [A] 28.887 26.969 24.754 23.575 22.418 T402 30.217 29.312 27.589 26.448 25.187 T701 25.010 25.888 27.147 27.857 28.540 T702 26.127 28.867 32.205 34.971 36.100 T431 30.737 29.496 28.200 27.599 27.228 T432 29.369 28.802 27.027 27.027 26.202 T731 23.774 24.667 25.825 26.449 27.011 T732 24.652 25.933 27.629 28.722 29.992

Table 5.2 shows the current distribution for the reference PCB. Here the current does not change as much in higher frequencies because all MOSFETs have the same specifications.

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5.3 Electromagnetic simulation 31

Table 5.2:Drain current for MOSFETs (TXXX) at different frequencies.

Freq [kHz] 100 200 400 600 1000 T400 [A] 27.907 27.363 27.048 27.060 27.410 T414 25.871 25.999 26.251 26.549 27.153 T420 26.325 27.556 28.657 29.319 30.370 T424 25.994 25.488 25.315 25.473 25.966 T403 24.492 24.450 24.481 24.583 24.840 T416 29.200 29.423 29.746 30.091 30.886 T423 23.337 23.509 24.010 24.479 25.275 T426 26.958 26.892 26.910 27.114 27.654

5.3.2 Winding loss

Figure 5.3 shows the total loss in the winding. With increase in frequency the winding loss increases. The winding loss in the new PCB is lower than the wind-ing loss in the PCB with embedded MOSFETs but larger in higher frequency. Comparing the primary winding loss, figure 5.1, and secondary winding loss, figure 5.2, the highest loss happens in the secondary winding. Both layouts made have a higher total winding loss compared to the reference layout in all frequen-cies. 200 400 600 800 1,000 1.5 2 2.5 3 3.5 4 Frequency [kHz] W inding loss [W] Embedded Reference New

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32 5 Result 200 400 600 800 1,000 2 3 4 5 6 Frequency [kHz] W inding loss [W] Embedded Reference New

Figure 5.2:Secondary side winding loss.

200 400 600 800 1,000 4 6 8 10 Frequency [kHz] W inding loss [W] Embedded Reference New

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5.3 Electromagnetic simulation 33

5.3.3 Leakage inductance

Figure 5.4 shows the leakage inductance in phase A and figure 5.5 in phase B. The PCB with the lowest leakage inductance is the one with embedded MOSFET which is in line with the lower induction of the embedded MOSFETs and the shorter connections. In phase B the difference is less which might be because of a less than optimum layout. The layout with new MOSFETs have the highest leakage inductance in both phases.

200 400 600 800 1,000 15 20 25 Frequency [kHz] Leakag e ind uctance [nH] Embedded Reference New

Figure 5.4:Leakage inductance phase A.

200 400 600 800 1,000 15 20 25 Frequency [kHz] Leakag e ind uctance [nH] Embedded Reference New

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34 5 Result

5.4 SPICE simulation

Table 5.3 shows the power loss in different component from the SPICE simulation. TX refers to the transistors on the primary side of the transformer, T4XX to the surface mounted transistor on the secondary side of the transformer and T7XX to the embedded transistor on the secondary side of the transformer. In the PSPICE model the transistors that are in parallel show the same power loss therefore only one of each group is shown. The last two digits in the name of the transistor indicate what group of parallel transistors it belongs to. The embedded MOSFETs have a higher power loss than the surface mounted MOSFETs, but all MOSFETs in the embedded PCB have a lower power loss than in the other PCBs.

Table 5.3:Power losses from SPICE simulation. Component Embedded [W] Reference [W] New [W]

T1 1.93611 1.94673 1.97444 T2 1.78599 1.79735 1.88941 T3 1.85986 1.86956 1.97459 T4 1.86212 1.87156 1.88966 T401 388 m 505 m 540 m T701 456 m T411 383 m 496 m 540 m T711 449 m T421 380 m 492 m 517 m T721 445 m T431 385 m 500 m 517 m T731 451 m Winding 8.2866 7.63166 8.75042 Efficiency [%] 97.38 97.33 92.58

To save on space the PCB with new MOSFET does not use active clamps, instead it has passive clamps. If an active clamp is used instead in the new PCB the wind-ing losses is decreased to 8.000 W which is lower than the PCB with embedded component but higher than the reference PCB.

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5.5 Thermal simulation 35

5.5 Thermal simulation

The thermal simulation shows slightly lower temperature for the embedded MOS-FETs than the maximum temperature of the surface mounted MOSMOS-FETs in the reference PCB, but the thermal resistance is higher. The temperature for the winding is also lower. Table 5.4 and 5.5 shows the maximum temperature for the MOSFETs and windings in the reference PCB and embedded PCB, respectively. It also shows the thermal resistance to ambient temperatures for the transistors. The temperature of the transistors is for the one with the highest temperature in that layer. Figure 5.6 shows where the heat is generated in the embedded PCB and how it is distributed.

Table 5.4:Simulated temperatures in reference PCB. Temperature [◦C] Thermal res [◦C/W]

Pri FET 98.81 19.936

Sec top FET 102.68 84.515

Sec bot FET 103.29 86.580

First turn 102.73 Last turn 103.73

Table 5.5:Simulated temperatures in embedded PCB. Temperature [◦C] Thermal res [◦C/W]

Pri FET 97.98 19.617

Sec top FET 99.84 102.680

Sec bot FET 99.90 103.636

Emb FET layer 7-8 101.01 89.934

Emb FET layer 9-10 101.23 91.419 First turn 101.04

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36 5 Result

Figure 5.6:Temperature distribution over the PCB.

5.6 Inductor simulation

The current density of the output inductor can be seen in figure 5.7. In an induc-tor the AC component of the current is pushed outward in the winding, while the DC component take the path with least resistance. The high current density in the center of the inductor shows that there is mostly DC current in the inductor. Figure 5.8 shows how the magnetic flux density is distributed in the ferrite core. The average flux density is 11.45 mT in the center of the core and 16.92 mT in one of the side legs. The simulated induction is 223 nH which fit in the criteria of 270 nH with a maximum of 25 % possible difference.

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5.6 Inductor simulation 37

Figure 5.7:Current density in the output inductor winding

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38 5 Result

5.7 Manufacturing

When the PCB was to be manufactures it was discovered that the pad to the gate in the bare die MOSFET is too small for the PCB manufacturer to make a connec-tion to it in the manufacturing process. The gate pad is a square with the width of 150 µm and the minimum trace width that "SCC" could do at that time was 300 µm. Making a prototype of the embedded PCB would be impossible unless some other MOSFET was used or the PCB manufacturer was changed. It was therefore decided to only do a manufacturing of the PCB with the new MOSFETs to do measurement on. Figure 5.9 shows a picture of the PCB that was manufactured.

Figure 5.9:Picture of the manufactured PCB.

5.8 Measurements

Following is the result from the measurement on the newly developed PCB proto-type that uses the new MOSFETs. The electrical verification shows the efficiency at different loads with the PCB having a set temperature and the wind tunnel test shows the efficiency and temperatures at different wind speeds. The temperature values are used to calculate the thermal resistance of the module.

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5.8 Measurements 39

5.8.1 Electrical verification

With an input voltage of 54 V and output of 12 V the efficiency can be seen in figure 5.10. The low efficiency at low power is because of the module is not able to drive that large of a load. The highest efficiency is at around 800 W.

200 400 600 800 1,000 1,200 93 94 95 96 97 98 Output Power [W] E ffi ciency [%]

Figure 5.10:Efficiency of module at a temperature of 23±5◦

C.

If the input voltage to the new PCB is set to 60 V and the output current to 120 A the turn on drain source voltage spike is 32 V for both the MOSFET closest and furthest away from the transformer. This is above the specification of the new MOSFETs which is 25 V.

5.8.2 Wind tunnel

Figure 5.11 shows the efficiency at different wind velocity. The measurement is done with a module that is thermally connection to a heat sink. The module is most efficient at around 800 W and as expected the efficiency is lower at low wind velocity from the fact that the module is running hotter.

The thermal resistance for the module with heat sink and test board is shown in figure 5.12 and is calculated using the method described in chapter 4.4.2. The thermal resistance is constant after a specific output power for each wind veloc-ities except for 1 m/s. Comparing it to "Flex Powers Modules" previous quarter brick DC/DC converter the module has a better electrical quality but higher ther-mal resistance. Large part of the therther-mal resistance comes from the difficulty of transferring the heat from the bottom side of the PCB to the heat sink. More on the thermal performance of the PCB can be seen in appendix A.

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40 5 Result 400 600 800 1,000 1,200 94 95 96 97 98 Output Power [W] E ffi ciency [%] 4 m/s 3 m/s 2 m/s 1 m/s

Figure 5.11:Efficiency of module in wind tunnel.

0.8 0.9 1 1.1 1.2 0 200 400 600 800 1,000 1,200 Thermal resistance [◦ C/W] Output P ow er [W] 4 m/s 3 m/s 2 m/s 1 m/s

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6

Discussion

6.1 Leakage inductance

The way to decrease leakage inductance is to use wide and short connections. In the case of the embedded PCB by having the MOSFETs spread out over different layer the connection to each of them is shorten. The lowest leakage inductance is in phase A where the MOSFETs are connected to the negative output. In the PCB many layers are dedicated to the negative output making it easy to make many connections between the embedded MOSFETs and the bottom side MOSFET. This leads to a drop in the leakage inductance. The path to the MOSFETs is also shorter in path B, but the layers to positive output are only the two top ones. This leads to phase B not having as many connections between the MOSFETs which increases the leakage inductance. The result is that the leakage inductance in phase B for the embedded PCB is about the same as in phase B for the reference PCB. In the new PCB the core of the transformer is made thinner and higher, keeping the effective area of it. To do that the winding is made thinner which increases the leakage inductance compared to the reference PCB in both phase A and B. The leakage inductance is also increased from there being a smaller connection to the output inductor when one of four MOSFETs in parallel is removed. In making the winding in the transformer thinner the winding in the output induc-tor can be made wider, lowering its leakage inductance and power losses. This can compensate for the increase in power loss in the transformer from the higher leakage inductance. The new PCB uses fewer MOSFET and they are put closer to the transformer, shortening the AC loop. The inductance form the AC loop is therefore smaller, but the winding width is the dominant factor in leakage

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42 6 Discussion

tance.

6.2 Winding loss

The primary side in the newly developed PCBs have a lower winding loss com-pared to the reference PCB at low frequency. The explanation for this in the case for embedded PCB is that the winding is wider in some places because of the added vias that connects layer 2 to 7 and layer 10 to 15. In the reference PCB the vias that connected the primary layers was PTH vias and took up space even in the layers they were not used. In the new PCB the primary layers are spread out over the primary MOSFETs to lower the thermal resistance and it can also lower the DC resistance. In the embedded PCB and the new PCB, the AC loop is shorter, and the primary layer is put more compactly. The winding loss in the pri-mary side for the embedded PCB follow the loss for the reference PCB at higher frequency while the winding loss for the new PCB is the largest of all PCBs. This can be explained by its higher leakage inductance.

The two layers, that were added to the secondary side in the embedded PCB, have a thickness of 70 µm. In total the two extra layers lowers the DC resistance slightly less than adding one extra thick layer would. A reason for the increase in losses on the secondary side of the embedded PCB, even with the extra layers, is that the number of vias that connect the secondary side was lowered to be able to fit the embedded MOSFETs. Comparing it to the new PCB which have a larger number of parallel vias and MOSFET with lower resistance the winding losses is larger for the embedded PCB until 600 kHz. After that the new PCB has the highest secondary winding loss out of all the PCB. The linearity of the winding loss for the new PCB can be a simulation error because it is the only module that has that pattern.

6.3 Thermal simulation

The result from the thermal simulation shows that there is no large difference be-tween embedded MOSFETs and surface mounted MOSFETs temperatures similar to the result in [13]. The low temperature difference between them is because of a difference in thermal resistance. The embedded MOSFETs had a larger power loss than the surface mounted MOSFETs in the PSPICE simulation meaning that more heat was generated. This is compensated by the fact that the thermal sistance is smaller for embedded components. The difference in the thermal re-sistance between embedded and surface mounted components can be because most of the heat is transferred through the copper in the PCB. For the embedded component the heat can both be transferred by the copper layer over and under it. Another reason for the lower thermal resistance can be because of the added copper layers.

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6.4 Current distribution 43

The embedded PCB have a lower number of vias compared to the reference PCB which can increases the thermal resistance to the surface and connection pins from the inner layers of the PCB but [10] shows that there is a diminishing return on the thermal resistance with vias. The difference in the number of vias have therefore only a small impact on the thermal resistance.

6.4 Current distribution

The reason why the drain current is higher for surface mounted component at lower frequency even though the embedded MOSFETs have a lower resistance can be because the path is longer to the embedded component, making the total resistance larger. At higher frequency the current is increasing in the embedded MOSFETs because they have a lower inductance.

6.5 Manufacturing of embedded PCB

When it comes to manufacturing a PCB with embedded component it is impor-tant to know the die size because it is not always compatible with the PCB man-ufacturing size limits. A big drawback with embedded bare die MOSFET is the added steps in manufacturing the PCB which increases the cost of each unit. To use embedded MOSFETs it is important to plan what layers they should be put in and to which layers the vias should connect to. This is to keep the number of steps as low as possibly which limits the usage of bare die MOSFETs as a replacement for surface mounted MOSFETs in an already made design.

6.6 Measurements on new PCB

The measurements done on the PCB with new MOSFETs shows that it is possible to have fewer MOSFETs in parallel while still having a high efficiency utilizing new and improved packaging. The increase in the thermal resistance can be im-proved by improving the design.

The result in the turn on voltage peak shows that is it too high. This is the result of not using active clamps. To lower it higher capacitance should be used to filter out the voltage spike and increase the longevity of the MOSFETs.

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7

Closing comment

Embedded MOSFETs do show promise in lowering leakage inductance in trans-former but the benefit is outweighed by the drawbacks. Embedded MOSFETs change the design of the PCB and cannot be a drop-in replacement for surface mounted component. Instead the PCB must be design with embedded MOS-FET from the start to take advantage of embedding as packaging. The cost for each PCB with embedded MOSFETs increases from the added steps in the man-ufacturing and it is confusing what die can be used for embedding. Embedded components also have the disadvantage of not being able to change component without creating a new PCB. The result is that the market for power electronics will probable still be dominated by surface-mounted components and continual development on surface mounted packaging.

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A

Thermal performance of new PCB

0.7 0.8 0.9 1 1.1 1.2 0 200 400 600 800 1,000 1,200 Thermal resistance [◦C/W] Output P ow er [W] 4 m/s 3 m/s 2 m/s 1 m/s

Figure A.1:Thermal resistance of the module with heat sink excluding pins.

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50 A Thermal performance of new PCB 0.4 0.6 0.8 1 1.2 0 200 400 600 800 1,000 1,200 Thermal resistance [◦C/W] Output P ow er [W] 4 m/s 3 m/s 2 m/s 1 m/s

Figure A.2:Thermal resistance of the test board.

15 20 25 30 35 40 45 0 200 400 600 800 1,000 1,200 Thermal resistance [◦C/W] Output P ow er [W] 4 m/s 3 m/s 2 m/s 1 m/s