On Design, Analysis, and Implementation of LDI/LDD Lattice Filters

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(1)Malardalen University Dissertation No. 1. On Design, Analysis, and Implementation of LDI/LDD Lattice Filters. Johnny Holmberg March 2002. Malardalen University Department of Electronics Applied Signal Processing and Control.

(2) TEL ET. RI EO. ISS NSM IONS T RA. TH. IN. G S T A K E TI M. E. c Johnny Holmberg, 2002 Copyright ISBN:91-88834-30-1 Printed by Arkitektkopia, Vaster as, Sweden Distribution: Malardalen University Press.

(3) Abstract This thesis focuses on design, analysis, and implementation of lossless discrete integrator and dierentiator (LDI and LDD) lattice lters. In the design part, a new modied LDI/LDD allpass lter structure is presented, along with a new design method. The analysis especially concerns suppression of parasitic oscillations in the LDI/LDD allpass lters. The stability is aected by the placement of the overow and quantization nonlinearities. For the second-order LDI/LDD allpass lters, two cases are studied: the rst when all nonlinearities are placed immediately before the delay elements, and the second when the quantizer is located after the adder which follows the multipliers. In the rst case, we study both zero-input limit cycles and forced-response instabilities, while the latter deals only with zero-input quantization limit cycles. It is also shown that zero-input overow limit cycles can be suppressed in general-order LDI/LDD allpass lters, provided that saturation overow arithmetics are used immediately before each delay element, and for certain restrictions for the values of the lter coecients. Both scaled and unscaled cases are considered. The analysis also includes a quantization noise level comparison between LDI and wave digital (WD) allpass lters. For rst- and second-order lters, analytic expressions of the scaled noise gain are derived. However, for higher lter orders the analysis is restricted to numerical evaluations. It is shown that LDI and LDD lters are preferably used when the poles are placed near z = 1 and z = ;1, respectively. A coecient quantization analysis of LDI/LDD and WD lattice lters is also made. The analysis shows that LDI/LDD lattice lters can implemented with as few bits in the lter coecients as the well-known WD lattice lters. Computational properties of the general-order LDI/LDD lattice lter are analyzed. The lter structure is shown to be advantageous in high-throughput and low-power applications. Single-interval and maximally fast schedules of the LDI/LDD lattice lter structure are presented. They are compared to corresponding schedules of WD lattice lters concerning resource requirements. The results show that LDI/LDD lattice lters can be implemented with fewer adders and D ip-ops than corresponding WD lters. Implementations with saturation arithmetics and magnitude truncation placed immediately before the delay elements are also presented. Finally, an initial study of the LDI lter in adaptive applications is presented. The study includes both stability analyses and simulations. The adaptive LDI lter is compared to corresponding realizations of direct-form and tapped state lattice lters. A stability criterion for the time-varying second-order LDI lter is presented, which is used to derive an adaptive algorithm for the lter. The results indicate that the LDI lter appears to be promising as adaptive lter in lowpass-type applications..

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(5) Acknowledgments I would like to express my sincere gratitude to my research supervisor Prof. Lennart Harnefors for supporting me through this work and helping me with both the technical and linguistical diculties. Thank you Lennart, without your guidance this work would not have been possible. My colleagues at the Department of Electronics in Vaster as deserve also many thanks, especially the Applied Signal Processing and Control group, for contributing with many stimulating discussions. I further would like to thank Prof. Svante Signell (Ericsson Radio Systems) who has provided with expertise and guidance, and Lic. Tech. K are Mossberg, the grandfather of the project, particularly having me as an un-announced guest for a couple of times. Thanks also go to Dr. Mark Vesterbacka, Linkoping University, for his inspiring ideas and for contributing with suggestions for my research. I am also thankful for the eorts by my opponent, Dr. H akan Johansson. I would also like to express my gratitude to Lic. Tech. Clas Nordin and Dr. Lennart Egnesund for helping me with some linear algebra diculties, especially for the Adaptive LDI Filters chapter. My mother and father also deserve many thanks for always supporting and believing in me. The rest of my family is not forgotten. Last, but not least, I would like to thank my (ancee) Sabina for her love and encouragement, and my dog Hilton for giving me the time to think during our endless walks. This work was supported nancially by Malardalen University and Ericsson Radio Systems..

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(7) Contents 1 Introduction. 1.1 Scientic Contributions . . . . . 1.2 Digital Filter Structures . . . . 1.3 Finite-Wordlength Eects . . . 1.3.1 Quantization . . . . . . 1.3.2 Overow . . . . . . . . . 1.3.3 Coecient Quantization 1.4 Digital Lattice Filters . . . . . . 1.5 Bilinear Transformation . . . . 1.6 An Introduction to WD Filters 1.7 Test Filter Specications . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. 2.1 Introduction . . . . . . . . . . . . . . . . . . . . 2.1.1 LDI Ladder Design Approach I . . . . . 2.1.2 LDI Ladder Design Approach II (BDLF) 2.2 LDI/LDD Lattice Filters . . . . . . . . . . . . . 2.3 Design Formulas . . . . . . . . . . . . . . . . . 2.3.1 Design Example . . . . . . . . . . . . . .. . . . . . .. . . . . . .. . . . . . .. . . . . . .. . . . . . .. . . . . . .. . . . . . .. . . . . . .. . . . . . .. . . . . . .. . . . . . .. . . . . . .. . . . . . .. . . . . . .. . . . . . .. 2 LDI/LDD Lattice Filters. 3 Suppression of Parasitic Oscillations. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .. 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Stability Theory for Nonlinear Systems . . . . . . . . . . . . . . . . . . . . 3.2.1 Nonlinear Discrete-Time Systems . . . . . . . . . . . . . . . . . . . 3.2.2 Nonlinear Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 Lyapunov Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.4 Lyapunov Theory for the Nonlinear Filter . . . . . . . . . . . . . . 3.2.5 Stability of the Forced Response . . . . . . . . . . . . . . . . . . . . 3.2.6 Tsypkin's Criterion . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Stability Analysis of the Second-Order LDIIII Allpass Filter Using Lyapunov Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 Test Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i. 1. 3 5 9 9 11 11 13 15 16 20. 23. 23 24 25 27 31 32. 35. 35 36 36 40 40 42 43 46 47 52 55.

(8) CONTENTS. ii. 3.4 Stability Analysis of the Second-Order LDIIII Allpass Filter with One Quantizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Suppression of Overow Limit Cycles in the General-Order LDIIII Allpass Filter . . . . . . . . . . . . . . . . . . . . . . 3.5.1 Stability Regions of the LDIIII Allpass Filter . . . . . . . . . . . . . 3.5.2 Test Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.3 Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.4 Stability Regions for the Scaled LDIIII Allpass Filter . . . . . . . . 3.6 Quantization Limit Cycle Simulation of the LDIIII Lattice Test Filters . . . 3.7 Stability Results for Other Digital Filter Structures . . . . . . . . . . . . . 3.7.1 Stability Result for WD Filters . . . . . . . . . . . . . . . . . . . . 3.7.2 Stability Result for the Second-Order DF Filter . . . . . . . . . . . 3.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4 Quantization Noise Analysis 4.1 4.2 4.3 4.4 4.5. Introduction . . . . . . . . . . First-Order Allpass Filters . . Second-Order Allpass Filters . Higher-Order Allpass Filters . Summary . . . . . . . . . . .. . . . . .. . . . . .. . . . . .. . . . . .. . . . . .. . . . . .. . . . . .. . . . . .. . . . . .. . . . . .. . . . . .. . . . . .. . . . . .. . . . . .. 5 Coecient Quantization Analysis. 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Pole Density of the Second-Order LDIIII Allpass Filter 5.3 Wordlength Optimization . . . . . . . . . . . . . . . . 5.3.1 Simulated Annealing Algorithm . . . . . . . . . 5.3.2 Cost Function . . . . . . . . . . . . . . . . . . . 5.3.3 Results . . . . . . . . . . . . . . . . . . . . . . . 5.4 Monte Carlo Analysis . . . . . . . . . . . . . . . . . . . 5.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . .. 6 Implementation of LDI/LDDIII Lattice Filters. 6.1 Introduction . . . . . . . . . . . . . . . . . . . . 6.2 Computational Properties of Digital Algorithms 6.2.1 Latency and Throughput . . . . . . . . . 6.2.2 Precedence Graph and Voltage Scaling . 6.2.3 Pipelining . . . . . . . . . . . . . . . . . 6.2.4 Computation Graph . . . . . . . . . . . 6.2.5 Minimal Sample Period . . . . . . . . . . 6.3 Bit-Serial Processing Elements . . . . . . . . . . 6.3.1 Bit-Serial Adder . . . . . . . . . . . . . . 6.3.2 Bit-Serial/Parallel Multiplier . . . . . . . 6.3.3 Magnitude Truncation . . . . . . . . . .. . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .. 56 60 64 67 70 72 75 75 75 76 79. 81. 81 82 85 90 92. 95. . 95 . 96 . 97 . 97 . 98 . 100 . 107 . 111 . . . . . . . . . . .. 113. 113 114 114 114 115 116 117 118 118 119 122.

(9) CONTENTS 6.4 6.5 6.6 6.7. iii. 6.3.4 Saturation Arithmetics . . . . . . . . . . . . . . . . 6.3.5 Control Unit . . . . . . . . . . . . . . . . . . . . . . Implementation Aspects of the LDI/LDDIII Allpass Filter . 6.4.1 Minimal Sample Period . . . . . . . . . . . . . . . . 6.4.2 Resource Comparison (Number of Adders) . . . . . 6.4.3 Modied Second-Order LDI/LDDIII Allpass Filter . Single-Interval Scheduling . . . . . . . . . . . . . . . . . . 6.5.1 First-Order Case . . . . . . . . . . . . . . . . . . . 6.5.2 Second-Order Case . . . . . . . . . . . . . . . . . . 6.5.3 General-Order Case . . . . . . . . . . . . . . . . . . Maximally Fast Scheduling . . . . . . . . . . . . . . . . . . 6.6.1 First-Order Case . . . . . . . . . . . . . . . . . . . 6.6.2 Second-Order Case . . . . . . . . . . . . . . . . . . 6.6.3 General-Order Case . . . . . . . . . . . . . . . . . . Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 Adaptive LDI Filters. 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . 7.1.1 Time-Varying Linear Discrete-Time Systems 7.1.2 NEMSE . . . . . . . . . . . . . . . . . . . . 7.2 General-Order Adaptive LDI Filter . . . . . . . . . 7.2.1 Second-Order LDI Filter . . . . . . . . . . . 7.3 Stability Analysis of Time-Varying Linear Systems 7.3.1 Stability Analysis Using Lyapunov Theory . 7.3.2 Slow-Variation Analysis . . . . . . . . . . . 7.4 Stability Analysis of the Time-Varying LDI Filter . 7.4.1 Second-Order Case . . . . . . . . . . . . . . 7.4.2 Third-Order Case . . . . . . . . . . . . . . . 7.4.3 General-Order Case . . . . . . . . . . . . . . 7.5 Adaptive Algorithms . . . . . . . . . . . . . . . . . 7.5.1 Modied Second-Order Adaptive LDI Filter 7.6 Simulation Results . . . . . . . . . . . . . . . . . . 7.6.1 Second-Order Case . . . . . . . . . . . . . . 7.6.2 Fifth-Order Case . . . . . . . . . . . . . . . 7.7 Summary . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 123 123 124 124 126 128 128 129 130 132 136 136 136 139 141. 143. 143 145 145 146 147 148 148 150 151 151 154 155 156 159 162 162 168 171. 8 Conclusion. 173. A LDIIII Lattice Filter Matlab Design Program. 177. 8.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 8.2 Future Research . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175.

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(11) Chapter 1 Introduction In modern very large-scale integrated (VLSI) electronic systems, particularly for communications, reduction of power consumption is a major issue. VLSI systems include application-specic integrated circuits (ASICs) and eld-programmable gate arrays (FPGAs). Clearly, the power consumption issue is highly important for battery-powered equipment, such as mobile telephones. Low power consumption is, however, important for many VLSI systems (not only battery-powered). Moore's law|doubling of performance of microelectronics every 18th month|today shows extraordinary vitality, even after several decades of continuous development. This means that the number of transistors integrated on one single chip roughly doubles every 18th month. Therefore, if the power consumption is not kept down, the chip temperature will exceed the acceptable level. Simply put, the chip will burn up! The digital lter is an important component in signal-processing VLSI systems, again, frequently as applied in communications. Over the years various dierent digital lter structures have been developed, which will be further discussed in this chapter. One structure may dier greatly from another when implementation (in a VLSI system) is concerned. Particularly, the required number of processing elements, such as adders and multipliers, varies. Filter structures which require few processing elements are generally advantageous for implementation, concerning power consumption 37]. (This is considered in Chapter 6.) Therefore, the choice of lter structure is important. Another property which is important to consider for digital lters is the sample period. There are many applications, once again often in communications, where the sample period is the main issue. In 92], an OFDM-WLAN system is considered where a sample rate of 60MHz is required. In radar or high-denition TV (HDTV), sample rates up to 500MHz are needed 73]. In this thesis, high-speed and low-power digital lters are considered. The driving motivations behind this should be apparent. The easiest way of implementing digital lters is in software, i.e., as code in a digital signal processor (DSP). Modern DSPs even have instructions dedicated to lter implementation. Software implementations are advantageous concerning low time-to-market and high portability/mobility 73]. It is also straightforward to change the lter coecients or 1.

(12) 2. CHAPTER 1. INTRODUCTION. the lter structure, simply by downloading new code. Even though modern DSPs are quite fast, hardware (i.e., ASIC or FPGA) solutions are preferable in very-high-speed (megahertz range) and/or low-power applications. Then, the lter is implemented using some hardware description language. Also, the selection of number representation is important when considering power consumption. In oating-point arithmetics the processing elements are complex, yielding high power consumption and large hardware solutions. Fixed-point arithmetics, on the other hand, are more common for low-power implementations. There are two basic disadvantages of xed-point arithmetics, namely that the number range is relatively limited, and the percentage error produced by quantization tends to increase as the magnitude of the number is decreased 7]. Other problems which can occur in xed-point arithmetics due to nite wordlength are limit cycles and forcedresponse instabilities, which will be studied in Chapter 3. Quantization noise is another nite-wordlength phenomenon which must be considered when analyzing digital lters. The noise aects the digital lter in an negative way, since it decreases the signal-to-noise ratio (SNR) at the output of the lter. In this thesis, a specic digital lter structure is studied, namely the lossless discrete integrator (LDI) lattice lter, as well as the very closely related lossless discrete dierentiator (LDD) lter (only dierence: z ! ;z ). The structure is known to exhibit low sensitivity, i.e., an adequate frequency function is obtained at relatively short coecient wordlengths. LDI/LDD lters can be implemented with a canonical number of delays and multipliers, which makes them well suited for low-power and high-throughput applications. Even though LDI/LDD lters have been studied since the 70s (relevant papers will be referred to in Chaper 2), not many papers, so far, have studied the LDI/LDD lter at nite conditions. This in the main contribution of the theses. The occurrence and suppression of parasitic oscillations is extensively studied. The LDI/LDD structure is also compared, concerning coecient sensitivity and quantization noise levels, to another low-sensitive lter structure, namely the wave digital lter. The computational properties of the lter structure are considered. Finally, the lter structure is used in adaptive applications and is compared to known adaptive lter structures.. A Remark on Names A logical name for the lter structure considered is digital ladder lter (DLF), as the structure originates from an analog ladder lter. In 90], it is called bilinear digital ladder lter (BDLF) where \bilinear" stands for the bilinear transformation. The lattice variant should, therefore, be called, lattice (bilinear) digital ladder lter. However, to avoid confusion with the Gray{Markel lattice/ladder structures 34], they are called LDI/LDD lattice lters. The name (B)DLF is reserved for structural ladder lters..

(13) 1.1. SCIENTIFIC CONTRIBUTIONS. 3. 1.1 Scientic Contributions New results in this thesis are as follows:. In Chapter 2, the LDI/LDD lattice lter structure is studied. An LDI/LDD lattice lter structure is presented which exhibits good stability properties at nite wordlength (Chapter 3). A modied implementation of the presented LDI lter structure is also introduced, which yields better computational properties. Design formulas for the general-order LDI/LDD lattice lter are given. Parts of the material in this chapter have been presented at the following conferences:. L. Harnefors, J. Holmberg, M. Sollander, and S. Signell, \Computationally fast lattice bilinear digital ladder lters with comparison to circulator WDF's," in Proc. IEEE International Symp. on Circuits and Systems, Monterey, CA, Vol. 5, pp. 383{386, June 1998. J. Holmberg, L. Harnefors, K. Landernas, and S. Signell, \Computational properties of LDI/LDD lattice lters," in Proc. IEEE International Symp. on Circuits and Systems, Vol. 2, pp. 685{688, Sydney, Australia, May 2001.. In Chapter 3, stability at nite wordlength of the LDI/LDD allpass lter structure is. analyzed. The phenomena which can occur at nite wordlength are quantization and overow limit cycles. Forced-response instabilities are also considered. The analysis is divided into second- and general-order cases. For the second-order LDI/LDD allpass lter it is shown that the lter can be implemented free from both overow and quantization limit cycles if the poles are placed around z = 1 (LDI) and z = ;1 (LDD). This is provided that energy-decreasing nonlinearities are used, such as magnitude truncation. It is also shown that the lter structure is free from forcedresponse instabilities, provided that saturation or triangular overow arithmetics are used. For all cases it is assumed that the nonlinearities are placed immediately before the delay elements. The case where only one quantizer is sucient is also analyzed, where Tsypkin's criterion is used, yielding the same restrictions in the z-plane as the case where the nonlinearities are placed immediately before the delay elements. Both scaled and unscaled cases are considered. The results are also presented in: J. Holmberg, L. Harnefors, and S. Signell, \Stability analysis of the second-order lossless digital integrator allpass lter," in Proc. IEEE International Symp. on Circuits and Systems, Geneva, Switzerland, Vol. 1, pp. 367{370, May 2000. For the general-order case a Lyapunov function is presented, which is used to prove absence of overow limit cycles if saturation arithmetics are used and the nonlinearities placed immediately before the delay elements. This is provided that the lter coecients are set to certain values. Stability regions in the z-plane are established.

(14) 4. CHAPTER 1. INTRODUCTION using the Lyapunov function. Also in this case both scaled and unscaled cases are considered. The general-order Lyapunov function is presented in: L. Harnefors, J. Holmberg, and S. Signell, \Suppression of overow limit cycles in LDI all-pass/lattice lters," IEEE Trans. on Circuits and Systems{I, Vol. 47, No. 4, pp. 594{598, April 2000.. In Chapter 4, quantization noise levels of the LDI/LDD allpass lters are studied and compared to those of corresponding wave digital allpass lters. Analytic expressions for the rst- and second-order allpass lters are established. However, for higher lter orders the analysis is restricted to numerical evaluations. Parts of the material in this chapter have been presented at the following conferences:. J. Holmberg, L. Harnefors, and S. Signell, \Quantization noise analysis of wave digital and lossless digital integrator allpass/lattice lters," in Proc. IEEE International Conf. on Acoustics, Speech, and Signal Processing, Phoenix, AZ, Vol. 3, pp. 1133{ 1136, March 1999. J. Holmberg, L. Harnefors, and S. Signell, \A comparison of quantization noise levels of the LDI and wave digital circulator allpass lters," in Proc. IEEE International Symp. on Circuits and Systems, Orlando, FL, Vol. 3, pp. 327{330, June 1999.. In Chapter 5, coecient quantization of the LDI/LDD allpass lter is analyzed. The. results are compared to corresponding wave digital allpass lter results. Pole density for the second-order allpass lters is studied. A well-known optimization method, simulated annealing, is used to nd the lter coecients of a number of test lters. Finally in this chapter, results from Monte Carlo analyses of the same test lters are presented.. In Chapter 6, the computational properties for bit-serial arithmetics of the LDI allpass lter are studied, which have also been presented at the following conference:. J. Holmberg, L. Harnefors, K. Landernas, and S. Signell, \Computational properties of LDI/LDD lattice lters," in Proc. IEEE International Symp. on Circuits and Systems, Vol. 2, pp. 685{688, Sydney, Australia, May 2001. Implementation proposals of magnitude truncation and saturation arithmetics (for bit-serial arithmetics) are presented, since they are advantageous in the suppression of limit cycles and forced-response instabilities. A modied second-order LDI/LDD allpass lter structure is presented, which yields a lower minimal sample period than the original LDI lter structure. The LDI lter structure is scheduled over a single interval as well as to be maximally fast. In the single-interval case hardware implementations are presented, with and without the mentioned nonlinearities. All the.

(15) 1.2. DIGITAL FILTER STRUCTURES. 5. realizations are compared concerning resource requirements to corresponding wave digital allpass lter implementations. Maximally fast implies that the sample period is equal to the minimal sample period. Maximally fast and single-interval scheduling of the second-order LDI allpass lter was presented at the following conference: J. Holmberg, K. Landernas, L. Harnefors, and M. Vesterbacka, \Implementation aspects of second-order LDI/LDD allpass lters," in Proc. European Conf. on Circuit Theory and Design, Vol. 1, pp. 237{240, Espoo, Finland, August 2001. Digit-serial implementation of LDI/LDD allpass lters is not considered in this thesis. However, an initial study of the topic is presented in: K. Landernas, J. Holmberg, L. Harnefors, and M. Vesterbacka, \Digit-serial implementation of LDI/LDD allpass lters," accepted to ISCAS 2002.. In Chapter 7, the LDI lter is used in adaptive applications, where the analysis starts. by studying the stability of LDI lters with time-varying coecients. Adaptive LDI lter structures are presented where the gradient realizations are studied. Simulations results are presented and compared to corresponding results, where either direct-form lters or tapped state lattice lters are used.. 1.2 Digital Filter Structures In this thesis, one-dimensional digital lters are considered. Ideally, such lters can be described by a time-invariant, linear, and causal dierence equation (DE):. y(n) =. M X i=0. biu(n ; i) ;. N X j =1. aj y(n ; j ):. (1.1). Time-varying digital lters will also be considered, however, only in Chapter 7. The DE describes how the output signal y(n) is calculated for a given input signal u(n). Another way of representation is by transforming the DE to the z-domain and expressing it as a transfer function (TF):. P. M b z ;i Y (z) = B (z) = H (z) i=0 i = P N ; j U (z) 1 + j=1 aj z A(z). (1.2). where bi and aj in (1.2) are the lter coe cients and N is the lter order. Digital lters are used mainly to suppress specied frequency bands. For example, lowpass lters retain frequencies between 0 and a specied cut-o frequency fc. Highpass lters work in the opposite way. There are, of course, also bandstop and bandpass lters. The lter coecients are set to give a certain frequency function, which is calculated by substituting z = ej in.

(16) CHAPTER 1. INTRODUCTION. 6. (1.2). The variable is here called the normalized frequency 1, and is dened as = ff = 2# (;0:5 0:5) (1.3) s where fs is the sample frequency 77]. Yet an alternative way of describing a digital lter is the state-space form. A state-space description of a linear discrete-time system, where the digital lter is a special case, can be expressed as. x(n + 1) = Ax(n) + Bu(n) y(n) = Cx(n) + Du(n). (1.4) (1.5). where x(n) is the N -dimensional state vector, and A, B , C , and D are referred to as the state-space matrices. (A and B are not to be confused with A(z) and B (z ) in (1.2).) It is easily shown that the transfer function can be obtained from the state-space description as H (z) = C (zI ; A);1B + D: (1.6) State-space descriptions are commonly used when lter properties such as noise gain, stability under nite conditions (Chapter 3), and coecient sensitivity (Paragraph 1.3.3) are examined. A TF has an innite number of possible state-space realizations fA B C Dg, giving dierent lter structures. To verify this, we introduce a new state vector, w(n), as follows: w(n) = Tx(n) (1.7) where T is an invertible N N matrix. The state-space equations can then be rewritten according to. T ;1w(n + 1) = AT ;1w(n) + Bu(n) ) w(n + 1) = TAT TB u(n) | {z0 ;}1 w(n) + |{z} A B0 y(n) = CT | {z;0 }1 w(n) + Du(n) C yielding the same TF as (1.6):. C 0(zI ; A0 );1B 0 + D = CT ;1(zI ; TAT ;1);1TB + D = CT ;1T (zI ; A)T ;1];1TB + D = C (zI ; A);1B + D:. (1.8). (1.9). Thus, fA0 B 0 C 0 Dg is also a realization of H (z). The choice of lter structure is hardly academic when nite-wordlength eects are considered. Regarding coecient sensitivity and quantization noise, for example, one structure may be much better than another. 1. Also popularly known as fnosk..

(17) 1.2. DIGITAL FILTER STRUCTURES. 7. Eqs. (1.1), (1.2), and (1.6), which describe the input-output relations mathematically, do not reveal in which order the arithmetic operations are to be executed. A lter can be implemented in many dierent ways and still have the same frequency behavior. Therefore, the above models are converted to a computational algorithm which is dened by a structure or network consisting of interconnections and arithmetic operations 100]. This structure is related to|but not fully specied by|the state-space model. The most commonly used is the signal

(18) ow graph (SFG) which consists of nodes and branches 98]. However, in the SFG the calculation order of each individual node is not completely specied. So, for a more correct description, the fully specied SFG is used 100]. Digital lter structures fall into two categories, namely nite impulse response (FIR) lters (Figure 1.1) and innite impulse response (IIR) lters (Figure 1.2). FIR lters are obtained by setting aj = 0 j 1 in (1.1), which makes the lter nonrecursive. The poles are located at the origin while the zeros can be placed anywhere in the z-plane. Hence, FIR lters are always stable (for any set of coecient values), even under nite conditions. This is a great advantage of non-recursive lters. Another advantage is that they can be realized with exactly linear phase, which is desirable in applications where phase-distorted information is not acceptable. The major disadvantage of FIR lters is that they need high orders to fulll a certain specication. Thus, when implementing FIR lters, large amounts of memory and arithmetic processing are needed. Take for example the case where a lter with cut-o frequency 0.01 and passband and stopband ripples 0.3dB and 40dB, respectively, is to be designed. In the FIR lter case the required lter order is 112, if the Remez-algorithm 87] is used, where for an IIR lter the required lter order is 7, for a Butterworth lter 87]. This makes FIR lters unattractive in many applications. IIR lters, described by (1.2), are, in contrast to FIR lters, recursive. Their poles and zeros can be placed anywhere within the z-plane. Of course, they become unstable if the poles are located outside the unit circle. Another problem is that they can exhibit limit cycles 18], as will be seen in Chapter 3. There are various dierent IIR lter structures. We shall consider the following. Direct-form (DF) lters (see Figure 1.2) have a very regular structure, which evidently makes them easy to implement. A disadvantage is that they have high coefcient sensitivities, especially for orders higher than two. So, for higher orders, the structure is divided into smaller (rst- and second-order) structures, which are either parallel or series connected 51]. The wave digital (WD) lter (WDF) theory originates from 70s when Fettweis combined electronics with microwave theory 25]. The idea is to simulate voltage waves in the reference lter (as further discussed in Section 1.6). The lter is transformed to the discrete domain using certain design rules. The lossless discrete integrator (LDI) lter, in contrast to the WDF, simulates voltages and currents in the reference lter. This thesis examines a class of the LDI lters, namely the LDI lattice lter, and comparisons to WDFs are made..

(19) CHAPTER 1. INTRODUCTION. 8. u(n) b0. D. D b1. D b2. +. D bM-1. +. bM. +. +. y(n). Figure 1.1: M th order FIR lter. \D" denotes the unit (one-sample) delay. u(n). +. +. y(n). b0 D +. + -a1. b1 D. +. + -a. b2. 2. +. + -a N-1. bN-1 D. -a N. bN. Figure 1.2: N th-order DF IIR lter..

(20) 1.3. FINITE-WORDLENGTH EFFECTS. 9. 1.3 Finite-Wordlength Eects A digital lter can be implemented in a DSP or in hardware (ASIC/FPGA). In both implementation methods, the coecients and the signals must be represented with nite wordlength, and must have a specic number representation. A number representation describes how a digital system interprets a binary value. There are two groups, namely xed-point and

(21) oating-point representation. Floating-point number representation uses a mantissa and an exponent. These are set in the single oating-point IEEE standard 57] to 24 and 8 bits, respectively. Many modern DSPs support oating-point arithmetics in the hardware, for example Motorola's DSP96001 100]. The arithmetic operations for oating-point number representation are complicated to implement, large in hardware, and consume a lot of power. Therefore, xedpoint arithmetics are more commonly used for high-performance digital lters. There are several dierent types of xed-point number representation. The most common is the two's-complement representation 57]. In digital lters, there are two dierent types of nonlinearity which originate from nite wordlength, namely quantization and over

(22) ow.. 1.3.1 Quantization Quantization of signals in digital lters is necessary, due to the fact that nite wordlength is used. For example, if a signal x and a coecient y, with wordlengths Wx +1 and Wy +1, respectively, are multiplied, the product's wordlength will be Wx + Wy + 1. Hence, the increase in wordlength must, in recursive digital lters, be eliminated. A quantization removes the lowest bits of a signal, which is equivalent to introducing an error to the signal. The error is modeled dierently depending on the type of quantization. For roundo quantization (see Figure 1.3), the error can be modeled as white stochastic noise e(n) with rectangular density function, variance e2 = 22(;Wd+1) =12 = Q2 =12 (where Wd is number of bits in the signal excluding the sign bit), and average value zero 18], provided that the input signal is white-noise type. Value truncation is merely a shifted version of the round-o quantization. Therefore, it can be modeled in the same way with the exception that the average value is ;Q=2. Magnitude truncation cannot, however, be modeled in the same way, since the quantization error is correlated with the signal (regardless of the signal properties). In 16], two dierent models of the quantization error for magnitude truncation are introduced. The resulting error is called quantization noise or round-o noise. It is of interest to analyze the total noise content at the lter output, since the SNR is aected in a negative way. Hence, it is desirable that the total noise content should be as low as possible. The noise variance at the lter output, provided that round-o quantization or value truncation.

(23) CHAPTER 1. INTRODUCTION. 10. is used and the input signal is (approximately) white, is calculated as. o2. NQ Z 1=2 NQ Z 1=2 X X 2 j 2 2 2 = e j Hi(e )j d = e j Hi(ej2 )j2d i=1 | ;1=2 {z } |i=1 ;1=2 {z }. (1.10). Gi Gtot where Hi(z) is the transfer function from noise source i to lter output, Gtot is the total unscaled noise gain, and NQ is the number of quantizers. Gi is called the unscaled noise gain, and can be rewritten using Parseval's relation 77]: Gi =. 1 X n=0. h2i (n). (1.11). where Hi(z) is the z-transform of the impulse response hi(n). In 16], it is shown that systems that use magnitude truncation instead of round-o quantization in general give the equivalence of 2 or 3 bits more noise at the lter output. In 27] and 52], it is shown that the coecient sensitivity is closely related to the quantization noise. That is, lters with low quantization noise at the lter output have also low sensitivity (Chapter 5). Quantization is a nonlinear and non-invertible function which can generate unwanted oscillations. These oscillations, which can be seen at the lter output, are called quantization limit cycles or granular oscillations. Having been investigated since the 70s, e.g., 101], their magnitudes are small, only a couple of least signicant bits (LSBs). So, their signicance can be reduced by using long data wordlengths and discarding the LSBs at the lter output 85]. This will, however, for bit-parallel implementations, increase the total chip area and, for bit-serial implementations, decrease the throughput of the lter (see Chapter 6). f(x). f(x). Q. f(x). Q. -Q. Q. -Q Q -Q. (a). -Q Q. x -Q. (b). Q. x. x. -Q. (c). Figure 1.3: Quantization: (a) Magnitude truncation. (b) Round-o. (c) Value truncation. Let f ( ) denote the quantization nonlinearity. Referring to Figure 1.3, value truncation is the quantization method easiest to implement, since it just discards the unwanted bits..

(24) 1.3. FINITE-WORDLENGTH EFFECTS. 11. Magnitude truncation always truncates towards zero, i.e., jf (x)j jxj, and that is a noble property for suppression of quantization limit cycles, as will be seen in Chapter 3.. 1.3.2 Overow. Overow occurs when the sum of two numbers is larger than the range of the number representation. Overow can easily be detected for two's-complement number representation: if the sum of two positive numbers becomes negative, or vice versa, an overow has occurred$ this is the wrapping characteristics of Figure 1.4. When an overow appears it can be handled in many ways, as illustrated in Figure 1.4, where the overow nonlinearity is denoted as o( ). Saturation arithmetics set the overowed signal to the largest or smallest value of the number representation, depending on the sign of the signal. Triangular characteristics invert all the bits of the signal (including the sign bit), and zeroing sets it to zero. If an overow occurs, the lter states may start to oscillate with large amplitude. These oscillations are called over

(25) ow limit cycles. They are sustained even when the input signal is zero, u(n) = 0. Overow limit cycles have been studied extensively, see e.g. 2], 19], 60], and 102]. The saturation nonlinearity is the most attractive choice, since it tends to suppress overow limit cycles. Generally, this is also true for the triangular nonlinearity. Forced-response instabilities are another phenomenon, which arises from an overow when the input signal is nonzero. Forced-response instabilities are generally complicated to analyze. The probability of overow can be reduced by scaling. The idea is to lower the gain after an adder which has a high probability of overow. One overow event per 104{106 samples is acceptable 100]. However, if more overows appear, scaling is necessary. Socalled scaling multipliers ki = 2j j = 1 2 : : : are inserted in the lter. Their values are always multiples of two (i.e., bit-shifts) as they should be easy to implement, and can be chosen in dierent ways. One is to calculate the L2-norm value at the node which is going to be scaled. The L2 -norm is dened as:. jjH (ej2 )jj2 =. sZ 1=2. j H (ej2 )j2d ;1=2. (1.12). where H (ej2 ) here is the frequency function from the input to the scaling node. There are some nodes in a digital lter which are more prone to getting overows than others. They are referred to as critical over

(26) ow nodes 100]. A typical critical overow node is one where an adder is followed by a multiplier. When an overow occurs in such a node the error is multiplied, i.e., the error is most likely increased.. 1.3.3 Coecient Quantization. In the implementation of a digital lter, the lter coecients must be represented with nite wordlength. Therefore, the ideal coecients must be truncated. This will alter the.

(27) CHAPTER 1. INTRODUCTION. 12 o(x). o(x). 1. 1. -1 x. -1. x. 1. 1. -1. -1. (a). (b). o(x). o(x). 1. 1. -1 x. -1. x. 1. 1. -1 (c). -1 (d). Figure 1.4: Overow characteristics: (a) Saturation. (b) Wrapping (two's complement). (c) Zeroing. (d) Triangular. positions of the poles and zeros$ the lter may even become unstable! The deviation of a pole's position is dependent on the number of bits used in the coecients. For a xed wordlength the poles can be placed only at a xed number of positions. These positions are concentrated to dierent areas of the z-plane depending on the lter structure. For example, the second-order DF lters have the lowest concentration of poles near the real axis, which is illustrated in Figure 1.5. The error in a lter coecient (aj ) due to coecient quantization aect the pole pk as follows 77]: pNk ;j @pk = ; (1.13) QN @aj m=1m6=k (pk ; pm ) where the pole polynomial is given by A(z) = 1 + a1z;1 + + aN z;N = (1 ; p1 z;1 )(1 ; p2z;1 ) : : : (1 ; pN z;1 ) ;1 ;1 ;1 ;1 ;1 = (1 ; pk z;1 ) (1 | ; p1z )(1 ; p2z ) : : : (1 ; pk;{z1z )(1 ; pk+1z ) : : : (1 ; pN z }) A1(z) = (1 ; pk z;1 )A1(z): (1.14) This is the so-called pole sensitivity and it shows that if the poles are placed closely together, a small variation in the lter coecient aj will give a large variation in the location.

(28) 1.4. DIGITAL LATTICE FILTERS. 13. 1. 0.8. 0.6. 0.4. Im(z). 0.2. 0. −0.2. −0.4. −0.6. −0.8. −1 −1. −0.8. −0.6. −0.4. −0.2. 0 Re(z). 0.2. 0.4. 0.6. 0.8. 1. Figure 1.5: Typical pole concentration of the second-order DF lter. of the pole pk . Further, the higher the lter order the higher the pole sensitivity. Therefore, digital lters are most commonly divided into smaller (rst- and second-order) structures, which are either parallel- or series-connected. Series-connected lters are referred to as cascade lters. Cascade lters are preferable, since they are more robust to coecient quantization 77]. The frequency function is also, of course, changed from the ideal one when the coefcients are truncated. There is usually a trade-o between the number of bits used and how much the frequency function may deviate. Filter structures that give an adequate frequency function at relatively short coecient wordlengths are referred to as low sensitive. As already stated, low-sensitive lter structures generally allow less power consumption, smaller chip area, and faster computation 100]. Reduction of bits in coecients is not so interesting when lters are implemented in DSPs, since all binary words have the same wordlength. However, for ASICs and FPGAs, the reduction may permit a signicantly smaller lter in terms of chip area and also higher throughput. Dierent optimization methods are used to nd the best set of coecients, e.g., the simulated annealing algorithm 56] (see further Chapter 5).. 1.4 Digital Lattice Filters The digital lattice lter originates from an equally resistively terminated symmetrical lattice two-port network, which is shown in Figure 1.6. The TF of the analog lattice network is (s) ; Z1(s) H (s) = VVout((ss)) = 21 (Z (sZ)2+ 1)(Z1(s) + 1) in 2.

(29) CHAPTER 1. INTRODUCTION. 14 r=1 Z1(s). Vin. Z2(s) r=1. Vout. Z (s) 2. Z1(s) 1. Figure 1.6: Reference lter of the digital lattice lter. 1 (s) + 1 ; 1 = 12 (ZZ2 ((ss));+Z1)( Z1(s) + 1) 2 1 ; Z1 (s) ; 1 = 12 ZZ2((ss)) ; 2 + 1 Z1 (s) + 1 1 (1.15) = (H1(s) ; H2(s)) 2 where H1(s) and H2(s) are analog allpass lters. The analog lattice network is not feasible in practice, since it has very high sensitivity to component variations. Therefore, it is only used as a prototype for the digital lattice lter. Digital lattice lters also consist of two allpass lters which are connected in parallel 66], 86], 104]: H (z) = H1(z) 2 H2(z) : (1.16) Digital lattice lters can be implemented with a canonical number of delays and multipliers, i.e., the same number, N , as the lter order. Low passband sensitivity is typically obtained, and the lters are desirable in applications where low power consumption and high throughput are major issues. Further, they can be designed as odd-order Cauer (elliptic), Chebyshev, or Butterworth lowpass/highpass lters as well as two times odd order (6,10,14,: : :) bandpass and bandstop lters. The frequency function of (1.16) can be expressed as z ;(}| ) { ej 1() ej 2() = ej 1() 1 ej(&2 ( ) ; &1 ( )) 2 2 j ( 1 ( )+;( )=2) e = (e;j;()=2 ej;()=2 ) (1.17) 2 + ) H (ej2 ) = cos((& ( ) ; & ( ))=2)ej( 2()+ 1 ())=2 = ; ) Hc(ej2 ) = sin((& 2( ) ; & 1( ))=2)ej( 2 ()+ 1 ()+=2)=2 2 1 where &x( ) x = 1 2 are the phase functions of the allpass lters. Hence, we introduce Hc as the transfer function obtained for the + sign, while H is kept for the ; sign in (1.16)..

(30) 1.5. BILINEAR TRANSFORMATION. 15. Note that jH (ej2 )j2 + jHc(ej2 )j2 = sin2((&2( ) ; &1 ())=2)+cos2((&2() ; &1( ))=2) = 1: (1.18) This relationship is called Feldtkeller's equation, where H (ej2 ) is the ordinary function (lowpass) and Hc(ej2 ) is the complementary frequency function (highpass). The stopband ripple for the complementary function is determined by the passband of the ordinary function. Large passband ripple of the latter gives small attenuation of the complementary function in the stopband. In digital lattice design, the poles of the desired lter are rst calculated in the splane, using for example Matlab. The next step is to separate the poles into two allpass lters, H1(s) and H2 (s). The pole(s) with the smallest real part is rst picked to H1(s). The pole pair having the second smallest real part is picked to H2 (s). Then every other pole pair is picked to H1 (s) and H2 (s), respectively 31]. This is illustrated in Figure 1.7. After separation the allpass lters are transformed to the z-plane using the bilinear transformation, see below. Digital lattice lters are, as mentioned earlier, known to exhibit low sensitivity in the passband. This can be explained using the results of Paragraph 1.3.3, i.e., if the poles are placed relatively far from each other, the lter structure becomes insensitive to lter coecient variations. In the separation, the poles which are placed nearest to each other are picked to dierent allpass lters. s-plane. Im(s). H (s) 1. H (s) 2. Re(s). Figure 1.7: Pole separation.. 1.5 Bilinear Transformation For digital lters, the bilinear transformation (BT) 90]: 1 , z = 1 + ks s = T2 zz ; (1.19) 1 ; ks |{z} + 1 1=k is attractive, since the j! axis in the s-plane is mapped onto the unit circle in the z-plane. The BT is also known as Mobius transformation or Tustin's formula 105]. It will be used frequently in the following..

(31) CHAPTER 1. INTRODUCTION. 16. 1.6 An Introduction to WD Filters This section gives a brief introduction to WD lters. WD lters represent the perhaps best known family of low-sensitive digital lter structures. In this thesis, WD lters are frequently compared to LDI lattice lters. Considering the vastness of the theory for WD lters, some other literature can be recommended to the interested reader: 24], 26], and 28]. A one-port network can be described as shown in Figure 1.8, with waves instead of voltages and currents. Eqs. (1.20){(1.21) describe Figure 1.8 mathematically$ A is the I A V B. R. Analog Passive Network. Figure 1.8: Waves owing in and out of a network. incident wave, B is the reected wave and R is the so-called port resistance. The port resistance corresponds to the characteristic impedance of a transmission line. Waves can propagate in two directions$ incident (into the network) and re

(32) ected (out of the network):. A(s) = V (s) + RI (s) B (s) = V (s) ; RI (s). (1.20) (1.21). The TF for the network, with waves used instead of voltages, is called re

(33) ectance function and is dened as follows: (s) = V (s) ; RI (s) : (1.22) S (s) = B A(s) V (s) + RI (s) An inductor has the following reectance function: RI (s) = fV (s) = sLI (s)g = ; 1 ; ks S (s) = VV ((ss)) ; (1.23) + RI (s) 1 + ks where k = L=R. Now, by using the BT, it is transformed into. S (z) = ;z;1 :. (1.24). Thus, an inductor can be simulated with a delay and negative sign in z-domain. Similar calculations for a capacitor yield S (z) = z;1 (1.25) where in this case k = RC . A resistor becomes a short-circuit. The interconnections between the elements in an analog network are transformed to so-called adaptors (symmetric two-port, three-port series, or three-port parallel adaptors).

(34) 1.6. AN INTRODUCTION TO WD FILTERS. 17. 25], which simulate Kirchho's laws. The symbols and SFGs of the adaptors are depicted in Figure 1.9. The element values correspond to port resistances in the adaptors: RC = Ck = tan(Cc) RL = Lk = tan(L ) : (1.26) c. where c is the cut-o frequency. The adaptor coecients are calculated from the port resistances as follows. Three-port series adaptor: (1.27) i = RRi RT = R1 + R2 + R3 : T. Three-port parallel adaptor:. i = GGi GT = G1 + G2 + G3 : T. . where Gi = R1i . Symmetric two-port adaptor:. 1 ; R2 =R R +R : 1. 2. (1.28). (1.29). A WD lattice lter consists of two allpass lters which are connected in parallel 6], 25]. WD allpass lters are built using circulators. An incident wave in a circulator has the property of traveling to the next port. WD lattice lters are implemented with rst- and second-order cascade-connected WD allpass sections (see Figure 1.10). The rst-order allpass section is, most often, implemented with one symmetric two-port adaptor. The second-order WD allpass lter can be implemented in several dierent ways. Here, two cases are considered. The rst case has a three-port series adaptor and the second two symmetric two-port adaptors. The former is attractive in the sense that it only has one multiplier in the so-called critical loop, which allows fast computation, as will be found in Chapter 6. However, the required coecient wordlength is generally longer for the former 53]. The three-port parallel adaptor, which is also depicted in Figure 1.9, will not be considered in this thesis, since it has a longer critical loop than the three-port series adaptor 37]. WD lattice lters are suitable for high-speed lter implementations, since they have a very parallel structure. They have a canonical number of multipliers and delay elements. A disadvantage is that they have very high stopband sensitivities, which is characteristic for lattice lters of any type, as previously mentioned..

(35) CHAPTER 1. INTRODUCTION. 18. A1. B1. R1. A3. -1. Three-port parallel adaptor A1. A2 -1. +. R3. + +. A3. 3. 1. B3. +. -1 -1. R2 A2. +. B2. Three-port series adaptor A1 B1. R1. +. B1. B2. B3. A1. A2. A3. + R3. A3 + B3. 1. +. +. R2. +. 3. -1 A2. B2 B1. B1. R1. B2. B3 A. A1. Symmetric two-port adaptor A1. -1 +. 2. + R2. A2. -1 1. B2 +. +. B2. B. Figure 1.9: Adaptors.. 1.

(36) 1.6. AN INTRODUCTION TO WD FILTERS. 19. -1. -1. D. D. 3. D. D. 1. A k. D. N-1. 2. B. 1. N. A. 1. k 1. B. 2. A. 2. k. 2. k. 3. N. BN. N-1. k. N. (a). D. D. D. D 1. D. -1. 3. 2N+1. -1. 2N+3. 1. A k. 1. 1. B. A. 1. k. 2. B. AN. 2. k 2. 3. k. N-1. BN k. N. (b). Figure 1.10: Odd-order WD allpass lters consisting of, (a): Symmetric two-port adaptors, and (b): Three-port series adaptors. ki i = 1 2 : : : N are scaling multipliers..

(37) 20. CHAPTER 1. INTRODUCTION. 1.7 Test Filter Specications In this thesis we will frequently consider three test lters: Filter Speci cation 1: a 7th-order lowpass lter with cut-o frequency 0:05 and passband and stopband ripples 0:05dB and 70dB, respectively (Figure 1.11). Filter Speci cation 2: a 10th-order bandpass lter with cut-o frequencies 0:2 and 0:3 and passband and stopband ripples 0:1dB and 80dB, respectively (Figure 1.12). Filter Speci cation 3: a 9th-order highpass lter with cut-o frequency 0:40 and passband and stopband ripples 0:02dB and 90dB, respectively (Figure 1.14). The lter structures under consideration are: the LDIIII and LDDIII lattice lters (see further Chapter 2), the WD lattice lter with two-port symmetric adaptors, and the WD lattice lter with three-port series adaptors. The WD lattice lters are scaled according to Figure 1.10. The LDI/LDDIII lattice lters are scaled before and after each allpass lter. L2-norm scaling is considered (see Section 1.3)..

(38) 1.7. TEST FILTER SPECIFICATIONS. 21 (a). 0. Magnitude [dB]. −0.01 −0.02 −0.03 −0.04 −0.05 0. 0.005. 0.01. 0.015. 0.02 0.025 0.03 Normalized frequency. 0.035. 0.04. 0.045. 0.05. 0.35. 0.4. 0.45. 0.5. (b). Magnitude [dB]. 0. −50. −100. −150. 0. 0.05. 0.1. 0.15. 0.2 0.25 0.3 Normalized Frequency. Figure 1.11: Filter Specication 1. (a) Passband. (b) Over-all.. (a) 0.1. Magnitude [dB]. 0.05 0 −0.05 −0.1 −0.15 −0.2 0.2. 0.21. 0.22. 0.23. 0.24 0.25 0.26 Normalized Frequency. 0.27. 0.28. 0.35. 0.4. 0.29. 0.3. (b) 0 Magnitude [dB]. −20 −40 −60 −80 −100 −120 −140 0. 0.05. 0.1. 0.15. 0.2 0.25 0.3 Normalized Frequency. 0.45. 0.5. Figure 1.12: Filter Specication 2. (a) Passband. (b) Over-all..

(39) CHAPTER 1. INTRODUCTION. 22 (a) 0. Magnitude [dB]. −0.005 −0.01 −0.015 −0.02 −0.025 −0.03. 0.4. 0.41. 0.42. 0.43. 0.44 0.45 0.46 Normalized Frequency. 0.47. 0.48. 0.49. 0.5. 0.4. 0.45. 0.5. (b). Magnitude [dB]. 0. −50. −100. −150. 0. 0.05. 0.1. 0.15. 0.2 0.25 0.3 Normalized Frequency. 0.35. Figure 1.13: Filter Specication 3. (a) Passband. (b) Over-all.. 1. 0.8. 0.6. 0.4. Im(z). 0.2. 0. −0.2. −0.4. −0.6. −0.8. −1 −1. −0.8. −0.6. −0.4. −0.2. 0 Re(z). 0.2. 0.4. 0.6. 0.8. 1. Figure 1.14: Pole locations. Filter Specication 1 (crosses). Filter Specication 2 (stars). Filter Specication 3 (rings)..

(40) Chapter 2 LDI/LDD Lattice Filters 2.1 Introduction Passive, especially so-called doubly-terminated, LC lters are known to exhibit low sensitivity to component variations 88]. Therefore, as active lter design became an intense research topic (beginning in the 50s), LC lters quickly became popular is prototype lters (reference lters) for active and switched-capacitor (SC) lters 33], 70]. Low-sensitive digital lter structures are advantageous in low-power and high-throughput applications, as discussed in Section 1.3. Hence, it is not surprising that researchers later also turned to LC lters as prototypes for digital lters. The best known example of this is undoubtedly the WD lter family (Section 1.6). Another, not quite as well known, digital lter structure is the LDI lter. The theory for this lter structure was rst presented by Bruton in the early 70s 11]. The idea is to simulate voltages and currents in an LC lter. Bruton introduced a number of analogto-digital transformations, e.g., the so-called LDI transformation. A problem which was encountered was that the LDI transformation yields an unstable digital lter. Bruton also showed that by using the BT, the obtained digital lter has delay-free loops: algebraic loops that cannot be realized. He extended the theory in 12]$ using the BT, the delay-free loops were eliminated with SFG manipulations. The obtained digital lter structure was shown to have low sensitivity, and could be realized as Butterworth and Type I Chebyshev TFs. Vaughan-Pope and Bruton derived exact design formulas for LDI ladder lters using the LDI transformation 96]. In 61], the design formulas were further developed concerning also LDD lters (see Section 2.2). Turner presented methods for lter design by mapping the magnitude response of an elliptic analog prototype lter 94], 95]. In 62], the theory for LDI ladder lters was summarized. In 90], another approach to the design of LDI lters was presented, there called a bilinear digital ladder lter (BDLF). In this case, the BT was used in the transformation. The delay-free loops were eliminated using matrix manipulations. (In Paragraph 2.1.2, a design example of the fth-order BDLF is given.) Other papers worth mentioning regarding this lter structure are 2], 3], 5], and 61]. 23.

(41) 24. CHAPTER 2. LDI/LDD LATTICE FILTERS. The idea (lattice lter approach) of using two allpass lter which are connected in parallel in digital lter design was introduced in the mid-70s 66]. In 25], Fettweis introduced the WD lattice lter (refer to Section 1.6). LDI allpass lters can be derived from the LDI ladder lter by using the so-called re

(42) ected voltage, as will be seen in Section 2.2. This was shown in, e.g., 38], 68], 69], and 71]. The LDI lattice lter structure has been modied a few times in order to improve the performance of the lter. For example, in 39], the critical loop was decreased by one multiplier by modifying the lter structure. In Section 2.2, a new LDI lattice lter structure is presented where the previously used input delay is eliminated 39].. 2.1.1 LDI Ladder Design Approach I. An analog LC lter can be simulated as an active leapfrog lter 11], 33], 90], which consists of interconnected continuous-time integrators 36]. This analog simulation can then be transformed into a digital counterpart in some dierent ways. The most commonly used is the BT. The problem with this transformation is that the numerator and the denominator are of the same degree, cf. (1.19). Hence, a delay-free forward path results 11]. Therefore, transforming the LC or leapfrog lter with the BT will give rise to a digital lter structure which has delay-free loops, which are not sequentially computable 100]. In the early 70s, Bruton presented other transformations 11], e.g., the LDI and LDD transformations. They are dened as follows: s = T1 zz

(43) 1=21 (2.1) where ; and + correspond to LDI and LDD, respectively. The transformations are called lossless, since they do not introduce a phase error: substituting z = ej!T in (2.1), we obtain (for the LDI case) j 2 sin(!=2) (2.2) T i.e., a 90-degree phase shift, just as for s = j!. However, the transformation maps the poles to the outside of the unit circle, i.e., the digital lter becomes unstable. Therefore, in 94] and 95], Turner expanded this theory further where both the LDI transformation and the BT were used. Each component is transformed to the z-plane with the LDI transformation, i.e., (Inductor) L(z) = VI ((zz)) = TL (z1=2 ; z;1=2 ) C (z) = VI ((zz)) = CT (z1=2 ; z;1=2 );1 (Capacitor) (2.3) R(z) = VI ((zz)) = R2 z1=2 (z1=2 + z;1=2 ): (Resistor) where L, C , and R are the analog component values. Note that the resistor is scaled with 1 1=2 1=2 ;1=2 ). The \digital components" are then transformed back to the s-plane 2 z (z + z.

(44) 2.1. INTRODUCTION. 25. with the BT, i.e.,. . . 2 s ;1 V ( s ) 1 T L(s) = I (s) = sL ; 4L (Inductor) 1 C (s) = VI ((ss)) = sC (Capacitor) (2.4) 1 Ts ;1 V ( s ) R(s) = I (s) = R ; 2R (Resistor) Hence, the bilinearly transformed impedance-scaled inductor, capacitor, and resistor are equivalent to an LDI transformed inductor, capacitor, and resistor, respectively. Now, by rewriting the analog LC lter with the \components" in (2.4), the BT can be used without introducing delay-free loops in the lter. However, the lter will consist of z;1=2 delay elements. They can be changed to z;1 by scaling the lter with z;1=2 . The SFG of a fth-order LDI ladder is depicted in Figure 2.2.. 2.1.2 LDI Ladder Design Approach II (BDLF). The BDLF design approach of 90] was the seed which, in several steps, was grown into the LDI structure studied in this thesis. Here, and in Section 2.2, we give a brief presentation of the steps in this development. We start by introducing the reference lter of the fth-order BDLF, see Figure 2.1. r1. Vin (s). L1 I 1. L3 L. V1 V2. 2. C2. I3. L5. I5. L. 4. C4. r2. Vout(s). V4. Figure 2.1: Analog LC -lter. Using a variant of the state-space model (1.4){(1.5), this lter can be described mathematically as follows: 0 = AX (s) + BVin(s) Vout (s) = CX (s) (2.5) where X = I1(s) V2(s) I3 (s) V4(s) I5(s) T , B = 1 0 0 0 0 T , C = 0 0 0 0 r2 T and 3 2 ;r ; sL ; sL ;1 ; sL2 0 0 1 1 2 77 66 ; 1 sC2 1 0 0 77 : (2.6) ;sL2 1 sL2 ; sL3 ; sL4 ;1 0 A = 66 5 4 0 0 ;1 sC4 1 0 0 ;sL4 1 sL4 ; sL5 ; r2.

(45) CHAPTER 2. LDI/LDD LATTICE FILTERS. 26. Now, applying the BT, then making row and column operations according to 90], the following matrix representation is obtained: 2 3 q ~ 66 r1 +

(46) 1 ;1 q~ 2 0 0 77 66 1 q 1 0 0 77 66 77

(47) 2 A = 666 q~ 2 ;1

(48) q~ ;1 q~ 2 777 (2.7) 66 0 0 13 q 1 77 66 77

(49) 4 4 0 0 0 0 r2 + q~ 5

(50) 5. where and. q = 1 ; z;1 q~ = zq = z ; 1 1 + r1 = (L1 + L2 ) k2 + 2kC 2 2 = C2 k 2 1 1 k 1 = (L2 + L3 + L4 ) 2 + 2k C + C 2 4 = C4 k2 1 + r2 = L4 k2 + 2kC 2 4 1 = L2 k2 + 2kC 2 k 1 4 = L4 2 + 2kC :. (2.8). 1

(51) 1 1

(52) 2 1

(53) 3 1

(54) 4 1

(55) 5 2. 4. . (2.9). . The vectors X and C are set as in the analog case, while B = z + 1 0 0 0 0 T . Note that 1=q and 1=q~ are delayed and non-delayed integrators, respectively. The problem with the obtained digital lter is that it consists of delay-free loops between the current nodes I1 I2 : : : IN . These can be eliminated in three ways 90]. Here we use the so-called forward elimination (FE), where

(56) 10 =

(57) 1

(58) 30 = 1 ;

(59) 32

(60)

(61) 4 1 3. 2 = 2

(62) 10. 4 = 4

(63) 30 : (2.10).

(64) 2.2. LDI/LDD LATTICE FILTERS. 27. The obtained digital lter is depicted in Figure 2.2. It is a structural lowpass lter. A highpass function can be obtained by using the power-complementary output. The powercomplementary output of the BDLF is obtained from the so-called reected voltage, which is dened as follows: Vr (s) = V1(s) ; Vin2(s) (2.11) where V1 is dened in Figure 2.1. Note that the BDLF has ve multipliers (when r1 = r2 = 1, which is the standard choice) and seven adders in the critical loop (dashed line). V. out. V. 2. r. 4. -1 +. +. +. +. +. +. +. + 3. 1. 5. D. D. -r. 1. D. + D V in. D 2. +. +. D 4. -r 2. +. +. +. + 2. 4. Figure 2.2: Fifth-order BDLF/LDI ladder lter.. 2.2 LDI/LDD Lattice Filters An LDI allpass lter can be obtained from the LDI ladder lter 68], 90]. The TF from the input Vin to the reected voltage Vr is an allpass function, provided that the load resistance is set to zero, as shown in Figure 2.3. Thus, an LDI allpass lter is obtained by setting r2 = 0 in Figure 2.2, since this multiplier can be shown to directly correspond to the load resistance of the prototype LC lter. This can easily be shown as follows: V1(s) = Z (Zs)(s+) R Vin(s) ) Z (s) R V (s) Vr (s) = Z (s) + R ; 1=2 Vin(s) = 12 ZZ ((ss)) ; (2.12) + R in. | {z } H (s). where H (s) is an allpass lter, since Z (j!) is imaginary, being an LC impedance. The.

(65) CHAPTER 2. LDI/LDD LATTICE FILTERS. 28 R V. V. in. Z(s). 1. Figure 2.3: Analog allpass lter where Z (s) is an LC impedance and the output is given by (2.11). upper and lower branches, i in Figure 2.2, can also be removed, since an N th-order allpass lter is fully determined by the N coecients of the pole polynomial, and, therefore, only needs N multipliers. Figure 2.4 shows the resulting lter. The allpass lter has the following state-space matrix (cf. (1.4)):. 2 1 ;

(66) 1 ;

(67) 2 0 0 66

(68) 1(1 ;

(69) 1) 1 ;

(70) 1

(71) 2 ;

(72) 2

(73) 3

(74) 3 ;

(75) 3

(76) 4 6 0 ;

(77) 2 1 ;

(78) 4 A = 66 64 0 ;

(79) 2

(80) 3

(81) 3 1 ;

(82) 3

(83) 4 ;

(84) 4

(85) 5 .... .... .... .... 3 777 77 : 75. (2.13). .... y(n). -1 +. +. +. +. +. 1. 3. D. D. -r =-1 1. D. + D u(n). D 2. +. +. 4. +. +. Figure 2.4: LDII allpass lter. We refer to the lter as LDII. It has two multipliers and ve adders in the critical loop. Two multipliers are still one too many. Therefore, in 39] a modied LDI allpass lter was presented, where the multipliers are moved. The new structure has only one multiplier and ve adders in the critical loop, and we call it LDIII . This structure is depicted in.

(86) 2.2. LDI/LDD LATTICE FILTERS. 29. Figure 2.5, where

(87) 10 =

(88) 1 ,

(89) 20 =

(90) 1

(91) 2 ,

(92) 30 =

(93) 2

(94) 3 , : : : The LDIII allpass lter has the following state-space matrix: 2 1 ;

(95) 0 ;

(96) 0 3 0 0 1 2 66 1 1 1 0 77 6 7 A = 66 ;

(97) 30 ;

(98) 30 1 ;

(99) 30 ;

(100) 40 ;

(101) 40 77 : (2.14) 64 0 0 7 1 1 5 ... ... ... ... . . . y(n). -1 +. +. +. +. + D. -r1=-1. D. D. D. +. +. D + u(n). +. + '. 1. + '. 2. '. 3. '. 4. Figure 2.5: LDIII allpass lter. The structure can be further modied by moving the delay elements, according to Figure 2.6. Although not explicitly shown in this thesis, this structure has better stability properties|see Chapter 3|than LDIII . This structure is referred to as the LDIIII allpass lter. It has one multiplier and only four adders in the critical loop. Note also that the input delay is eliminated. The LDIIII lter has the following state-space matrix: 2 1 ; 1 ;2 0 0 3 66 1 ; 1 1 ; 2 ; 3 1 ;4 77 6 ;3 1 ;4 777 : A = 66 0 (2.15) 64 0 7 ;3 1 1 ; 4 ; 5 5 ... ... ... ... ... The LDIIII structure, with some additional minor modications, is the structure that will be studied in the remainder of this thesis. The LDIIII allpass lter has good properties, which we shall later see, when the poles are placed in the right side of the unit circle. However, for poles in the left side it is.

(102) CHAPTER 2. LDI/LDD LATTICE FILTERS. 30 y(n). -1 +. +. +. +. +. +. D D. D. +. -r1=-1 u(n). D. +. +. + 2. 1. +. 3. 4. Figure 2.6: LDIIII allpass lter. not as advantageous. For this case, the transformation z ! ;z should be used, where the integrators are changed to dierentiators, i.e., a lossless discrete dierentiator lter is obtained. The substitution mirrors the poles and zeros to the left side of the unit circle. A lowpass lter with cut-o frequency 0:1 becomes, after the substitution, a highpass lter with cut-o frequency 0:4. In the state-space model the substitution is equivalent to letting A ! ;A and B ! ;B . In Figure 2.7, the poles of a fth-order LDI lattice lter and the poles of its corresponding LDD lattice lter are depicted. 1. 0.8. 0.6. 0.4. Im(z). 0.2. 0. −0.2. −0.4. −0.6. −0.8. −1 −1. −0.8. −0.6. −0.4. −0.2. 0 Re(z). 0.2. 0.4. 0.6. 0.8. 1. Figure 2.7: Pole positions of a fth-order LDI lattice lter (crosses) and its corresponding LDD lattice lter (stars)..

(103) 2.3. DESIGN FORMULAS. 31. 2.3 Design Formulas Design formulas for the LDII allpass lter were presented in 38]. In this section, design formulas for the general-order LDIIII allpass lter are presented. We start by modifying the state-space system (1.4){(1.5) by applying the z-transform and introducing a \dierentiator variable," = z ; 1, giving. X (z) = A0X (z) + BU (z) Y (z) = CX (z) + DU (z). (2.16). where A0 = A ; I . The characteristic polynomial of A0 is as follows:. p( ) = det(I ; A0 ) = N + c1 N ;1 + + cN ;1 + cN = ( + 1 ; p1)( + 1 ; p2) ( + 1 ; pN ). (2.17). where N , as before, is the lter order and pi i = 1 2 : : : N , are the system's poles in the z-plane. The poles in the -plane are the original poles shifted a unit step to the left: i = pi ; 1 i = 1 2 : : : N . The benet of this modied state-space description is that recursive formulas exist for solving the lter coecients i i = 1 2 : : : N from ci i = 1 2 : : : N :. 1 = c1 ; c2 + ; cN ;1 + cN 2 = c1 ; 1 + 1 (;c3 + 2c4 ; ; (N ; 2)cN ). 0 1 BB CC N X 1 1 ; c4 + 2c5 ; 3c6 + + (N ; 2)cN + G(m 1 1)C c1 ; 1 ; 2 + B B CC B 2@ 1 m=5 | {z1 }A e1 2 3 66 77 0 1 66 77 BBX C 6 N N CC77 X 6 1 1 1 B 1 77 c1 ; 1 ; 2 ; 3 + 66;e1 + B G(m 2 1) + G(m 2 2)C C 36 2B 1 @m=6 66 | m=7 {z2 }A777 64 e2 | {z }75 1. 3 =. 4 =. 5 = c1 ; 1 ; 2 ; 3 ; 4 + 1 f;e22 4. e12.

(104) 32. N. where. CHAPTER 2. LDI/LDD LATTICE FILTERS. 9 > > 2 3> > > 66 77> 0 1 66 77> > > B C 7 > 6 N N B = C X X 6 7 1 1 1 B C 1 7 6 + 6;e2 + B G ( m 3 2) + G ( m 3 3) C CA77> 3 6 2 B 1 m=9 m =8 @ 66 | {z3 } 77> > > 7 64 e3 5 {z2 }> | > > e3 > | {z1 }> > e3. ... 1 1 + 1 ;e2 + = c1 ; 1 ; ; N ;1 + ; e N ;3 N ;3 N ;1 N ;2 X ! #) N 1 1 G(m N ; 2 N ; 3) + (G(N N ; 2 N ; 2)) + 2 1 m=N ;1 (m ; (n + 2))! G(m n l) = cm (1 + l)!(m (;1)m+n : ; (n + 2) ; (l + 1))!. (2.18). As these formulas are not particularly friendly, a Matlab design program is presented in Appendix A.. 2.3.1 Design Example. In this paragraph, a design example of a fth-order LDIIII lattice lter with cut-o frequency 0:12, passband ripple 0:1dB, and stopband ripple 50dB is presented. The poles of the lter are obtained with the help of Matlab, giving. p1 = 0:606364 p23 = 0:609108 j 0:408099 p45 = 0:638074 j 0:660877: The next step is to separate the poles into two allpass lters, H1(z) and H2 (z), as described in Section 1.4. After separation the following poles are picked to H1(z): p1 = 0:606364 p45 = 0:638074 j 0:660877 and p23 = 0:609108 j 0:408099 (2.19).

(105) 2.3. DESIGN FORMULAS. 33. are picked to H2(z). Now, the poles are shifted one step to the left in the z-plane by the transformation = z ; 1. The characteristic polynomials in the new variable of the rst and second allpass lters are:. D1( ) = 3 + 1:117487 2 + 0:852682 + 0:223486 D2( ) = 2 + 0:781784 + 0:319341:. (2.20). The lter coecients are obtained from the above design formulas. For the rst allpass lter (H1(z)) they are:. 1(1) = c1 ; c2 + c3 = 0:488291 3 2(1) = c1 ; 1(1) ; c(1) = 0:171506 1 3(1) = c1 ; 1(1) ; 2(1) = 0:457690:. (2.21). The lter coecients of the second allpass lter (H2(z)) are:. 1(2) = c1 ; c2 = 0:462443 2(2) = c1 ; 1(2) = 0:319341:. (2.22). The SFG of the lter is depicted in Figure 2.9 and the frequency function in Figure 2.8. (a) 0. Magnitude [dB]. −0.02 −0.04 −0.06 −0.08 −0.1 −0.12 −0.14 0. 0.02. 0.04. 0.06 0.08 Normalized frequency. 0.1. 0.12. (b) 0. Magnitude [dB]. −20 −40 −60 −80 −100. 0. 0.05. 0.1. 0.15. 0.2 0.25 0.3 Normalized frequency. 0.35. 0.4. 0.45. 0.5. Figure 2.8: Frequency function of the fth-order lter of the design example. (a) Passband. (b) Over-all..

(106) CHAPTER 2. LDI/LDD LATTICE FILTERS. 34. -1 +. +. + + D D. D. +. -1. -1 + u(n). +. +. 0.488291. -0.171506. -0.457690. y(n). + -1 +. + + D D. +. -1 +. + 0.462443. -0.319341. Figure 2.9: SFG of the resulting fth-order LDIIII lattice lter..

(107) Chapter 3 Suppression of Parasitic Oscillations 3.1 Introduction A digital lter implemented using nite-wordlength arithmetics is, as mentioned in Section 1.3, a nonlinear system. Unlike linear systems, stability analysis of nonlinear systems is hardly straightforward. Also unlike linear systems, nonlinear systems can exhibit sustained oscillations, so-called limit cycles (parasitic oscillations). The study of parasitic oscillations in digital lters started in the late 60s with 19] and 85]. In 19], Ebert showed that for wrapping (two's complement) overow arithmetics, the states of a second-order DF lter may oscillate with constant amplitude, even though the input signal is set to zero. The study also concerned quantization limit cycles. In 85], Sandberg showed that the amplitude of a quantization limit cycle in a digital lter can be decreased by increasing the wordlength of the signal. Forced-response stability was rst considered by Willson in 101]. In the mid-70s, many papers concerning parasitic oscillations were published by Claasen, et al., 14]{18]. In this chapter, we apply the theory presented in the mentioned papers to the LDI/LDDIII allpass lter. Not many papers, so far, have studied stability of LDI/LDD lters. Those known to the author are 35], 41], 40], and 47]. This chapter is the most extensive in this thesis. It is divided as follows:. In Section 3.2, we introduce stability theory for nonlinear systems and see how it can be applied to digital lters. In Paragraphs 3.2.3 and 3.2.6, Lyapunov theory and Tsypkin's criterion are discussed, respectively.. In Section 3.3, the second-order LDI/LDDIII allpass lter is stability analyzed using. Lyapunov theory. Both scaled and unscaled cases are considered. Some simulations are made to verify the results. The results in this section are also presented in 47].. Using Tsypkin's criterion, limit cycles in the second-order LDI/LDDIII allpass lter. with one quantizer are analyzed in Section 3.4. Also in this case, simulations are made to verify the results. The results are also presented in 47]. 35.

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