Design of a predriver for an EDMOS-based Class-D power amplifier

Institutionen för Systemteknik

Department of Electrical Engineering

Examensarbete

Design of a predriver for an EDMOS-based

Class-D power amplifier

Master thesis performed in Electronic Devices

by

Taif Mohsin

LiTH-ISY-EX--13/4714--SE

Linköping 2013

TEKNISKA HÖGSKOLAN

LINKÖPINGS UNIVERSITET

Class-D power amplifier

Master thesis

Performed in Electronic Devices

Department of Electrical Engineering

Linköping Institute of Technology

by

Taif Mohsin

LiTH-ISY-EX--13/4714--SE

Supervisor: Professor Atila Alvandpour

Examiner: Adjunct Professor Ted Johansson

18-09-2013 _______________________

Publishing Date (Electronic version) _______________________

Department of Electrical Engineering

Type of Publication Licentiate thesis X Degree thesis Thesis C-level Thesis D-level Report

Other (specify below)

Language

X English

Other (specify below)

Number of Pages 14 6

ISBN (Licentiate thesis)

ISRN: LiTH-ISY-EX--13/4714--SE

Title of series (Licentiate thesis) Series number/ISSN (Licentiate thesis)

Abstract

This thesis addresses the potential of implementing a predriver for class-D power amplifier for WLAN in 65 nm CMOS technology. In total, eight different predrivers have been created using Cadence Virtuoso CAD tools. All designs have been tested using Agilent's Advance Design System (ADS) and simulated using the ADS-Cadence dynamic link. Furthermore, a comparison between the eight designs and the reference design has been done. The examined parameters were output power (Pout), efficiency, and

effective area consumption.

The simulation results show that most of the proposed designs obtain higher output power, higher efficiency, and lower effective area than the reference design. For the reference design, output power of 34.2 dBm, efficiency of 20.8 %, and effective area of 63952 um2 _{were obtained. For design No.1, the}

effective area was 31511um2_{, which was almost half of the area occupied by the reference design. For}

design No.3, the efficiency was 71.2 %, which was almost 3 and half times higher than the efficiency of the reference design. Furthermore, all designs, except design NO.7, gave more or less the same output power (around 34.4 dBm).

URL, Electronic Version

http://www.ep.liu.se

Publication Title

Design of a predriver for an EDMOS-based Class-D power amplifier

Author

To my lovely Parents!

To my Lovely Wife!

To my Lovely Son!

This thesis addresses the potential of implementing a predriver for class-D power amplifier for WLAN in 65 nm CMOS technology. In total, eight different predrivers have been created using Cadence Virtuoso CAD tools. All designs have been tested using Agilent's Advance Design System (ADS) and simulated using the ADS-Cadence dynamic link. Furthermore, a comparison between the eight designs and the reference design has been done. The examined parameters were output power (Pout), efficiency, and effective area

consumption.

The simulation results show that most of the proposed designs obtain higher output power, higher efficiency, and lower effective area than the reference design. For the reference design, output power of 34.2 dBm, efficiency of 20.8 %, and effective area of 63952 um2 _{were obtained. For design No.1, the effective area was}

31511um2_{, which was almost half of the area occupied by the reference design. For design No.3, the}

efficiency was 71.2 %, which was almost 3 and half times higher than the efficiency of the reference design. Furthermore, all designs, except design NO.7, gave more or less the same output power (around 34.4 dBm).

First and foremost, I would like to express my deepest appreciation to my examiner Adjunct Professor Ted

Johansson for giving me the chance to work in this field, and for his valuable ideas, guidance during the

project work. I would also like to thank my supervisor Professor Atila Alvandpour for his support. He was a great father to all students. At last I am also grateful for all the valuable help namely I have received from Ph.D. Students: Fahad Qazi, Amin Ojani, Ameya Bhide, Ali Fazli, Muhammad Irfan Kazim and Daniel Svärd

God bless you all

Taif Mohsin

Linköping, 2013

Abstract...ix

Acknowledgments...xi

Contents...xiii

List of Figures...xvi

List of Tables...xviii

Chapter 1 Introduction …...1

1.1 Motivation...1

1.2 Aim of Thesis...2

1.3 Thesis Organization...2

1.4 Tools and programs...2

1.5 List of Acronyms...2

Chapter 2 Generalized Proposed CMOS Driver...4

2.1 Introduction...4

2.2 The MOSFET Device...5

2.2.1 Operation Concept of the NMOSFET...6

2.2.2 Static Current-Voltage Characteristics...9

2.2.2.1 Cutoff region...9

2.2.2.2 Linear region...10

2.2.2.3 Saturation region...11

2.2.2.3.1 Channel Length Modulation...11

2.2.3 Sub-threshold Conduction...12

2.2.4 The PMOS Transistor...13

2.2.5 CMOS Device Reliability...15

2.2.5.1 Oxide breakdown...15

2.2.5.2 Hot carrier degradation...16

2.2.5.3 Punchthrough...17

2.3 The CMOS Inverter...18

2.3.1 Operation Principle of CMOS Inverter...18

2.3.2 Transfer Characteristic of CMOS Inverter...19

2.3.3 Noise Margin...21

2.3.4 Transient Characteristics...23

2.3.5 Power Dissipation in CMOS Inverter...24

2.3.5.1 Dynamic Power Dissipation...24

2.3.5.1.1 Switching Power...24

2.3.5.1.2 Short-Circuit Power...26

2.3.5.2 Static Power Dissipation...27

2.3.5.2.1 Leakage Power...27

2.5 References...31

Chapter 3 Level Shifter Implementation...35

3.1 Introduction...35

3.2 Conventional Level Shifter (Type-I)...36

3.3 Conventional Level Shifter (Type-II)...38

3.4 Single Level Shifter...39

3.5 Implemented Level Shifter...40

3.6 References...41

Chapter 4 RF Power Amplifier...43

4.1 Introduction...43

4.2 Power Amplifier Classes...44

4.2.1 Linear Power Amplifier...44

4.2.1.1

Power Amplifier (Class-A)...

...44

4.2.1.2 Power Amplifier (Class-B and AB)...46

4.2.1.3 Power Amplifier (Class-C)...47

4.2.2 Non-Linear Power Amplifier...48

4.2.2.1 Power Amplifier (Class-D)...48

4.2.2.2 Power Amplifier (Class-E)...52

4.2.2.3 Power Amplifier (Class-F)...54

4.3 Power Amplifier Performance Parameters...57

4.3.1 Output Power...57

4.3.2 Gain and Efficiency...59

4.4 References...60

Chapter 5 Predriver Design Implementation...62

5.1 Introduction...62

5.2 Full Outphasing PA and Test Bench...64

5.3 Reference Predriver Design...65

5.4 Proposed Predriver Designs...66

5.4.1 Predriver Design No.1...66

5.4.2 Predriver Design No.2...67

5.4.3 Predriver Design No.3...68

5.4.4 Predriver Design No.4...69

5.4.5 Predriver Design No.5...70

5.4.6 Predriver Design No.6...72

5.4.7 Predriver Design No.7...73

5.4.8 Predriver Design No.8...75

5.5 Comparison of Results...76

5.6 Summary and Conclusion...77

5.7 References...78

Chapter 6 Summary and Future Work...79

6.1 Summary …...79

Appendix E...106

Appendix F...113

Appendix G...117

Appendix H...121

Figure 2.1: The physical structure of NMOSFET...5

Figure 2.2: Simplified symbol for NMOSFET...6

Figure 2.3: Depletion layer formation[4]...7

Figure 2.4: Free electron accumulation[4]...7

Figure 2.5: Formation of inversion layer[4]...8

Figure 2.6: Simplified circuit symbol for NMOSFET...9

Figure 2.7: Output I -V characteristics of a NMOSFET...10

Figure 2.8: Drain current characteristic for gate-source voltage [11]...13

Figure 2.9: Simplified symbol for PMOSFET...13

Figure 2.10: Illustration of punchthrough phenomena in a NMOSFET [26]...17

Figure 2.11: Schematic of a CMOS Inverter...18

Figure 2.12: Switch models of a CMOS inverter [1]...19

Figure 2.13: The CMOS inverter voltage transfer characteristic [1][20]...20

Figure 2.14: Transfer function of a digital inverter[1][20]...21

Figure 2.15: Chain of two inverters to demonstrate the concept of noise margin[20]...22

Figure 2.16: The full definition of

t

R ,

t

F ,

t

PHL and

t

PLH [20]...23

Figure 2.17: Schematic of a basic CMOS inverter, including capacitor charging...24

Figure 2.18: Schematic of a basic CMOS inverter, including capacitor discharging...25

Figure 2.19: Schematic of a basic CMOS inverter, including short circuit current...26

Figure 2.20: Leakage current components in an NMOS transistor[16]...27

Figure 2.21: Conventional LDMOS device [30]...29

Figure 2.22: N-type EDMOS...30

Figure 2.23: P-type EDMOS...30

Figure 3.1: Schematic of the Conventional Level Shifter (Type-I)...36

Figure 3.2: Schematic of the Conventional Level Shifter (Type-II)...38

Figure 3.3: Schematic of the Single Level Shifter...39

Figure 3.4: Schematic of Implemented Level Shifter...40

Figure 4.1: Power Amplifier (Class-A)[2]...45

Figure 4.2: Operation of PA Class-A [2]...45

Figure 4.3: The linear relation between drain current and voltage in Class-A[2]...46

Figure 4.4: The bias and threshold voltage for Class-B[4]...47

Figure 4.5: Drain voltage and current for Class-B[2]...47

Figure 4.10: Simplified block diagram of an outphasing system [19]...51

Figure 4.11: Class-E power amplifier[2]...52

Figure 4.12: Waveforms for Class-E power amplifier[2]...53

Figure 4.13: Drain voltage and current for ideal Class-F power amplifier[10]...54

Figure 4.14: Class-F power amplifier[10]...55

Figure 4.15: Output Power Definition[7]...57

Figure 4.16: Power amplifier (PA) with two driver stages[8]...59

Figure 5.1: Class-D full outphasing PA architecture [1]...63

Figure 5.2 : Test Bench for all PAs...64

Figure 5.3 : The schematic of the reference design...65

Figure 5.4 : The schematic of the design no.1...66

Figure 5.5 : The schematic of the design no.2...67

Figure 5.6 : The schematic of the design no.3...68

Figure 5.7 : The schematic of the design no.4...69

Figure 5.8 : The schematic of the design no.5...71

Figure. 5.9: The schematic of the design no.6...72

Figure 5.10:The schematic of the design no.7...74

Table 5.1: The simulation results of the full PA (reference design)...65

Table 5.2: The simulation results of the full PA (design no.1)...67

Table 5.3: The simulation results of the full PA (design no.2)...68

Table 5.4: The simulation results of the full PA (design no.3)...69

Table 5.5: The simulation results of the full PA (design no.4)...70

Table 5.6: The simulation results of the full PA (design no.5)...71

Table 5.7: The simulation results of the full PA (design no.6)...73

Table 5.8: The simulation results of the full PA (design no.7)...74

Table 5.9: The simulation results of the full PA (design no.8)...75

Table 5.10 Comparison of Results...76

Table A.1: Transistors size of Driver-1...81

Table A.2: Transistors size of Driver-2...82

Table A.3: The size of Inverter-Bias-Circuit(1.2 - 2.5) V supply...83

Table A.4: Transistors size of Driver-3...84

Table A.5: Transistors size of Driver-4...85

Table A.6: The size of Inverter-Bias-Circuit(2.5 - 5) V supply...86

Table B.1: Transistors size of Level-Shifter-1 (1.2 - 2.5) V supply...88

Table B.2: Transistors size of Driver-1...90

Table B.3: Transistors size of Driver-2...91

Table B.4: Transistors size of Level-Shifter-2 (2.5 - 5) V supply...92

Table B.5: Transistors size of Last Stage (PA)...95

Table C.1: Transistors size of Level-Shifter-1 (1.2 - 2.5) V supply...96

Table C.2: Transistors size of Driver-1...97

Table C.3: Transistors size of Driver-2...98

Table C.4: Transistors size of Last Stage...99

Table D.1: Transistors size of Level-Shifter-1 (1.2 - 2.5) V supply...101

Table D.2: Transistors size of Driver-1...102

Table D.3: Transistors size of Driver-2...103

Table D.4: Transistors size of Inverter_Bias_Circuit (2.5 - 5) V supply...104

Table E.1: The size of Inverter_Bias_Circuit...106

Table E.2: Transistors size of Driver-1...107

Table E.3: Transistors size of Driver-2...108

Table F.3: Transistors size of Driver-2...114

Table F.4: Transistors size of Inverter_Bias_Circuit (2.5 - 5) V supply...115

Table G.1: Transistors size of Driver-1...117

Table G.2: Transistors size of Driver-2...118

Table G.3: Transistors size of Inverter_Bias_Circuit (1.2 - 5)V supply...117

Table H.1:The size of Inverter_Bias_Circuit (1.2 - 2.5) supply...120

Table H.2: Transistors size of Driver_1_1...120

Table H.3: Transistors size of Driver-2...121

Table H.4: Transistors size of Inverter_Bias_Circuit...121

Table I.1: Transistors size of Inverter_Bias_Circuit(1.2 - 5) V supply...123

Table I.2: Transistors size of Driver-1...125

Table I.3: Transistors size of Driver-2...126

Chapter 1

Introduction

1.1 Motivation

With real and growing demand for portable devices such as cellular phones, multimedia devices, personal note books, and so on, there is an immense will for decreasing the size of the electronic devices. So, the inventions of the MOS devices and CMOS circuits lead the scientists to a real revolution in electronic devices, because the CMOS technology has many benefits for integration circuit (IC) in terms of higher device speed and cost reduction. Simultaneously, many issues that will rise according to the using of CMOS technology. The most important one is the power dissipation that has become the most important design concern for the VLSI circuits and system in low power devices. With increasing the power consumption, the reliability problem also rises and the cost of packaging goes high.

At the same time there are many questions to be asked including the possibility of integrating the power amplifier (PA) with other parts of the RF transmitter (baseband), and how much power that can be achieved from the PA. To reach high output power, the extended drain MOS transistor (EDMOS) has been used in recent research projects to cope with the low breakdown voltage problem. There is however a problem with level/swing of input signal that must be high enough to drive the EDMOS transistors.

The high efficiency of the switch-mode amplifiers (class-D PA) comes from the sharp waveforms of the input signal, with a little or (ideally) no overlap between the switch voltage and current. If the predriver is not working correctly, for instance because of too high loads or insufficient driving levels, both the efficiency and the output power will be affected.

1.2 Aim of Thesis

The aim of this thesis is to design a predriver for an EDMOS Class-D PA to increase the swing of low input signal from 1.2 to 5 V supply at 2 GHz. The main problem is to drive a large EDMOS transistor (high fanout), therefore the output signal of the predriver chain should have sharp edges so the efficiency of the EDMOS PA will not be affected.

1.3 Thesis Organization

The organization of this thesis is as follow. In chapter two, the principles of the CMOS driver will be discussed through explaining the characteristics of the MOSFET (N-Type and P-Type) and the functionality of each of them. Moreover, the characteristic and operation principle of CMOS inverter which is considered the main block in predriver design will be introduced. In chapter three, several types of level shifter designs will be discussed. Chapter four will cover the classes of the PA which can be divided into linear and non-linear PAs. Furthermore, different PA performance parameters (output power, efficiency, and effective area) which can be used to measure the quality of the PA will be also discussed. In chapter five, the designed architectures in this project will be discussed, and the result of the previous work (reference work) will be presented. In chapter six, the summary, conclusion, and future work will be introduced.

1.4 Tools and programs

The technical part of this thesis includes a simulation study of predriver performance of different structures in 65 nm CMOS using foundry PDKs. Most of the predriver schematics have been created by using the Cadence Tools (CAD). The test bench has been created by using the Advance Design System (ADS).

1.5 List of Acronyms

CMOS Complementary Metal-Oxide-Semiconductor CF Crest Factor

DC Direct Current DE Drain Efficiency

EDMOS Extend Drain metal Oxide Semiconductor Transistor FET Field-Effect Transistor

IC Integrated Circuit

IEEE The Institute of Electrical and Electronics Engineers MOS Metal-Oxide-Semiconductor

MOSFET Metal-Oxide-Semiconductor Field Effect Transistor PAE Power-Added Efficiency

PA Power Amplifier RF Radio Frequency

VLSI Very Large Scale Integration WLAN Wireless Local Area Network

Chapter 2

Generalized Proposed CMOS Driver

2.1 Introduction

The inventions of the MOS devices and CMOS circuits lead the scientist to a real revolution in electronic devices. The CMOS has become one of the most important factors in electronic devices industry. Moreover, the use of CMOS technology has many benefits for integration circuit (IC) in terms of higher device speed and cost reduction [1]. In this thesis, CMOS technology is used to design a typical standard CMOS driver which includes many tapered inverters. Each inverter has the ability to drive another larger inverter (a factor of 3 is usually used as a tapering factor) until an inverter is large enough to drive the last stage (biggest inverter) with a reasonable raise time [2].

2.2 The MOSFET device

MOSFET is an acronym for Metal Oxide Semiconductor Field Effect Transistor which can be used for amplifying or switching electronic signals. Depending on the type of carrier in the channel, the device may be an n-channel (for electrons) or a p-channel (for holes) MOSFET. For instance, t he physical structure of NMOSFET can be seen in Fig. 2.1 and the symbol in Fig. 2.2. As is clear from Fig. 2.2, NMOSFET has four terminals: gate, drain, source and bulk or body. NMOSFET includes two strongly doped (n+) areas which form the Source (S) and Drain (D). The substrate is used as base for the device and is formed of P-doping. It is called bulk. It is important to connect the bulk to the ground to keep the junction between the substrate and the source/drain revered biased. Therefore, there is no current flow between the substrate and the source/drain terminals. The area between the gate and P-substrate can be used for isolation and is formed of silicon dioxide (SiO2), where the physical thickness of this layer is approximately 1.0-5.0 nm in sub-micron

CMOS technologies [3]. The layer formed between the drain and source and under the gate is called the channel. This channel can be only formed under certain biasing conditions at the four terminals [3],[4]. The complementary characteristics of NMOSFET can be seen in PMOSFET.

Fig. 2.2 Simplified symbol for NMOSFET.

2.2.1 Operation Concept of the NMOSFET

Initially, there is no path for current flowing between the source and drain ends, since both p-n junctions between the source-bulk and the drain-bulk are reversed bias. In addition, there is no current flow from the gate due to a perfect insulation of silicon dioxide (SiO2). The channel between the drain and source terminals

can be formed when there is positive voltage applied on the gate terminal with respect to the source, thus the silicon surface under the gate oxide will be change into n-type layer. This layer will permit the carriers to move or flow between the drain and source. Moreover, there is a high quality capacitor which has been formed due to the perfect insulation (SiO2) between the metal of the gate and the p-substrate, so any small

voltage applied on the gate terminal results in a depletion region that can be created in the silicon. That can be seen in Fig. 2.3. The depletion region can be defined as some of electrons and holes diffuse or move to regions with fewer concentrations of electrons and holes. For example, P-type semiconductor has minority of electrons, as for N-type it has minority of holes. When both types are combined together to form a junction, some electrons migrate into P-side and vice versa. When the electrons fill the holes, negative ions will result, and positive ions will be left behind on the n-side. That operation builds up the depletion region. One way to inhibit or prevent any further electrons transfer is by putting a forward bias on the junction [4]-[6].

Fig. 2.3 Depletion layer formation [4].

Actually, when the positive voltage has been applied on the gate terminal, the majority carriers (holes) will be rejected from the interface area between the gate oxide and the p-substrate. Therefore, the negatively charged acceptors and the depletion region are exhibited. With increasing the gate voltage (VGS), the

depletion region will be thicker and the electric field at the oxide-silicon interface gets larger and begins to attract free electrons [4]. This is shown in Fig. 2.4.

Fig. 2.4 Free electron accumulation [4].

If the VGS is increased more, the free electrons at the interface region will become equal to the free hols in the

p-substrate region under the depletion region. The inversion layer is the free electrons layer at oxide-silicon interface. This is seen in Fig. 2.5. The characteristics of the inversion layer are the same as an n-type

VGS which is called Gate - Source threshold voltage (VT). If the VGS value is increased more than VT, that

layer will be thicker and more conductive due to increasing of free electrons [4]-[7].

Fig. 2.5 Formation of inversion layer [4].

One of the most important parameters of MOSFET modeling and characterization is the threshold voltage (VT) which is considered as the most significant factor that can be used to control the current between source

and drain terminals, where the equation for the threshold voltage is seen in(2.1) [8].

V

_T

=

V

_To

 

_

2

_F



V

_SB

−

_

2

_F



2.1

The γ is defined as the body-bias coefficient, which depends on physical parameters of the device and ФF is

2.2.2 Static Current-Voltage Characteristics

As previously mentioned the MOSFET has four terminals. The voltage on the gate can be used to control the amount of current between the source and drain. In fact, the source is grounded in the NMOSFET. The simple symbol of a NMOSFET can be shown in Fig. 2.6. The characteristics of a NMOSFET can be understood by plotting the drain current (ID )as a function of the drain–source voltage VDS. This is shown in

Fig. 2.7.

Fig. 2.6 Simplified circuit symbol for NMOSFET.

According to the value of VGS the output characteristics of the NMOSFET can be divided into three regions.

These regions are explained in the three sections below.

2.2.2.1 Cutoff region

In case the VGS is less than VT, there are no mobile carriers in the channel. Without these mobile carriers, no

2.2.2.2 Linear region

The linear region is also called triode or ohmic region. If the VGS is more than VT , the channel stretches from

the source to the drain. The voltage condition where this is true is when VDS is less than VDSat, where VDSat is

equal to VGS – VT ( Note: if VDS is less than VDSat, the channel stretches from the source to the drain, while

when VDS is more than VDSat, the channel stops short of the drain). The primary case of current flowing is by

drift. Once there is a conductive channel, applying VDS will set up an electric field that points from drain to

source. This electric field causes electrons to flow from source to drain. Thus, the current is flowing from drain to source. If the channel goes all the way to the drain, the voltage between the drain and source must be dropped across the channel (short circuit behavior). That means the electric field will depend on VDS, so will

the current. The VGS will affect the current since it controls how much charge is in the channel. Finally, the

equation for the current in this region can be seen in (2.2) [7],[9].

Fig. 2.7 Output I -V characteristics of a NMOSFET.

_I

_D

₌

_μ

_n

_C

_ox

W

L

[

V

GS

−

V

T



V

DS

−

V

2_DS

2

]

2.2

where μn is the charge-carrier effective mobility, W is the gate width, L is the gate length and COX is the gate

2.2.2.3 Saturation region

If the VDS is more than VDSat, there is no channel between the source and drain. In fact, the channel will end

up before the drain edge. However, when VDS is equal to VDSat, the channel ends exactly at the drain edge

which is called pinch-off (since the channel is pinched off from the drain). Here, VDSat does not depend on

VDS, which means the electric field across the channel (and therefore ID) no longer depends on VDS in

saturation. Finally, the equation for the current in this region is seen in(2.3) [7],[9].

I

_D

=

1

2

μ

n

C

ox

W

L



V

GS

−

V

T



2

_2.3

2.2.2.3.1 Channel Length Modulation

As earlier mentioned, the voltage drop across the channel does not depend on VDS in saturation region, by

assumes that the channel length does not change. But, this assumption is not completely correct. Because any increase in the drain voltage results in increase in the reverse bias on the PN junction between the drain and p-substrate. This will increase the depletion region which causes gradually increased pinch-off the channel. Thus, the drain current have some dependence on VDS in saturation region due to channel length modulation.

To fix this situation, there is a correctional term which can be added to the above equation. Thus, the new drain current equation is seen in(2.4) [7],[9].

I

_D

=

μ

_n

C

_ox

W

L



V

GS

−

V

T



2

_{1 V}

DS



 2.4

2.2.3 Sub-threshold Conduction

As it is clear from the previous section the VGS is used to adjust the potential carriers between the source and

drain. In Fig. 2.8, the current will not instantly go to zero when the VGS goes around or below the VT. Instead

of that, the current will take an exponential shape in sub-threshold region. At sub-threshold region, the current depends on how many electrons are injected over the source-side potential barrier and it is called sub-threshold conduction current. This current depends on the value of VT, if VT is large then the OFF-state

current will be small which results in small static power consumption. It also means a smaller VDSat (since

VDSat = VGS – VT, that means a less amount of ON-state current. Unlikely, choosing a smaller value of VT

results in more OFF-state leakage current and more ON-state current as well. The sub-threshold conduction current can be modeled as equation given in (2.5) [10]-[12].

I

_{D ,subth}

=

μ

_n

C

_ox

W

L

V

T

2

_e

1.8

_e

1/m vTVGS−Vth0−VSVD

1−e

−VDS/Vt

_

 2.5

where Vtho is the zero bias threshold voltage, VT is the thermal voltage, γ is the body effect coefficient, and m

(a) linear scale, (b) semi-log scale

Fig. 2.8 Drain current characteristic for gate-source voltage [11].

2.2.4 The PMOS Transistor

The simplified symbol of PMOSFET is shown in Fig. 2.9. The drain current is flowing from the source to drain. In PMOS transistor, the majority charge carriers are holes. However, the PMOSFET behaviors are very similar to NMOSFET(with few sign changes).

The drain current depends on the region that the transistor works within. That can be seen in equations below.

I

_D

=

0 Cut off region 2.6

_I

_D

₌

_μ

_p

_C

_ox

W

L

[∣

V

GS

∣−∣

V

TH

∣∣

V

DS

∣−

∣

V

_DS

∣

2

2

]

 Linear region (2.7)

I

_D

=

1

2

μ

p

C

ox

W

L

∣

V

GS

∣−∣

V

TH

∣

2

_{ Saturation 2.8}

2.2.5 CMOS Device Reliability

In the last four decades, many scientists have been scaling devices to be compatible with a real and growing demand for portable devices such as cellular phones, multimedia device, personal note book and the like. There is an immense will of decreasing the size of devices which has mentioned above. So there are two major factors which are driven this trend, the first one is to get better performance, the second one is to win in the fierce global competition. These days, the scaling of CMOS technology is very important to meet the specific requirements such as, power consumption, speed, complexity, and finally cost which are required for many modern applications. Of course, there are some side effects or drawbacks due to ultra-scaling of CMOS devices that the designers have to deal with to get more reliable integrated circuits in nanometer CMOS processes.

2.2.5.1 Oxide breakdown

The oxide layers is used as dielectric layers between the metal of the gate and semiconductor (silicon) in MOSFET and can be used to isolate conductors from each other and so on. However, due to the immense will for decreasing the size of the MOSFET devices, many issues are raised. One of these issues is the oxide breakdown which has always been a serious reliability issues in the semiconductor industry because of the continuous trend towards small devices. Oxide breakdown can be defined as the destruction of an oxide layer in a semiconductor device due to the scaling in oxide thickness. The thinnest oxide layers today are already less than 50 angstroms (Å) thick. An oxide layer can breakdown instantaneously at an electrical field of 8-11 MV per cm of thickness, or 0.08 - 0.11 V per Å of thickness. The main reason for the oxide breakdown is the high electrical field in the oxide which results in increasing the tunneling of carriers from the channel into the oxide. These carriers will change the conduction properties over time for the oxide. This phenomena is called time dependent destructive breakdown (TDDB).

There are other two phenomenons which can be related to oxide breakdown. These phenomenons are called EOS/ESD-Induced dielectric breakdown and early-life dielectric breakdown. They can exist if a high voltage is applied across the oxide, and if the oxide has weak spots due to poor processing. Therefore, that high voltage will lead to dielectric breakdown and allow current to flow [20]. This current causes localized heating, so with time a vicious cycle of increasing current flow and localized heating ensue, eventually causing a meltdown of the silicon [20],[21].

2.2.5.2 Hot carrier degradation

Generally, the hot carriers are particles which have a high dynamic energy. The main reason of dynamic energy is that these hot carriers are exposed to a high electric field. Thus, these accelerated carriers can be injected into forbidden areas of the device such as the gate oxide. Consequently, the threshold voltage and transconductance of the gate oxide will be shifted. There are four distinguished injection mechanisms of the hot carriers injection. The first one is called channel hot-electron injection (CHE) which can be caused if the voltage of the gate terminal is equal to the voltage of the drain terminal, where some of carriers (electrons) are attracted to SiO2 barrier (at the drain side of the channel) by the high gate voltage. The second

mechanism is called drain avalanche hot-carrier injection (DAHC) which can be caused when the drain voltage is higher than the gate voltage. Here, the carriers (holes or electrons) have a high energy because of a high electric field at the drain area. Electrons and holes are injected at the same time, so it is very difficult to measure DAHC. Moreover, some of these carriers lead to a bulk current. The third mechanism is called secondary generated hot-electron injection (SGHE) which can be existed as a result of a photo induced generation process. Photons are usually created in the high electric field region around the drain area and induce a generation process for electron-hole pairs. There is a second factor which can play a main role in SGHE. This is the avalanche multiplication around the drain area which leads to the injection of both types of carriers (electrons and holes) into the dielectric. The substrate bias voltage can support the injection process which can be considered as an additional driving of the carriers to jump into the Si-SiO2 interface.

The fourth mechanism is called substrate hot-electron injection (SHE). The basic reason for this mechanism is the negative or positive bias of the substrate which leads to driving the carriers to jump into Si-SiO2

interface. The carriers in substrate can be generated as a normal consequence for optical generation or by electrical injection from a buried p-n junction. Finally, these carriers (holes or electrons) overcome the barrier at the interface and are injected into the gate oxide. There are many solutions to avoid or minimize the effect of hot carrier degradation such as double diffusion for the source and drain areas, larger channel length, etc [22],[23].

2.2.5.3 Punchthrough

If the VGS is less than the threshold voltage and there is no VDS or equal to zero, there is no current between

the drain and the source. This is because the energy barrier which exists between the source and the area below the gate oxide which prevents the carriers (electrons) from passing through anywhere. However, there is some current considered as a leakage current from the drain to substrate due to reverse-biased diode between drain-substrate junction. The space-charge depletion width at the source and drain ends are symmetrical (dashed line a in Fig. 2.10). Now, if the VGS is more than the threshold voltage, the barriers will

be less and that allows for electrons to move form the source to the drain through the conduction channel. At that time, if VDS is increased and VGS is kept constant, the depletion region around the drain will be increased

towards the source (dashed line b in Fig. 2.10). When the VDS is increased more and more, the drain depletion

area will be expanded more and more until it touches the depletion region of the source (dashed line c in Fig. 2.10). Therefore, there is a large leakage current which flows between the drain and source terminal even though there is no voltage on the gate terminal. This phenomena is called punchthrough and the leakage current due to this phenomena is called punchthrough current. The punchthrough voltage Vptcan be defined

as the voltage that causes a small amount of drain current at gate voltage is equal to zero. This voltage is approximately calculated in the relation below [24],[25].

V

_pt

≈

q N

b

2

₀



_si



L− X

dd



2

−

_bi

2.9

Fig. 2.10 Illustration of punchthrough phenomena in a MOSFET. The drain voltage increase

from (a) to (c). At (c) drain depletion width touches source depletion width resulting in the

2.3 The CMOS Inverter

At present time, the complementary MOSFET (CMOS) technology are used as the nucleus of the most digital designs in numerous and varied electronic applications. As it has been previously mentioned, CMOS technology offers several key advantages such as low power dissipation, high speed and high noise margin when both low and high states are large. Especially, the CMOS inverter has excellent logic buffer characteristics or properties. The next sections will cover some details about the basic understanding of the how a CMOS inverter works and the power dissipation for it.

2.3.1 Operation Principle of CMOS Inverter

The schematic of an ordinary CMOS inverter is seen in Fig. 2.11. Generally, a CMOS inverter includes two MOS transistors: the upper one is PMOS transistor (T1), and the lower one is a NMOS transistors (T2). The PMOS transistor (T1) is connected to supply voltage (VDD) at the source terminal and connected to input

signal at the gate terminal. The NMOS transistor (T2) is connected to the ground at the source terminal and connected to input signal (Vin) at the gate terminal. The input signal of the CMOS inverter varies between zero and VDD, thus the state of the NMOS and PMOS varies accordingly.

Fig. 2.11 Schematic of a CMOS Inverter.

Generally, the MOS transistor can only be considered as a switch with an infinite off-resistance when VGS is

less than VT and with a finite on-resistance when VGS is more than VT. That can lead to a completely

Fig. 2.12 Switch models of a CMOS inverter [1].

when the input signal is equal to VDD, the NMOS transistor is turned ON, while the PMOS transistor is

turned OFF, so the inverter will be equivalent to the schematic in Fig. 2.12(a). Here, it is easy to notice the direct path between Vout and the ground node which results in a steady-state value of 0 V. On the other hand,

when the signal input is equal to 0 V, the NMOS transistor is turned OFF, while the PMOS transistor is turned ON. Thus, the inverter is be equivalent to the schematic in Fig. 2.12(b). There is a direct path from the supply voltage to Vout which results in a high output signal [19].

2.3.2 Transfer Characteristic Of CMOS Inverters

The CMOS inverter and the MOS transistors (n- and p-channel transistors) characteristics are shown in Fig. 2.13. At point 1, the input signal is 0 V, so the output is VDD. At point 2, the input signal is increased, the

n-channel transistor enters in the saturation region (constant current region) and the p-n-channel transistor in the linear region. At point 3, the input signal is more and more increased, so both transistors are in the saturation region. At point 4, the input signal is increased more than point 3, the n-channel transistor moves to the linear region, while the p-channel transistor is still in the saturation region. At point 5, the input is increased to VDD

+ Vtp, so the p-channel transistor is in the cut off region and n-channel transistor is still in linear region [1],

Fig. 2.13 CMOS voltage transfer characteristic shown with (a) CMOS inverter transfer

characteristic, (b) NMOS transistor characteristics, (c) PMOS transistor characteristics .

Points 1 through 5 correspond to increasing Vin from 0 to VDD. Note: Dash characteristics on

2.3.3 Noise Margin

Typically, the transfer function of a digital inverter looks something like that in Fig.2.14.

Fig. 2.14 Transfer function of a digital inverter [1],[20].

Essentially, there are three regions in Fig. 2.14.

1.The region where VTH is low, so the output voltage Vout is high or VDD.

2.The region where Vin is high, so that the output voltage Vout is low.

3.The transition region, where the input/output voltages are in an indeterminate state.

Here, the transition area can be defined as the points on the transfer function where the slope value is more than one



d

_vo

/

d

_vi

1

[1],[20]. To understand how to calculate the noise margin, we have to use two inverters where one of them drives the second one. Both inputs and outputs of the two inverters are indicated in Fig. 2.15. Obviously, the high output of first inverter VOH1is more than the high input of the second

inverter VIH2, and the low output of first inverter VOL1 is less than the low input of send inverter VIL2. There

are two terms to define, the first one is a noise margin high NMH which can be used to guarantee that a logic

(1) output from the first inverter is understood as a logic (1) input to the second one.

The second term is a noise margin low NML which can be used to guarantee that a logic (0) output from the

first inverter is understood as a logic (0) input to the second one. The equations for two types of noise margin can be seen below.

Fig. 2.15 Chain of two inverters to demonstrate the concept of noise margin [19].



NM

_H

 =

V

_OH

−

V

_IH

2.10



NM

_L

 =

V

_IL

−

V

_OL

 2.11

Finally, there are some of parameters which can be used to point out the transfer characteristics of the inverter such as:- VOH is the minimum output voltage of an inverter to point to a logic 1;- VOL is the

maximum output voltage from an inverter to point to a logic 0, VIH is the minimum input voltage to an

inverter to output a logic 0, VIL is the maximum input voltage to an inverter to output a logic 1, and VM is the

2.3.4 Transient Characteristics

It is very important to determine how much time is required to change the status of the output when the input changes its status. The required time is called the propagation delay. The explanation of the time propagation of a CMOS inverter is seen in Fig. 2.16. The rise time tR can be described as the required time for the input

or output signal to change from 10 % of its high magnitude to 90 % of its high magnitude, while the fall time tF can be described as the required time for the input or output signal to change from 90 % of its high

magnitude to 10 % of its high magnitude. There are two transitions, the first is from high to low tPHL, and the

second is from low to high tPLH. These two can be determined by measuring the delay time between 50 %

point of the input and output signals, Therefore the total propagation delay is determined by using the equation below [1],[17],[18].

t

_p

=

t

PHL



t

PLH

2

2.12

2.3.5 Power Dissipation in CMOS Inverter

Initially, The most important factor that the designers have to be careful with is the power consumption. The power consumption in CMOS inverter can be divided into two types. The first one is the dynamic power consumption which can be divided into two sources, switching power and short-circuit power consumption. The second one is the static power dissipation which arises from leakage currents in various forms.

2.3.5.1 Dynamic Power Dissipation

The average of the dynamic power can be summarized in the following equation.

P

_average

=

P

_switching



P

_{short−circuit}

2.13

2.3.5.1.1 Switching Power

This kind of the dynamic power dissipation is due to the charging and discharging of the capacitor of the load. The charging of the load capacitor can be realized by assuming the input voltage is equal to zero, so the PMOS transistor is turned ON and will start to charge the capacitor CL. At the same time, the NMOS

transistor is turned OFF. However, the required energy to charge CL with C·VDD is C·V2DD. The operation of

capacitor charging is seen in Fig. 2.17.

Once the input voltage is high (VDD), the PMOS is turned OFF and the NMOS turns ON. In this case, the

NMOS transistors can be represented as a wire (short circuit), so the capacitor CL is connected to the ground.

Therefore, no additional power dissipation in this case. The operation of capacitor discharging is shown in Fig. 2.18.

Fig. 2.18 Schematic of a basic CMOS inverter, including capacitor discharging.

Switching power can be described by using the equation in (2.14), the ƒclkis the clock frequency with which

the gate switches. The α is the switching activity ratio, which determines how frequently the output switches from low-to-high per clock cycle [1],[11].

2.3.5.1.2 Short-Circuit Power

This kind of dynamic power dissipation is due to the direct path between the VDD and the ground. This

dissipation arises when both NMOS and PMOS transistor are turned ON simultaneously which results in direct current from the supply to the ground. Significant short-circuit power dissipation can be avoided if the output rise/fall time of a gate is much longer than the input rise/fall time. The short-circuit power dissipation can be summarized in equation (2.15), where β is the gain factor of the transistors, τ is the input rise/fall time, VT is the threshold voltage of the transistors and T is the time duration of input signal [13],[14]. The

short-circuit power can be kept below 10 % of the switching component in a well sized static CMOS gate [15]. The short circuit current from the voltage supply (VDD) to the ground can be seen in Fig. 2.19.

Fig. 2.19 Schematic of a basic CMOS inverter, including short circuit current.

P

Short−Circuit 

=



12



V

DD

−2 V

T



3

_{. }

2.3.5.2 Static Power Dissipation

Due to the MOS transistors becoming more and more smaller and faster, the static power dissipation plays the major role in the CMOS transistors design. Technology scaling increases both the absolute and relative contributions of static power dissipation. There are many scientific reports point to 40 % or even higher percentage of the total power consumption is due to the static power dissipation. This percentage will increase with technology scaling unless efficient techniques are introduced to bring that dissipation under control [15],[16].

2.3.5.2.1 Leakage Power

In a CMOS transistor, the leakage power dissipation can be divided into four main sources, seen clearly in Fig. 2.20.

Fig. 2.20 Leakage current components in an NMOS transistor [15].

2.3.5.2.1.1 Reverse-biased junction leakage current (IREV)

This kind of leakage can happen when a transistor is turned OFF. The junction leakage can take place between source or drain and the well or substrate. There are two components for this leakage current. The first one is the minority carriers diffusion beside or near the edge of the depletion region. The second one occurs due to the pair of hole-electron generations in the depletion region of source/drain - substrate junction. For example, if the input signal is low, the PMOS transistor is turned ON and the NMOS transistor is turned OFF, thus the output will be high or VDD. Subsequently, the voltage between the drain and substrate of the

This difference in voltages will result in a leakage current through the reverse-biased diode. The value of that current can be determined by how large the area of the drain or source is, and by doping concentration. This current is considered significant in the applications that spend a long time as idle, since this power is always being dissipated even there is no switching [15].

2.3.5.2.1.2 Gate induced drain leakage (IGIDL)

This kind of leakage occurs when there is a high electric field under the gate/drain overlap region causing deep depletion. GIDL occurs at low VGS and high VDD that generates carriers into the substrate and drain

from surface traps or band-to-band tunneling [15].

2.3.5.2.1.3 Gate direct-tunneling leakage (IG)

This kind of leakage occurs when the gate voltage or the electric field at the gate is high, so the current passes through the silicon dioxide (SiO2). This phenomenon is common in the scaled down devices with

reduced thickness of the gate silicon dioxide (SiO2) [15].

2.3.5.2.1.4 Sub-Threshold (weak inversion) leakage (ISUB)

The sub threshold leakage can be defined as the leakage due to the current between the drain and source of a MOSFET transistor when is operating in the weak inversion region, while in the strong inversion region the drift current is dominated [16]. For example, if the input signal of a CMOS inverter is low, the NMOS transistor is OFF and the PMOS transistor is ON.

Although, the NMOS is OFF, there is a current passes through due to the high potential (VDD) between the

drain and source. The value of this current depends on temperature, supply voltage, device size, and so on. The sub threshold current is larger than other types of leakage currents in present CMOS technologies. The dominant reason is the low VT in modern CMOS devices. ISUB can be calculated by using the following

equation.

I

_SUB

=

W

L

μV

th 2

_C

sth

e

Vgs−VTVDS n Vth

1−e

−VDS Vth



2.16

where μ is the carrier mobility. Vth = KT/q is the thermal voltage at temperature (T).Csth = Cdep + Cit equals

2.4 EDMOS Device

The scaling down of MOSFET has many advantages. Simultaneously, there are numerous challenges in terms of semiconductor designing and manufacturing. One of these challenges is the electrical field, where the normal result of scaling down is that the electrical field dramatically increases. Moreover, the high electrical field has many degrading effects, some of them are called hot carrier injection and breakdown voltage. The basic explanation of the hot carrier injection and breakdown voltage phenomena have been previously introduced. These phenomena can reduce the reliability of the MOS transistor for long term of operation, changing or shifting the characteristics of the MOS device degrades the performance of the circuit. Thus, the operating voltage has to be decreased to keep the electrical fields constant. The decreasing of operating voltage has direct effect on the threshold voltage, noise margins, output power and delay requirements [26].

There are many solutions to fix the problems of the high electrical field and breakdown voltage. One of solutions is the LDMOS transistor. LDMOS is the acronym for Lateral double-diffuse Metal Oxide Semiconductor. The simple structure of LDMOS can be clearly seen in Fig. 2.21.The advantages of LDMOS for RF PA applications are its thermal stability, high ruggedness, and good linearity characteristics. LDMOS devices can be added to a conventional CMOS process with only a few extra masks and process steps [27].

LDMOS active devices can also be created by using layout and design environment changes without added extra masks or other extra process. This is attractive to CMOS foundries, thus not risking any change of the device parameters of existing CMOS devices. However, optimal performance (breakdown voltage, on-resistance, and parasitics) will not be achieved in this way [26]. The second solution is EDMOS transistor. EDMOS is an acronym for Extend Drain Metal Oxide Semiconductor. The EDMOS is a simpler form of the LDMOS. The drain expanding can be created by adding a lightly doped n-type drain drift region among the drain and the channel of the device. The structure of EDMOS is clearly seen in Fig. 2.22 and Fig. 2.23. The idea of adding the lightly doped n-type region is to enclose the electrical field within this region, so the hot carrier effect can be enclosed within this region, instead of the channel. So as to increases the reliability of the device. Additionally, the EDMOS provides a kind of trade-off between the breakdown voltage (VDS) and

on-resistance of the device [27]. Finally, the actual EDMOS transistors which are used in the simulation part of this thesis are reported in [27].

2.5 References

[1]

J.M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits, Upper Saddle

River, New Jersey, USA: Prentice-Hall, Second Edition, 2003.

[2]

B. Deutschmann, and T. Ostermann,

“

CMOS Output Drivers With Reduced Ground

Bounce and Electromagnetic Emission,” IEEE Proceedings of the 29

th

_{European Solid-State}

Circuits Conference, Estoril, Portugal, pp. 537-540, September 2003.

[3]

J. Fritzin, ”Power Amplifier Circuits in CMOS Technologies,” Ph.D. Dissertation, Dept.

Elect. Eng., Linköping Univ., Linköping, Sweden, 2011.

[4]

E.E IIT Kharagpur (2009, September 3). Metal Oxide Semiconductor Field Effect

Transistor (MOSFET)Lesson-6. SlachDocs[Online]. Avaliable:

http://www.slashdocs.com

/kxtsxp/lesson-6-metal-oxide-semiconductor-field-effect-transistor-mosfet.html.

[5] B. Razavi, Design of Analog CMOS Integrated Circuits, New York: McGraw-Hill, 2001.

[6]

A. Shik, H. E. Ruda, D. Pelinovsky, and W. Craig, “Depletion layer and contact capacitance

in non-uniformly doped semiconductors,” Journal of Physics D: Applied Physic, Canada

vol. 35, no. 22, pp. 2988-2933, November 2002.

[7]

M. Acar, ”POWER AMPLIFIERS IN CMOS TECHNOLOGY: A CONTRIBUTION TO

POWER AMPLIFIER THEORY AND TECHNIQUES,” PhD. dissertation, Center for

Telematics and Information Technology, University of Twente, The Netherlands, 2011.

[8]

A. Ortiz-Conde, F.J. Garcıa Sanchez, J.J. Liou, A. Cerdeira, M. Estrada, and Y. Yue , “A

review of recent MOSFET threshold voltage extraction methods,” Microelectronics

Reliability, vol. 42, issues 4-5, pp. 583-596, May 2002.

[10]

B.S. Deepaksubramanyan, and A. Nunez, “Analysis of Subthreshold Leakage Reduction in

CMOS Digital Circuits,” 50th Midwest Symposium on Circuits and Systems,Montreal,

Que., pp. 1400-1404, August 2007.

[11]

M. Hansson, ”Low-Power Clocking and Circuit Techniques for Leakage and Process

Variation Compensation,” Ph.D. Dissertation, Dept. Elect. Eng., Linköping Univ.,

Linköping, Sweden, 2008.

[12]

V. Sharma, and S. Kumar, “Design of Low-Power CMOS Cell Structures Using

Subthreshold Conduction Region,” International Journal of Scientific & Engineering

Research, vol. 2, issue 2, February 2011.

[13]

J.M. -H. -Veendrick, “Short-Circuit Dissipation of Static CMOS Circuitry and Its Impact

on the Design of Buffer Circuits,” IEEE Journal of Solid-State Circuits, vol.19, issue 4,

pp. 468-473, August 1984.

[14]

A.P. Chandrakasan, and R.W. Brodersen, “Minimizing Power Consumption in Digital

CMOS Circuits,” Proceeding of the IEEE, vol. 83, issue 4, pp. 498-523, April 1995.

[15] M. Pedram, and F. Fallah, “Standby and Active Leakage Current Control and

Minimization in CMOS VLSI Circuits,” IEICE Transactions on Electronics,vol.E88-C,

no. 4, pp. 509-519, 2005.

[16]

K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, “Leakage Current Mechanisms

and Leakage Reduction Techniques in Deep-Submicron CMOS Circuits,” Proceedings of

the IEEE, vol. 91, issue 2, pp. 305-327, February 2003.

[17]

H.C Chow, and W.S. Feng, “Model for propagation delay evaluation of CMOS inverter

including input slope effects for timing verification,” IEEE Electronic Letters, vol. 28, issue

12, pp. 1159-1160, August 2002.

[18]

S. Nikolaidisi, and A. Chatzigeorgiou, “Analytical estimation of propagation delay and

short-circuit power dissipation in CMOS gates,” International Journal Of Circuit Theory

And Applications, no.27, pp. 375-392, 1999.

[19]

B. H. Calhoun, Design principle for Digital CMOS Integrated Circuit Design, Modular

Series of Microelectronic Device & Circuit Design, USA: NTS Press, 2012.

[20]

SiliconFarEast.com (2001). OxideBreakdown. SiliconFarEast.com [Online]. Available:

http://www

.siliconfareast.com/oxidebreakdown.htm

.

[21]

Y. Teong San, N.R Kamat, R.S Nair, and H. Shze Jer, “Gate oxide breakdown model in MOStransistors,” IEEE International 33rd _{Annual Proceedings Reliability Physics Symposium, Las}

Vegas, NV, pp. 149-155, April 1995.

[22]

E. Takeda, N. Suzuki, and T. Hagiwara, “Device Performance Degradation to Hot-Carrier Injection at Energies Below the Si-SiO2 Energy Barrier,” IEEE International Electron Devices

Meeting, pp. 396-399, 1983.

[23]

A. Acovic, G. La Rose, and S. Yuan-Chen, “A review of hot-carrier degradation

mechanisms in MOSFETs,” Microelectronics Reliability, vol. 36, issues 7-8, pp. 854-869,

August 1996.

[24]

N. Arora, Mosfet Modeling For VLSI Simulation Theory and Practice, 5 Toh Tuck Link,

Singapore: World Scientific Publishing Co. Pte. Ltd., 2007.

[25]

M. Prabhakar Pagey, “Characterization and Modeling Of Hot-Carrier Degradation In Sub-Micron NMOSFETS,” M.S. thesis, Dept. Elect. Eng., Vanderbilt Univ., Nashville, USA, 2000.

[26]

K.M. Wu, J.F. Chen, Y.K. Su, J.R Lee, Y.C. Lin, S.L. Hsu, Shih, and J.R., “Anomalous

Reduction of Hot-Carrier-Induced On-Resistance Degradation in n-Type DEMOS

Transistors,” IEEE Transactions on Device and Materials Reliability, vol. 6, no. 3, pp. 371–

[27]

T. Johansson, and J. Fritzin, "Watt-level CMOS RF power amplifiers", submitted for

publication.

Chapter 3

Level Shifter Implementation

3.1 Introduction

The level shifter circuits are widely used in many portable applications as a bridge that connects a lower input voltage to a higher output voltage gate. Therefore, the level shifter can be seen as a communication circuit between different modules without extra supply pins. When few supply voltages are used in low power circuit, the probability of a low/high input voltage which may be not enough to turn OFF/ON an PMOS/NMOS transistor is relatively high. Thus, that can form a DC leakage current between the VDD and

source which causes power loss. To solve this problem, a swing or level shifter can be used. There are many types of level shifter such as the Conventional Level Shifter I), the Conventional Level Shifter (Type-II), and the Single Supply Level Shifter [1].

3.2 Conventional Level Shifter (Type-I)

It is one of many designs of the level shifter which can be used as interface between low voltage and high voltage gates. The schematic for the Conventional level shifter is shown in Fig. 3.1. The input is low voltage regarding to VDD1 and the output is high voltage according to VDD2. When the input (In) goes to ground or Vss,

the transistor T5 turns ON and the transistor T8 turns OFF. Therefore, the point M1 goes to Vss and M2 goes

to VDD2. The transistor T6 and T7 turn OFF and ON, respectively because of the positive feedback action of

cross-coupled for T6 and T7. On the other hand, when the input (In) goes high or VDD1, the T5 turns OFF and

T8 turns ON. At that time, T6 turns ON due to M2 having been shorted to ground, thus M1 is charged to VDD2 which causes T7 to turn OFF. Therefore, in the two cases, there is no leakage current between VDD2 and

the ground. The delay time between the input and output is decided by the current driving capability for T6 and T7. The size of T5 and T8 has to be larger than T6 and T7 to overcome the latch action of PMOS (T6 and T7) before the output change state.

The first disadvantage of the Conventional level shifter (Type-I) is that the transistors T5 and T8 are thick oxide transistors, thus they can not operate under 1V, due to high threshold voltage of T5 and T8. The second one is the current driving capability for T6 and T7 depends on VDD2. Therefore, the shifting in VDD2 results in

3.3 Conventional Level Shifter (Type-II)

The schematic for the Conventional level shifter (Type-II) is shown in Fig. 3.2. Here, the current driving capability for M6 and M7 is decided the gate-source voltage (VGS, M6) regardless of VDD2, and the saturation

current of M5 can determine the VGS of M6. The current driving ability of M6 and M7 is not affected by VDD2

but M6 and M7 threshold voltage. The Conventional level shifter (Type-II) provides stable current capability. Thus, it can be used for high speed applications. It has one disadvantage. The transistors M5 and M8 are thick oxide transistors, thus they can not operate under 1V [2]-[5].

3.4 Single Level Shifter

The flexibility of a design can be increased by reducing the number of the voltage supplies (number of pins). To increase the flexibility, the single level shifter with one VDD can be used, and is used to provide high

voltage at the output. The schematic for the single level shifter is seen in Fig. 3.3. Connecting the gate of the transistor T5 directly to VDD2 leads to T5 is always ON. T5 provides virtual VDD1 (low supply voltage) to the

input inverter (T3 and T4), where the voltage at M is VDD2 - Vtn, (as diode) where Vtn is the threshold voltage

of T5. In order to avoid the leakage current, a feedback from output to T8 which is considered as a half latch which pulls up the input of the inverter (T9 and T10) to VDD2. When the input signal is High, the node M will

be charged to VDD2 - Vtn to decrease VGS for T3 to make sure T3 is fully OFF. When the input signal is Low,

T8 will be ON to charge node M toVDD2 just to compensate Vtn drop. Thus, the inverters (T3, T4) supply

voltage is dynamically changed between VDD2 - Vtn and VDD2 depending on the input signal. The main

disadvantage of using the single level shifter is that the leakage current is higher than in other designs, specially when the input is lower than VDD2 by more than Vtn. Then, it is useless for a wide range of input and

output voltage. Additionally, it suffers from extra delay due to the limited speed of T5 [2],[8].

3.5 Implemented Level Shifter

In this thesis, the level shifter has been implemented is Conventional Level-Shifter (Type-II). The operation principle can be seen in the section 3.3. There are two Conventional Level Shifters (Type-II) that have been used in the thesis. The first one is to increase the input signal swing from 1.2 V to 2.5 V. The second one to increase the input signal from 2.5 V to 5 V. Because of designing eight schematics for the predriver, the transistors size is different from one design to another. That can been seen in the full predriver implementation chapter 5 [9].