Implementing a receiver in a fast data transfer system : A feasibility study

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Examensarbete

LITH-ITN-ED-EX--03/017--SE

Implementing a receiver in

a fast data transfer system

-

A feasibility study

Filip Hall

Pär Håkansson

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LITH-ITN-ED-EX--03/017--SE

Implementing a receiver in

a fast data transfer system

-

A feasibility study

Examensarbete utfört i Elektronikdesign

vid Linköpings Tekniska Högskola, Campus

Norrköping

Filip Hall

Pär Håkansson

Handledare: Adriana Serban

Examinator: Shaofang Gong

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Rapporttyp Report category x Examensarbete B-uppsats C-uppsats x D-uppsats _ ________________ Språk Language Svenska/Swedish x Engelska/English _ ________________ Titel Title

Implementing a receiver in a fast data transfer system -A feasibility study

Författare Author Filip Hall Pär Håkansson Sammanfattning Abstract

This report is an outcome of a master degree project at Linköpings University in co-operation with Micronic Laser Systems AB.

The purpose with this master degree project was to investigate how to implement a receiver in a data transfer system. The system consists of several data channels, where every channel consists of three parts: driver, transmission lines and receiver. The driver send low amplitude differential signals via the transmission lines to the receiver that amplifies and converts it to a single-ended signal. The receiver has to be fast and be able to feed an output signal with high voltage swing. It is also needed for the receivers to have low power consumption since they are close to the load, which is sensitive to heat.

Different amplifier architectures were investigated to find a suitable circuit for the given prerequisites. In this report the advantages and disadvantages of voltage and current feedback are discussed.

The conclusions of this work are that in a system with an amplifier as a receiver with differential transmission lines, a single operational amplifier cannot be used. An input stage is needed to isolate the feedback net from the inputs of the operational amplifier. When fast rise time and large output swing are wanted the best amplifier architecture is current feedback amplifiers. A current feedback amplifier in CMOS with the required high voltages and slew rate is hard to realize without very high power consumption.

ISBN

____________________________________________ _________

ISRN LITH-ITN

-

ED-EX--03/017--SE

_________________________________________________________________

Serietitel och serienummer ISSN

Title of series, numbering ___________________________________ Datum

Date 2003-10-17

URL för elektronisk version http://www.ep.liu.se/exjobb/itn/2003/ed/017

Avdelning, Institution Division, Department

Institutionen för teknik och naturvetenskap Department of Science and Technology

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ABSTRACT

Abstract

This report is an outcome of a master degree project at Linköpings University in co-operation with Micronic Laser Systems AB.

The purpose with this master degree project was to investigate how to implement a receiver in a data transfer system. The system consists of several data channels, where every channel consists of three parts: driver, transmission lines and receiver. The driver sends low amplitude differential signals via the transmission lines to the receiver that amplifies and converts it to a single-ended signal. The receiver has to be fast and be able to feed an output signal with high voltage swing. It is also needed for the receiver to have low power consumption since they are close to the load, which is sensitive to heat.

Different amplifier architectures were investigated to find a suitable circuit for the given prerequisites. In this report the advantages and disadvantages of voltage and current feedback are discussed.

The conclusions of this work are that in a system with an amplifier as a receiver with differential transmission lines, a single operational amplifier cannot be used. An input stage is needed to isolate the feedback net from the inputs of the operational amplifier. When fast rise time and large output swing are wanted the best amplifier architecture is current feedback amplifiers. A current feedback amplifier in CMOS with the required high voltages and slew rate is hard to realize without very high power consumption.

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PREFACE

Preface

This is a report of a Master degree project within the program Electronic Design. The task of the Master degree project was given by Micronic Laser Systems AB and performed at ITN, campus Norrköping, Linköpings Universitet. The work was financially supported by Micronic Laser Systems AB

Micronic Laser Systems is a world-leading manufacturer of high-end laser pattern generators for production of photomasks. Since semiconductor devices become more complex, high data rates are needed in future laser pattern generators. In this report a model for very high-speed data transmission is investigated.

We would like to thank our supervisor Adriana Serban at ITN for support and assistance. We are also grateful to our examiner Shaofang Gong at the University of Linköping, Campus Norrköping for support and technical ideas. We would also like to thank Leif Odselius at Micronic Laser Systems AB.

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TABLE OF CONTENTS

List of Figures

Fig. 2.1 A data transmission channel with transmission line and receiver ...15

Fig. 2.2 The differential input signals to the receiver ...16

Fig. 2.3 The output signal of the receiver ...17

Fig. 3.1 Schematic of a folded-cascode OTA ...22

Fig. 3.2 CFA in a non-inverting feedback configuration...26

Fig. 3.3 VFA in a non-inverting feedback configuration...26

Fig. 3.4 Simplified schematic of a CFA ...27

Fig. 3.5 Input stage to a VFA...28

Fig. 3.6 Compound transistor in CMOS ...29

Fig. 3.7 Source follower with increased transconductance...30

Fig. 3.8 Voltage follower with compound transistors...31

Fig. 3.9 CFA in CMOS ...32

Fig. 3.10 Op-amp in a difference amplifier configuration...33

Fig. 3.11 Triple-OP IA configuration ...34

Fig. 3.12 Dual-OP IA configuration ...35

Fig. 3.13 Block schematic of a CCII...37

Fig. 3.14 Differential to single converter based on CCII...37

Fig. 3.15 Differential amplifier using CCII and Op-amp ...38

Fig. 3.16 CCII in CMOS...39

Fig. 3.17 NMOS CTA and its three timing phases ...40

Fig. 3.18 Simplified schematic of CMOS CTA...42

Fig. 4.1 Transmission line with terminations...45

Fig. 4.2 Signals at near- and far-end of the transmission, (Γ=0) ...46

Fig. 4.3 Signals at near- and far-end of the transmission, (Γ=-0.2) ...46

Fig. 4.4 Signals at near- and far-end of the transmission line with different lengths ..47

Fig. 4.5 THS3001 in difference amplifier configuration without transmission lines ..48

Fig. 4.6 Output and positive input signals of the difference amplifier with different feedback resistors ...49

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Fig. 4.10 Output signal of the difference amplifier with different load resistances ....51

Fig. 4.11 Output signal of the difference amplifier with different capacitive loads....51

Fig. 4.12 Difference amplifier in the data transmission channel ...52

Fig. 4.13 The full swing output signal of the difference amplifier in the data transmission channel ...52

Fig. 4.14 The current flowing trough Rg1 (dashed line) and Rg2 in the difference amplifier in the data transmission channel...53

Fig. 4.15 The input voltages to the difference amplifier in the data transmission channel ...53

Fig. 4.16 Triple-Op-amp IA using THS3001...54

Fig. 4.17 Full swing output voltage of the triple-Op-amp IA...54

Fig. 4.18 The power consumption the triple-Op-amp at full swing...55

Fig. 4.19 The steady state power consumption of the triple-Op-amp IA ...55

Fig. 4.20 Dual-Op-amp IA using THS3001...56

Fig. 4.21 Input and output signals of the dual-Op-amp IA...56

Fig. 4.22 The input delay between the inputs of Op2 in the dual-Op-amp IA ...57

Fig. 4.23 The CMRR versus the frequency of the dual-Op-amp IA...57

Fig. 4.24 The dynamic power consumption of the dual-Op-amp IA...58

Fig. 4.25 The steady state power consumption of the dual-Op-amp IA ...58

Fig. 4.26 The CMOS CFA in a non-inverting configuration...59

Fig. 4.27 The input and output voltage of the CMOS CFA...60

Fig. 4.28 The steady state power consumption of the CMOS CFA ...60

Fig. 4.29 The dynamic power consumption of the CMOS CFA at full swing ...61

Fig. 4.30 A differential to single converter based on CCII...62

Fig. 4.31 The differential input and the single-ended output signals of the differential to single converter ...62

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ABBREVIATION

Abbreviation

ASIC Application Specific Integrated Circuits BJT Bipolar Junction Transistor

BiCMOS Bipolar CMOS

CCII Second generation Current Conveyor CFA Current Feedback Amplifier

CM Common Mode CMOS Complementary MOS

CMRR Common Mode Rejection Ratio CTA Charge Transfer Amplifier DAC Digital to Analog Converter

FC-OTA Folded Cascode Operational Transconductance Amplifier IA Instrumentation Amplifier

IC Integrated Circuit KVL Kirschoff´s Voltage Law KCL Kirschoff´s Current Law MCM Multi Chip Module

MOS Metal-oxide Semiconductor NMOS N-channel MOS

Op-amp Operational Amplifier

OTA Operational Transconductance Amplifier PMOS P-channel MOS

RF Radio Frequency SOC System On Chip SR Slew Rate

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INTRODUCTION

1 Introduction

1.1 Background

In data transmission systems where large amounts of data are transmitted at high rate, fast and accurate electronic systems are needed. High rate of data flow raises demands not only on electrical circuits but also on the transmission systems. To overcome limitations of electrical circuits new components are used with, e.g., high-speed, high accuracy and low power consumption. State-of-the-art circuits can be realized by using new IC technologies as well as new circuit techniques.

Mainstream IC technologies continue to be CMOS and BiCMOS because of their low cost and high level of integration and low power dissipation. Another advantage is the possibility for digital and analog circuits to coexist on the same chip, i.e., mixed signal design. These advantages motivate the extensive work of developing high-speed CMOS designs and new circuit techniques, despite many difficulties and limitations designers are confronted with.

To push the frequency towards RF-limits implies another set of problems, i.e., how to model and simulate the system or circuit interconnects using the transmission line concept and how to simulate the system including the packaging model.

Micronic Laser Systems is a world-leading manufacturer of high-end laser pattern generators for production of photomasks. Since semiconductor devices become more complex, high data rates are needed in future laser pattern generators. In this report a model for very high speed data transmission is investigated. The task of the work was given by Micronic Laser Systems AB and performed at ITN, campus Norrköping, Linköpings Universitet. This work is financially supported by Micronic Laser Systems AB.

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INTRODUCTION

1.2 Task

The task of this master degree project is to make a study of how to design and use an amplifier as a receiver in a data transfer system. The high speed data transmission system investigated is proposed by Micronics Laser Systems AB. The transmission system consists of several channels, where every channel can be divided into three parts: driver, transmission lines and receiver. The driver sends a signal via the transmission lines to the receiver that feeds the load with an amplified signal. The receiver has to be fast and be able to feed the load with a high voltage swing. It is also required to use a receiver with low power consumption.

The task is to present a study containing solutions both with commercial amplifiers and designs in CMOS. Despite the main task to design an amplifier with the required driving capabilities it should also be compatible with the transmission system. Thus, other design problems must also be dealt with.

1.3 Purpose

The purpose of this work is to present the possibilities and limitations of using amplifiers in a very high speed transmission system. The main purpose is not to achieve a final solution of the receiver problem but to point out different methods to solve it. The master degree project shall also present details to consider when investigating solutions for similar problems.

1.4 Method

Parts of this project have been contributed to study available amplifier architectures. Different architectures have been evaluated to find an amplifier to meet our requirements. The amplifiers simulated can be divided into two groups, designs in CMOS and analyzes of commercial amplifiers. The CMOS schematics were designed and simulated in a 0.6µm process, XC06 from XFAB Semiconductor Foundries AG. Medium-voltage transistors from the XC06 process were used in the simulations. In terms of commercial amplifiers THS3001 from Texas Instrument Inc. was found to be the fastest operational amplifier on the market, so THS3001 was used in this project. Our simulations were done in Hspice and the results viewed in Mentor Graphics Awaves. The schematics were done in Mentor Graphics’ Led.

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INTRODUCTION

1.5 Report Outline

This chapter consists of a background of the work. The task, purpose and method are also presented here. Chapter 2 contains a more detailed presentation of the task and its difficulties. First, one data channel is introduced to give a general picture of the task, and second the requirements of the receiver are presented. In Chapter 3 theory of the amplifier architectures investigated is introduced. This chapter also contains descriptions of the feasibility of using various amplifiers in the data transmission channel. In chapter 4 simulations of different amplifier circuits from chapter 3 are presented. Simulations on both amplifiers alone and amplifiers as receivers in the data channel are shown. The results from chapter 3 and 4 are discussed in chapter 5. Chapter 6 contains the conclusions of the discussion in chapter 5. The best solution found and a suggestion for further work is also presented here. Appendixes are implemented at the end of the report to enhance understanding of the technical parts.

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SYSTEM OVERVIEW AND PROBLEM DESCRIPTION

2 System Overview and Problem Description

In a high speed data transmission system, cross talk, signal skew and switching noise may cause problems to signal integrity. To overcome these problems it is known that differential data transmission provides less cross talk, less signal skew and less switching noise than single-ended data transmission techniques [1].

As a starting point for our study, a low-swing, differential analog data transmission technique with an amplifier array close to the load has been proposed [1]. The data transmission technique has high demands on the amplifier array in terms of speed and power consumption.

2.1 System overview

A block schematic of one data transmission channel with differential driver, near-end terminations, transmission lines, far-end terminations and amplifier is shown in Fig. 2.1, where Vdiff is the differential input signal, Vcm is the common mode signal, Rterm

are the terminating resistors and Vb is the termination voltage. Because of demands on

signal rise time, bandwidth and cable length, it has been concluded that transmission lines with controlled impedance must be used in the system [1]. Hence, the impedance of the cable, connector and line driver must be matched. The low-swing differential data transmission channel requires an amplifier close to the load to amplify and convert the differential signal to a single-ended signal.

Vdiff Vcm RTerm Vout RTerm Vb

Line driver Transmission Line Amplifier

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2.1.1 Input and Output Signals

The differential analog input signal of the amplifier is shown in Fig. 2.2. The voltage at the center of differential signals is called the common-mode (CM) level The CM voltage at the input is 0.25V. Vin+ and Vin- have a voltage swing of 0.5V and the

differential signal at the input is equal to Vindif=Vin+-Vin-. The differential input signal

ranges from –0.5 to 0.5V and thus the peak-to-peak swing of the input voltage is 1V.

Fig. 2.2 The differential input signals to the receiver

For this study it is supposed that the input signal comes from a 10-bit

digital-to-analog converter (DAC) with a sampling frequency of 40MHz. Since the input signal

consists of 10 bits there are 210 =1024 discrete values for the amplifier to distinguish. The voltage magnitude of one step at the input is

mV V V_in_step inpp 1 1024 1 210 , = = ≈ (eq. 2.1)

where Vin,step is the smallest step of the input voltage. Since the sampling frequency of

the DAC is 40MHz, the input signal holds a constant value for 1/40MHz = 25ns.

0.5 Vin+,V

(V)

Vin+

Vin--

CM level of the input signal

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The maximum magnitude of the output signal is 12V. Since the input peak-to-peak voltage is 1.0V the amplifier needs a gain of 12. The common mode of the output signal is 6V, Fig. 2.3 shows the output voltage. The smallest output voltage amplitude step at the amplifier is

mV V

Voutstep outpp 12

1024 12 210

, = = ≈ (eq. 2.2)

where Vout,pp is the output peak-to-peak voltage swing.

Fig. 2.3 The output signal of the receiver

The rise/fall time of a signal is usually defined as the time taken to go from 10% to 90% of the final value. The sampling period is 25ns and the rise and fall time must be less than 5ns [1]. The slew rate (SR) needed for a 5ns rise time and a 12V output swing is given by s kV dt dV SR 1.9 µ 10 5 6 . 9 9 = ⋅ = = ₋ (eq.2.3) 12 Vout (V) Vo

CM level of the output signal

t 6

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2.2 Amplifier Requirements

As previously stated the main objective of this work is to study the amplifier used as a receiver in the system. The most critical requirements of the amplifier are the broad bandwidth, high slew rate and low power consumption.

2.2.1 Bandwidth

The pulse rise time for a circuit with single-pole transfer function is related to the bandwidth according to dB R f t 3 35 . 0 − = (eq. 2.4) where tR is the rise time and f-3dB is the frequency where the system gain has

decreased with 3 dB (Appendix A). For circuits with multiple-pole transfer functions the rise time can often be estimated with eq. 2.4 because the dominant pole normally determines the -3dB frequency. The information given by the rise time might not be sufficient because problems may arise after the signal reached its peak. Circuits with a transfer function containing complex poles can generate a high frequency peak in the frequency response that makes the pulse response to exhibit overshoots and damped sinusoidal oscillation. Thus, it is important to not only look at the rise time but also the settling time to get the information of the maximum speed of a circuit.

In eq. 2.4 it is assumed that the signals are small i.e., the amplifier acts in the linear area. If the input pulse is large enough to cause nonlinear operation the pulse response may get a different appearance than predicted by a small signal analysis.

The amplifier needed in the data channel has a rise time of 5ns, which gives a minimum -3dB frequency of 70 MHz when using eq. 2.4.

2.2.2 Slew Rate

Since the rise time in eq. 2.4 is only applicable for small signals other methods are used to determine the large signal bandwidth. For large output signals, the amplitudes can be close to the power supply, the operation speed is limited by the ability of the amplifier to provide sufficient current to charge the capacitive load. The rate of voltage change when the load is charged at its maximum rate is called the slew rate and is given by

out

I dV

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The rise time for an amplifier at a slew rate limited operation is given by

SR H 8 . 0 tR = (eq. 2.6)

where H is the height of a voltage step and 0.8 originates from the definition of the rise time (10 to 90%).

From eq. 2.3 the slew rate of the amplifier must be 1.9kV/µs and the load is modeled as a capacitor of 10pF. Putting these values into eq. 2.5

mA C SR Iout load 1.9 10 10 10 19 10 19 3 12 9_⋅ _⋅ ₌ _⋅ ₌ ⋅ = ⋅ = − − _{(eq. 2.7)}

Thus, we need an output current equal to 19mA during 5ns to have the desired slew rate.

2.2.3 Common Mode Rejection

The common mode voltage is defined as the average input voltage, i.e., (vin++vin-)/2.

Since the input signals are differential the common mode voltage is always supposed to be the same. Variation in the common mode voltage can arise due to noise and it is thus important for the amplifier to suppress any such variation since it should not affect the output signal.

The common mode rejection ratio (CMRR) is given by

⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ = CM DM A A CMRR 20log (eq. 2.8)

where ADM is the differential mode gain and ACM is the common mode gain. Assume

a common mode rejection of 60dB,

3 10 12 1000 12 1000_⇒ ₌ ₌ _⋅ − = CM CM DM A A A (eq. 2.9) If we want a common mode noise to be less than 10% of the smallest signal (1.2mV) at the output the maximum common mode signal at the input is

V A V V CM out CM in 0.1 10 12 10 2 . 1 3 3 max , max , _⋅ = ⋅ = = ₋− (eq. 2.10)

With a CMRR of 60dB we can allow a common mode noise of 0.1V without getting a distortion larger than 10% of the minimum output signal.

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2.2.4 Power Consumption

The current in an amplifier flows mainly through the output and supply pins. The power dissipated in the amplifier can be divided into two parts, internal and external power dissipations. The internal power consumption arises from transistor biasing. The external power consumption is made up of the current flowing out from the circuit, i.e., the output current.

It was mentioned earlier that a great number of amplifiers will be used in the entire system on a finite area. Many amplifiers active on a small area lead to a high heat radiation. In this project the area around the amplifiers is sensitive to heat and it is thus important that the amplifiers have as low power consumption as possible. In fact, low power consumption is one of the key characteristics of the amplifiers

2.2.5 Amplifier Specifications

A short summery of the amplifier specification is listed below.

• Differential input, Vin,diff =0-1V, Vin,cm=0.25V

• Single-ended output, Vout=0-12V

• Gain(closed loop) 12 times

• Voltage resolution 12mV at the output • 40 Msamples/s

• Rise time <5ns • Bandwidth 70MHz

• Worst case slew rate 1.9 kV/µs • Cload=10pF

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AMPLIFIER ARCHITECTURES

3 Amplifier Architectures

In this chapter theory of the investigated amplifier architectures is presented. Also presented are the advantages and disadvantages of the different architectures and the feasibly to use them in the transmission system. Architectures investigated in this work are current feedback, voltage feedback and charge transfer amplifiers. Theory about differential amplifiers is also presented.

3.1 Operational Transconductance Amplifier

Today a lot of high-speed Op-amps realized in CMOS are designed to drive purely capacitive loads. Since the system described in chapter 2 has a purely capacitive load it is possible to design faster amplifiers with higher output swing than those designed for driving resistive loads. The high speed is obtained by only having one high-impedance node, i.e., the output node, and all internal nodes have low-high-impedance. Examples of amplifiers using these features are the folded-cascode amplifier and the current mirror amplifier [2]. These amplifiers are often referred to as Operational Transconductance Amplifiers (OTAs).

The OTA is basically a conventional Op-amp without an output buffer. An op-amp designed to drive capacitive loads does not need a buffer to obtain low output impedance and hence can the OTA be useful.

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The circuit in Fig. 3.1 is referred to as a Folded-Cascode OTA (FC-OTA) [2]. It is called folded-cascode since the differential input pair (appendix B) is folded down from the active load (Mp0-Mp3). The basic idea with folded-cascode is to use

transistors of opposite type in the active load and in the differential input pair. The opposite transistor type arrangement makes it possible for the output to be taken at the same bias-voltage levels as the input signals [2]. The only high impedance node in Fig. 3.1 is the output node. The open loop gain of the amplifier is determined by the product of the input transconductance and the output impedance. Since the output impedance is high due to the cascode technique a high gain is obtained. The differential to single conversion in the circuit is realized with a wide swing current mirror (Mn4-Mn7).

Fig. 3.1 Schematic of a folded-cascode OTA

Vbias1 Vbias3 Vbias2 Vbias4 Vinp Vinn Mp0 Mp2 Mn1 Mn0 Mn4 Mn6 Mn7 Mn5 Mn2 Mn3 Mp1 Mp3 Vout VSS VDD

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S

MALL

S

IGNAL

A

NALYSIS

If the high-frequency poles and zeros are ignored the small signal transfer function of the FC-OTA is given by

) ( ) ( ) ( , Z s g s V s V A _m_in _L in out v = = (eq. 3.1)

where gm,in is the transconductance of each transistor in the differential input pair and

ZL(s) is the impedance at the output node [2]. ZL(s) consists of the output load

capacitance, the impedance of the stabilizing network and the output impedance of the FC-OTA. When the amplifier is stabilized by the output capacitance, the small signal transfer function is L out out in m v C sr r g A + = 1 , _{(eq. 3.2)}

where rout is the output impedance. When operated at high frequencies the load

capacitance dominates and the transfer function is thus

L in m v sC g A = , (eq. 3.3)

and the unity-gain frequency is then

L in m t C g _, = ω (eq. 3.4) To maximize the unity-gain frequency, the transconductance of the input transistors must be maximized. The transconductance of a transistor is raised by increasing its width or drain-source current or both. Eq. 3.4 shows the relationship between the unity gain frequency and the capacitive load.

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S

LEW RATE

The slew rate available in a FC-OTA is derived from internal currents of the amplifier. When a large input signal is applied to the input Mn1 is turned on hard and

Mn0 is turned off. This means that all the biasing current in the transistor Mp1 is

flowing through Mp3. Since Mn0 is turned off all the current from the current source

(Mn2 and Mn3) is flowing through Mn1. The current flowing in the current source must

be larger than IDp0. Therefore, the current available for charging CL is IDp2, which is

half of the total biasing current. A similar reasoning is valid for discharging the load. Hence, the maximum available slew rate in the FC-OTA in Fig. 3.1 is given by

L tot L Mp C I C I SR ⋅ = = 2 2 (eq. 3.5) If we were supposed to design a FC-OTA for the slew rate of 1.9kV/µs, the current flowing in MTp2 and MTp4 has to be

mA C SR I IMp Mp L 1.9 10 10 19 11 9 2 0 = = ⋅ = ⋅ ⋅ = −

If the supply voltage is assumed to be 14V and the power dissipated in the biasing network is ignored, the power dissipated is

(

V V

)

I I mW

P_diss= _dd − _ss ⋅( _Tp₂ + _Tp₄)=14*0.038=538

The slew rate of a current mirror amplifier can be larger than a FC-OTA for a given biasing current. However, it is still the biasing current that charges/discharges the load.

To increase the driving capabilities of the OTA an output buffer can be added. An OTA with output buffer is a conventional voltage feedback Op-amp [3].

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3.2 Voltage-Feedback and Current-Feedback Op-amp

In the previous chapter it was shown that the slew rate of an OTA is derived from the internal currents (i.e., biasing currents) and the load capacitance. The large slew rate and capacitive load given in chapter 2 (i.e., 1.9kV/µs and 10pF) leads to high power consumption of the OTA. Therefore, conventional Op-amps are investigated in the following chapter.

When high slew-rate, large-signal and wide bandwidth is of interest, as in our project, the current-feedback operational amplifier (CFA) is the first choice to analyze. CFAs have gained popularity during the last years since modern process technologies make it possible to make use of the advantages of the CFA. Large signal CFAs are usually designed in bipolar technologies due to the availability of high-speed complementary bipolar transistors. Slew rates of CFAs can normally reach 500V/µs to 2500V/µs compared to maximum slew rates of about 100V/µs for voltage feedback operational amplifier (VFA) with comparable quiescent currents.

3.2.1 Voltage-Feedback Vs Current-Feedback Op-amps

Main differences between CFAs and VFAs as well as a presentation of a classical CFA architecture and its basic function are presented below.

The slew rate of VFAs is inherent limited by the fixed tail current in the input stage and the compensation capacitance.

The large slew rate of CFAs is obtained as a result of using current as a feedback error signal. In other words, the input stage current is not fixed. In closed-loop configuration the gain-bandwidth product of VFA is constant,

i.e., the closed-loop gain is dependent on the bandwidth. In CFA the product of bandwidth and gain is not constant.

A VFA has high impedance at both the non-inverting and inverting inputs. CFA inputs are asymmetrical, the non-inverting input has high impedance but

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The closed loop gain of the CFA in Fig. 3.2 is given in eq. 3.6 and is very similar to the closed loop gain of the VFA in Fig. 3.3 (eq.3.8). However, eq. 3.7 has some interesting features compared to the voltage feedback gain bandwidth product (eq. 3.9). The VFA closed loop bandwidth decreases with increased loop gain. In contrast, the closed loop bandwidth of the CFA is independent of the closed loop gain. Moreover, eq. 3.7 implies that the CFA requires specific values of Rf and Cc

(compensating capacitor) to be properly compensated. To increase the stability of the amplifier the value of the Rf or Cc can be increased. A derivation of the closed loop

gain and bandwidth is given in appendix C.

) 6 . 3 .( 1 eq R R V V A g f in out = + = ) 7 . 3 .( 2 1 eq C R BW c f π =

Fig. 3.2 CFA in a non-inverting feedback configuration

) 8 . 3 .( 1 1 2 eq R R V V A in out = + = ) 9 . 3 ( . eq f BW A GBP= ⋅ = t

Fig. 3.3 VFA in a non-inverting feedback configuration

2 R 1 R in V err V err aV Vo Ierr in V g R err tI z f R o V

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3.2.2 The Current Feedback Op-amp

The CFA usually consists of an input stage, current mirrors, a high impedance node and an output buffer. Fig. 3.4 shows a simplified schematic of a CFA in a non-inverting feedback configuration [2].

The input stage (Q1-4) forces the inverting and non-inverting inputs to have the same potential. If there is a difference in potential between the inverting and non-inverting input a current start flowing out from or into the inverting input to counteract the voltage difference. This current (If) is the difference between the collector currents of

Q2 and Q4 in Fig. 3.4. These collector currents are mirrored, using current mirrors (CM1 and CM2), to the high impedance node denoted as Cc and Ro in Fig. 3.4. This

results in a high voltage swing at the high impedance node. Hence, the actual amplification is done at this node. The last stage is a unity gain buffer that buffers the voltage at the high impedance node to the output.

Fig. 3.4 Simplified schematic of a CFA

x1 Rf Rg Ro Cc Buffer If IR Ir Q1 Q2 Q3 Q4 Vin+ Vin- CM2 CM1

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In Fig. 3.4 a class-AB input stage is used to force the inverting input to follow the non-inverting input. In contrast, Fig. 3.5 shows an input stage that is typical for a conventional VFA. This type of configuration is called a differential pair. The differential pair is in many ways different from the input stage in a CFA. Both of the inputs in a VFA (differential pair) have high impedance, resulting in essentially no current flowing into the nodes.

Fig. 3.5 Input stage to a VFA

The slew rate at the high impedance node in the VFA is usually limited by the current flowing in the biasing transistor (Q3 in Fig. 3.5). However, the slew rate of the CFA is not limited by the biasing current since the current flowing into or out from the inverting input also affects the slew rate. The current flowing through the inverting input helps charging/discharging the high impedance node. This gives the CFA a much higher slew rate compared to the VFA with the same quiescent currents and bandwidth.

In applications the CFA can be configured similar to the VFA but with one exception, a capacitance can never be connected between the output and the input of the amplifier. The open loop inverting input with low impedance causes much concern among designers and is often viewed as making a CFA unsuitable as a difference amplifier. However, a CFA can be used as a difference amplifier with the same configuration as the VFA [4].

The VFA has better DC-performance characteristics than the CFA. The VFA also has better CMRR. Even though a VFA has better DC-characteristics, a CFA is needed in

Vin+ Vin-

Vbias

Q2 Q1

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3.2.3 A CMOS Current Feedback Amplifier

A disadvantage when using CMOS transistors in analog amplifiers is their relative low transconductance (gm) compared to bipolar transistors. The gm of a MOS

transistor in the saturated region is proportional to √ID, eq. 3.10, whereas it is

proportional to IC for a BJT. Increasing ID to get higher gm also increases the power

dissipation. To double gm of a MOS transistor the drain current has be increased four

times. Another way to get higher gm is to increase the width of the transistor, but large

transistors generates more parasitic capacitance and the frequency response gets reduced (appendix D). D ox n m I L W C g = 2µ (eq 3.10)

A method used to generate higher gm, without increasing the current or dimensions, is

to combine two or more transistors. A circuit designed for this purpose is referred to as a compound transistor.

C

OMPOUND TRANSISTOR

A compound circuit with increased transconductance is shown in Fig. 3.6 [5]. The circuit consists of two source followers and one current mirror. One of the source followers is made with an NMOS-transistor and the other with a PMOS-transistor. The current mirror feeds Mn1 with a bias current. The bias current is fed back with a

ratio of α to 1.

The circuit is equivalent to a PMOS transistor where the compound gate is the gate of Mn1 and the source of Mp1 is the compound source. The compound drain terminal can

be achieved by duplicating the drain current in Mp1 using an extra output from the

current mirror. The compound transistor transconductance is calculated through a small signal analysis. The small signal analysis gives a Gm of (gmn1gmp1)/(gmn1- αgmp1)

from the gate of Mn1 to the source of Mp1. The current mirror transfer ratio should be

set to α=gmn1/gmp1 for a maximized transconductance.

Mn1 Mp1 α:1 source gate Ibias

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S

OURCE FOLLOWER WITH INCREASED TRANSCONDUCTANCE

There are two drawbacks with the simple source follower when it is used as an output buffer. The first is that there is a DC level shift between the input and output voltage, Vout=Vin-Vgs. The second is that it has high output impedance. The output impedance

of a source follower is inversely proportional to the transconductance, eq. 3.11. A method to achieve lower output impedance is thus to increase the transistor transconductance which can be realized by using compound transistors.

1

m out

g

Z = (eq. 3.11)

A source follower implemented with an n- and p-type current mirror is shown in Fig. 3.7 [5]. The source follower is a realization of the p-compound device in Fig. 3.6. Since the compound circuit is a source follower it is meant to have equal output and input voltage. To achieve a linear transfer function the gate-source voltage of transistor Mn1 and Mp1 must be the same. The n- and p-type current mirror made by

Mn2 and Mp2 acts as a gate-source voltage matching circuit for Mn1 and Mp1.

Assuming that Mp1 and Mp2 have the same size and equal drain current the gate source

voltage has to be identical. The same reasoning is valid for Mn1 and Mn2. Since Mn2

and Mp2 have the same gate source voltages, Mn1 and Mp1 have to have identical gate

source voltages. The matching circuit removes the gate-source voltage differences between Mn1 and Mp1, thus the output-offset voltage problem removed and the output

voltage follows the input voltage. Even though it is supposed to be matched, input-output matching problems can arise due to body effects in the transistors. Using a twin-well process can reduce the body effect and generate better DC-accuracy [5].

Mn1 Mp1 Mp2 Mn2 source gate Ibias

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B

UFFER WITH COMPOUND TRANSISTORS

An output voltage buffer is often used in Op-amp to isolate the load from the high impedance node. In high-speed amplifiers it is important to have a fast voltage buffer that can feed large output currents. A voltage follower used in high-speed Op-amps should have high input impedance, very low input capacitance, very low output impedance, gain near unity, high linearity, wide frequency response and the ability to drive large capacitive loads without oscillation. The voltage follower in Fig. 3.8 is designed to meet these requirements better than the conventional voltage follower [5].

Fig. 3.8 Voltage follower with compound transistors

The voltage follower in Fig. 3.8 is implemented with two compound transistors, one p-type and one n-type. The p-type is realized with Mn1, Mp1 and a current mirror

implement by Mn2 and Mp2. The n-type is realized with Mn3, Mp3 and a current mirror

implement by Mn4 and Mp4. The compound transistors are connected in a push-pull

configuration. Since the compound transistors have high gm the output impedance is

low. Mn3 Mp3 Mn1 Mp1 Mp2 Mn2 Vout Mn4 Mp4 vss2 vss1 vdd2 vdd1 Vin+

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C

URRENT

F

EEDBACK

O

P

-

AMP IMPLEMENTATION

A CFA designed for high frequency is shown in Fig. 3.9 [5]. The CFA consists of two voltage followers of the technique presented above. The voltage followers are used as input and output buffers. The circuit in Fig. 3.9 has the typical current feedback features, a high impedance non-inverting input, a low impedance inverting input, a high impedance gain node and a unity voltage gain output buffer.

The input stage (Mn1-Mn4 and Mp1-Mp4) forces the inverting and non-inverting inputs

to have the same potential. When the amplifier is in a non-inverting feedback configuration (Fig. 3.2) and there is a difference in potential between the inverting and non-inverting input a current start flowing out from or into the inverting input to counteract the voltage difference. This current is the difference between the source currents of Mn5 and Mp3. These source currents are mirrored, using Mn5 and Mp5, to

the high impedance node (H). The last stage is a unity gain buffer that buffers the voltage at the high impedance node to the output.

Fig. 3.9 CFA in CMOS

Vin+ Mp4 Mn9 Mn3 Mp2 Mn2 Mp3 Mp5 Mp6 Mp9 Mn7 Mp7 Mp8 Mn8 Mn5 Mn1 _M_n6 CC Vdd1 Vout Mp1 Mn10 Mn4 Mp10 Vdd3 Vss1 Vss3 Vdd2 Vss2 V in-Vbias1 Vbias2 (H)

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3.3 Differential Amplifiers

Differential amplifiers can be realized using one or more Op-amps in different configurations. A differential-to-single input stage together with an Op-amp can also be used as a differential amplifier.

3.3.1 Op-amp in a Difference Amplifier Configuration

An Op-amp in a difference amplifier configuration is shown in Fig. 3.10. To have true differential amplification, eq. 3.12 must be satisfied.

2 2 1 1 g f g f R R R R = (eq. 3.12) When eq. 3.12 is true, the amplified voltage is given by

) ( 1 1 = V_diff R R V g f amp (eq. 3.13)

The output voltage is given by Vo=Vamp+Vref

Fig. 3.10 Op-amp in a difference amplifier configuration.

Rf1 Vref CL RL Vo Rg1 Rf2 Rg2 Vdiff Vcm _ +

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3.3.2 Instrumentation Amplifiers

The classic difference amplifier configuration can be unsuitable in some applications. A configuration involving more than one Op-amp can be used to achieve a better differential amplifier and is referred to as an instrumentation amplifier (IA). An IA should meet following specifications: very high common-mode and differential-mode input impedance, low output impedance, accurate and stable gain, and extremely high CMRR [6]. IAs are often used in test and measurement instruments and hence their name.

T

RIPLE

-O

P

-

AMP

IA

The IA in Fig. 3.11 consists of two stages, the input or first and the output or second stage [6]. The first stage consists of two Op-amps, Op1 and Op2. The second stage

consists of Op3 in a difference amplifier configuration.

Fig. 3.11 Triple-OP IA configuration

The voltage across Rg is given by the difference of the input voltages, vin1-vin2, since

the inverting and the non-inverting input of an Op-amp have the same voltage. The same current flows through R3 and Rg since no current flows through the inputs of

Op-amps. The output voltage of the first stage is given by

(

₁ ₂

)

3 2 1 2 1 _in _in g out out v v R R v v _⎟⎟ − ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ + = − (eq. 3.14) Vout Rf Ri R3 Rg R3 Rf Ri Vin1 Vin2 Op1 Op3 Op2 Vref

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Combining eq. 3.14 and eq. 3.15 gives

(

in2 in1

)

out Av v

v = − (eq. 3.16)

where A is the total gain. The total gain is given by

⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ × ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ + = × = _Ι _ΙΙ i f g R R R R A A A 1 2 3 (eq. 3.17)

where the total gain A is the product of the first- and second-stage gains AI and AII.

Since the input Op-amps are connected in a non-inverting configuration their input impedance becomes extremely high. Likewise the output impedance of Op3 is low.

Hence the circuit in Fig. 3.11 meets all the requisites for an IA given above.

D

UAL

-O

P

-A

MP

IA

It can be advantageous to use as few Op-amps as possible in an IA. An IA with two Op-amps is shown in Fig. 3.12 [6]. The configuration in Fig. 3.12 is referred to as a Dual-OP IA.

Fig. 3.12 Dual-OP IA configuration

Since Op1 is a non-inverting amplifier its output voltage is

1 4 3 1 1 in out v R R v _⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ + = (eq. 3.18)

The output voltage of the circuit, vout, is given by

2 2 1 2 ₁ in out out v R v R v ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ + + ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ − = (eq. 3.19) R4 R2 Op2 R1 Op1 R3 Vin2 Vin1 Vout Vref

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Combining eq. 3.18 and eq. 3.19 gives following expression of Vout

⎠ ⎞ ⎜ ⎜ ⎝ ⎛ + + − ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ + = ₁ 2 1 4 3 2 1 2 / 1 / 1 1 in in out v R R R R v R R v (eq. 3.20)

For true differential operation the resistances must have the relationship of

2 1 4 3 R R RR = (eq. 3.21)

When eq. 3.21 is true the output voltage is given by

(

2 1

)

1 2 1 in in out v v R R v − ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ + = (eq. 3.22) The circuit in Fig. 3.12 has high input impedance and low output impedance. The obvious advantages with a dual-op-IA compared to the more common used triple-op-IA is the fewer Op-amps and resistors that makes the circuit cheaper, smaller and more power effective. A drawback of the circuit is that the input signals are treated asymmetrically because vin1 first has to propagate through Op1 before it catches up

with vin2. The delay in Op1 makes a deterioration of the common-mode component

cancellation in the two input signals when the frequency arises. Thus a degradation of the CMRR with respect to the frequency is the trade off for using fewer Op-amps. In the equations of both the triple-Op and dual-Op IA the reference voltage is assumed to be at ground potential. The reference voltage determines the CM-level of the output voltage, which in this case is 0V.

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AMPLIFIER ARCHITECTURES Iy Vy Vx Ix Iz Vz Z Y X

3.3.3 Op-amp with Differential to Single Input Stage

Instead of using multiple Op-amps in an IA, a differential amplifier can be realized using a differential to single converter and one Op-amp.

D

IFFERENTIAL TO SINGLE CONVERTER

To handle a differential input and convert it to a single-ended signal a differential-to-single converter has to be designed. One idea is to use two second generation current

conveyors (CCII) to design a differential-to-single converter.

A CCII is a three port device that operates as a voltage follower between port X and Y, and a current follower between port X and Z [7]. The definition of a CCII is shown in eq. 3.23 – eq. 3.25. Key features of CCII are low gain error, low DC error, high linearity and a wide bandwidth.

0 = y I (eq. 3.23) y x V V = (eq. 3.24) x z I I = (eq. 3.25)

Fig. 3.13 Block schematic of a CCII

A differential-to-single converter using two CCII is shown in Fig. 3.14. Eq. 3.23 implies that no current is flowing into or out from the Y port of the differential to single converter.

Fig. 3.14 Differential to single converter based on CCII

It is concluded from eq. 3.24 that the voltage across R1 is equal to Vin+-Vin-. The

voltage across R produces a current equal to

Vin+ V in-Vref R1 _R₂ CCII CCII Ie Ie Vout Y X Y Z X

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The current (Ie) is flowing out from one of the CCII and into the other CCII. From eq

3.25 we know that Ix = Iz. Hence, the same current is flowing in both R1 and R2. The

voltage across R2 has to be equal to

2

R I V

V_out − _ref = _e⋅ (eq. 3.27)

Combing eq. 3.26 and eq. 3.27 gives

(

in in

)

ref out V V V R R V = ⋅ ₊ − ₋ + 1 2 _{(eq. 3.28)}

Hence, the differential signal is converted to a single-ended signal.

A

D

IFFERENTIAL TO

S

INGLE

A

MPLIFIER

The circuit in Fig. 3.15 consists of two stages. The first stage is the differential-to-single converter presented above and the second stage is Op-amp in a non-inverting configuration. The gain of the amplifier is given by

⎠ ⎞ ⎜ ⎜ ⎝ ⎛ + = 4 3 R R R R G 1 1 2 _{(eq. 3.29)}

Fig. 3.15 Differential amplifier using CCII and Op-amp

Vin+ V in-Vref R1 R2 R₄ R3 CCII CCII Op-amp + - Ie Ie Vout

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A

S

ECOND

G

ENERATION

C

URRENT

C

ONVEYOR IN

CMOS

Fig. 3.16 shows an implementation of a current conveyor in CMOS [7]. With properly matched transistors Mn5 and Mp5 have the same gate- source voltage and same drain

current (Ibias). Since, Mn5 and Mp5 have the same drain current Iy is ideally equal to

0A.

The translinear cell, Mn5, Mn6 and Mp5, Mp6, is designed to have equal gate-source

voltages. A KVL (Kirschoffs voltage law) in the translinear cell gives the relationship Vx = Vy.

The drain current of Mn6 and Mp6 are equal at the quiescent point. A current flowing

out from or into node X is mirrored to node Z (Ix = Iz). This implies that all the

conditions of a CCII are satisfied.

Fig. 3.16 CCII in CMOS

Y X Z Ibias Mp1 Mp2 Mp3 Mp4 Mp5 Mp6 Mn6 Mn5 Mn4 Mn3 Mn2 Mn1

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3.4 Charge Transfer Amplifier

The last architecture investigated in this work is the charge transfer amplifier (CTA), which is very different from the OTA and Op-amp. The advantage with CTA is mainly their potentially low power consumption. The CTA consumes little or no power during static operation.

The charge transfer amplifier (CTA) operates by transferring a charge to or from the capacitor CT to the load capacitor. The quantity of charge transferred to or from the

load capacitor is proportional to the input voltage (transconveyance).

3.4.1 NMOS CTA

A simplified schematic of the NMOS CTA amplifier core is shown in Fig. 3.17 [8]. The NMOS CTA requires three different timing phases, shown in Fig. 3.17. The phases are called Reset-, Precharge- and Amplify-phase. The dynamic behavior of a CTA is difficult to characterize, a complete description of the dynamic behavior is carried out in [8]. In the following relationships all second order effect are ignored.

Fig. 3.17 NMOS CTA and its three timing phases

Reset phase

In the reset phase, CT is connected to Vss and discharged. The output node is

connected to the precharge voltage VPreC and Cload is charged. Thus, the voltages at the

end of the reset phase are

SS B V V = (eq. 3.30) eC O V V = _Pr (eq. 3.31) Time

Res Pre Amp Res

S1 S2 Vss Vin S2 VpreC S1 S1 CT Cload VB Vo

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Precharge phase

CT is connected to the source of the NMOS transistor during the precharge phase. At

beginning of this phase VB = Vss and Vo = VPreC. Current flows from output node to CT

until the transistor reaches the cutoff region. At the end of the precharge phase we have TN IN B V V V = − (eq. 3.32) eC O V V = _Pr (eq. 3.33) Amplification phase

A change in VIN (∆VIN) will result in the same change at the source of the NMOS

transistor (node B). TN IN IN B V V V V = +∆ − (eq. 3.34)

The change in Vin produces a current flowing from the output node to the node B

(From Cload to CT). The change in charge at the CT is equal to

T IN C

V

Q=∆ ⋅

∆ (eq. 3.35)

Since the current is conveyed from Cload through the NMOS transistor to CT the

following relationship is valid at the output

(eq. 3.36) Combining eq. 3.35 and 3.36 gives

(eq. 3.37) To conclude, at the and of the amplification phase

TN IN IN B V V V V = +∆ − (eq. 3.38) IN load T eC O V C C V V = _Pr − ∆ (eq. 3.39)

The idea with a charge transfer amplifier is that when the device reaches cutoff region

load o C V Q=∆ ⋅ ∆ IN load T O V C C V = ∆ ∆

(45)

can only amplify positive input signals. This makes the NMOS CTA not feasible to our application.

3.4.2 Other CTA Architectures

A solution to the problem incorporated with the NMOS CTA is to add a PMOS CTA in parallel with NMOS counterpart (Fig. 3.18) [9]. The main idea of the CMOS CTA is that the non-idealities such as subthreshold current should cancel each other out.

Fig. 3.18 Simplified schematic of CMOS CTA

The CMOS CTA is reset in a similar way as the NMOS CTA, the capacitors are discharged. At the end of the precharge phase the output has the potential of

eC Out V

V = _Pr (eq. 3.40)

and the sources of the transistors (gate precharged to VPreC)

TN eC B

A V V

V _, = _Pr ± (eq. 3.41)

The drain-source voltage is equal to |VTN|, an increase in Vin (positive or negative)

leads to a charge transfer trough the transistor with the corresponding voltage drop. However, the maximum output voltage possible before both of the devices reaches the cutoff region (V =0) is Cload Vss S2 VpreC S1 S1 CT Vss Vdd S1 S1 CT Vdd Vin=Vpre+∆Vin VA VB Vout

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have overcome some of the problems with the differential CTA. However, to the authors’ knowledge the limited output voltage range still remains.

An application of the CTA is to use it as a preamplifier followed by a track and latch stage in A/D converters [9]. The gain in the CTA is normally 4 to 10 times and the output voltage of the preamplifier is normally in the order of a few tens of mV.

(47)

(48)

SIMULATIONS

4 Simulations

In this chapter simulations are presented. The simulations in this report are delimited to transmission lines, current feedback operational amplifiers and instrumentation amplifiers. The simulations were done in Hspice and the results viewed in Mentor Graphics Awaves. The schematics were done in Mentor Graphics’ Led.

4.1 Transmission Lines

Signals in the data channel are transmitted in transmission lines. A schematic of differential transmission lines with termination resistors is shown in Fig. 4.1.

Fig. 4.1 Transmission line with terminations

Hspice allows the user to create cable models based upon measured data. Using data from [1] a model for a 50Ω cable was created. The parameters of the transmission lines used in our simulations are

vrel=0.67 Attenuation –2dB at 250 MHz Z0=50Ω VT1 Z0=50 Ω l=0.5 m Zs=50 Ω Vdiff ZT2=50 Ω Zs=50 Ω ZT1=50 Ω Driver Line Vcm VT2

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SIMULATIONS

Fig. 4.2 shows the positive signal at near-end (solid line) and far-end (dashed line) with perfect match (Γ=0) (appendix F). The wire model used in this simulation is loss-less and has the length of 0.5m. The total delay time for the pulse from the source to the output of the transmission lines is given by

(eq. 4.1) where lTline is the length and vcable is the speed of the transmission lines.

Fig. 4.2 Signals at near- and far-end of the transmission, (Γ=0)

To illustrate the consequence of termination mismatch at the near- and far-end a simulation with ZT = 75Ω was performed. The simulation with transmission lines

without attenuation is shown in Fig. 4.3. The simulation shows a reflection of 20% of the incident wave, which was expected (Γ=-0.2).

ns v l t cable Tline ₂_.₅ 10 0 . 2 5 . 0 8 = ⋅ = =

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SIMULATIONS

The delay and attenuation of the signal changes with wire length. Fig. 4.4 shows the signals with wire lengths of 0.5m, 1m and 1.5m, respectively. The delay is consequently 2.5ns, 5ns and 7.5ns. Compared to Fig. 4.2, the signal degradation owing to cable loss is apparent.

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SIMULATIONS

4.2 A Bipolar Current Feedback Amplifier: THS3001

There are many general purpose amplifiers available on the market. In a research, the most suitable amplifier was the current feedback amplifier Op-amp THS3001 from Texas Instrument Inc. As the majority of the available CFAs it is designed in a bipolar technology. The THS3001 is manufactured in a complementary, high speed and high voltage bipolar process.

According to the specification of THS3001, it has a unity gain frequency of 420MHz and a maximum slew rate of 6500 V/µs (25% to 75% of the output voltage at 30V power supply) [11]. When driving a capacitive load larger than 10pF a series resistor of at least 20Ω must be used to ensure stabile operation [12].

4.2.1 Difference Amplifier using THS3001

To determine if THS3001 could handle the requirement given, it was simulated in a difference amplifier configuration, Fig. 4.5. Since there is a relationship between the feedback resistor and the bandwidth of a CFA, the configuration in Fig. 4.5 was simulated with feedback resistors (RF) of 900, 1000, 1200, 1500 and 1700Ω. The gain

of the amplifier had a constant value of 12.

Fig. 4.5 THS3001 in difference amplifier configuration without transmission lines

Vref=6 V Rf1 CL=10 pF RL=20 Ω Vo Rg1 Rf2 Rg2 Vdiff Vcm - +

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SIMULATIONS

Fig. 4.6 shows the full swing input and output signals of the setup in Fig. 4.5 with different values of the feedback resistor, 0.9-1.7kΩ. The rise times and overshoots differ with different feedback resistors. The highest slew rate, but also the largest overshoot (6%), is achieved with the smallest feedback resistor (0.9kΩ). The rise time with a 0.9kΩ resistor is 1.6ns and with a 1.7kΩ resistor the rise time has increased to 4.7ns.

Fig. 4.6 Output and positive input signals of the difference amplifier with different

feedback resistors

Fig. 4.7 zooms in the output signal in Fig. 4.6 to estimate the settling time (note the first overshot in Fig. 4.6 is excluded in Fig. 4.7). The output signal, when RF=1.2kΩ,

settles within 0.1% of the output swing at 62ns. Since the signal start rising at 50ns the settling times becomes 12ns. The settling time is 10 and 18ns for values of RF of

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SIMULATIONS

P

OWER CONSUMPTION

The power consumption, when the output swings between 0 and 12V every 25ns, is shown in Fig. 4.8. The average power consumption at full output swing is given in Table 4.1.

Fig. 4.8 Full swing power consumption of the difference amplifier

Fig. 4.9 shows the steady state power consumption. The input voltage is ramping from 0 to 1V during 200ns. The average steady state power consumption is given in Table 4.2.

Table 4.1 Average power

consumption of Fig 4.8 (CL=10pF, RL=20Ω) Rf Power 0.9kΩ 240mW 1.0kΩ 225mW 1.2kΩ 210mW 1.5kΩ 190mW 1.7kΩ 180mW

consumption of Fig 4.9 (CL=10pF, RL=20Ω) Rf Power 0.9kΩ 170mW 1.0kΩ 160mW 1.2kΩ 145mW 1.5kΩ 135mW 1.7kΩ 128mW

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SIMULATIONS

R

ISE AND FALL TIME WITH DIFFERENT LOADING

To investigate how different load resistances affect the rise time of the amplifier, simulations with different load resistors were done. The different load resistors (RL)

used in the simulation was 0Ω, 20Ω, 50Ω, 100Ω and 500Ω. The power consumption is independent of the load resistance. RF used in the simulation is 1.5kΩ.

Fig. 4.10 Output signal of the difference amplifier with different load resistances

If the load resistance becomes too large the amplifier cannot meet the speed requirement. The crucial load resistance is between 50 and 100Ω. It is also interesting to be aware of the influence of the capacitive load. Simulation with different load capacitances is shown in Fig. 4.11. The rise time becomes faster when CL decreases

but with the payoff of large overshoots. The power consumption becomes higher due to larger CL, Table 4.2.

consumption with different load capacitance

(CL=10pF, RL=20Ω, Rf=1.5kΩ) CL Power 5pF 180mW 10pF 190mW 20pF 235mW 50pF _535mW

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SIMULATIONS

4.2.2 Difference Amplifier using THS3001 with Transmission Lines

Fig. 4.12 shows THS3001 in a difference amplifier configuration connected to transmission lines. The transmission lines used are presented in chapter 4.1.

Fig. 4.12 Difference amplifier in the data transmission channel

Even though the ratio of the feedback resistors (Rf/Rg) is 12 (i.e., the gain) and the

differential input toggles between 0 and 1V the output voltage of the amplifier does not have a swing of 0-12V, Fig. 4.13. The gain of the system is reduced due to currents flowing in the feedback resistors.

Vout Z0=50 Ω l=0.5 m Rs=50 Ω Rf1=1.5 kΩ CL=10 pF Vb=0 V RL=20 Ω Vdiff THS3001 RT2=50Ω Rs=50 Ω Rg1=125Ω RT1=50 Ω Vb=0 V Driver Line Vb=0 V Vcm Rf2=1.5kΩ Rg2=125Ω + _ Vref=6V

(56)

SIMULATIONS

The currents flowing through RF1 and RF2 is illustrated in Fig 4.14, where the current

fed back from the output is the solid line and the current from the reference voltage is the dashed line. The currents are not symmetrical since different voltages are across the feedback resistors. The voltage across RF1 is determined by Vout-Vin and the

voltage across RF2 is equal to Vref-Vin, where Vin is the input voltage at the

non-inverting port of the Op-amp.

Fig. 4.14 The current flowing trough Rg1 (dashed line) and Rg2 in the difference

amplifier in the data transmission channel

A current fed back may not be crucial to the application, but the non-symmetry will causes problems for the differential input signal. Fig. 4.15 shows the differential input signals to the amplifier and it can be seen they are not each other’s inverse. The non-symmetry of the input voltage is due to the non-non-symmetry in the currents flowing in the terminating resistors (RT).

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SIMULATIONS

4.2.3 Triple-Op-amp Instrumentation Amplifier

It was shown in the previous chapter that a single Op-amp in a difference amplifier configuration cannot be used in the data transmission system. The input signals get corrupted due to currents flowing through the feedback resistors. Hence, an input stage is needed to isolate the feedback net from the transmission lines. In an IA the inputs are isolated from the feedback net.

The triple-Op-amp IA in Fig. 4.16 consists of three THS3001 Op-amps. The IA has a total gain of 12. The gain is divided into the first and second stage where the first stage has a gain of 3 and the second of 4. The amplifier was simulated with the inputs connected to the transmission line presented in chapter 4.1.

Fig. 4.16 Triple-Op-amp IA using THS3001

The rise time of the triple-Op-amp IA configuration in Fig 4.17 is 3.8ns and the fall time is 4.2ns and is shown in Fig 4.17. Changing the size of the feedback resistors alter the slew rate. The IA has a –3dB frequency of 83MHz.

Vout Rf Ri R3 Rg R3 Rf Ri Vin+ V in-Op1 Op3 Op2 Vref Rload Cload

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SIMULATIONS

The power consumption at full swing is shown in Fig. 4.18 and the average consumption is 300mW.

Fig. 4.18 The power consumption the triple-Op-amp at full swing

The steady state power consumption of the triple-Op-amp IA varies between 230 and 260mW and is shown in Fig. 4.19.

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SIMULATIONS

4.2.4 Dual-Op-amp Instrumentation Amplifier

A dual-Op-amp IA is shown in Fig. 4.20. The setup was simulated using two THS3001 Op-amps and its inputs connected to the transmission line in chapter 4.1.

Fig. 4.20 Dual-Op-amp IA using THS3001

With the setup in Fig 4.20 the rise and fall time are both 4.3ns. The –3dB frequency of the configuration is 90MHz. The input and output signals of the dual-Op-amp IA are shown in Fig. 4.21. R4=11kΩ R2=1.5kΩ Op2 R1=136Ω Op1 R3=1kΩ V in-Vin+ Vout Cload=10pF RLoad=20Ω Vref=6V

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SIMULATIONS

The non-inverting (dashed) and inverting (solid) input voltages of Op2 in Fig. 4.20 are

shown in Fig. 4.22. The inverting input is delayed 2.5ns due to the propagation delay in Op1.

Fig. 4.22 The delay between the inputs of Op2 in the dual-Op-amp IA

The CMRR versus the frequency is shown in Fig. 4.23. The CMRR is poor for high frequencies due to the delay in Fig. 4.22

Implementing a receiver in a fast data transfer system : A feasibility study

Examensarbete

LITH-ITN-ED-EX--03/017--SE

Implementing a receiver in

a fast data transfer system

-

A feasibility study

Filip Hall

Pär Håkansson

LITH-ITN-ED-EX--03/017--SE

Implementing a receiver in

a fast data transfer system

-

A feasibility study

Examensarbete utfört i Elektronikdesign

vid Linköpings Tekniska Högskola, Campus

Norrköping

Filip Hall

Pär Håkansson

Handledare: Adriana Serban

Examinator: Shaofang Gong

-

Abstract

Preface

Table of contents

List of Figures

Abbreviation

1 Introduction

1.1 Background

1.2 Task

1.3 Purpose

1.4 Method

1.5 Report Outline

2 System Overview and Problem Description

2.1 System overview

2.1.1 Input and Output Signals

2.2 Amplifier Requirements

2.2.1 Bandwidth

2.2.2 Slew Rate

2.2.3 Common Mode Rejection

2.2.4 Power Consumption

2.2.5 Amplifier Specifications

3 Amplifier Architectures

3.1 Operational Transconductance Amplifier

S

S

A

S

(

)

3.2 Voltage-Feedback and Current-Feedback Op-amp

3.2.1 Voltage-Feedback Vs Current-Feedback Op-amps

3.2.2 The Current Feedback Op-amp

3.2.3 A CMOS Current Feedback Amplifier

C

S

B

C

F

O

-

3.3 Differential Amplifiers

3.3.1 Op-amp in a Difference Amplifier Configuration

3.3.2 Instrumentation Amplifiers

T

-O

-

IA

(

)

(

)

D

-O

-A

IA

(

)

3.3.3 Op-amp with Differential to Single Input Stage

D