IN
DEGREE PROJECT
ELECTRICAL ENGINEERING,
SECOND CYCLE, 30 CREDITS
,
STOCKHOLM SWEDEN 2020
Modelling & Design of a Prototype
DC/DC Converter for Trip Coil
Applications
GEORGIOS APOSTOLOU
Modelling & Design of a Prototype DC/DC
Converter for Trip Coil Applications
Georgios Apostolou
School of Electrical Engineering and Computer Science
KTH, Royal Institute of Technology
Stockholm, Sweden
Head Supervisor (KTH): Staffan Norrga
Daily Supervisor (Megger): Pari Ibrahim
Examiner: Staffan Norrga
Abstract
High voltage circuit breaker testing is a major part in substation test industry. The minimum trip voltage test is one of the standard circuit breaker tests performed. In this master thesis, a prototype switch-mode DC/DC power supply with digital control has been designed and implemented on behalf of Megger Sweden AB targeting at assessing developing a battery-powered product dedicated to perform the minimum trip voltage test. The report consists of several parts.
In the first part, the theoretical background on modelling switch-mode power converters in continuous and discrete domain is presented. Then, the presented modelling recipe is followed to model a syn-chronous four-switch double-mode DC/DC converter, which can operate either in buck or buck-boost mode. Given the preliminary specifications, the power components are dimensioned using an analytical approach. Digital voltage mode control is implemented for each mode. The whole system is modelled in Matlab/Simulink and its operation is verified by means of simulations.
The modelled power converter is implemented as prototype. The power components are selected as a result of the dimensioning analysis. The digital control loop is implemented using a Texas Instruments C2000 micro-controller. Lab measurements are obtained for six different test cases and they are compared with the corresponding simulation results. The obtained measurement data depict close match to the simulated expected values, which verifies the modelling stage.
Finally, discussion is hold on how layout and hardware issues have compromised the prototype design specifications. Moreover, concrete hardware changes are proposed that will enable improvements in the next prototype version.
Sammanfattning
Test av högspänningsbrytare är en viktig del vid testning av ställverk. Ett standardtest vid brytarprovning är minsta utlösningsspänning. I detta examensarbete har ett switchat DC/DC-kraftaggregat konstrue-rats och implementekonstrue-rats med digital styrning på uppdrag av Megger Sweden AB. Syftet är att utröna möjligheten att utveckla en batterimatad produkt avsedd att utföra test av minsta utlösningsspänning. Rapporten består av olika delar.
I första delen presenteras den teoretiska bakgrunden för modellering av switchade kraftaggregat både i kontinuerlig och diskret tid. Sedan används det presenterade modelleringskonceptet för att modellera en synkron fyra-switch dubbel-mod DC/DC-omvandlare, som kan antingen fungera i buck- eller buck-boost-mod. Givet de preliminära specifikationerna dimensionerades kraftkomponenterna genom ett analytiskt tillvägagångssätt. Digital spänningsstyrning implementeras för varje driftsmod. Hela systemet modelleras i Matlab/Simulink och dess drift verifieras genom simuleringar.
Det modellerade kraftaggregatet implementeras som prototyp. Kraftkomponenter väljs med utgångspunkt från dimensioneringsanalysen. Digital styrning realiseras med hjälp av en Texas Instruments C2000-mikroprocessor.
Laboratoriemätningar görs för sex olika driftfall och jämförs med motsvarande simuleringsresultat. Mät-ningarna stämmer väl överens med de förväntade simuleringsvärdena, vilket verifierar modellen. Avslut-ningsvis, förs en diskussion angående komponentplacering och hur hårdvaruproblem har försvårat upp-fyllelse av de preliminärt ställda kraven. Vidare, föreslås konkreta förändringar för att förbättra nästa prototyp.
Acknowledgements
While reaching the end of this journey, I wish to thank those ones who have contributed to this thesis project, though keeping myself solely responsible for the contents of this report.
Starting from KTH, I would like to thank my head supervisor and examiner Staffan Norrga, for his support and motivation, as well as for granting me the chance to complete my studies at KTH with a thesis in the field of power electronics.
Furthermore, I would like to thank Megger Sweden AB for giving me the opportunity to conduct my thesis project within their team. Primarily, I would like to thank Pari Ibrahim for accepting the role of my supervisor, as well as my colleague Takeshi for his comments on my final report. I would also like to express my gratitude to my friend, colleague and mentor in power electronics Zoran for the endless inspiration and his invaluable input at every stage of the project.
From the close ones, allow me to thank my family for believing in me and supporting me by all means. Next, let me thank my friends Panos and Anastasia for our inspirational discussions. Closing, I do want to thank my partner Vasiliki for her love and encouragement.
Abbreviations
AC Alternating current
ADC Analog-to-digital converter DAC Digital-to-analog converter
DC Direct current
DPWM Digital pulse-width-modulator ESR Equivalent series resistance IGBT Insulated-gate bipolar transistor JTAG Joint test action group
MCU Micro-controller unit
MOSFET Metal–oxide–semiconductor field-effect transistor PCB Print circuit board
PWM Pulse-width-modulator
CONTENTS
Contents
Abstract i Acknowledgements iii Abbreviations iv List of Figures viList of Tables vii
1 Introduction 1 1.1 Background . . . 1 1.2 Thesis objectives . . . 1 1.3 Approach . . . 2 1.4 Limitations . . . 3 1.5 Thesis outline . . . 3
2 Continuous modelling of DC/DC converters 4 2.1 Introduction . . . 4
2.2 Modelling principles . . . 5
2.3 Steady-state analysis . . . 7
2.4 State-space averaging and small-signal modelling . . . 12
3 Discrete modelling and control of DC/DC converters 17 3.1 Introduction . . . 17
3.2 Discrete small-signal modelling . . . 17
3.3 Digital compensator . . . 20
4 Design and implementation of the prototype converter 23 4.1 Preliminary design specifications . . . 23
4.2 Dimensioning of the power components . . . 25
4.2.1 Power inductor . . . 25
4.2.2 Output capacitor . . . 27
LIST OF FIGURES
4.3 Tuning and implementation of the controller . . . 32
4.4 Simulation and measurement results . . . 36
5 Conclusions and discussion of issues 44 5.1 General conclusions . . . 44 5.2 Design issues . . . 44 5.3 Technical issues . . . 44 5.4 Future Work . . . 45 References 46 A Appendix 47 A.1 Matlab script - "MyConverterModelling.m" . . . 47
A.2 Matlab function - "conv_models.m" . . . 48
A.3 Matlab script - "MyConverterSimulink.m" . . . 52
A.4 Simulink function block - "Gc" . . . 52
List of Figures
1 Typical setup of minimum trip voltage test. . . 22 Structure of a DC/DC switch-mode power supply. . . 4
3 PWM scheme. . . 4
4 Modulation waveforms. . . 5
5 Inductor volt-second balance. . . 6
6 Capacitor charge balance. . . 6
7 Synchronous buck converter. . . 7
8 Equivalent of synchronous buck converter during state 1. . . 8
9 Equivalent of synchronous buck converter during state 0. . . 8
10 Equivalent for small-ripple approximation in synchronous buck converter at state 1. . . . 9
11 Equivalent for small-ripple approximation in synchronous buck converter at state 0. . . . 9
12 Synchronous non-inverted buck-boost converter. . . 10
13 Equivalent of synchronous buck-boost converter during state 1. . . 11
14 Equivalent of synchronous buck-boost converter during state 0. . . 11
LIST OF TABLES
16 Discrete small-signal modeling for trailing-edge modulation and Ts≤ td< (1 + D) Ts. . . 19
17 Block diagram representation for z-domain voltage-mode control. . . 21
18 Voltage-mode control including feedback dynamics in G0uvoz(z). . . 21
19 Application schematic of the power converter. . . 24
20 Scaling sequence in the digital control loop. . . 35
21 Simulink model of the prototype converter. . . 37
22 Testing the prototype board on the lab bench. . . 37
23 Simulation buck, Vi = 24V , Vo= 10V , RL= 1.8Ω. . . 38 24 Measurement buck, Vi= 24V , Vo= 10V , RL= 1.8Ω. . . 38 25 Simulation buck, Vi = 100V , Vo= 50V , RL= 7.2Ω. . . 39 26 Measurement buck, Vi= 100V , Vo= 50V , RL= 7.2Ω. . . 39 27 Simulation buck, Vi = 250V , Vo= 100V , RL= 13.5Ω. . . 40 28 Measurement buck, Vi= 250V , Vo= 100V , RL= 13.5Ω. . . 40 29 Simulation buck-boost, Vi= 24V , Vo= 28V , RL= 7.5Ω. . . 41 30 Measurement buck-boost, Vi= 24V , Vo= 28V , RL= 7.5Ω. . . 41 31 Simulation buck-boost, Vi= 100V , Vo= 120V , RL= 50Ω. . . 42 32 Measurement buck-boost, Vi= 100V , Vo= 120V , RL= 50Ω. . . 42 33 Simulation buck-boost, Vi= 250V , Vo= 300V , RL= 200Ω. . . 43 34 Measurement buck-boost, Vi= 250V , Vo= 300V , RL= 200Ω. . . 43
List of Tables
1 Preliminary specifications of the prototype converter. . . 232 Operation modes of the prototype converter. . . 24
3 Design specifications for the power inductor. . . 26
4 Design specifications for the power inductor. . . 27
5 Design specifications for the output capacitor. . . 28
6 Specifications for the selected output capacitor. . . 29
7 Specifications for the MOSFET parts. . . 31
8 Specifications for the selected MOSFET part. . . 32
9 Values of the controller coefficients for different operation cases. . . 36
LIST OF TABLES
1
Introduction
1.1
Background
In modern electric power systems the circuit breakers are components of critical importance, since they are used to ensure the safe and reliable operation of the network. During normal operation the breakers allow the current flow presenting very low conducting resistance. On the other hand, in a fault case they have to operate under highly accurate margins and in some cases after long periods of inactivity in order to effectively interrupt the current flow and protect expensive equipment like transformers.
There are several reasons for testing circuit breakers and among the most important ones are [1] • to ensure that costly equipment is protected
• to prevent power outages in the power network • to ensure reliable power delivery
• to verify the proper operation of the breaker according to its specifications
Circuit breaker testing in substations involves performing a number of different recommended tests and among those is the minimum pick-up measurement [2, 3]. The minimum pick-up is described both in international and national standards such as IEC 62271-100, ANSI C37.09 etc. The purpose of performing the minimum pick-up measurement is to determine the minimum voltage for which the command coil latches and the circuit breaker is operated. The command coil can be either "open" or "close" and both of them must be tested independently. It should be noted that the timing parameters of the contact are not of interest in this type of test.
Circuit breaker trip coils are typically powered by batteries located in the substation and they are specified to latch at much lower voltage than the nominal voltage of the battery. The purpose of this test is therefore to ascertain that the breaker coils trip at the minimum specified voltage. Divergence in the tripping voltage level may depict sluggish operation of the protective mechanisms which shall need to be addressed by means of maintenance.
The testing procedure is rather simple. Short pulses of incremental DC voltage are applied to the trip coil varying from 20% up to 120% of the battery’s nominal voltage. The test is completed either when the coil trips or when the test voltage reaches 120% of the battery’s nominal voltage. The measurements are obtained and then it is assessed whether or not further actions are needed to be addressed.
It is evident that in order to conduct this test the minimum equipment needed is a power source (battery) and a voltage regulator (power converter) which shall yield variable DC voltage pulses as output. During each pulse the DC voltage output shall be kept within specified margins (output voltage ripple). A typical test setup is illustrated in fig. 1, including a DC power source or battery, a DC/DC power converter dedicated to regulate the DC voltage, a switch analyser and the command coils which are parts of the high voltage circuit breaker.
Most commonly, the product alternatives which can perform the minimum pick-up test include a module or function in physically heavier instruments powered by mains (AC), which perform a wider range of circuit breaker tests. The case study being conducted in this thesis aims at investigating the concept of designing a lighter, portable, battery-powered product to perform the minimum pick-up measurement. The presumed future product will be placed in the market as an alternative (back-up) test instrument in the cases when mains is not available in the substation.
1.2
Thesis objectives
The project can be considered as a prestudy conducted on behalf of Megger Sweden AB company. The desire of the company was to build a prototype wide voltage range DC/DC non-isolated power
1.3 Approach DC/DC Power Converter Input Disconnectors DC Power Source or Battery Switch Analyser High Voltage Circuit Breaker open coil close coil + + + − + −
Figure 1: Typical setup of minimum trip voltage test.
supply, which could be used for the purpose of developing a product at a later stage, solely dedicated for performing the minimum pick-up measurement. Furthermore, Megger have expressed their interest in having a solution based on digital control implementation if applicable, in order for them to explore and evaluate the application possibilities and limitations which yield with the transition from analog to digital control implementation.
Based on this, the primary aim of the project is to design, implement in hardware and deliver a functional prototype DC/DC converter, which shall establish the base for developing a product as aforementioned. In addition, since the project consists of numerous multidisciplinary tasks to be executed and given the tight time horizon of the thesis, it is unavoidably expected that there shall be imperfections, omissions and mistakes, which can eventually compromise the initial design specifications set. For this reason, one further goal set is to actually identify those problems, explain their origins and propose effective solutions in order to overcome them in the next prototype version.
1.3
Approach
Hardware development is often a procedure which does not evolve linearly. As far as this project is concerned, initial models and specifications had to be modified after the prototype board was designed, in order to meet the first goal of delivering a functional converter. Therefore, the system specifications presented in this report is a result of iterations and adjustments on the initial design specifications. The tasks executed during the thesis period were highly extensive and therefore, many aspects are omitted in this report. Briefly, the actual development procedure could be described by the following stages:
• Theoretical and practical comparative investigation between different converter topologies, such that proper topology is selected for our application.
• Investigation of whether it would be feasible and beneficial to implement digital control instead of analog or hybrid.
• Determination of the controller type to be used for the main converter and model verification using Matlab/Simulink.
• Dimensioning of the power components and design of magnetics.
• Hardware design of the auxiliary power supplies (housekeeping), analog (gate drivers, signal mea-surement, fault protection) and digital (micro-controller, logic, serial communication) circuitry. • Schematic and layout design of the prototype board.
• Hardware debugging and verification for each functional block separately. • Programming of the micro-controller firmware (digital controller, user interface). • Processor-in-Loop (PiL) testing using commercial software.
1.4 Limitations
1.4
Limitations
The most important limitations encountered are mentioned below.
1. The time itself was the most critical limitation as multiple tasks had to be executed in sequence, until the first prototype boards were ready to order. Considering also an average lead time of 4-6 weeks for delivering of the prototype boards, it is easily perceivable that it takes much time to perform layout corrections or changes. Hence, some critical problems and omissions which were present in board level they had to be addressed with temporary solutions (patching of components) wherever it was possible.
2. The author’s lack of experience in hardware design at the time of the project was also an impor-tant limitation to admit. Realizing a model in hardware involves much and wide knowledge and experience. Compromising functionality, especially in the first prototypes is almost unavoidable for an inexperienced hardware designer.
3. Lastly, certain limitations were imposed by the instrumentation availability at the time of the project. As it was difficult to include measurements from different industrial tripping coils, we have used resistive loads instead, which were available in the lab. Moreover, the lab power supply which emulates our battery source in the conducted lab tests it has a lower maximum output power than the one we specify in our application and therefore, we were not able to test for maximum power. Finally, we did not have access to a frequency response analyzer, in order to be able to verify our loop response in frequency domain. Instead, the system verification is implemented by obtaining a close match between time simulations and measured waveforms in the lab.
1.5
Thesis outline
The thesis report includes the following chapters.
• Chapter 1 - Introduction.
• Chapter 2 - Continuous modelling of DC/DC converters.
• Chapter 3 - Discrete modelling and control of DC/DC converters. • Chapter 4 - Design and implementation of the prototype converter. • Chapter 5 - Conclusions and discussion of issues.
2
Continuous modelling of DC/DC converters
2.1
Introduction
Switch-mode power converters are electronic devices which perform power conversion of DC/DC, AC/DC and DC/AC. There are various PWM topologies of DC/DC power converters, extensively studied and described in the literature [4–8]. In this chapter we will present certain concepts and principles which shall enable the reader to follow our analysis in modelling and implementing our prototype DC/DC converter. The structure of a DC/DC switch-mode power supply is the same regardless of the topology. An input power source (input voltage vi(t)) feeds an electronic circuit, which switches between two topological states 0 and 1 and eventually converts the input voltage to a different level, feeding the load connected at the output (fig. 2). Assuming that the switching frequency is constant Ts, a control signal uc(t) is compared to a modulating signal um(t) which yields the driver signal c(t) (fig. 3). For "trailing edge modulation" with Um to be the peak of the modulation signal the respective waveforms are depicted in fig. 4. The duty cycle d(t) determines the ratio between the time the converter operates in state 1 and the switching period. This could be expressed as
d(t) = t1 Ts
= uc(t) Um
, (1)
where t1 is the time the system remains in state 1. For constant duty cycle d(t) = D, the time interval at state 1 yields t1= DTs(fig. 4).
0 1 − + vi(t) Load + − vo(t) c(t)
Figure 2: Structure of a DC/DC switch-mode power supply.
− + uc(t) um(t) c(t) Figure 3: PWM scheme.
The switch-mode operation results in generating waveforms of currents and voltages which have harmonic components at the switching frequency fs = 1/Ts and higher. From an analytical perspective, when designing a control system for a switch-mode converter we are typically interested in frequencies lower than fs/5. For this reason, it is quite useful to work with signal averaging at the switching period. For a given signal u(t) we denote as hu(t)iT
s the moving average of the signal for a time interval Ts. This is formulated as hu(t)iT s= 1 Ts Z t+Ts/2 t−Ts/2 u(t)dt. (2)
The moving average method acts as a low pass filter for the signals, which means that the high frequency components are filtered out and therefore, the analysis becomes significantly simpler when the frequencies of interest are lower than the switching frequency.
2.2 Modelling principles Um t1 Ts uc(t) um(t) c(t)
Figure 4: Modulation waveforms.
2.2
Modelling principles
Our analysis shall repeatedly refer to the concepts of small-ripple approximation in combination with the inductor volt-second balance and the capacitor charge balance. Hence, in this paragraph we shall give a brief insight on these concepts [4].
The small-ripple approximation is a quite straightforward concept, which aims at reducing the complexity of our models. Without loss of generality, for a given signal usig(t) in time domain we can express it as follows:
usig(t) = Usig+ usig,r(t), (3)
where Vsig corresponds to the DC frequency component of the signal and usig,r(t) denotes the rest of the frequencies or AC ripple. On the condition that
usig,r(t) Usig << 1, (4)
we can disregard the AC ripple and write
usig(t) ≈ Usig. (5)
We can then consider an inductor switching with constant switching period Tsand duty cycle D, between states 0 and 1, applying voltages v0(t) and v1(t) respectively (fig. 5). Then the inductor voltage vL(t) is expressed in relation to its current iL(t) as follows:
vL(t) = L diL
dt. (6)
By integrating both sides of the equation for one switching period it yields
LiL(Ts) − iL(0) = Z Ts 0 vL(t)dt = Z DTs 0 v1(t)dt + Z Ts DTs v0(t)dt. (7)
2.2 Modelling principles 0 1 − + v1(t) v0(t) −+ + − vL(t) iL(t) L
Figure 5: Inductor volt-second balance.
0 1 0 1 i1(t) i0(t) + − vC(t) iC(t) C
Figure 6: Capacitor charge balance.
The new expression states that the net flux change is proportional to the integral of voltage applied to the inductor during one switching period. This also means that under steady-state the net flux change remains constant, which in turn can be expressed as
Z Ts 0 vL(t)dt = 0 ⇒ Z DTs 0 v1(t)dt = − Z Ts DTs v0(t)dt. (8)
The principle of volt-second balance is based on eq. (8) and it describes the condition for steady-state operation of the switching converter. At this point, we can explain the link to the small-ripple approxi-mation. By invoking the small-ripple approximation method for v1(t) and v0(t), it yields that v1(t) = V1 and v0(t) = V0and in combination to eq. (8) the steady-state condition is expressed by
V1D = −V0(1 − D). (9)
Recalling eq. (2) we can express the steady-state inductor volt-second balance as follows:
hvL(t)iTs = 0. (10)
In a respective manner, we assume a capacitor switching between states 0 and 1, with switching period Ts, duty cycle D, under currents i0(t) and i1(t) (fig. 6). The equation linking the voltage vC(t) and the current iC(t) of the capacitor is given by
iC(t) = C dvC
dt . (11)
Integration of the equation for one switching period yields
CvC(Ts) − vC(0) = Z Ts 0 iC(t)dt = Z DTs 0 i1(t)dt + Z Ts DTs i0(t)dt. (12)
2.3 Steady-state analysis
The last expression illustrates that the charge change of the capacitor in one period is proportional to the current applied and therefore, the charge balance principle refers to the second steady-state condition obtained by Z Ts 0 iC(t)dt = 0 ⇒ Z DTs 0 i1(t)dt = − Z Ts DTs i0(t)dt. (13)
The last expression for small ripple i.e. for i1(t) = I1 and i0(t) = I0 simplifies the steady-state condition as follows:
I1D = −I0(1 − D). (14)
Additionally, direct consequence of the capacitor charge balance in steady-state is that
hiC(t)iTs= 0. (15)
2.3
Steady-state analysis
In this paragraph we will begin by modelling different DC/DC converter topologies at steady-state opera-tion. The topologies to be discussed are the synchronous buck converter and the synchronous non-inverted buck-boost converter. Those topologies have been implemented in our prototype design and therefore, they are explicitly chosen to be analysed and presented. Notably, the methodology to be followed is presented such that it can globally be applied for different topologies.
A synchronous buck converter is a DC/DC converter used to step-down the input voltage while allowing bidirectional power flow. It is composed of two semiconductor devices T1, T2 operated as switches, a power inductor L, an output capacitor C and the load RL connected at the output stage. In fig. 7 a synchronous buck converter is illustrated, with vi(t) and vo(t) to be the input and output voltage, io(t) the output current, vL(t), iL(t) represents the inductor’s voltage and current, while vC(t), iC(t) is the capacitor voltage and current. For a switching period Tsand duty cycle d(t) = D, we call state 1 when T1 is ON, whereas during state 0 T2is ON instead. We will furthermore assume that each of the switches T1, T2have a conduction resistance ron and the inductor’s internal resistance is rL. Finally, we also assume that the capacitor is not ideal and that it has a series equivalent resistance resr. Based on these, we can derive the equivalent circuits for states 1 and 0 in figs. 8 and 9.
− + vi(t) + − vL(t) iL(t) iC(t) + −vC(t) io(t) + − vo(t) L T1 T2 C RL rL resr
Figure 7: Synchronous buck converter. For state 1 the following equations apply:
2.3 Steady-state analysis − + vi(t) + − vL(t) iL(t) iC(t) + −vC(t) io(t) + − vo(t) L C RL rL resr ron
Figure 8: Equivalent of synchronous buck converter during state 1.
+ − vL(t) iL(t) iC(t) + −vC(t) io(t) + − vo(t) L C RL rL resr ron
Figure 9: Equivalent of synchronous buck converter during state 0.
vL(t) = L diL(t) dt = vi(t) − vC(t) − resriC(t) − (ron+ rL)iL(t), iC(t) = C dvC(t) dt = iL(t) − io(t) = iL(t) − vC(t) + resriC(t) RL , (16)
whereas for state 0 it yields
vL(t) = L diL(t) dt = −vC(t) − resriC(t) − (ron+ rL)iL(t), iC(t) = C dvC(t) dt = iL(t) − io(t) = iL(t) − vC(t) + resriC(t) RL , (17)
In order to define the steady state ratio M (D) between the output and the input voltage, we first need to invoke the small-ripple approximation for the inductor current and the voltage of the output capacitor, such that iL(t) = IL, vC(t) = VC. It is furthermore given that the input voltage is constant with vi(t) = Vi. Application of the small-ripple approximation from a physical perspective means that for each topological state the capacitor voltage is modelled as voltage source and the inductor current as current source (figs. 10 and 11). Moreover, the derivation of the output voltage vo(t) in each state yields by applying the superposition theorems for the two independent sources IL and VC. Therefore, when referring to the steady-state output voltage we actually mean the averaged value of vo(t), i.e., Vo= hvo(t)iTs.
2.3 Steady-state analysis − + Vi + − vL(t) iC(t) − + V C io(t) + − vo(t) IL RL rL resr ron
Figure 10: Equivalent for small-ripple approximation in synchronous buck converter at state 1.
+ − vL(t) iC(t) − + VC io(t) + − vo(t) IL RL rL resr ron
Figure 11: Equivalent for small-ripple approximation in synchronous buck converter at state 0.
vL(t) = Vi− VC− resriC(t) − (ron+ rL)IL, iC(t) = − 1 RL+ resr VC+ RL RL+ resr IL, vo(t) = RL RL+ resr VC+ resrRL RL+ resr IL. (18)
Re-expressing eq. (17) in a respective manner it yields for state 0 as follows:
vL(t) = −VC− resriC(t) − (ron+ rL)IL, iC(t) = − 1 RL+ resr VC+ RL RL+ resr IL, vo(t) = RL RL+ resr VC+ RLresr RL+ resr IL. (19)
Subsequently, we apply the inductor volt-second balance and capacitor charge balance for steady-state by combining eqs. (18) and (19) as follows:
2.3 Steady-state analysis hvL(t)iTs = ViD − RL RL+ resr VC− ron+ rL+ resrRL RL+ resr ! IL= 0, hiC(t)iTs = − 1 RL+ resr VC+ RL RL+ resr IL= 0. hvo(t)iTs = Vo= RL RL+ resr VC+ RLresr RL+ resr IL. (20)
Therefore, by combining the expressions in eq. (20) it yields
ViD − Vo 1 +
ron+ rL RL
!
= 0. (21)
Finally, we can derive the steady state output-to-input voltage ratio for the synchronous buck converter as M (D) = Vo Vi = D 1 +ron+ rL RL . (22)
For a lossless buck converter i.e., ron, rL, resr= 0 the output-to-input voltage ratio is given by
M (D) = Vo Vi
= D. (23)
Next topology to discuss is the synchronous non-inverted buck-boost DC/DC converter, which is im-plemented by using four switches instead of two. As the name of the topology declares, a non-inverted buck-boost converter can both step-up and step-down the input voltage and at the same time it supports bidirectional power flow which is an attribute of the synchronous operation. Taking a look at the arrange-ment of the power components (fig. 12), it can be observed that a non-inverted buck-boost converter is actually a cascade combination of a buck converter in series with a boost converter (not covered in our analysis), sharing the same inductor.
During state 1 switches T1 and T3 are turned ON together while T2, T4 are OFF. In state 0, T1 and T3 are turned OFF and T2, T4 are ON. For the same switching period Tsand duty cycle d(t) = D, we can again derive the equivalent circuits for states 1 and 0 (figs. 13 and 14).
− + vi(t) iL(t) iC(t) io(t) + − vo(t) + − vC(t) + − vL(t) L T1 T2 T4 T3 C RL rL resr
2.3 Steady-state analysis − + vi(t) iL(t) + − vL(t) iC(t) io(t) + − vo(t) + − vC(t) L C RL rL ron resr ron
Figure 13: Equivalent of synchronous buck-boost converter during state 1.
iL(t) + − vL(t) iC(t) io(t) + − vo(t) + − vC(t) L C RL rL ron resr ron
Figure 14: Equivalent of synchronous buck-boost converter during state 0.
At state 1, we can derive the following expressions for the inductor voltage and the capacitor current:
vL(t) = vi(t) − (rL+ 2 · ron) iL(t), iC(t) = − vo(t) RL . (24)
The respective equations for state 0 yield,
vL(t) = −vo(t) − (2 · ron+ rL) iL(t), iC(t) = iL(t) − vo(t) RL . (25)
Using the small-signal approximation and following the same assumptions as in buck case we have for state 1: vL(t) = Vi− (rL+ 2 · ron) IL, iC(t) = − vo(t) RL , vo(t) = RL RL+ resr VC, (26)
2.4 State-space averaging and small-signal modelling vL(t) = −vo(t) − (2 · ron+ rL) IL, iC(t) = − 1 RL+ resr VC+ RL RL+ resr IL, vo(t) = RL RL+ resr VC+ RLresr RL+ resr IL. (27)
Invoking again the inductor volt-second balance and capacitor charge balance on equations eqs. (26) and (27) for steady-state operation we have that
hvL(t)iTs = ViD − RL(1 − D) RL+ resr V − 2 · ron+ rL+ RLresr(1 − D) RL+ resr ! IL= 0, hiC(t)iTs = − 1 RL+ resr VC+ RL RL+ resr IL(1 − D) = 0, hvo(t)iTs = V = RL RL+ resr VC+ RLresr RL+ resr (1 − D) IL. (28)
Replacement between the variables in eq. (28) yields the output to input voltage ratio as follows:
M (D) = Vo Vi = D 1 − D RL RL+ resr +2 · ron+ rL RL(1 − D) , (29)
and the ideal output-to-input voltage ratio disregarding the losses is derived by the expression below:
M (D) = Vo Vi
= D
1 − D. (30)
2.4
State-space averaging and small-signal modelling
A quite effective way to model the converters for small-signal analysis is to make use of the state-space averaging method [9]. State-space modelling is a generalized mathematical tool, which is proven very powerful in our field of interest. In particular, as far as power converter modelling is concerned, making use of state-space equations enables us to perform for our system equilibrium state analysis, small-signal analysis and what is more, large-signal analysis for frequencies lower than the switching frequency. So far we have defined what is signal averaging for systems switching between two topological states and moreover, for each converter we have derived the equivalent circuits which correspond to state 1 and 0. The initial aim is to derive a model of system for each topological state (k ∈ 0, 1) such that we formulate it in the following standard form:
dx dt = Akx + Bku, y = Ekx + Fku, (31) where x =iL(t) vC(t) T
is the chosen state vector, u = vi(t) is the input voltage. The output vector composed in our case of the inductor current and the output voltage variables i.e. y =iL(t) vo(t)
T .
2.4 State-space averaging and small-signal modelling
In section 2.3, we have analysed two different topologies of power converters quite extensively and we have written the corresponding equations for their topological states. Hence, we just need to recall those expressions and reformulate them in order to fit the standard form described in eq. (31). Small-ripple approximation is applied as described for the inductor current and the capacitor voltage in every case. For the synchronous buck converter and for state 1 we can write eq. (18) as follows:
diL dt = − 1 L ron+ rL+ RLresr RL+ resr ! iL(t) − 1 L RL RL+ resr ! vC(t) + vi L, dvC dt = 1 C RL RL+ resr ! iL(t) − 1 C 1 RL+ resr ! vC(t), vo(t) = RLresr RL+ resr iL(t) + RL RL+ resr vC(t). (32)
For state 0 we recall eq. (19), which yields
diL dt = − 1 L ron+ rL+ RLresr RL+ resr ! iL(t) − 1 L RL RL+ resr ! vC(t), dvC dt = 1 C RL RL+ resr ! iL(t) − 1 C 1 RL+ resr ! vC(t), vo(t) = RLresr RL+ resr iL(t) + RL RL+ resr vC(t). (33)
Subsequently, the state matrices are obtained by the following expressions:
A1= A0= −1 L ron+ rL+ resrRL resr+ RL ! −1 L RL resr+ RL ! 1 C RL RL+ resr ! −1 C 1 RL+ resr ! , (34) B1= 1 L 0 , B0= 0, (35) E1= E0= 1 0 resrRL RL+ resr RL RL+ resr , (36) F1= F0= 0. (37)
Moving to the synchronous buck-boost converter, from eq. (26) we formulate the expressions for state 1 as follows:
2.4 State-space averaging and small-signal modelling diL dt = − 1 L(rL+ 2 · ron) iL(t) + vi L, dvC dt = − 1 C 1 RL+ resr ! vC(t), vo(t) = RL RL+ resr vC(t). (38)
For state 0, we have from eq. (27):
diL dt = − 1 L rL+ 2 · ron+ RLresr RL+ resr ! iL(t) − 1 L RL RL+ resr ! vC(t), dvC dt = 1 C RL RL+ resr ! iL(t) − 1 C 1 RL+ resr ! vC(t), vo(t) = RLresr RL+ resr iL(t) + RL RL+ resr vC(t). (39)
The state matrices are respectively derived below:
A1= −1 L(rL+ 2 · ron) 0 0 −1 C 1 RL+ resr ! , A0= −1 L rL+ 2 · ron+ RLresr RL+ resr ! −1 L RL RL+ resr ! 1 C RL RL+ resr ! −1 C 1 RL+ resr ! , (40) B1= 1 L 0 , B0= 0, (41) E1= 1 0 0 RL RL+ resr , E0= 1 0 resrRL RL+ resr RL RL+ resr , (42) F1= F0= 0. (43)
Having modelled our converters according to the state-space approach for each topological state, we can derive the corresponding averaged matrices for a constant duty cycle d(t) = D, as follows:
2.4 State-space averaging and small-signal modelling A = A1D + A0(1 − D) , B = B1D + B0(1 − D) , E = E1D + E0(1 − D) , F = F1D + F0(1 − D) . (44)
Since we have assumed constant duty cycle, this means that the system operates in equilibrium. Therefore, we can calculate its steady-state operation point by solving for the averaged equations,
dX
dt = AX + BVi= 0, Y = EX + F Vi,
(45)
with X to be the equilibrium vector state and Y is the steady-state output vector. From eq. (45) the solution for the corresponding vectors yields
X = −A−1BVi,
Y =−EA−1B + FVi.
(46)
We can observe the we reach the same results for the steady-state output to input voltage ratio as in section 2.3 by calculating from eq. (46)
M (D) = Vo Vi
=Y (2) Vi
= −EA−1B + F . (47)
However, the reason we have derived the steady-state operation point is not for validating purposes, but in order to use the equilibrium point as instant around which we are going to linearize our system. From the two topologies we have analysed, only buck converter has linear transient behaviour, meaning that the derivative of the output-to-input voltage ratio with regard to the duty cycle is constant, with ∂M (D)/∂D = const.
For the small-signal analysis we first need to take the averaged state equations, assuming that the input voltage always remains constant with u = Vi which yields
dx dt = h A1d(t) + A0 1 − d(t) i x +hB1d(t) + B0 1 − d(t) i Vi, y =hE1d(t) + E0 1 − d(t) i x +hF1d(t) + F0 1 − d(t) i Vi. (48)
Subsequently, for the equilibrium operation point we shall introduce a small perturbation by setting the duty cycle d(t) = D + ˆd, which causes a small perturbation both for the state vector x = X + ˆx and for the output y = Y + ˆy, where ˆx, ˆy, ˆd, are the respective perturbation signals. This yields,
d (X + ˆx) dt = " A1 D + ˆd+ A0 1 −D + ˆd # (X + ˆx) + " B1 D + ˆd+ B0 1 −D + ˆd # Vi, Y + ˆy = " E1 D + ˆd+ E0 1 −D + ˆd # (X + ˆx) + " F1 D + ˆd+ F0 1 −D + ˆd # Vi. (49)
2.4 State-space averaging and small-signal modelling
Substitution between eqs. (44), (45) and (49) results in formulating the small-signal system as follows:
dˆx dt = Aˆx + G ˆd, ˆ y = E ˆx + H ˆd, (50) with G = (A1− A0) X + (B1− B0) Vi, H = (E1− E0) X + (F1− F0) Vi. (51)
Therefore, in order to derive the transfer between output and duty cycle we need first to move to Laplace domain by applying the Laplace operator on both sides of the expressions in eq. (50), assuming without loss of generality zero initial conditions ˆx(0) = 0, which gives
sˆx(s) = Aˆx(s) + G ˆd(s) ⇒ ˆx(s) = (sI − A)−1G ˆd(s), ˆ
y(s) = E ˆx(s) + H ˆd(s) ⇒ ˆy(s) =hE (sI − A)−1G + Hi ˆd(s), (52)
where I is the unity matrix.
The transfer function between output and duty cycle can be now derived from eq. (52) as follows:
Gdy(s) = ˆ y(s) ˆ d(s) = E (sI − A) −1 G + H. (53)
As a last part in this paragraph, we will analytically derive the transfer functions between the duty cycle and the output voltage for the two topologies we have presented and according to the averaged equivalent models we have obtained. For the buck converter, assuming that rL, ron= 0, we have
Gdvo(s) = ˆ vo(s) ˆ d(s) = Gdy[2] ⇒ Gdvo(s) = Vi(resrCs + 1) LC RL+ resr RL ! s2+ L RL + resrC ! s + 1 , (54)
whereas the corresponding the output voltage-to-duty cycle transfer function for a synchronous lossless buck-boost converter with rL, ron, resr= 0) yields
Gdvo(s) = Vi (1 − D)2 − LD RL(1 − D) 2s + 1 ! LC (1 − D)2s 2+ L RL(1 − D) 2 ! s + 1 . (55)
3
Discrete modelling and control of DC/DC converters
3.1
Introduction
The discrete modelling of switching power converters has its origins long before, in [10]. The aim in this section is to obtain small-signal models for the previously analysed DC-DC converters, such that the sampling effects, the modulations effects and the delays are taken into consideration. The small-signal models are to be used in order to tune the digital controllers using the "loop shaping" method. The generalized method described in [11, 12] shall be followed in order to derive the small-signal discrete models for the synchronous buck and the synchronous buck-boost converter. Quantization effects which pertain both to analog-to-digital conversion and the digital pulse-width modulator will be disregarded in our analysis.
3.2
Discrete small-signal modelling
We shall assume that the digital modulator is implemented by the means of a trailing-edge waveform. The total delay between the sampling instant and the modulating edge is denoted as td. The small-signal discrete modelling is based on [12], where DTs≤ td< Tsis assumed. However, in our case we will expand the analysis presented and we shall also evaluate the case, when Ts≤ td< (1 + D) Ts.
The state equations for small-signal analysis in discrete domain and for total system delay DTs≤ td < Ts are given as follows:
ˆ
x[n + 1] = Φˆx[n] + γ ˆuc[n], ˆ
y[n] = δ ˆx[n], (56)
where n denotes the n-th sequential sample for the state vector perturbation ˆx[n], the control signal ˆuc[n], and the output vector ˆy[n]. In addition, Φ, γ, δ correspond to matrices which depend on the topology, the modulation waveform and the topological state at the sampling instants. It should be noted that the state vector ˆx[n] and therefore the output vector ˆy[n] correspond to sampled magnitudes, which means that they can depict differences compared to the respective continuous system.
The corresponding waveforms of the modulation and the sampling instants are described in fig. 15. Matrices Φ, γ, δ are derived as follows:
Um DTs Ts td td1 UC c(t) tn tm tn+1 ˆ uc[n]
3.2 Discrete small-signal modelling Φ = eA0(Ts−td)eA1DTseA0(td−DTs), γ = Ts Um eA0(Ts−td)G m, δ = E0, (57) with Gm= (A1− A0) Xm+ (B1− B0) Vi, Xm= I − eA1DTseA0(1−D)Ts −1 · −eA1DTsA−1 0 I − eA0(1−D)TsB 0− A−11 I − eA1DTsB 1 Vi. (58)
Vector Xmphysically represents the state vector values when the system has reached equilibrium, at the time instant tm, when the signal c(t) is modulating (switching from topological state 1 to 0). To explain it in a simpler manner, we shall compare Xm to X which is obtained from eq. (46). Vector X has the state values of the averaged system and therefore, those values are constant for a certain operation point. In contrast to this, Xmrefers again to steady-state, but includes the switching phenomena as well, which in turn yields that state values are not constant in the sense that the system is constantly switching. Respectively, Gm is the slope of the small-signal state vector at the same time instant, i.e., it reflects the slope of ˆx(tm). By comparing Gm to G from eq. (51), we can see the difference that G refers to the slope of the state vector for the averaged system without providing information about the instant of sampling.
Looking at vector Φ, we can easily understand that it represents the propagation of a state perturbation between two sampling instants in sequence. The way it is formulated makes it quite intuitive to correlate the respective time intervals with the corresponding topological state matrix. We can describe it in a more qualitative way and assume for example three time intervals t1, t2, t3 corresponding to topological states k1, k2, k3 ∈ {0, 1}. In that case the matrix would be obtained as Φ = eAk1t1eAk2t2eAk3t3.
The vector which corresponds to the propagation of the control signal perturbation is γ and it again presents a quite intuitive interpretation. The reader can imagine that the perturbation is applied at time instant tmand it propagates until the next sample. At the same time, the propagation also depends on the topological state during that interval. Based on the studied case, the state is 0 and the time interval is (Ts− td), so the corresponding coefficient which appears is eA0(Ts−td).
Finally, the vector δ reflects the sampling of the state values which compose the output vector, or alternatively it corresponds to the observation of the state vector in the respective topological state when the sampling occurs.
Next, we will consider that the total delay between sampling instant and modulating edge is Ts≤ td < (1 + D) Ts (fig. 16). In that case the state equations themselves will be formulated a little bit differently having an input delay of one sample, with
ˆ
x[n + 2] = Φˆx[n + 1] + γ ˆuc[n], ˆ
y[n] = δ ˆx[n], (59)
3.2 Discrete small-signal modelling Φ = eA1[(1+D)Ts−td]eA0(1−D)TseA1(td−Ts), γ = Ts Um eA1[(1+D)Ts−td]eA0(1−D)TsG m, δ = E1, (60)
with Gm to be described from eq. (58).
Um (1 − D) Ts Ts td td1 UC c(t) tn tn+1 tm tn+2 ˆ uc[n]
Figure 16: Discrete small-signal modeling for trailing-edge modulation and Ts≤ td< (1 + D) Ts.
This case is quite realistic when implementing digital controller in real hardware. What happens is that we sample the state vector perturbation ˆx[n] at instant tn and then we calculate a new control signal value ˆuc[n] using a desirable control law. However, the processing unit will not load this new value until the end of the modulation period. After the new control signal value is loaded to the respective register, there is further delay up to the instant of the modulating edge at tm. Finally, the digital processing unit will not realize this perturbation of control signal until the next sampling instant after tm, coming at tn+2.
We can subsequently derive the transfer functions between input and output vectors by using the z-transform for the discrete domain. In the first case when td < Ts, mapping eq. (56) in the z-domain yields,
z ˆx(z) = Φˆx(z) + γ ˆuc(z), ˆ
y(z) = δ ˆx(z), (61)
and hence, the discrete transfer function between output and input (control signal) perturbation is ob-tained from eq. (61) as follows:
Guyz(z) = ˆ y(z) ˆ uc(z) = δ (zI − Φ)−1γ. (62)
Respectively, the z-transform for the second case where Ts≤ td< (1 + D) Tsis derived from eq. (59),
z2x(z) = zΦˆˆ x(z) + γ ˆd(z), ˆ
3.3 Digital compensator
and the transfer function between output and input yields
Guyz(z) = ˆ y(z) ˆ uc(z) = z−1δ (zI − Φ)−1γ. (64)
We have seen that in order to derive analytically the transfer functions between input and output we need to use a representation for the exponential matrix. Different approaches on how to approximate the exponential matrix have been proposed in [13], which aim at reducing the complexity when it comes to analytical expressions. We shall typically be using a mathematical software package like MATLAB to perform those calculations and in that case the complexity level is not a concern. As example though, we shall derive analytically the approximate discrete small-signal transfer function of control signal-to-output voltage for a synchronous lossless buck converter (rL, ron, resr = 0). We will use a first order approximation for the exponential matrix such that for the k-th topological state the following applies:
eAkt≈ I + A
kt. (65)
For the case when DTs ≤ td < Ts and Um = 1, the duty cycle-to-output voltage transfer function is derived by combining eqs. (57), (58), (61) and (65) as follows:
Guvoz(z) = ˆ vo(z) ˆ uc(z) = Guyz[2] ⇒ Guvz(z) = ViTs LC (Ts− td) z + td Ts− td z2+ Ts RLC − 2 ! z + T 2 s LC− Ts RLC + 1 ! (66)
The respective transfer function for Ts≤ td< (1 + D) Tsand Um= 1, yields in a similar manner,
Guvoz(z) = ViTs LC (2 · Ts− td) z + td− Ts 2 · Ts− td z z2+ Ts RLC − 2 ! z + T 2 s LC− Ts RLC + 1 ! (67)
3.3
Digital compensator
Discrete modelling of the PWM converters enables us to directly synthesize the desirable control structure in the z-domain, using well-known methods from analog control theory. Assuming voltage mode control is applied, then the block diagram of the corresponding transfer functions composing the loop is illustrated in fig. 17, where Gc(z) is the controller transfer function, Hf bis the feedback gain assuming wide bandwidth, ˆ
3.3 Digital compensator + − Gc(z) Guvoz(z) Hf b ˆ vref[n] e[n]ˆ vˆo[n] ˆ ux[n] ˆ uy[n] ˆ vs[n]
Figure 17: Block diagram representation for z-domain voltage-mode control.
When we design a control loop using the "loop shaping" method we are actually interested in the loop gain in frequency domain. From fig. 17, we define as loop gain T (z) the following expression:
T (z) = −uˆy(z) ˆ ux(z)
= Gc(z)Guvoz(z)Hf b. (68)
In the case that the feedback function cannot be treated as gain, but further dynamics need to be included, the solution is to include those dynamics when deriving the state equations of the system. In this way, the transfer function G0uvoz(z) incorporates the discrete representation of Guvo(s)Hf b(s) (fig. 18) and the loop gain yields
T (z) = Gc(z)G0uvoz(z). (69) + − Gc(z) G 0 uvoz(z) ˆ vref[n] ˆ vs[n] ˆ uc[n] ˆ e[n]
Figure 18: Voltage-mode control including feedback dynamics in G0uvoz(z).
The type of compensator that we will be using is two pole/two zero, where its transfer function in discrete domain is given by
Gc(z) =
b0+ b1z−1+ b2z−2 1 − a1z−1− a2z−2
, (70)
where a1, a2, b0, b1, b2are coefficients which are determined by the placement of the poles and zeros. Having defined the transfer function of the controller, we can tune the aforementioned coefficients such that we shape the loop gain T (z) according to the given design specifications for crossover frequency ωc, phase margin φmand the gain margin gm. This target can be achieved in two different ways.
The first way is the analytical approach. In this method the discrete transfer function of the loop gain is firstly mapped to the continuous p-domain applying the bilinear transformation by substituting
z = 1 + pTs 2 1 − pTs 2 . (71)
3.3 Digital compensator
Therefore, a given T (z) applying the transformation in eq. (71) yields the mapped transfer function in p-domain T0(p). Subsequently, we can work in the continuous domain using well known analog techniques to shape the loop and based on the specifications to derive the values for a1, a2, b0, b1, b2.
This method involves an issue which shall be addressed. The bilinear transformation maps the unit circle z = ejωTs into the p-domain with p = jω0and this transformation yields a distortion between frequencies ω and ω0 known as frequency warping with
ω0= 2 Ts tan ωTs 2 ! . (72)
The frequency in the loop gain which is of highest importance is the crossover frequency ωc, typically set as one of the design specifications. Hence, we would rather have a perfect match at ωc when mapping the system from z-domain to p-domain. This can be achieved by using prewarping, meaning that we modify the mapping relation in eq. (71) such that the distortion in the frequency of interest ωc is zero. The modified bilinear transformation which will be given by substituting
z = 1 + p tan ωcTs 2 ! ωc 1 − p tan ωcTs 2 ! ωc . (73)
The second method and the one that we will be using in the present project is to directly shape the loop gain T (z) in the discrete domain. By using the Matlab Control System Designer tool, we can visually shape the loop by placing the corresponding poles and zeros and changing the total gain. The result of this procedure determines the coefficients a1, a2, b0, b1, b2, which we can then upload to our digital controller.
4
Design and implementation of the prototype converter
4.1
Preliminary design specifications
The prototype DC/DC converter to be delivered is a voltage regulating unit with its preliminary design specifications to be summarized in table 1.
Preliminary Specifications
Input voltage Vi 24 − 250V
Output voltage Vo 0.2Vi− 1.2Vi
Rated output current IoR 10A
Output voltage ripple ∆Vo/Vo 1% Output voltage regulation ∆Vo/Vo 3%
Table 1: Preliminary specifications of the prototype converter.
The parameter given for the output current refers to a point of load application, which means short time intermittent operation. It should be noted that the converter regulates the output voltage according to the given reference without being loaded, or realistically speaking with very low load. Subsequently, the load is coupled to the output and the task of the controller is to withhold the voltage level within the specified margins for time interval of the test. From application’s perspective, the load is typically unknown, though based on experience in 90-95% of the cases it will be highly inductive. This means that designing and testing for step changes of the output current (resistive load) corresponds to the worst case scenario, but in reality this approach is proven to be way too conservative.
Therefore, considering the preliminary specifications, the operation of the converter requires both stepping down and boosting up the input voltage, while at the same time it should cover a wide operation range. The criteria set in order to decide on the topology can be summarized into the following points:
• The size and the cost of the converter should be kept low in a reasonable manner. Based on this and considering the fact that no isolation was required, we had excluded from the beginning topologies which include a transformer (for ex. single or double-switch forward converter), in order to reduce the size of magnetics.
• The small signal model for the different operation points should be invariable from the steady-state duty cycle as much as possible. This simply means that designing a control loop for a certain operation point does not necessarily ensures stability for other operation points. Hence, we needed to strategically choose topology such that we decrease the complexity of the controller.
• The chosen topology should be implemented in synchronous operation mode in order to achieve better transient response and be able to regulate the output voltage level both upwards and down-wards. This point is related to the nature of our application. If we use a non-synchronous topology, during the regulation interval our converter will operate in discontinuous mode. At the instant of the load coupling the converter has to undergo a transition from discontinuous mode to continuous mode and this will present a negative effect on the output voltage (slower response causing larger voltage dip). In addition to this, there is a real application scenario we need to evaluate. Assuming that we regulate the output voltage in discontinuous conduction mode, then if the user commands the output voltage to be reduced to a certain level, there is no ability to discharge the output capacitor by transferring power backwards and hence, the discharging rate of the output voltage is determined by the time constant between the output capacitor and the bleeder resistance.
Taking the aforementioned points into consideration, we have decided to use the non-inverted buck-boost topology (fig. 12), but operate it in two different modes based on the relation between input voltage and desired output voltage. Those modes correspond to buck and buck-boost mode, while the operation of the switches is described for each mode in table 2, with c, ¯c to represent the control signal and its complementary one respectively.
4.1 Preliminary design specifications
Mode Vo T1 T2 T3 T4
Buck 0.2Vi− 0.8Vi c ¯c OFF ON
Buck-boost 0.8Vi− 1.2Vi c ¯c c ¯c Table 2: Operation modes of the prototype converter.
The reasoning behind this choice lies mainly in the fact that we want to utilize as much as possible the buck converter, because its small signal model is the most linear from all our alternatives and without the presence of right half plane zero. This will simplify the controller design process quite a lot. The buck-boost mode is used in order to cover the rest of the operation range, which is not covered by the buck mode. In the case that we had chosen to implement boost converter mode to step up the voltage, we would also need a buck-boost mode in order to ensure that we can regulated within the range of Vi≈ Vo. Regarding the control scheme, we have chosen to implement digital voltage model control for both op-eration modes using the generalized 2 pole/2 zero structure. The choice of digital control stems from the demand for wide operation range. The flexibility provided by digital control implementation is the key factor in our application. In particular, the digital control implementation including the analog-digital converter is realized using a micro-controller unit from Texas Instruments with part number TMS320F28069 ( [14]).
The application level schematic of the power converter including the control loop is illustrated in fig. 19.
− + vi(t) iL(t) iC(t) io(t) + − vo(t) + − vC(t) + − vL(t) + − vf 1(t) − + + − vo,s(t) L T1 vGT 1 T2 vGT 2 T4 vGT 4 T3 vGT 3 C RL rL resr ADC REF Control Law DPWM Gate Drivers vcT 1, ..., vcT 4 vGT 1, ..., vGT 4 + -TMS320F28069 Rb1 Rb2 Cf 1 Rf 2 Cf 2
4.2 Dimensioning of the power components
4.2
Dimensioning of the power components
The dimensioning and selection process of the main power components i.e., power inductor, main output capacitor and power semiconductors based on fig. 12 shall be presented in this section.
4.2.1 Power inductor
The selection and design of the power inductor is primarily determined by the following specifications:
• The desired current ripple at a given operation point, which sets the minimum inductance value Lmin.
• The maximum instantaneous current ILp, which determines the size of the magnetic core such that it can store the respective amount of energy without being driven into saturation mode.
• The rated current ILR, which reflects the maximum allowable winding resistance, such that the copper losses are limited within a certain value and the inductor itself can effectively dissipate the heat generated.
We have decided not to allow more that 70% current ripple at rated load. Denoting the maximum current ripple (peak-to-peak) as ∆ILmax, this specification can mathematically be formulated as follows:
∆ILmax ILR
< 0.7. (74)
Moreover, its has been decided to use a switching frequency of fs= 50kHz, which is the equivalent of a switching period
Ts= 20µs. (75)
At this point it should be noted that there is not only one choice which is the "right" one, both for the switching frequency and current ripple. Of course, higher switching frequency yields smaller inductor size for the same current ripple, though at the same time the switching losses on the semiconductors are increased and in some cases the electromagnetic emissions can become an issue.
The previously derived expression in eq. (74) has to be fulfilled for all operation points, both for buck and buck-boost mode. Therefore, we need to perform some steady-state analysis for our converter in order to obtain the mathematical conditions which yield the minimum inductance value. To simplify our analysis, we will consider a lossless converter.
For the buck converter mode, we can apply the small ripple approximation which yields the following for the rated inductor current:
ILR,bu= IoR= 10A. (76)
Respectively, we can express the output voltage as
Vo= DVi. (77)
The expression linking the inductance to the current ripple for the buck mode is derived by integrating on the inductor equation at the interval [0, DTs], which yields
4.2 Dimensioning of the power components
L = (Vi− Vo) DTs ∆IL
. (78)
We can calculate the minimum inductance Lmin,bu for the worst case scenario by combining eqs. (74), (77) and (78)
Lmin,bu=
Vi,max 1 − Dcr,bu Dcr,buTs
0.7ILR,bu
= 179µH, (79)
where Vi,max= 250V is the maximum input voltage and Dcr,bu= 0.5 is the critical duty cycle for which
Lmin,bu is maximized.
Considering the buck-boost mode, the average inductor current at worst case operation yields
ILR,bb=
IoR 1 − Dmax,bb
= 22A, (80)
where Dmax,bb= 0.546 is the corresponding maximum duty cycle in buck-boost mode.
In similar way as we did in the buck mode case, we can express the inductance in relation to the current ripple as follows:
L = ViDTs ∆IL
. (81)
Subsequently, the minimum inductance for the buck-boost operation mode is obtained by combining eqs. (74), (80) and (81) in such way that Lmin is maximized with
Lmin,bb=
VimaxDmax,bbTs
0.7ILR,bb
= 177µH, (82)
Regarding the rated current of the inductor ILR, we need actually to choose the higher value between the two modes (eqs. (76) and (80)) and therefore, we have
ILR= maxILR,bu, ILR,bb = 22A. (83)
Finally, we need to decide on value for the maximum instantaneous current ILp, which eventually will determine the size of the core in order not to reach saturation at ILp. Our design choice is
ILp= 35A. (84)
Finally, we can summarize the specifications for the inductor in table 3. Inductor Specifications Minimum inductance Lmin 179µH
Rated current ILR 22A
Peak current ILp 35A
Table 3: Design specifications for the power inductor.
Based on these specifications we will be using a prototype inductor which utilizes its magnetic core with ferrite material and with specifications as mentioned in table 4.
4.2 Dimensioning of the power components
Prototype inductor specifications
Inductance L 230µH
Rated current ILR 30A
Saturation current ILsat 40A Equivalent series resistance RL 0.02Ω Table 4: Design specifications for the power inductor.
4.2.2 Output capacitor
The output capacitor is typically selected based on the maximum voltage ripple allowed on the output and together with the power inductor it forms a low-pass filter with a cutoff frequency of approximately
fLC = 1
2π√LC. (85)
The expected fundamental frequency of the voltage ripple is the switching frequency fs= 50kHz. Ideally, the whole AC component of the current flows through the output capacitor and only the DC component of the current is injected into the load.
Most commonly, the type of output capacitor used in cases of higher DC voltage is electrolytic and this is the one we will be using. In reality though, since our output capacitor needs to be rated for high voltage, unless we add a huge amount of capacitance the impedance of the electrolytic capacitor at the switching frequency with be dominated by the equivalent series resistor (resr) of the capacitor. This technically means that our output capacitor behaves as resistor at the switching frequency and thus, the output ripple independently of the capacitance is calculated as
∆vo(t) = iC,r(t)resr, (86)
where iC,r(t) and ∆vo(t) denote the instantaneous current ripple flowing through the capacitor and voltage ripple respectively.
Furthermore, an important parameter which sets the thermal limit on the operation of the electrolytic capacitors is the RMS value of the ripple current. Typically, the manufacturer attaches two different RMS current values in the datasheet, corresponding to two different frequencies. Of course, for the same rated voltage, the bigger is the volume of the capacitor, the higher is the capacitance and the lower is equivalent series resistance, which yields higher rated ripple current.
After this brief introduction on the underlying concepts on the output capacitor, we can name the following points based on which a part selection was made.
• Firstly, the capacitor needs to withstand the maximum output voltage with an extra margin, which based on experience should be at least 30%.
• Subsequently, the value of capacitance should be kept as low as possible, given that we fulfill the worst case specified RMS current ripple. The reasoning behind this guideline lies on the fact that if we select a bigger capacitor (several mF ), this will primarily yield a very low resonant frequency introduced by L and C components. From a design perspective, higher L and C means higher "electrical inertia" which will eventually cause issues when designing our digital control loop. Briefly explained, given a desirable crossover frequency in the loop gain, a higher gain needs to be applied when that resonance is moved to lower frequencies and because of quantization effects both in the ADC and the DPWM an issue known as limit cycles will show up, which is undesirable. • In relation to the previous point, we will calculate the worst case RMS current ripple, both for
4.2 Dimensioning of the power components
obtained will be used to select part. However, because of the intermittent nature of our application, we will multiply this maximum RMS current value by a correction factor of 0.7. In this way we can account for the lighter expected thermal stress in the actual application.
• After selecting a specific capacitor part we will calculate the worst case voltage ripple on the output. In the case that we do not fulfill the ripple specification presented in table 1, we will need to add a second stage filter.
To begin with, we have that the maximum output voltage is given for the buck-boost operation mode when
Vi,max= 250V −→ Vo,max = 1.2Vi,max= 300V. (87)
Therefore, the minimum rated output voltage yields
VoR,min= 1.3Vo,max= 390V. (88)
Next, we are going to estimate the RMS value of the capacitor current starting by the buck mode. Assuming ideal buck converter, the capacitor current is expected to have a triangular form with maximum peak-to-peak ripple
∆IL,bu,max=
Vi,max 1 − Dcr,bu Dcr,buTs
L = 5.43A. (89)
Subsequently the worst case RMS current for buck mode is calculated as
ImaxC,rms,bu=
∆IL,bu,max
2√3 = 1.57A. (90)
In the case of the buck-boost mode the maximum RMS capacitor current can be derived from
ImaxC,rms,bb= IoR
s
Dcr,bb
1 − Dcr,bb
= 10.95A, (91)
with Dcr,bb = 0.546 corresponds to the critical duty cycle (maximum theoretical value for buck-boost operation) for which the RMS value of the capacitor current is maximized.
Afterwards, we apply a correction factor to the RMS capacitor current as aforementioned and finally, the minimum RMS capacitor current is obtained as follows:
IC,rms,min= 0.7 · maxImaxC,rms,bu, ImaxC,rms,bb = 7.67A. (92)
We can summarize the capacitor specification in table 5.
Capacitor Specifications
Rated voltage VoR,min 390V
Rated RMS current IC,rms,min 7.67A Table 5: Design specifications for the output capacitor.
4.2 Dimensioning of the power components B43305A9108M000 Specifications Nominal capacitance CR 1000µF Capacitance tolerance ∆C/CR ±20% Rated voltage VR 400V Rated RMS current1 I R,rms 8.62A
Equivalent series resistance2 resr 130mΩ Table 6: Specifications for the selected output capacitor.
The capacitor selected is from TDK Electronics Inc. and it has a part number B43305A9108M000 ( [15]). The most important of its specifications are presented in table 6.
Based on this value we will calculate the worst case peak-to-peak voltage ripple using the expression given in eq. (86) and in this way we can decide whether or not we need to design a second stage filter in order to meet the specification on relative voltage ripple on the output.
The worst case ripple voltage for buck mode is calculated by the following expression:
δvbu,max= ∆Vo Vo max = iC(t)resr max= 1 − Dcr2,bu resrTs L = 0.9%, (93)
where Dcr2,bu= 0.2 is the critical (minimum) duty cycle for buck mode which yields worst case voltage ripple on the output.
Respectively, the worst case voltage ripple for buck-boost mode is calculated for input voltage Vimin = 24 and critical duty cycle Dcr2,bb= 0.444 as follows:
δvbb,max= ∆Vo Vo max = iC(t)resr max= IoRresr ViminDcr2,bb = 12.2%. (94)
It can be easily observed from eq. (94) that the worst case voltage ripple for the buck-boost mode lies way beyond the desirable specification. This entails that a second stage output filter needs to be designed and implemented in order to meet the respective specification of 1% ripple. Since this aspect was not considered from an early point in our first prototype design, we have not included a second stage filter, which means that it will be a part in our future work considerations.
4.2.3 Power semiconductors
When selecting semiconductor components in real applications there are typically many parameters to be taken into consideration. In this paragraph, we are going to cover the most important aspects of the part selection process as defined by the needs of our application. Below we can summarize the following points:
• First of all, based on the specified output current it is preferable to use MOSFET technology instead of IGBT. This argument stems from the fact that for lower currents MOSFET technology yields more efficient operation because of the lower conduction losses. Of course in high current applications (over 100A) IGBTs are preferred because of their architecture, which allows small voltage drop variations between collector and emitter for high currents.
1Given at the frequency of 50kHz and temperature 60◦C. 2Given at the frequency of 50kHz.
4.2 Dimensioning of the power components
• It has been decided that all four semiconductors will be realized by the same MOSFET part. The main reason is the reduction of the total cost.
• One basic specification is that the MOSFETs must tolerate at least the maximum applied voltage under normal operation, given an extra margin of 50% on top of that maximum voltage.
• During the buck mode operation switch T2 is suffering from diode’s reverse recovery losses at the instants when the high side switch (T1) is switched ON. Respectively, in buck-boost mode both T2 and T4depict reverse recovery losses. For this reason, we have specified that the selected MOSFET part should have an ultra fast recovery built-in diode and moreover, we have set the maximum allowable reverse recovery time of the diode to be trr,max= 200ns.
• There are different types of losses which are generated on the semiconductors and from an appli-cation perspective there are relatively simple expressions to approximate them analytically [16]. In this case study though, we will set a design specification of keeping the total conduction losses within 2.5% of the maximum output power at worst case. From this design specification we can derive the maximum acceptable on-state resistance rDS,on,max of the MOSFET part.
• Another design specification is related to the abnormal current that each part must be able to handle in case of a fault. Thus, we specify that each MOSFET can carry a maximum peak current of 80A for 1µs. We presume that our short circuit protection circuit shall guarantee that neither the current value nor the specified time are going to be violated.
• The rated current and the estimated losses on a semiconductor do not directly determine the package size (case). It is rather the mechanical design (heatsink and fan) which sets the limitation on how much power can be dissipated effectively. It is therefore up to the designer’s choice to select package size and there is not only one straightforward solution. Of course, as a rule of thumb a MOSFET in a bigger case will present lower on-state resistance for the same breakdown voltage compared to one in a smaller case. In our design we have determined that a MOSFET part of TO-247 package is to be selected.
Taking the aforementioned points into account, we can firstly calculate the minimum specified breakdown voltage of the MOSFET. From our converter topology we can identify that the worst case voltage appears in buck-boost mode with Vi,max = 250V and Vo,max = 300, where Vo,max is applied both in T3 and T4. Hence, we can obtain
VDS,min= 1.5Vo,max = 450V. (95)
The next step is to determine the maximum on-state resistance. Based on the given specification, the highest limit of conduction losses at maximum output power is calculated
PC,max= 0.025Po,max = 0.025Vo,maxIoR= 75W. (96)
In buck mode, by applying small-ripple approximation for the inductor current and assuming lossless converter, we can express the RMS currents of the switches Irms,T 1− Irms,T 4 as follows:
Irms,T 1=Io √ D, Irms,T 2=Io √ 1 − D, Irms,T 3=0, Irms,T 4=Io, (97)
