Modeling and Implementation of Current-Steering Digital-to-Analog Converters

(1)

Linköping Studies in Science and Technology Dissertation No. 944

M

ODELING AND

I

MPLEMENTATION OF

C

URRENT

-S

TEERING

D

IGITAL

-

TO

-A

NALOG

C

ONVERTERS

K Ola Andersson

Department of Electrical Engineering

Linköpings universitet, SE-581-83 Linköping, Sweden Linköping, May 2005

(2)

Digital-to-Analog Converters

Department of Electrical Engineering Linköpings universitet

SE-581 83 Linköping Sweden

(3)

Abstract

Data converters, i.e., analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), are interface circuits between the analog and digital domains. They are used in, e.g., digital audio applications, data communication applica-tions, and other types of applications where conversion between analog and digi-tal signal representation is required. This work covers different aspects related to modeling, error correction, and implementation of DACs for communication applications where the requirements on the circuits in terms of speed and linear-ity are hard. The DAC architecture considered in this work is the current-steering DAC, which is the most commonly used architecture for high-speed applications. Transistor-level simulation of complex circuits using accurate transistor models require long simulation times. A transistor-level model of a DAC used in a sys-tem simulation is likely to be a severe bottleneck limiting the overall syssys-tem sim-ulation speed. Moreover, investigations of stochastic parameter variations require multiple simulation runs with different parameter values making transistor-level models unsuitable. Therefore, there is a need for behavioral-level models with reasonably short simulation times. Behavioral-level models can also be used to find the requirements on different building blocks on high abstraction levels, enabling the use of efficient top-down design methodologies. Models of different nonideal properties in current-steering DACs are used and developed in this work.

Static errors typically dominates the low-frequency behavior of the DAC. One of the limiting factors for the static linearity of a current-steering DAC is mismatch between current sources. A well-known model of this problem is used exten-sively in this work for evaluation of different ideas and techniques for linearity enhancement. The high-frequency behavior of the DAC is typically dominated by dynamic errors. Models of two types of dynamic errors are developed in this

(4)

source.

The encoding used for the digital control word in a current steering DAC has a large influence on the circuit performance, e.g., in terms static linearity and glitches. In this work, two DAC architectures are developed. These are denoted the decomposed and partially decomposed architectures and utilize encoding strategies aiming at a high circuit performance by avoiding unnecessary switch-ing of current sources. The developed architectures are compared with the well-known binary-weighted and segmented architectures using behavioral-level sim-ulations.

It can be hard to meet a DAC design specification using a straightforward imple-mentation. Techniques for compensation of errors that can be applied to improve the DAC linearity are studied. The well-known dynamic element matching (DEM) techniques are used for transforming spurious tones caused by matching errors into white or shaped noise. An overview of these techniques are given in this work and a DEM technique for the decomposed DAC architecture is devel-oped. In ∆Σ modulation, feedback of the quantization error is utilized to spec-trally shape the quantization noise to reduce its power within the signal band. A technique based on this principle is developed for spectral shaping of DAC non-linearity errors utilizing a DAC model in a feedback loop. Two examples of utili-zation of the technique are given.

Four different current-steering DACs implemented in CMOS technology are developed to enable comparison between behavioral-level simulations and mea-surements on actual implementations and to provide platforms for evaluation of different techniques for linearity improvement. For example, a 14-bit DEM DAC is implemented and measurement results are compared with simulation results. A good agreement between measured and simulated results is obtained. Moreover, a configurable 12-bit DAC capable of operating with different degrees of seg-mentation and decomposition is implemented to evaluate the proposed decom-posed architecture. Measurement results agree with results from behavioral-level simulations and indicate that the decomposed architecture is a viable alternative to the commonly used segmented architecture.

(5)

Acknowledgments

First of all, I would like to thank my supervisor, Prof. Mark Vesterbacka for his guidance and enthusiasm. I would also like to thank all my colleagues at Elec-tronics Systems, Linköping University, for contributing to a pleasant working environment. Special thanks go to Lic. Eng. Robert Hägglund, Lic. Eng. Henrik Ohlsson, and Ph.D. Oscar Gustafsson for interesting discussions on research and life in general.

My former colleagues at Ericsson Microelectronics also deserve my gratitude. Specifically, I would like to thank Ph.D. J. Jacob Wikner, M.Sc. Niklas U. Andersson, and Ph.D. Mikael Karlsson Rudberg. I also thank Ph.D. Gunnar Björklund and M.Sc. Magnus Hägglund for supporting my work during the years I spent doing research at Ericsson Microelectronics.

Finally, I thank my wonderful family, especially my wife Helena and my daugh-ter Elin, for always believing in me and supporting me.

The work was supported by the Microelectronics Research Center (MERC) at Ericsson Microelectronics and the Center for Industrial Information Technology (CENIIT) at Linköping University.

(6)

(7)

1 Introduction

Data converters, i.e., analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), are interface circuits between the analog and digital domains. They are used in, e.g., digital audio applications, data communication applica-tions, and other types of applications where conversion between analog and digi-tal signal representation is required. This thesis covers different aspects related to modeling, error correction, and implementation of DACs for communication applications. This chapter is an introduction to the thesis providing relevant back-ground information and an overview of the thesis and the author’s contributions to the different areas.

1.1 Digital-to-Analog Conversion

An overview of fundamental theories for digital-to-analog conversion is provided in this section. The concepts of sampling and reconstruction are discussed in Sec. 1.1.1, and reconstruction using pulse-amplitude modulation is overviewed in Sec. 1.1.2. Ideal reconstruction using sinc pulses and reconstruction using square pulses are presented in Sec. 1.1.3 and Sec. 1.1.4, respectively, followed by a dis-cussion on the ideal DAC in Sec. 1.1.5.

1.1.1 Sampling and Reconstruction

Let denote time and let denote an analog signal, which is uniformly sam-pled to a discrete-time signal according to

, (1.1)

t z t( )

x n( )

(12)

where is the sequence index and is the sample period. If is band limited, having no spectral content above a frequency , and the sampling frequency

has the property

, (1.2)

then the analog signal can be reconstructed from the discrete-time signal according to the sampling theorem [1].

1.1.2 Pulse-Amplitude Modulation

The reconstruction of a signal can be performed using pulse-amplitude modula-tion (PAM), in which case the reconstructed signal is given by

, (1.3)

where is a pulse. A model system for constructing is shown in Fig. 1.1. An intermediate signal given by

(1.4)

is constructed, where is the unit impulse. Let denote angular frequency and let and denote the Fourier transforms of and , respec-tively. can be expressed as [2]

. (1.5)

Further, is filtered with a filter having the impulse response , resulting in the reconstructed output . Hence, the Fourier transform of is

, (1.6)

where is the Fourier transform of . Different choices of the pulse are discussed in the following sections.

n T z t( ) f₀ f_s = 1 T⁄ f_s>2 f⋅ ₀ z t( ) x n( ) y t( ) y t( ) x n( ) p t( –nT) n =–∞ ∞

∑

= p t( ) y t( ) y₀( )t y₀( )t x n( )δ t nT( – ) n =–∞ ∞

∑

z t( ) δ t nT( – ) n=–∞ ∞

∑

= = δ t() ω Z( )ω Y₀( )ω z t( ) y₀( )t Y₀( )ω Y₀( )ω _T---1 Z ω k2π T ---– ( ) k =–∞ ∞

∑

f_s Z(ω k2π f– _s) k =–∞ ∞

∑

= = y₀( )t p t( ) y t( ) y t( ) Y( )ω P( )Yω ₀( )ω P( ) fω _s Z(ω k2π f– _s) k=–∞ ∞

∑

      = = P( )ω p t( ) p t( )

(13)

Digital-to-Analog Conversion

1.1.3 Ideal Reconstruction

In ideal reconstruction, . Hence,

. (1.7)

This is obtained if the filter in Fig. 1.1 is an ideal low-pass filter with bandwidth , i.e.,

. (1.8)

The shape of the pulse for ideal reconstruction can be found by performing an inverse Fourier transform on (1.8), resulting in [2]

. (1.9)

1.1.4 Reconstruction with Square Pulses

Because the sinc pulse, , has infinite extension in time, it is not practi-cally possible to use the sinc pulse for signal reconstruction. Therefore, other pulse shapes are used in practice. The most commonly used pulse shape is the square pulse

, (1.10)

resulting in a piecewise constant reconstructed signal Figure 1.1 Model system for signal reconstruction.

PAM d(t), T x(n) y0(t) P(w) y(t) PAM p(t), T x(n) y(t) y t( ) = z t( ) Y( )ω P( ) fω _s Z(ω k2π f– _s) k =–∞ ∞

∑

      Z( )ω = = f_s⁄2 P( )ω T for ω π f< s 0 otherwise    = p t( ) p t( ) sin(π fst) π f_st --- sinc f( _st) = = sinc f( _st) p t( ) 1 for T 2 ---– t T 2 ---< ≤ 0 otherwise    =

(14)

. (1.11) The Fourier transform of the square pulse is

. (1.12)

For frequencies close to , the reconstructed signal is attenuated approxi-mately 3.9 dB compared with the ideally reconstructed signal [3]. Further, the spectral images of that are present in (corresponding to the terms in (1.5) where ) are not completely eliminated. Therefore, a DAC that per-forms signal reconstruction using square pulses usually requires additional filter-ing of the output to remove unwanted high-frequency signal components. The filter performing this task is usually denoted reconstruction filter or image-rejec-tion filter. The effects of using sinc and square pulses for signal reconstrucimage-rejec-tion are illustrated in the frequency domain in Fig. 1.2.

1.1.5 The Ideal DAC

In analogy with the discussion on ideal reconstruction in Sec. 1.1.3, it would be natural to define an ideal DAC as a device that performs the mapping

. (1.13)

However, since this is not practically possible, we define an ideal DAC as a device that performs PAM with a square pulse, yielding a piecewise constant out-put as in (1.11). In this work, we consider the DAC inout-put to be a sequence of inte-gers, whereas the output is represented with a voltage or a current. Therefore, a scaling factor is required in the mapping between the digital and the analog domains. We also allow an offset added to the analog signal. Hence, the ideal DAC performs the mapping

. (1.14)

The input to the DAC is digital and, hence, it is quantized. Therefore, even for an ideal DAC, the output is subject to a quantization error. The quantization error , sometimes referred to as quantization noise, can often be accurately mod-eled with a white-noise signal having rectangular distribution. In the case of

trun-y t( ) x n( ) for nT T 2 ---–    _≤_t _nT T 2 ---+     < = P( )ω T sinc ω 2π f_s ---    = f_s⁄2 Z( )ω Y₀( )ω k≠0 y t( ) x n( )sinc f( _s(t–nT)) ∞ – ∞

∑

= K m y t( ) K x n⋅ ( ) m for nT T 2 ---–     _≤_t _nT T 2 ---+     < + = q n( )

(15)

Digital-to-Analog Conversion

(a)

(b)

(c)

(d)

Figure 1.2 Illustration of the effects of using different pulses for reconstruction on the sig-nal spectrum. and are shown in (a) and (b), respectively, and using sinc and square pulses for reconstruction are shown in (c) and (d), respectively. −4 −3 −2 −1 0 1 2 3 4 Normalized frequency (f/f s) |Z (2 π f)| 0 A −4 −3 −2 −1 0 1 2 3 4 Normalized frequency (f/f s) |Y 0 (2 π f)| 0 T⋅A −4 −3 −2 −1 0 1 2 3 4 Normalized frequency (f/f s) |Y (2 π f)| 0 A −4 −3 −2 −1 0 1 2 3 4 Normalized frequency (f/f s) |Y (2 π f)| 0 A Z( )ω Y₀( )ω Y( )ω

(16)

, (1.15) where is the quantization step. The power of the quantization noise is given by its variance, which for the quantization-noise model in (1.15) is

. (1.16)

1.2 Telecommunication Applications

In this work, we focus on DACs for high-speed telecommunication applications, specifically wireline applications. Examples of such applications are the different digital subscriber line (DSL) applications. In this section, we give a brief over-view of these applications, present the analog front end, illustrate the effects of nonideal transmission, and discuss the DAC requirements for DSL.

1.2.1 Digital Subscriber Line Applications

Due to the increasing demand for low-cost and high bit-rate internet connections, it is desirable to use existing infrastructures for wideband data communication. One example of such existing infrastructures is the twisted-pair copper wires originally intended for the plain old telephone service (POTS), which uses a sig-nal bandwidth of approximately 3.4 kHz [4]. The different DSL technologies, sometimes referred to with a common name as xDSL, utilize these copper wires to provide data transmission with high bit rates compared with analog modems. The signal bandwidths for DSL are considerably higher than the 3.4 kHz used in POTS, making the design of DSL circuits a challenging task. Some examples of DSL technologies are asymmetric DSL (ADSL), very high bit-rate DSL (VDSL), high bit-rate DSL (HDSL) and single-pair high-speed DSL (SHDSL) [4, 5, 6, 7, 8]. Some properties of these technologies are listed in Table 1.1. The achievable data rates for each technology depend on the quality (e.g., attenuation and noise levels) of the copper wires [4].

In ADSL, the information is transmitted using a discrete multi-tone (DMT) sig-nal. The frequency bands used in frequency division multiplexing (FDM) ADSL [4] are shown in Fig. 1.3. The frequency range up to 4 kHz is reserved for POTS transmission. Data is transmitted upstream, i.e., from the customer premises equipment (CPE) to the central office (CO), in the frequency band between 30 and 138 kHz. The frequency band between 138 kHz and 1.104 MHz is used for data transmission in the reverse direction, i.e., downstream. A guard band, where no information is transmitted, is present between the POTS band and the ADSL

q n( )∈Re 0( ,∆) ∆ Var q n( ( )) --- xx_∆2d 0 ∆

∫

x ∆ --- xd 0 ∆

∫

       2 – ∆2 12 ---= =

(17)

Telecommunication Applications

upstream band to ensure low interference between POTS and ADSL transmis-sion. Another type of ADSL is the echo-canceled hybrid (ECH) ADSL [4], in which the downstream band overlaps the upstream band to increase the down-stream data rate compared with FDM ADSL. ECH ADSL requires the use of echo cancellation to separate received data from transmitted data [4].

As can be seen from Fig. 1.3, the maximum signal bandwidth in ADSL is approximately 1 MHz. For DMT VDSL, the standard allows bandwidths up to approximately 18 MHz [5], i.e., roughly an order of magnitude higher than for ADSL.

Technology maximum bit rate required bandwidth

ADSL 8 Mbit/s (downstream) 900 kbit/s (upstream) 1.104 MHz VDSL 52 Mbit/s (downstream) 26 Mbit/s (symmetric) 17.664 MHz HDSL 1.5 Mbit/s

(per wire pair) 400 kHz

SHDSL 2.3 Mbit/s 385 kHz

Table 1.1 Characteristics of some DSL technologies.

Figure 1.3 Frequency bands used in FDM ADSL.

0 4 30 138 1104

Frequency bands in FDM ADSL

Frequency [kHz]

POTS

guard band

ADSL upstream

(18)

No specific application is targeted in this work. Instead, the bandwidths required in ADSL and VDSL are used as guidelines for typical bandwidth requirements in wideband communication applications.

1.2.2 The Analog Front End

The analog front end (AFE) in a DSL transceiver is the interface between the dig-ital signal processing (DSP) blocks and the telephone line, as shown in Fig. 1.4. In the transmit path, there are a DAC, one or more analog filters for spectral image rejection, and a line driver. In the receive path, there are a receive ampli-fier, one or more anti-aliasing filters ensuring that the signal is band limited before sampling, and an ADC. The illustration in Fig. 1.4 is a simplified view of an AFE. For example, circuits for echo cancellation and the line transformer have been omitted in order not to obscure the view. Oversampling (see Sec. 1.4.1) is often used to relax the circuit requirements. This requires the use of interpolation filters for increasing the sampling frequency in the transmit path, and decimation filters for decreasing the sampling frequency in the receive path. The DSP blocks contain, e.g., an inverse fast Fourier transform (IFFT) circuit for modulation of the transmitted data and a fast Fourier transform (FFT) circuit for demodulation of the received data.

1.2.3 Effects of Nonideal Transmission

A brief overview of the effects of nonideal transmission is given in this section. The discussion is limited to the effects on DMT signals utilizing quadrature amplitude modulation (QAM). This type of signal is commonly used in DSL applications [4, 5].

In the time domain, a DMT signal, , can be expressed as Figure 1.4 Typical AFE for DSL applications.

DAC ADC image-rejection filter anti-aliasing filter line driver receive amplifier DSP blocks communication channel AFE x t( )

(19)

Telecommunication Applications

. (1.17)

The different amplitudes ( and ) are determined by the transmitted data. To each carrier, there is an associated QAM constellation [4]. A 16 QAM constella-tion, representing four data bits, is illustrated in Fig. 1.5(a). Every point in the constellation corresponds to a unique combination of the four data bits. The amplitudes and are the coordinates of the point in the constellation, as indicated on the axes in Fig. 1.5(a).

During transmission, the signal is subject to both nonlinear and linear distortion, e.g., due to nonlinearities in the transmitter and attenuation in the transmission medium. Moreover, noise is added to the signal due to thermal activity and exter-nal interferers. The effects caused by these sources of nonideal transmission are illustrated in Fig. 1.5(b)-(d), using a discrete-time signal

for , (1.18)

where . To each tone, there is an associated 16 QAM constellation, as plotted in Fig. 1.5(a). A set of 100 random combinations of data points from the constellations corresponding to all is generated. Each of these stochastic outcomes is combined with all data points in the constellation corresponding to , resulting in a total of 1600 different test signals. How the constellation corresponding to is affected by linear distortion, nonlinear distortion, and noise is illustrated in Fig. 1.5(b), (c), and (d), respectively. Fig. 1.5(b) shows how the constellation is influenced when the signal is filtered through a simple finite-length impulse response (FIR) filter

. (1.19)

The constellation is scaled and rotated. However, there is a one-to-one mapping between the original and distorted constellation, so the original constellation can be restored from the distorted constellation if this mapping is known. Hence, error-free transmission is possible if the signal is only subject to linear distortion. The case is different if the distortion is nonlinear. The data points resulting from the nonlinear mapping

(1.20) x t( ) a_kcos(kω₀t)+b_ksin(kω₀t) k

∑

= a_k b_k a_k b_k x n( ) a_kcos(kΩ₀n)+b_ksin(kΩ₀n) k =1 7

∑

= n = 0 1, , ,… 15 Ω₀ = π 8⁄ k≠4 k = 4 k = 4 y n( ) = 0.5x n( )+0.1x n( –1) y n( ) = x n( )+0.02x3( )n

(20)

are plotted in Fig. 1.5(c). For this case, there is no one-to-one mapping between the original and the distorted constellation. Instead, due to intermodulation dis-tortion, the location of the points are dependent on the data transmitted on the other tones. For more severe nonlinearities, the regions in which the points can appear start to overlap, which in turn results in bit errors in the transmission. The situation is similar when noise is present. The constellation resulting from addi-tion of a white Gaussian noise sequence, , is plotted in Fig. 1.5(d).

(a) (b)

(c) (d)

Figure 1.5 (a) 16 QAM constellation, (b) linearly distorted constellation, (c) nonlinearly distorted constellation, and (d) constellation with added noise.

ε n( )∈N 0 0.1( , ) −0.75 −0.25 0.25 0.75 −0.75 −0.25 0.25 0.75 a k b k Original constellation −0.75 −0.25 0.25 0.75 −0.75 −0.25 0.25 0.75 a k b k

Linearly distorted constellation

−0.75 −0.25 0.25 0.75 −0.75 −0.25 0.25 0.75 a k b k

Nonlinearly distorted constellation

−0.75 −0.25 0.25 0.75 −0.75 −0.25 0.25 0.75 a k b k

(21)

Performance Metrics The nonlinearities and the noise set limits on the feasible size of the constellation, i.e., how many data bits that can be allocated to each carrier [4]. Therefore, it is important that the components in the transmitters and the receiver have good noise and linearity properties, which is a motivation for having the linearity prop-erties of DACs as one of the main focuses in this work.

1.2.4 DACs for DSL

A brief overview on how to choose a proper number of bits for a DAC in a DSL transmitter is given in this section. More detailed descriptions are given in [4, 6, 9]. As discussed in Sec. 1.2.3, the amount of noise added to the signal in the channel limits the feasible constellation sizes. Hence, the achievable data rate in a DSL system is a function of the signal-to-noise ratios for the sub channels and the desired maximum error probability. For example, the maximum allowed number of bits that are mapped onto a carrier in ADSL is 15, resulting in a 32 768 QAM constellation [9]. In order to accommodate 15 bits with an error probability of in a sub channel, the required signal-to-noise ratio in that sub channel is approximately 53 dB [6]. Assuming that this value is obtained, the output step-size, , corresponding to one LSB, is chosen small enough so that the quantization noise does not degrade the overall SNR too much. The output swing, , of the DAC is chosen in order to obtain a low probability of clipping [4, 6]. Finally, the number of bits, , is given by

. (1.21)

Carrying out this analysis for an ADSL transmitter typically results in 12-14 bits, depending on if echo cancellation is used or not [4].

1.3 Performance Metrics

Some performance metrics are required to characterize the performance of a DAC. In Sec. 1.3.1, some commonly used code-domain performance metrics are presented. These metrics can only characterize the DAC’s static (settled) behav-ior. In telecommunication and other high-speed applications, the DAC perfor-mance is usually limited by the dynamic behavior. In that case, the DAC is better characterized by frequency-domain metrics [10], which are presented in Sec. 1.3.2. 10–7 ∆ S N N log₂ S ∆ ---( ) =

(22)

1.3.1 Metrics in the Code Domain

The integral nonlinearity (INL) and the differential nonlinearity (DNL) are per-formance metrics in the code domain that describe the static linearity of a DAC. The static transfer characteristic of a nonideal 4-bit DAC, i.e., the settled output level as a function of the input code, is plotted in Fig. 1.6. Also included in Fig. 1.6 is a straight line representing the nominal DAC transfer characteristic

. (1.22)

The gain and the offset are chosen such that is a best-fit (least squares) straight line with respect to the actual transfer characteristic. Some-times, alternative choices for the nominal characteristic are used [11], e.g., using the endpoints of the characteristic to define a straight line according to

and . (1.23)

However, in this work we exclusively use the nominal characteristic given by the least-squares method. This is further discussed in Sec. 2.1.

Integral Nonlinearity

The INL of a DAC is defined as

(1.24) Figure 1.6 Transfer characteristic of nonideal 4-bit DAC plotted together with best-fit

nom-inal transfer characteristic.

y_nom( )x = Kx+y_offset K y_offset y_nom( )x K y 2( N–1)–y 0( ) 2N–1 ---= y_offset = y 0( ) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Input code (x) Output level ( y)

Static transfer characteristics, nonideal DAC

INL x( ) y x( )–ynom( )x

K

---=

(23)

Performance Metrics and measures the deviation from the nominal transfer characteristic. If for all , the DAC is guaranteed to be monotone, i.e., if and only if . The INL for the nonideal 4-bit DAC with the characteristic in Fig. 1.6 is plotted in Fig. 1.7.

Differential Nonlinearity

The DNL of a DAC is defined as

(1.25) and measures the deviation from the nominal step size at the DAC output in the transition from to at the input. Combining (1.22)-(1.25) yields

. (1.26)

If for all , the DAC is guaranteed to be monotone. The DNL for the nonideal 4-bit DAC is plotted in Fig. 1.8. In some literature, the “unit” LSB is associated with the INL and DNL metrics. In this work, however, these metrics are considered unitless.

1.3.2 Metrics in the Frequency Domain

The metrics presented in Sec. 1.3.1 are useful for characterizing the static linear-ity of DACs. However, in high-speed applications, the dynamic properties of a DAC tend to limit the performance. Hence, the static metrics are insufficient for these types of applications. Therefore, communication DACs are often character-ized in the frequency domain rather than in the code domain [10].

Figure 1.7 INL curve for the nonideal 4-bit DAC.

INL x( ) <0.5 x y x( ₁)>y x( ₂) x₁> x₂ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 −0.4 −0.3 −0.2 −0.1 0 0.1 0.2 0.3 0.4 Input code (x) INL

INL curve, nonideal DAC

DNL x( ) y x( )–y x( –1) K ---–1 = x–1 x DNL x( ) = INL x( )–INL x( –1) DNL x( ) <1 x

(24)

Sinusoidal test signals are often used for DAC characterization. A typical power spectral density (PSD) plot of the output from a DAC with a single-tone input is shown in Fig. 1.9. The largest peak in Fig. 1.9 represents the signal, whereas the spectral content at other frequencies are unwanted signal impurities. These signal impurities are usually divided into noise and distortion, even if it can be difficult to make a clear distinction between the two. Noise is independent of the signal, whereas distortion is signal dependent [12]. In the frequency domain, noise is often characterized by a smooth spectral density, whereas (nonlinear) distortion is visible as distinctive peaks in the output spectrum. There are, however, gray zones present in the analysis. For example, quantization errors are clearly signal dependent, but are often considered as sources of noise.

Figure 1.8 DNL curve for the nonideal 4-bit DAC.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 −0.7 −0.6 −0.5 −0.4 −0.3 −0.2 −0.1 0 0.1 0.2 0.3 Input code (x) DNL

DNL curve, nonideal DAC

0 0.1 0.2 0.3 0.4 0.5 −120 −100 −80 −60 −40 −20 0 SFDR Normalized frequency (f/f s) PSD [dB]

(25)

Performance Metrics

Signal-to-Noise Ratio

The signal-to-noise ratio (SNR) is used to characterize how well the signal can be distinguished from the noise. SNR is defined as

, (1.27)

where is the signal power and is the noise power.

Signal-to-Noise-and-Distortion Ratio

If a large amount of distortion is present in the output, the signal quality is better characterized with the signal-to-noise-and-distortion ratio (SNDR, in some litera-ture abbreviated SINAD). SNDR is defined as

, (1.28)

where is the total power for the noise and the distortion.

Effective Number of Bits

If a full-scale sinusoid is applied at the input of an ideal -bit DAC, for which the only errors are caused by quantization, the SNDR is approximately [11]

. (1.29)

Using (1.29) as a starting point, the effective number of bits (ENOB) for a noni-deal DAC is defined as

. (1.30)

Spurious-Free Dynamic Range

Nonlinearities in the DAC give rise to harmonic distortion. The spurious-free dynamic range (SFDR) measures the linearity of a DAC according to

, (1.31)

where is the power of the largest spurious tone at the DAC output. The SFDR is indicated in Fig. 1.9. SNR Psignal P_noise ---= P_signal P_noise SNDR Psignal P_nd ---= P_nd N SNDR≈6.02N+1.76 dB ENOB SNDR–1.76 6.02 ---= SFDR Psignal P_ls ---= P_ls

(26)

Multi-Tone Power Ratio

Nonlinear systems, as opposed to linear systems, cannot be fully characterized by their response to single-tone signals [13]. Therefore, the single-tone performance metrics described above are insufficient if the DAC is used in a multi-carrier application. The multi-tone power ratio (MTPR) measures the linearity of a DAC when subject to a multi-tone input. A multi-tone signal

(1.32)

for belonging to some interval , is used as an input. and are chosen such that the signal becomes a relevant test signal for a given application. The amplitudes are chosen equal for all but one, for which the amplitude is set to zero. Intermodulation caused by the DAC nonlinearities give rise to a spurious tone at the frequency for which the amplitude was set to zero. The MTPR is defined as the power ratio between one of the wanted tones and this spurious tone, as indicated in the multi-tone spectrum in Fig. 1.10.

In a single-tone test, the only relevant parameters are the amplitude and the fre-quency of the test tone. In an MTPR test, however, the degrees of freedom are higher. Besides the amplitude, the resulting MTPR is depending on which tone that has zero amplitude, and also the mutual phase differences between the other tones. Hence, it is easier to set up and interpret the result from a single-tone test. Therefore, the single-tone performance metrics are often used, even if they give insufficient information. In this work, multi-tone tests are used to some extent, Figure 1.10 Multi-tone output spectrum for a nonideal 14-bit DAC.

x n( ) c_ksin(kΩ₀n+φ_k) k

∑

= k ξ ξ Ω₀ c_k k 0 0.1 0.2 0.3 0.4 0.5 −100 −80 −60 −40 −20 0 MTPR Normalized frequency (f/f s) PSD [dB]

(27)

Converter Architectures

1.4 Converter Architectures

An overview of some different DAC architectures is given in this section. The differences between Nyquist-rate and oversampled DACs are outlined in Sec. 1.4.1. The current-steering, charge-redistribution, R-2R ladder, and resistor-string DAC architectures are discussed in Sec. 1.4.2-Sec. 1.4.5. Common to these architectures is that they perform a memory-less mapping from the digital input to the analog output. They are commonly referred to as flash or parallel convert-ers [14], since the convconvert-ersion of an input sample is performed during one clock cycle. In ∆Σ DACs, outlined in Sec. 1.4.6, noise-shaping techniques are used together with oversampling to allow the signal to be reconstructed with a flash DAC having fewer input bits than the input signal. Due to the noise shaping, most of the quantization noise caused by the additional quantization appears outside of the signal band and can, hence, be filtered out.

1.4.1 Nyquist-Rate and Oversampled Converters

According to the sampling theorem, it is required that

, (1.33)

where is the bandwidth of the signal. A data converter with just a small fraction larger than is commonly referred to as a Nyquist-rate converter [9, 11], whereas a data converter with considerably larger than is referred to as an oversampled converter [9, 11]. The oversampling ratio (OSR) is defined as

. (1.34)

There are several reasons for using oversampling. If the number of bits in a con-verter is large, the quantization noise is approximately white. Hence, the PSD of the quantization noise is approximately constant, i.e.,

. (1.35)

From (1.35), it is evident that the total noise power within the signal band ( ) is decreased if is increased. Hence, an oversampled converter has less quantization noise power within the signal band than a Nyquist-rate con-verter with the same .

f_s>2 f₀ f₀ f_s 2 f₀ f_s 2 f₀ OSR fs 2 f₀ ---= PSD_Q( )f ∆2 12 --- fs 2 ---    ⁄ ≈ f ≤ f₀ f_s ∆

(28)

Another reason for using oversampling is that it simplifies the design of the (ana-log) anti-aliasing filters for ADCs and image-rejection filters for DACs. The unfiltered output spectra for a Nyquist-rate DAC and a DAC with are shown in Fig. 1.11(a) and (b), respectively (the desired spectrum is plotted in Fig. 1.2(a)). The spectral images that appear around multiples of are better separated for the oversampled converter, since its sampling frequency is higher than that of the Nyquist-rate DAC. Further, the output of the oversampled con-verter is less distorted by the sinc weighting within the signal band, and the spec-tral images are better attenuated by the sinc weighting. Hence, requirements on the filters for attenuation of the spectral images is lower for the oversampled con-verter than for the Nyquist-rate concon-verter. The relaxed filter requirements a allows for larger design margin and/or a reduced filter order compared with the Nyquist-rate case.

1.4.2 Current-Steering DACs

The current-steering DAC, which is based on the switched-current technique [15], is suitable for high-speed applications [9, 14, 16] and, therefore, the most frequently used DAC architecture in wideband communication applications. A differential current-steering DAC is shown in Fig. 1.12. It consists of a number of weighted current sources, a number of switches, and two load resistors. Bit of a digital control word controls a switch that steer the current from the current source to one of the two load resistors. With ideal switches and current sources, the positive output current is

(1.36)

and the negative output current is

, (1.37)

where denotes the complement of . The differential output current is

. (1.38)

There are also positive, negative, and differential output voltages, which are the corresponding currents multiplied with the load resistance . In an ideal cur-rent-steering DAC, each current is given by

OSR = 2 f_s b_l l:th I₊ b_lI_l l

∑

= I_– b_lI_l l

∑

I_l l

∑

b_lI_l l

∑

– = = b_l b_l I_diff I₊–I_– 2 b_lI_l l

∑

I_l l

∑

– = = R_L I_l

(29)

where is the integer weight of the current source and is the unit current. If the digital control word represents the DAC input , i.e.,

, (1.40)

(a)

(b)

Figure 1.11 Output spectra from (a) Nyquist-rate DAC and (b) oversampled DAC. Frequency

|Y

(2

π

f)|

Output spectrum, Nyquist−rate DAC

−8f 0 −6f0 −4f0 −2f0 0 2f0 4f0 6f0 8f0 0 A Frequency |Y (2 π f)|

Output spectrum, OSR = 2

−8f 0 −6f0 −4f0 −2f0 0 2f0 4f0 6f0 8f0 0 A w_l I_unit x x b_lw_l l

∑

=

(30)

we have that

. (1.41)

The performance of a current-steering DAC is influenced by how the input is encoded to form the digital control word, and, hence, the choice of the weights . For matching purposes, a current source with weight is usually imple-mented with unit current sources connected in parallel. Commonly used architectures are the binary-weighted architecture [9], for which

, (1.42)

the thermometer-coded architecture [9], for which

for every , (1.43)

and a hybrid between the binary-weighted and the thermometer-coded architec-tures known as the segmented architecture [9, 17].

1.4.3 Charge-Redistribution DACs

The charge-redistribution DAC architecture, which is based on the switched-capacitor technique [18], is illustrated in Fig. 1.13. The charge-redistribution DAC, in contrast to the current-steering DAC, requires an operational amplifier Figure 1.12 Differential current-steering DAC architecture.

I+ I V+ V RL RL Il1 Il Il+1 bl1 bl bl+1 VDD b_lI_l l

∑

= xI_unit w_l w_l w_l w_l = 2l w_l = 1 l

(31)

Converter Architectures for proper operation. This operational amplifier limits the speed of the circuit, making the charge-redistribution DAC less suited for wideband applications than the current-steering DAC. The charges in Fig. 1.13 are given by

(1.44) and

. (1.45)

The total charge, , on all capacitor plates connected to the negative input of the operational amplifier is constant over time. is given by

, (1.46)

which, together with (1.44) and (1.45), yields

. (1.47)

In an ideal charge-redistribution DAC, each capacitance is given by

, (1.48)

where is the integer weight of the capacitor and is the unit capacitance. If the digital control word represents the input as in (1.40), then

Figure 1.13 Charge-redistribution DAC architecture.

Q_l = V_refb_lC_l Q_L = V_outC_L Q_tot Q_tot Q_tot Q_L Q_l l

∑

+ = V_out Qtot C_L --- V_ref b_lCl C_L ---l

∑

– = C_l C_l = w_lC_unit w_l C_unit x b_l1 b_l b_l+1 Ql1 Ql Ql+1 Cl Cl+1 Cl1 CL QL Vout V_ref

(32)

. (1.49) It should be noted that the circuit diagram in Fig. 1.13 only illustrates the basic principle behind charge-redistribution conversion. Since cannot be changed, one must settle with the value that results from the fabrication of the circuit. This value will be different for different circuits, and the offset voltage for the DAC cannot be controlled. Therefore, in an actual implementation of a charge-redistri-bution DAC, a more elaborate circuit structure than that in Fig. 1.13 must be used where, e.g., part of the clock cycle is used for offset-voltage compensation [11].

1.4.4 R-2R Ladder DACs

R-2R ladder networks can be utilized in different ways to perform digital-to-ana-log conversion [9, 11, 19]. An R-2R ladder DAC with current references is illus-trated in Fig. 1.14. The current flowing through the load resistor is

, (1.50)

and, hence,

. (1.51)

Hence, the R-2R ladder DAC in Fig. 1.14 is a binary-weighted DAC. A benefit of this R-2R ladder DAC, compared with a binary-weighted current-steering DAC, is that equal currents flow through all switches and, hence, it is easier to obtain good mutual matching between the individual switches. Drawbacks of the R-2R ladder architecture are that it requires high-precision linear resistors and that the use of an operational amplifier may limit the speed of the circuit.

1.4.5 Resistor-String DACs

In a resistor-string DAC [9, 11], the different output voltage levels required in an -bit DAC are created with voltage division in a resistor string, as illustrated in Fig. 1.15. The encoder maps the -bit input onto a control word where a single bit is activated. The switch controlled by this bit connects the correspond-ing node in the resistor strcorrespond-ing to the positive input of the operational amplifier that acts as a buffer. For large , the numbers of switches and resistors are large. In such cases, it is possible to use multi-stage resistor-string DACs [11, 19].

V_out Qtot C_L --- V_refCunit C_l --- x – = Q_tot I_L I_L Iref 2N–1 --- b_l2l l=0 N–1

∑

= V_out RLIref 2N–1 --- b_l2l l=0 N–1

∑

– = 2N N N x N

(33)

1.4.6∆Σ DACs

DACs utilizing∆Σ modulation [20] are different from the previously presented converter architectures in that oversampling is used in conjunction with prepro-cessing of the input in order to allow the input to be represented internally with Figure 1.14 R-2R ladder DAC architecture.

Figure 1.15 Resistor-string DAC architecture.

Iref Iref Iref Iref Iref

R R R R 2R 2R 2R RL Vout bN1 bN2 b3 b1 b0 VDD IL encoder x R R R R R V_ref Vref+ Vout

(34)

fewer bits. The quantization noise added by the extra quantization step is shaped with a feedback filter so that most of its power appears outside of the signal band. A general∆Σ modulator is shown in Fig. 1.16(a). This system is nonlinear and, consequently, difficult to analyze. The quantizer is often modeled with the addi-tion of an error signal, , as shown in Fig. 1.16(b), in order to get a linear sys-tem that is simpler to analyze. In the frequency domain, the output can be expressed in terms of the input and the quantization error as

, (1.52)

where STF is the signal transfer function and NTF is the noise transfer function. It is desired that STF is an allpass or a lowpass filter and that NTF is a highpass filter.

The shaping of the quantization noise is illustrated in Fig. 1.16(c) and (d) for a first-order modulator with a 1-bit quantizer and . For this first order modulator, we have

(1.53) and

. (1.54)

The spectrum of the 8-bit input is shown in Fig. 1.16(c), and the corresponding 1-bit output is shown in Fig. 1.16(d). The main benefit of using a ∆Σ modulator with a 1-bit output is that the output can be reconstructed with a DAC having only two quantization levels. Even if these quantization levels differ from those intended by the designer due to process variations, the INL and DNL will be 0 for all codes. Hence, the static linearity of the 1-bit DAC is perfect. Using a first-order modulator with a 1-bit quantizer requires a high OSR that often cannot be afforded in high-speed communication applications. In order to reduce the OSR, the use of multi-bit quantizers and/or higher-order modulators are required.

1.5 CMOS Technology

Complementary metal-oxide-semiconductor (CMOS) processes are popular for implementing integrated circuits. This is mainly due to low cost, but also because they enable the implementation of digital circuits with low power consumption. The word complementary refers to the fact that both NMOS and PMOS transis-tors are available. An NMOS transistor consists of heavily N-doped drain and source regions implanted in lightly P-doped silicon. The drain and source regions are separated with a gate region. The gate of the transistor consists of a sheet of

e n( ) Y z( ) X z( ) E z( ) Y z( ) = STF z( )X z( )+NTF z( )E z( ) OSR = 128 STF z( ) = 1 NTF z( ) = 1–z–1

(35)

CMOS Technology

polycrystalline silicon (poly), which is separated from the substrate with a thin layer of silicon dioxide (oxide). Free electrons in the substrate can be attracted to the region under the gate and form a conducting channel between the drain and the source by applying a proper voltage at the gate. The principle of a PMOS transistor is similar, but the type of doping used is opposite to that of the NMOS transistor.

The DAC circuits in this work have all been implemented in CMOS technology. A brief overview of the characteristics of CMOS transistors is given in this sec-tion.

1.5.1 Large-Signal Models

Simple large-signal models for CMOS transistors [11], assuming long-channel devices, are presented in this section to illustrate the basic behavior of the devices. These models are similar to that presented by Shichman and Hodges in 1968 [21]. As device sizes decrease, these models become less accurate. There-fore, circuit simulators often make use of more elaborate models to obtain results with higher accuracy, such as the BSIM3 model [22].

(a) (b)

(c) (d)

Figure 1.16 (a) General∆Σ modulator and (b) ∆Σ modulator with quantizer modeled with an added error signal. The spectra for the 8-bit input and the 1-bit output of a first-order∆Σ modulator (OSR = 128) are shown in (c) and (d), respectively.

Q linear feedback filter x(n) y(n) linear feedback filter x(n) y(n) e(n) −100 −50 0 f 0 fs/2

Frequency (log scale)

PSD [dB/Hz] Modulator input −100 −50 0 f 0 fs/2

Frequency (log scale)

PSD [dB/Hz]

(36)

A symbol for an NMOS transistor is shown in Fig. 1.17(a). It has four terminals; gate (G), source (S), drain (D), and bulk (B). In all implementations presented in this work, the bulk terminal is connected to ground for all NMOS transistors. In that case, the symbol in Fig. 1.17(b), where the bulk terminal is omitted, can be used instead. Similar symbols for PMOS transistors are shown in Fig. 1.17(c) and (d), where the omitted bulk terminal in Fig. 1.17(d) implies that the bulk is con-nected to the supply voltage ( ).

In the simple model, the transistors have three different regions of operation; the cut-off region, the linear region, and the saturation region. The approximate cur-rent-voltage relationships for NMOS and PMOS devices are listed in the follow-ing sections. The model parameters, e.g., carrier mobility and body-effect constants, for NMOS and PMOS transistor typically have different values. How-ever, we use the same notation for the two transistor types in order to avoid the use of additional indices.

NMOS Devices

An NMOS transistor operates in the cut-off region if

, (1.55)

where is the threshold voltage of the transistor. In the transistor model used

(a) (b)

(c) (d)

Figure 1.17 Device symbols for (a) four-terminal NMOS transistor, (b) NMOS transistor with the bulk connected to ground, (c) four-terminal PMOS transistor, and (d) PMOS transistor with the bulk connected the supply voltage.

V_DD VGS G S D B VBS V_DS ID G D S VSG G S D B VSB VSD ID G S D V_GS<V_T V_T

(37)

CMOS Technology (1.56) in the cut-off region. In reality, a small subthreshold current flows in the device. When is increased such that

, (1.57)

a channel of free electrons is formed under the gate and the transistor is conduct-ing current.

In the linear operation region,

, (1.58)

where is the effective gate-to-source voltage. The current is modeled with

, (1.59)

where is the electron mobility and is the oxide capacitance per unit area. and are the width and the length of the transistor, respectively.

The saturation region is characterized by the relationship

(1.60) and the current in the saturation region is modeled with

. (1.61)

is a parameter known as the channel-length modulation parameter and is roughly proportional to . Due to the body effect, the threshold voltage of the transistor is dependent on the bulk-to-source voltage according to

, (1.62)

where is the threshold voltage at zero . The built-in Fermi potential, , and the body-effect constant, , are process dependent parameters.

PMOS Devices

A PMOS transistor in the cut-off region is characterized by

I_D = 0 V_GS V_GS≥V_T V_DS<V_GS–V_T = V_eff V_eff I_D I_D µ₀C_oxW L --- V_effV_DS VDS 2 2 ---–     = µ₀ C_ox W L V_DS≥V_eff I_D µ0Cox 2 ---W L ---V_eff2 (1+λ V( _DS–V_eff)) = λ 1 L⁄ V_T = V_{T 0}_, +γ( 2Φ_F –V_BS– 2Φ_F ) V_{T 0}_, V_BS Φ_F γ

(38)

, (1.63) and the drain current is modeled with

. (1.64)

A PMOS transistor is conducting current when

. (1.65)

In the linear region,

, (1.66)

where is the effective source-to-gate voltage. The current is modeled with

, (1.67)

where is the hole mobility, which is typically a factor three or so lower than the electron mobility for an NMOS transistor.

The transistor operates in the saturation region when

, (1.68)

and the current is modeled with

. (1.69)

The threshold voltage, which is negative, varies with the source-to-bulk voltage according to

. (1.70)

1.5.2 Small-Signal Models

The models presented in Sec. 1.5.1 have nonlinear relationships between currents and voltages. Therefore, the analysis of a circuit containing more than just a few transistors becomes complicated if these models are used. Linearized models, or small-signal models, are commonly used in order to analyze the influence of a small perturbation in some voltage or current [11].

V_SG< V_T I_D = 0 V_SG≥ V_T V_SD<V_SG– V_T = V_eff V_eff I_D µ₀C_oxW L --- V_effV_SD VSD 2 2 ---–     = µ₀ V_SD≥V_eff I_D µ0Cox 2 ---W L ---V_eff2 (1+λ V( _SD–V_eff)) = V_T = V_{T 0}_, –γ( 2Φ_F –V_SB– 2Φ_F )

(39)

CMOS Technology A g-parameter small-signal model of an NMOS transistor is shown in Fig. 1.18(a). The current and the voltages shown in the figure are the small signal quantities, i.e., the deviations from the dc levels. The small-signal parameters are given by

, (1.71)

, (1.72)

and

, (1.73)

where the index Q indicates that the partial derivatives are evaluated in the quies-cent point. For both the linear region and the saturation region, we have

. (1.74)

In analog circuits, the transistors are usually biased to operate in the saturation region, because the transconductance, , is higher and the output conductance, , is lower than in the linear region for the same . In the saturation region, we have

(a)

(b)

Figure 1.18 Simple small-signal models for (a) NMOS and (b) PMOS transistors.

g_m V_GS ∂ ∂I_D Q = g_mbs V_BS ∂ ∂I_D Q = g_ds V_DS ∂ ∂I_D Q = g_mbs γ gm 2 2Φ_F –V_BS ---= g_m g_ds V_GS g_m·v_gs g_mbs·v_bs g_ds v_gs v_ds id D S G gm·vsg gmsb·vsb gds id vsd vsg G D S

(40)

(1.75) and

. (1.76)

For a PMOS transistor,

, (1.77)

in both the linear region and the saturation region. Further, in the saturation region, we have

(1.78) and

. (1.79)

1.5.3 Parasitics

The transistor models discussed in Sec. 1.5.1 and Sec. 1.5.2 model the transistor behavior for low signal frequencies. For higher frequencies, the transistor behav-ior is also influenced by capacitive parasitics [11]. Simple small-signal models of NMOS and PMOS transistors with parasitic capacitances included are shown in Fig. 1.19(a) and (b), respectively. In Fig. 1.19, it is assumed that the bulk termi-nals are connected to small-signal ground, i.e., constant voltages. The source-to-bulk capacitance, , and the drain-to-bulk capacitance, , are depletion capacitances in the reverse-biased p-n junctions between the source and the bulk and the drain and the bulk, respectively. They also include the depletion capaci-tance between the conducting channel and the bulk. In the saturation region, the channel is pinched off at the drain side, and the channel-to-bulk capacitance is entirely associated with the source-to-bulk capacitance [11]. The gate-to-source capacitance, , and the gate-to-drain capacitance, , are due to the thin oxide layer between the gate and the substrate. They consist of an overlap capac-itance, caused by a small overlap between the gate and the diffused drain and source areas, and of a capacitance between the gate and the channel. Due to that the channel is pinched off in the saturation region, the gate-to-channel capaci-tance is entirely associated with the gate-to-source capacicapaci-tance.

g_m 2µ₀C_oxW L ---I_D ≈ g_ds≈λI_D g_msb γ gm 2 2Φ_F –V_SB ---= g_m 2µ₀C_oxW L ---I_D ≈ g_ds≈λI_D C_SB C_DB C_GS C_GD

(41)

CMOS Technology

1.5.4 Device Matching

Due to variations in, e.g., oxide thickness and doping concentrations, the parame-ters of a manufactured device (transistor, resistor, capacitor, etc.) deviate from the nominal values. Therefore, two devices on the same die that are designed to be identical have different parameter values. This is referred to as mismatch or matching errors. Two nominally identical rectangular devices are shown in Fig. 1.20(a). The rectangles may represent, e.g., an MOS transistor gate, a paral-lel-plate capacitor, or a resistor. The devices have a nominal length , a nominal width , and are separated by a distance . Much of research on MOS match-ing properties is based on the work presented by Pelgrom in [23]. In [23], the processes causing mismatch in a parameter are divided into two different classes. The processes in the first class cause short-distance variations, or local variations, for which the correlation distance is much smaller than the device dimensions. For this class, the resulting matching errors are independent of the distance between the devices. However, parameters typically show a circular value distribution over a wafer, as illustrated in Fig. 1.20(b). The processes in the second class give rise to these global variations. Over a small area (e.g., a chip), the global parameter variations are often approximated by a plane (i.e., the

first-(a)

(b)

Figure 1.19 Simple small-signal models for (a) NMOS and (b) PMOS transistors with para-sitic capacitances included.

gm·vgs gmbs·vbs gds D S G CGS CGD C_DB CSB gm·vsg gmsb·vsb gds G D S CSB CDB CGD CGS L W D P

(42)

order Taylor expansion) as indicated in Fig. 1.20(b). The global variations are, therefore, also referred to in terms of parameter gradients or as linearly graded errors.

Let denote the difference in the value of parameter between the two devices. According to [23], can be modeled as a stochastic variable with Gaussian distribution having zero expectation value and variance

, (1.80)

where and are proportionality constants for parameter . A further anal-ysis in [23], using the simple square-law model for a MOS device in saturation, yields that the difference in drain current between two transistors has a Gaussian distribution and that

(a)

(b)

Figure 1.20 (a) Two nominally identical rectangular devices and (b) illustration of circular parameter variation over a wafer.

W L D ∆P P ∆P σ2₍_∆P₎ AP2 WL ---+S_P2D2 = A_P S_P P

(43)

CMOS Technology

, (1.81)

where

(1.82) and denotes the variance operator. Having well-matched drain currents is important in order to obtain high accuracy in a current-steering DAC. Some gen-eral guidelines for obtaining good matching can be extracted from (1.80) and (1.81). For example, the local variations have less influence on the parameters for transistors with large areas than for transistors with small areas, and the influence of the global variations is decreased if the devices are placed closer together. There is, of course, a trade-off, since increasing the device dimensions also causes an increase in the minimum required distance between two devices. From (1.81), it can be concluded that increasing the effective gate-to-source voltage decreases the influence of variations in the threshold voltage.

In [24], it is argued that (1.80) is applied incorrectly to the threshold voltage in the analysis in [23], and a mismatch model, based on the BSIM3 MOS model, that better fits observed data is derived. However, the general guidelines for tran-sistor matching that were observed from (1.80) and (1.81) are still valid with this more accurate mismatch model.

Apart from device geometries and biasing, there are other factors that influence the matching accuracy. For example, wire routing in low-level metal layers over transistors having critical matching requirements should be avoided [25]. More-over, it is important that the devices have the same geometrical boundary condi-tions. Therefore, an array of transistors or capacitors is often surrounded by a frame of unused dummy elements that ensures that the outer devices in the array have the same surroundings as the inner devices.

1.5.5 CMOS Transistors in Current-Steering DACs

Two critical basic building blocks used in current-steering DACs are the current source and the current switch. An overview on how these building blocks can be implemented in CMOS technology is given in this section.

σ2 _I D ( ) I_D2 --- 4σ 2 _V T ( ) V_GS–V_T ( ) --- σ2( )β β2 ---+ = β µ0Cox W L ---= σ2_{( )}_·

(44)

The Current Source

The current delivered by an ideal current source is independent of the voltage drop across it, i.e., it has infinite output impedance. A current source imple-mented with a single PMOS transistor, M_source, is shown in Fig. 1.21(a). For the simple transistor model, the output resistance of this current source is

. (1.83)

As discussed in Sec. 1.5.2, is smaller (i.e., is larger) in the saturation region than in the linear region. Hence, in order to obtain a high output resis-tance, M_sourceshould be biased in the saturation region. For some applications, the obtainable output resistance using a single transistor is too low. Increased out-put resistance can be obtained with the use of a cascode transistor [11], as illus-trated in Fig. 1.21(b). The output resistance for the current source in Fig. 1.21(b) is approximately

. (1.84)

Usually, for a transistor biased in the saturation region. Hence, the out-put resistance for the current source using a cascode transistor is much higher than for a single-transistor current source. For higher frequencies, the magnitude of the output impedance is limited by capacitive parasitics. The output imped-ance of a current source is approximately

, (1.85)

where is the effective capacitance to ground associated with the output node of the current source. For the current source in Fig. 1.21(a), is approxi-mately a parallel connection of and for transistor M_source. For the cur-rent source in Fig. 1.21(b), is approximately a parallel connection of and for transistor M_casc, the parasitics in transistor M_sourceare suppressed due to the use of a cascode transistor. If the widths of M_source and M_casc are approximately the same, then is approximately the same for both types of current source. Hence, their output impedances are approximately the same for high frequencies. R_out 1 g_{ds source}_, ---= g_ds R_out R_out 1 g_{ds source}_, ---gm casc, g_{ds casc}_, ---≈ g_m»g_ds Z_out 1 R_out ---+sC_out    –1 = C_out C_out C_GD C_DB C_out C_GD C_DB C_out

(45)

CMOS Technology

The Switch

A differential current switch can, e.g., be implemented with two PMOS transis-tors, as depicted in Fig. 1.22(a). If both transistors are simultaneously cut off, charge is accumulated at the output node of the current source. This results in severe glitches in the transient response of the DAC when one of the transistors in the switch starts to conduct. Therefore, when the state of the switch is changed, it is important to have a short moment when both transistors are conducting in order to avoid charge accumulation [26]. This is obtained with the nonoverlap-ping control signals shown in Fig. 1.22(b). If NMOS transistors are used in the switch, the control signals should instead be overlapping in order to avoid having both transistors simultaneously off.

(a) (b)

Figure 1.21 PMOS current source implemented (a) with a single transistor and (b) with a cascode transistor.

(a) (b)

Figure 1.22 (a) Differential switch implemented with two PMOS transistors and (b) proper control signals for the switch in (a).

Msource Vbias Iout Vbias Vcasc Msource Mcasc Iout I_in I+ I Q+ Q low high Voltage Time Q + Q −

Modeling and Implementation of Current-Steering Digital-to-Analog Converters

M

ODELING AND

I

MPLEMENTATION OF

C

URRENT

-S

TEERING

D

IGITAL

-

TO

-A

NALOG

C

ONVERTERS

K Ola Andersson

Digital-to-Analog Converters

Abstract

Acknowledgments

Contents

Chapter 1

Introduction . . . 1

Chapter 2

Modeling of Current-Steering DACs . . . 45

Chapter 3

Digital Encoding in Current-Steering DACs . . . 93

Chapter 4

Correction and Compensation of Errors . . . 117

Chapter 5

Test-Chip Implementations . . . 139

Chapter 6

Conclusions . . . 171

1 Introduction

1.1 Digital-to-Analog Conversion

∑

∑

∑

∑

∑

∑

∑

∑

1.2 Telecommunication Applications

∫

∫

∑

∑

1.3 Performance Metrics

∑

1.4 Converter Architectures

∑

∑

∑

∑

∑

∑

∑

∑

∑

∑

∑

∑

1.5 CMOS Technology