EVALUATION OF A LOW-POWER
RANDOM ACCESS MEMORY
GENERATOR
Master thesis in Electronics Systems at Linköping University
by
Kameswar Rao Vaddina
EVALUATION OF A LOW-POWER
RANDOM ACCESS MEMORY
GENERATOR
Master thesis in Electronics Systems at Linköping University
by
Kameswar Rao Vaddina
Reg nr: LiTH-ISY-EX-06/3976--SE
Supervisor: Oscar Gustafsson and Kenny Johansson Examiner: Prof. Lars Wanhammar
Presentation Date 2006-11-16
Publishing Date (Electronic version) 2006-11-27
Division of Electronics Systems Department of Electrical Engineering
URL, Electronic Version http://www.ep.liu.se
Publication Title
Evaluation of a Low-Power Random Access Memory Generator Author(s)
Kameswar Rao Vaddina
Abstract
In this work, an existing RAM generator is analysed and evaluated. Some of the aspects that were considered in the evaluation are the optimization of the basic SRAM cell, how the RAM generator can be ported to newer technology’s, automating the simulation process and the creation of the workflow for the energy model.
One of the main focus of this thesis work is to optimize the basic SRAM cell. The SRAM cell which is used in the RAM generator is not optimized for area nor power. A compact layout is suggested which saves a lot of area and power. The technology that is used to create the RAM generator is old and a suitable way to port it to newer technology has also been found.
To create an energy model one has to simulate a lot of memories with a lot of data. This cannot be done in the traditional way of simulating circuits using the GUI. Hence an automation procedure has been suggested which can be made to work to create energy models by simulating the memories comprehensively.
Finally, basic ground work has been initiated by creating a workflow for the creation of the energy model.
Number of pages: 32
Keywords
SRAM, generator, low-power, layout, NanoSim, SKILL, OCEAN, Automation, Layout Optimization, Energy Model, Technology,
Language X English
Other (specify below)
Number of Pages 32 Type of Publication Licentiate thesis X Degree thesis Thesis C-level Thesis D-level Report
Other (specify below)
ISBN (Licentiate thesis)
ISRN: LiTH-ISY-EX-06/3976--SE Title of series (Licentiate thesis)
ABSTRACT
In this work, an existing RAM generator is analysed and evaluated. Some of the aspects that were considered in the evaluation are the optimization of the basic SRAM cell, how the RAM generator can be ported to newer technolo-gys, automating the simulation process and the creation of the workflow for the energy model.
One of the main focus of this thesis work is to optimize the basic SRAM cell. The SRAM cell which is used in the RAM generator is not optimized for area nor power. A compact layout is suggested which saves a lot of area and power. The technology that is used to create the RAM generator is old and a suitable way to port it to newer technology has also been found.
To create an energy model one has to simulate a lot of memories with a lot of data. This cannot be done in the traditional way of simulating circuits using the GUI. Hence an automation procedure has been suggested which can be made to work to create energy models by simulating the memories compre-hensively.
Finally, basic ground work has been initiated by creating a workflow for the creation of the energy model.
AKNOWLEDGEMENTS
Time has flown by very fast while doing this thesis work. One of the reasons is that the topic that I worked on is an exciting one and has a lot of scope to improvise in many different ways. I would like to thank my examiner Prof. Lars Wanhammar who suggested me such an exciting topic.
A very big thanks to my supervisors Dr. Oscar Gustafsson and Kenny Johans-son who were always there with their excellent suggestions and comments on various things relating to the thesis work. I would also like to thank Emil Hjalmarson, Henrik Fredriksson, and Tekn. Lic. Martin Hansson for their suggestions on various things from setting up the environment to various other analog questions.
This is the first oppurtunity that I have got to thank my family and I would not let go. For all their moral, intellectual and spiritual support all through my life I thank my parents Narasimha Murthy Vaddina and Kalavathi, brother Pra-kash Rao Vaddina, and sister Sujatha Vaddina.
I would also thank all the people whom I met in the course of my life and who have inspired, entertained and enlightened me with their wit, dumb jokes and their expertise in various fields respectively. Reading and opposing a thesis can hardly be done for fun. So, a very big thanks to my opponent Raghu Kishore Pendyala. A big thanks to my roommate Amol Kumar Singh who allowed me to concentrate on writing my thesis report while he was cooking food at home for me.
Finally, I would like to thank the generous Swedish education system which has provided me with a golden oppurtunity to study in one of the best institu-tion of higher learning in europe. I would like to thank all the Swedes for being such a great and gracious hosts for us all international students.
iii
TABLE OF CONTENTS
1
Introduction
1
1.1 Background . . . 1
1.1.1 User’s Knowledge Level . . . 3
1.2 RAM Generator . . . 3
1.2.1 What is a RAM Generator . . . 3
1.2.2 What is a Schematic Generator . . . 4
1.2.3 Zero-Aware Asymmetric SRAM Cell . . . 4
1.3 List of Abbreviations . . . 5
2
Tools and Softwares
6
2.1 The electronic Design Tool Cadence . . . 62.1.1 Views in Cadence . . . 6
2.2 Cadence Spectre. . . 7
2.3 NANOSIM Simulator . . . 7
2.4 SKILL Programming Language . . . 8
2.5 OCEAN Scripting Language . . . 8
3
Technology Aspects
10
3.1 Process Description . . . 103.2 Effects of the Change in Technology. . . 11
3.2.1 Grid Problems . . . 11
3.2.2 ‘45 Degree’ Path Problems . . . 12
3.2.3 DRC Errors . . . 12
3.3 Some Good News . . . 12
4
Layout Optimization
13
4.1 Efficient Layout of an SRAM Cell . . . 134.2 Area Comparison of the SRAM Cells . . . 15
4.3 Power Comparison of the SRAM Cells . . . 17
5
Automation
18
5.1 Using OCEAN to Simulate Circuits . . . 195.2 More Suggestions to Automate . . . 20
6
Energy Model
22
6.1 Spectre versus Nanosim . . . 247
Conclusions
26
7.1 Compact SRAM Cell . . . 267.2 Effects of the Change in Technology. . . 27
7.3 Automating and Creation of Energy Model. . . 27
iv
References
29
1
1
INTRODUCTION
As the need for mobile solutions in computing, communications and enter-tainment increases with more and more people taking to it, there is an increased demand for devices which consume less power. Fast data access and retrieval is also on the top of the list for most consumers and corporates alike. Data is stored on high-speed memories for fast access. Memories in mobile devices often contribute to a large portion of the total power con-sumed. Hence, using low-power memories in the design yields a large reduc-tion of the total power consumpreduc-tion.
1.1 BACKGROUND
This thesis work has been carried out in the division of Electronics Systems at Linköping Institute of Technology. The division focuses its research on design and implementation of signal processing and communication systems. This research concentrates on digital signal processing (DSP) systems, ana-log and digital filters, as well as mixed signal circuits. In DSP systems, ran-dom access memories (RAM) are often needed and the division of Electronics Systems needs to have access to low-power RAMs of different sizes. It is within this framework that a RAM generator, i.e., a program that creates a layout of a RAM of a specified size, with proper inputs from the user has been developed. The memories generated by the tool will be embed-ded on-chip together with other circuits.
2 Evaluation of Low-Power RAM generator
The development of the generator was started as a thesis work by Deborah Capello in 2002/2003 [1]. She was later employed for about one year by the Electronics Systems division to extend her work. The memory generator has been constructed by keeping in mind that the generated memory shall respond to some basic requirements that have been set, like size, power, flexi-bility, memory control, speed, and chip area.
She developed all the circuit parts except the Block Decoder. Initially, the RAM generator was not supposed to generate memory layouts automatically due to the large amount of design considerations at this stage. But the idea was to generate memories with some manual intervention first and make it workable, and then the RAM generator can be further developed to decrease this manual intervention. Though most of the parts that are being generated by the RAM generator are workable, there is a lot of manual intervention on the part of the user that is required inorder to generate the final layout of the memory.
The memories that are being generated by the RAM generator have not been tested because of the complexities involved in testing such large circuits. However, tests on various circuit parts of the memories have been carried out. The cadence tool used for the implementation has powerful features for both analog and digital electronics design, but has stability problems with large designs.
Later on, Markus Åkerman [2] was assigned to add some new features to the RAM generator. Some of those features are as follows.
❑ To complete the Block Decoder.
❑ To evaluate and implement a new SRAM cell, called Zero-Aware
Asym-metric SRAM cell.
❑ To create a schematic generator.
Markus Åkerman was able to generate a memory with 2048 words of 16 bits word length, but had to correct many errors, mainly by hand in this memory. However, he could not test the complete memory. This memory can be used as a template [2] for future developers and testers who would like to test the RAM generator.
Chapter 1 – Introduction 3
1.1.1 USER’S KNOWLEDGE LEVEL
The reader of this thesis is expected to have a basic technical knowledge of electronic design. It is furthermore advised to read [1], [2], [3], and [4] prior to this thesis report if you want to know more about the RAM generator, schematic generator and zero-aware SRAM cell. In the following some of these things are briefly discussed.
1.2 RAM GENERATOR
1.2.1 WHAT IS A RAM GENERATOR
The RAM generator is a program (actually a set of several files) written in SKILL programming language (see Section 2.3). This generator uses some basic blocks like SRAM cell, buffers, decoders etc., which have been made by hand (these blocks are tested and free from DRC errors) and can be used in layouts (by placing them recursively). The layout is done by the RAM gener-ator.
Limitations of the RAM Generator
❑ The number of words can only be powers of two, that is 2, 4, 8,...., in
order to simplify the addressing of the memories and their architecture.
❑ The range of words may vary from 2k to 10k, but the memory generator
will be optimised to work best when designing memories in the lower part of this range, that is, up to a few k words.
❑ The number of bits in each word can take all possible values between 8
and 48.
There are also other limitations, which are not data related, but are discussed in detail in the Users Manual [4] and Developers Manual [3].
Some of the parameters that are needed
The parameters that are needed to generate the memory are Buffer speed, Block Decoder Speed and Memory Load.
There are various limitations on these values and the user is only allowed to choose from a set of predetermined values provided by the developer.
4 Evaluation of Low-Power RAM generator
Additional things to get the RAM generator to work
The RAM generator does not generate the memories in a straight forward way. There are a lot of intermediate stages where it needs the user’s interven-tion. For example the user has to manually compute the resistances and capacitances of wires in between buffers, add the values to a file, and then regenerate the memory. Some other things are adjusting bus widths, creation of a Block Decoder unit, connecting all blocks to VDD and GND, creating the Control unit block, and then testing the Partition, Buffer, and I/O blocks.
1.2.2 WHAT IS A SCHEMATIC GENERATOR
This generator generates schematics of the different memort blocks. The pur-pose of the schematic generator is to obtain a better overview of the memory circuit and to make it easy to do circuit level simulations and Layout versus Schematics (LVS) checks. Like the layout files, the schematics for the basic blocks have been made by hand. The generator then duplicates and connects different parts together depending on the memory specification. The sche-matic generator generates complete schesche-matics without any manual interven-tion.
1.2.3 ZERO-AWARE ASYMMETRIC SRAM CELL
According to the research done on the cache memorys it has been found that a zero is written between 69 and 94 percentage of the times. Therefore, the zero-aware SRAM cell, using an asymmetric inverter pair, reduces the amount of power consumption when writing a zero to the memory. The basic idea behind this is to reduce the number of times that the bitlines in the mem-ory array have to be recharged [11].
In this thesis the evaluation of a low-power random access memory generator has been done. The things that I have looked into are as follows.
❑ Optimization: Whether the basic cells that are used in generating large
RAM layouts are optimised for area and power?
❑ Technology Aspects: Can the RAM generator be ported to newer
technol-ogys? How this can be acheived?
Chapter 1 – Introduction 5
part. This saves a lot of time of the tester and designer of the energy model.
❑ Energy Model: To find a suitable way to create an energy model that
computes the amount of energy consumed by the memory when writing and when reading from the memory respectively.
1.3 LIST OF ABBREVIATIONS
DSP Digital Signal Processing RAM Random Access Memory DRC Design Rule Check LVS Layout vs Schematic
SRAM Static Random Access Memory
SPICE Simulation Program with Integrated Circuits Emphasis OCEAN Open Command Environment for ANalysis
6 Evaluation of Low-Power RAM generator
2
TOOLS AND SOFTWARES
In this chapter we introduce the tools that have been used in this work as well as in [1] and [2].
2.1 THE ELECTRONIC DESIGN TOOL CADENCE
The tool that have been used in this project is the Cadence electronics design package, which is the standard tool to generate and test layouts both in the industry and in the academia.
2.1.1 VIEWS IN CADENCE
In Cadence, a circuit can be described in many different views, each with its own significance. Some of the most important views that have been used in this project are as follows.
SCHEMATIC VIEW
The schematic is a view where symbols are used to represent circuits or indi-vidual circuit parts. These symbols can then be connected by drawing wires, placing pins, and connected to each other making a complete circuit with all the inputs, outputs, supply sources etc. The functionality of the circuit can then be tested by extracting the netlist and running a simulation using the
Chapter 2 – Tools and Softwares 7
Affirma simulation tool. One of the main advantages with the schematic is that the circuits and circuit parts can easily be created and tested.
LAYOUT VIEW
Layout view is where different layers of different materials that are being used in that particular technology is shown with proper sizes, shapes, and positions. When the schematic is made and its functionality is tested and ver-ified, then one goes into creating a layout using the schematic as a template. Each object in the layout can be given a unique name, so that it can easily be identified. Furthermore, each of these objects is usually assigned a database number, so that it can be identified by the software.
There are set of rules and guidelines called DRC rules, which are being pro-vided by the vendor of the technology. The layout should conform to those rules so that it can be fabricated.
2.2 CADENCE SPECTRE
This is the Cadence version of the SPICE simulator. Spectre lets us simulate different behaviours of the circuit and gives very accurate results. Simulating large circuits with Spectre is not feasible as they take a long time to run.
2.3 NANOSIM SIMULATOR
NanoSim is a fast-SPICE event driven, power simulator and analysis tool for CMOS and BiCMOS circuit designs. NanoSim’s accurate power and current measurements and extensive diagnosis capabilities enable us to successfully design for low power. The power analysis simulation of very large circuits like an SRAM with a tool like Spectre would take many days and is, hence, not feasible. So, a lot of time can be saved by using NanoSim. One can set different accuracy levels for NanoSim. As always, the more the accuracy the more time it is going to take to simulate the design.
8 Evaluation of Low-Power RAM generator
2.4 SKILL PROGRAMMING LANGUAGE
SKILL is a high level programming language based on LISP (which is the favoured programming language for research in Artificial Intelligence) and improved with some C-like commands and features. SKILL programs can immediately be executed within the Cadence environment. The Cadence environment has been created with SKILL.
SKILL allows users to write scripts and perform any task within the Cadence environment. One can use SKILL to create circuits, schematics, layouts, and test them.
All the objects that are created within the Cadence Virtuoso environment (design platform) are given a specific database ID. SKILL uses this database ID to access that particular object and perform operations (like resizing, aligning, placing, changing properties, shapes, rotating it etc.) on that object. SKILL is more effective for repetitive tasks. For example, if one wants to resize or scale the poly layers on a very large circuit he can write a SKILL program to do that, instead of manually sizing each and every poly layer.
2.5 OCEAN SCRIPTING LANGUAGE
OCEAN stands for Open Command Environment for ANalysis. OCEAN can be used to setup, simulate, and analyse circuit data, all from the command prompt without opening a GUI.
Typically one can use Analog circuit design environment when creating cir-cuits (in composer). After the circuit has the required performance, then OCEAN can be used to test the circuit under a variety of conditions. OCEAN lets us to run repeatedly to verify the circuit performance, run longer analysis and Corner cases [12].
Doing so will be a fast and effective way to get the results. OCEAN can be combined with SKILL and other scripting languages like Perl/TCL.
Chapter 2 – Tools and Softwares 9
10 Evaluation of Low-Power RAM generator
3
TECHNOLOGY ASPECTS
A chip can be made with different process technologies and with different characteristics. In newer process technologies the geometrics are often smaller than the older ones. The transistors, substrate contacts and wires all become smaller, and, hence, the same circuitry can be accommodated into a much smaller chip area. In this chapter I have analysed the effects that the change in technology, from older to newer, would have on the RAM genera-tor.
3.1 PROCESS DESCRIPTION
The technology that is being used for the RAM generator is Thomson’s (now ST Microelectronics) 0.18 m HCMOS8D process and the VDD being 1.55 V, which implies that the process is a low power one. But the generator is meant to be able to be suited to newer processes as well, with few changes to the structure and by substituting the basic blocks. This particular technology is old and almost no one in the Electronic Systems or Electronic Devices divi-sions is using it right now, which made working with this technology a big challenge.
Chapter 3 – Technology Aspects 11
3.2 EFFECTS OF THE CHANGE IN TECHNOLOGY
One of the main tasks that was given to me was to analyse, the effects that the change in technology would have on the RAM generator. Some of the things that I have considered are as follows.
❑ Will the RAM generator work with the change in technology?
❑ What changes has to be done in the RAM generator to make it work for
the newer technologies?
The following two are generic thumb rules for any circuit in the layout level, which has to be ported to a newer technology.
❑ If the same devices are available in the new technology, then the aspect
ratios are kept the same. In other words, shrink the geometry by the shrink factor, change the mult factor of the devices if the new technology has limitations in maximum width.
❑ For the devices which are there in the old technology, but the new
tech-nology’s foundry does not have it, you need to look for closest device characteristics (through simulation) and compare the device strength with the desired aspect ratio. Extend it for resistances, metals etc.
Things that one has to keep in mind are discussed in the following.
3.2.1 GRID PROBLEMS
Any process has a technology grid to which all the objects must align. The size of this grid will be less in the newer technologies compared to the older ones. So placing/re-laying out the objects without getting any grid errors is a big challenge as many objects now does not lie on the new grid. This can be solved by scaling the design to a new grid resolution, by adjusting the ratio of database units to user units. Cadence supplies with a scale tool called “scale”. One has to keep in mind that scaling does not work on pcells (the cells which have been instantiated in the layout).
12 Evaluation of Low-Power RAM generator
3.2.2 ‘45 DEGREE’ PATH PROBLEMS
Sometimes if the layout has paths with 45 degree angles, moving such a lay-out from one technology to a new technology will give rise to a lot of grid errors. This can be solved by using SKILL code that replaces 45 degree paths with polygons.
3.2.3 DRC ERRORS
In newer processes, the geometrics are often smaller than the older processes, which introduces a lot of DRC errors when moving from older to a newer process technology. This is a major problem and there is no easy solution to this. One can write a SKILL program that decreases the geometrics of the layout. But care must be taken, so that this does not introduce new DRC errors.
3.3 SOME GOOD NEWS
As all basic blocks that have been used to create the RAM generator are man-ually created, a process change will probably imply that they easily can be re-layouted again in the newer technology. The SKILL code will take care of the rest with some minor modifications.
Chapter 4 – Layout Optimization 13
4
LAYOUT OPTIMIZATION
The SRAM cell that is being used to generate memories is not efficiently layed out. Hence, the cells a lot of area. Some of the fundamental rules, which can be followed while doing layouts so that it consumes less area and power, have not been followed. So this was the motivation for my work on this, where in I have designed a layout of the SRAM cell in a compact way. Some of the results of this are presented in this chapter.
4.1 EFFICIENT LAYOUT OF AN SRAM CELL
The SRAM cell that has been used by the RAM generator is not optimised for area and nor for power consumption. The layout of the SRAM cell that was originally used by the RAM generator is shown in Fig. 4.1.
14 Evaluation of Low-Power RAM generator
Figure 4.1: Original SRAM cell used by the RAM generator.
The SRAM cell that I have designed, which consumes less area compared to the original one, is shown in Fig. 4.2.
Chapter 4 – Layout Optimization 15
Figure 4.2: The compact version of the SRAM cell.
The compact cell that is shown in Fig. 4.2 has three transistors with only one contact, as I have found that those contacts are redundant and will only increase the capacitance, and, hence, the power consumption. Due to some unforeseen grid errors I have used poly polygons instead of a poly path. The poly polygons have been merged as well.
4.2 AREA COMPARISON OF THE SRAM CELLS
Table 4.1 shows the area comparison of the original SRAM cell used in the RAM generator with the new, compact SRAM cell designed by me.
16 Evaluation of Low-Power RAM generator
The Fig. 4.3 shows the two SRAM cells on the same scale. This gives a fairly good idea on how much smaller the compact SRAM cell is when compared to the original SRAM cell.
Figure 4.3: Original SRAM cell versus Compact SRAM cell
One can still reduce the area, and, hence, the capacitance and the power by laying out the SRAM cell according to the state of the art technology cur-rently available. Fig. 4.3 shows the state of the art six transistor SRAM cell of 0.57 m2 at the poly layer [10]. Though this is in 60nm process, it would give a fairly good idea on how our RAM cell can be layed out.
Original
SRAM cell
Compact
SRAM cell
Percentage
Reduction
28 m
218.5 m
234%
Table 4.1: Area comparison of the SRAM cells.
µ µ
Chapter 4 – Layout Optimization 17
Figure 4.4: 0.57 m2, six transistor SRAM cell at poly layer [10].
4.3 POWER COMPARISON OF THE SRAM CELLS
A power analysis was also done to find out how much power that can be saved by the new compact layout. The results are given in Table 4.2.
As can be seen from above that there is a 77% reduction in the power con-sumed when writing a ‘1’. This is a significant reduction in power. It is not known why there is an increase of 12% in the power consumption when writ-ing a ‘0’. Nevertheless, the results show that a significant amount of power can be saved by laying out the SRAM cell in a compact one.
Original
SRAM cell
Compact
SRAM cell
Percentage
Reduction
Writing a ‘1’
11.66 W
2.635 W
77%
Writing a ‘0’
2.09 W
2.375 W
-12%
Reading a ‘1’
5.113 W
2.904 W
43%
Reading a ‘0’
2.762 W
2.111 W
23%
Tabel 4.2: Power comparison of the SRAM cells.
µ
µ µ
µ µ
µ µ
18 Evaluation of Low-Power RAM generator
5
AUTOMATION
Generating memories is just one part of the story. The second part comes into the picture when one needs to simulate those memories. Different types of simulations that can be done are:
1) To check if the memories are properly working or not.
2) To compute the power consumption or creating an energy model for a particular memory to see how much power that is consumed when writing and when reading from it respectively.
Consider the following situations.
1) Suppose that a user wants to test the memory circuit with a set of data, by repeatedly changing the hamming distance (the number of positions for which the corresponding digits are different between 2 data words). or
2) The user wants to compute the energy consumed by the memory, and he is using Spectre/NanoSim to do that. There are various accuracy set-tings that one can use to obtain the power consumption. If the user feels that the power consumption is not accurate enough or he would want to refine it to a higher accuracy then he has to do the simulations all over again.
Chapter 5 – Automation 19
The two cases above are perfect scenarios where automating the tasks would considerably reduce the amount of time and/or repeating trivial tasks over and over again.
Hence, automation has been one of the major requirements of this project. This is solved by using an OCEAN (a part of Cadence’s SKILL programming language) script, which performs tasks like starting the simulator, selecting the design for simulation, supplying modelfile list variables, selecting the result directories, performing the required analysis, selecting different results and writing those results in different files for further analysis. All of this is done from the command prompt, without starting the tool manually. The advantage of doing this process from the command prompt is that it is much faster than doing it manually, and we can do all the tasks on more than one circuit at a time.
5.1 USING OCEAN TO SIMULATE CIRCUITS
In Fig. 5.1 an example code of OCEAN, is shown where in one can use the netlist created to initiate a simulation and to get the output results.
20 Evaluation of Low-Power RAM generator
The data (for example out0.dat) that we obtain is illustrated in Fig. 5.2.
Figure 5.2: The output data format.
5.2 MORE SUGGESTIONS TO AUTOMATE
Instead of using ‘Vpulse’ (pulse voltage source) we can use Vpwlf (where pwl stands for piece wise linear, V for voltage and f for file). That is, Vpwlf sources accept files as their inputs, which are of the time-voltage form as shown in Fig. 5.3.
Chapter 5 – Automation 21
These PWL files can easily be created with MATLAB.
By using Vpwlf sources we can simulate more test cases than by using the traditional sources because we can stream input data much faster using files to the inputs of the design under test.
22 Evaluation of Low-Power RAM generator
6
ENERGY MODEL
One of the major requirements of this project is to analyse how one can create an energy model of the RAM generator. I have given it a start by analysing the choice of the simulator one can use in order to create an energy model. The energy model should be able to provide an estimate of the power con-sumption based on input parameters such as data wordlength and memory size (while writing into or when reading from). Furthermore, as the memories are designed using several blocks, the effect of the aspect ratio (which is the ratio of the number of rows to the number of columns of the memory) of the memories can also be tested.
An interesting fact to note is that a square RAM will consume less power compared to the rectangular RAM because the total wire length (column + row wire) and the total number of cells connected to a wire are minimized for square RAM’s.
The RAM generator has two different memory cells, one standard SRAM cell and one asymmetric SRAM cell (where in writing a zero is significantly less energy consuming than writing a one). Creating a data dependent model (ratio of zero to one) for these two RAM cells would also be an interesting research to do.
A typical work flow that one can follow in order to create an energy model is shown in the Fig. 6.1.
Chapter 6 – Energy Model 23
Figure 6.1: A typical work flow.
The third step of this work flow is the most interesting part. As the memories are considered to be very large circuits, simulating them at the layout level and finding an energy model out of it is very difficult. Because the simulation of a single RAM itself would take several days, and we have to simulate a lot of memories in order to arrive at a reasonable energy model. I have looked into using Spectre, which is a typical cadence simulator with a high degree of
24 Evaluation of Low-Power RAM generator
accuracy, and NanoSim a fast SPICE simulator from Synopsys with good flexibility and can be adjusted to several accuracy levels. My observations are discussed in the following.
6.1 SPECTRE VERSUS NANOSIM
The power analysis simulation of an SRAM with a tool like Spectre would take many days and may not be feasible in creating an energy model. So, I have explored the possibilities of using other fast-SPICE simulators like NanoSim. Hence, a lot of time can be saved by using NanoSim. Moreover, one can set different accuracy levels for NanoSim. But one has to trade between time and accuracy. That accuracy may sometimes be so bad (if proper accuracy level is not set) that one may be fooled into wrong conclu-sions. To alleviate that fear, one can use Spectre simulations as a sort of benchmark for comparing the accuracy of NanoSim first.
I have researched on the possibility of using the three following methods for the power analysis, which were not considered for various reasons.
1) Spectre can solely be used for the simulation, if all the components that are used in the SRAM generation are parametrized. Then one can create a critical path netlist and do a power estimation fairly quickly. However, all the compo-nents are not parametrized (except compocompo-nents in Control Logic Block and some gates that are used in some cells). Hence, this idea has been dropped. 2) One can use NanoSim, after making a comparison of the power consumed by an SRAM (say of word length 8k) with that of the result obtained from Spectre simulation. So, if I happen to use NanoSim, then I need to make a comparison with Spectre results just to be sure that the NanoSim results are within the acceptable range.
3) One can also make an analysis using Spectre for only one row in the SRAM and then using the multiplicity factor to compute the power consumed by the entire memory. This could make a dramatic difference in the speed of the simulation. However, this kind of approach can only be made on the sym-metric memory core cells, and not on the other logic blocks (like sense ampli-fiers, decoder blocks and so on).
I have narrowed it down to use Nanosim which happens to be a simple tool and can give fairly accurate results. Though the comparison of results from NanoSim with that of Spectre is a good idea, it may not be necessary in this case as it could be possible to use NanoSim by changing the time step to
Chapter 6 – Energy Model 25
increase the accuracy (of course higher accuracy results in longer simulation time). We can also attain the required accuracy by repeating NanoSim simu-lations.
26 Evaluation of Low-Power RAM generator
7
CONCLUSIONS
This thesis work has focused on the following three different tasks.
1) Creating a new and efficient layout of the SRAM cell, which consumes less area and power.
2) Analyse the effects that a change in technology would have on the RAM generator.
3) Automating the energy simulations and do the ground work for the energy model.
This chapter contains a summary of the results and some suggestions.
7.1 COMPACT SRAM CELL
The implemented compact SRAM cell differs from the original SRAM cell in several ways. Three of its transistors has only one contact as the other contact has been found to be redundant, contributing only to the capacitance, and, hence, consuming more power. The layout of this SRAM cell is also interest-ing as all the like-transistors (transistors of n-type or p-type dopinterest-ing) are over-lapped wherever possible. This has resulted in a significant reduction of the area.
Chapter 7 – Conclusions 27
I also had to introduce a polygon instead of a ‘poly’ path because of unfore-seen grid errors. This might have a insignificant increase in the capacitance of the SRAM cell.
If one follows the state of the art example that I have provided in Section 4.2, then the area can be further reduced, which will have a direct effect on the power consumption.
7.2 EFFECTS OF THE CHANGE IN TECHNOLOGY
The effects of the change in technology have been thoroughly investigated. A lot of interesting facts and tools came into light during this research, which could be helpful for the division when they want to port layouts from one technology to another.
The newer technologies that are in the market right now are on the same lines of 0.18 m technology, which has been used in this thesis work, [1] and [2]. According to the latest reports from ITRS (International technology roadmap for semiconductors) the future technologies will also tend to develop in the same direction as that of 0.18 m. Hence, the assumptions that were made while making the RAM generator will hold (true), and the RAM generator can be ported to newer technologies fairly easy by updating the SKILL code.
7.3 AUTOMATING AND CREATION OF ENERGY
MODEL
A lot of time of the designer and tester can be saved by automating the simu-lation process. A suitable way has been suggested in this thesis, which can be used to the advantage of the designer and the tester. I strongly recommend to use this automation method that I have suggested to anyone who would want to test the memories comprehensively, and to the person who would be work-ing on creatwork-ing the energy model.
µ
28 Evaluation of Low-Power RAM generator
7.4 SUGGESTIONS
The following are my suggestions that I would strongly recommend to any one who would extend this work on creating the energy model or to a person who would want to test the memories comprehensively.
Though the RAM generator generates memories, no one has ever tested those memories. Therefore, I strongly recommend that a new thesis is initiated to comprehensively test a complete memory generated by the RAM generator. I was using the old environment setup for a long time due to the lack of knowledge in the department on this technology as it has become old and no one is working on it right now. There were some warnings about the layer purpose pairs being missing, which suggested that the technology file I was using did not match with the rule file. This was later corrected. So I recom-mend the department to setup an internal wiki where in this information can be stored in a proper manner.
For large layouts, as a memory layout often is, an extraction can require much computing time. Cadence is not stable on such large layouts, and, if run on computers with insufficient memory, the computer may crash. This was also being suggested by Deborah [1].
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REFERENCES
[1] D. Capello, Design and Implementation of a Low-Power Random Access Memory Generator, LiTH-ISY-EX-3318-2003, Linköping, 2003.
[2] M. Åkerman, Implementation of a Zero Aware SRAM Cell for a Low Power RAM Generator, LiTH-ISY-EX--05/3746--SE, Linköping, 2005. [3] D. Capello, M. Åkerman, “Developers Manual,” Linköping 2004, 2005. [4] D. Capello, “Users Manual,” 2003.
[5] E. Hjalmarson, “Introduction to SKILL,” Linköping 2002. [6] SKILL Language User Guide, product version 06.00, June 2000. [7] OCEAN Reference version 4.4.6, Oct. 2001.
[8] P. Bai, C. Auth, “A 65nm Logic Technology Featuring 35nm Gate Lengths, Enhanced Channel Strain 8 Cu Interconnect Layers, Low-k ILD and 0.57um2 SRAM cell”.
[9] Y. J. Chang, F. Lai and C. L. Yang, “Zero-Aware Asymmetric SRAM Cell for Reducing Cache Power in Writing Zero,” IEEE Transactions on very
large scale integration (VLSI) systems, vol. 12, no. 8, pp. 827--836, Aug.
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APPENDIX - OCEAN REFERENCE
This appendix includes a short description of commands that were used in the Example OCEAN code which is shown in Fig. 5.1. of this thesis. For a com-plete description of various other OCEAN features and commands see the OCEAN users manual [7].
simulator
Starts an OCEAN session and sets the simulator name for that session. OCEAN is designed to work with more than one simulator backend.
Example: simulator(spectre)’
In the example case a spectre simulator is chosen.
design
Specifies the name of the design to be simulated. More specifically this com-mand takes the netlist of the circuit that we are about to simulate as its input. Example: design( ”CADENCE/Sim/FullDesign/spectre/schematic/netlist”)
modelFile
Specifies model files (of resistors, capacitors, diodes etc.) to be included in the simulator input file.
Example: model_file=list(...)
resultsDir
This is the directory where all the results are stored. Example: resultDir(/CADENCE/RESULTS/DUT)
analysis
The type of analysis that is to be simulated. This also takes the amount of time the simulator has to run.
32 Evaluation of the Low-Power RAM generator
Example: analysis(‘tran ?stop “90n”)
In the example case we are performing transient analysis which has to stop at 90 ns.
selectResults
Select the results for the specified analysis. Example: selectResults(‘tran)
ocnPrint
Saves the output waveform results in the specified directory. Example: ocnPrint(?output “/CADENCE/RESULTS/out0.dat).
