Analysis and Design of a High-Frequency RC Oscillator Suitable for Mass Production

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Master of Science Thesis in Electrical Engineering

Department of Electrical Engineering, Linköping University, 2017

Analysis and design of a

high-frequency RC

oscillator suitable for mass

production

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Analysis and design of a high-frequency RC oscillator suitable for mass production Jianxing Dai LiTH-ISY-EX--17/5060--SE Supervisor: Dr. Erik Säll Fingerprint Cards AB Martin Nielsen Lönn

isy_{, Linköpings universitet}

Examiner: Dr. J Jacob Wikner

isy_{, Linköpings universitet}

Division of Integrated Circuits and Systems Department of Electrical Engineering

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Abstract

Oscillators are components providing clock signals. They are widely required by low-cost on-chip applications, such as biometric sensors and SoCs. As part of a sensor, a relaxation oscillator is implemented to provide a clock reference. Lim-ited by the sensor application, a clock reference outside the sensor is not desired. An RC implementation of the oscillator has a balanced accuracy performance with low-cost advantage. Hence an RC relaxation oscillator is chosen to provide the clock inside the sensor.

This thesis proposes a current mode relaxation oscillator to achieve low frequency standard deviation across different supplies, temperatures and process corners. A comparison between a given relaxation oscillator and the proposed design is made as well. All oscillators in this thesis use 0.18 µm technology and 1.8 V nom-inal supply. The proposed oscillator manages to achieve a frequency standard de-viation across all PVT variations less than ±6.5% at 78.4 MHz output frequency with a power dissipation of 461.2 µW. The layout of the oscillator’s core area takes up 0.003 mm2.

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Acknowledgments

I appreciate that Fingerprint Cards AB offers me the opportunity to work on this thesis. The project has been challenging and meaningful.

I would like to thank Dr. Erik Säll for being my supervisor at Fingerprints. His suggestion always pointed out a way to solve the issue. Dr. Robert Hägglund, Anders Nordström, Dr. Christer Jansson and Dr. Prakash Harikumar helped me a lot during the project period at Fingerprints as well.

Special thanks to Dr. J Jacob Wikner and Martin Nielsen Lönn for being my examiner and supervisor at campus. Dr. J Jacob Wikner’s guidance helped me in different stages of this project.

I would also like to thank my office mate Jimmy Johansson, who had worked the whole period with me at Fingerprints. I would like to thank Carl-Fredrik Tengberg for teaching me the Swedish alcohol culture as well as being another thesis student at Fingerprints with me.

Finally I would like to thank my parents for supporting me during the past two years.

Linköping, June 2017 Jianxing Dai

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5.3 Noise simulation . . . 56 5.4 Results comparison . . . 58 5.5 Practical issue . . . 59 5.5.1 Trimming range . . . 59 5.5.2 VT variation . . . 60 5.5.3 Extraction variation . . . 61 6 Discussion 63 6.1 Method . . . 63 6.2 Noise . . . 64 6.3 Trimming system . . . 64 6.3.1 Trimming step . . . 65 6.4 External reference . . . 65 6.5 Sizing . . . 65

6.6 Improved performance of the improved oscillator . . . 66

6.7 Improved performance of post-layout simulation . . . 66

6.8 VT dependence . . . 66

6.9 Simulator issue . . . 67

7 Conclusion and future’s work 69 7.1 Future’s work . . . 69

Bibliography 71 A Appendix 77 A.1 Opponent’s questions and respondent’s responses . . . 77

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Contents ix

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1.1 The configuration of the original oscillator. . . 2

2.1 Distribution of 100-points Monte Carlo simulation at −40◦C with 1.98 V supply of the original oscillator. . . . 8

3.1 Conventional relaxation oscillator schematic. . . 10

3.2 Original design of the oscillator. . . 11

3.3 Bias generation module design of the original oscillator. . . 14

3.4 Schmitt trigger design of the current oscillator. . . 15

3.5 Comparator design of the original oscillator. . . 16

3.6 Trimming module design of the original oscillator. . . 18

3.7 SR latch design of the oscillators. . . 19

3.8 The block diagram of the current mode oscillator. . . 20

3.9 The configuration of the proposed current mode oscillator. . . 22

3.10 Cascode current mirror design of the oscillator. . . 23

3.11 Simplified model of the cascode current mirror design of the oscil-lator. . . 24

3.12 Current mode comparator design of the proposed oscillator. . . 26

3.13 Current comparison circuit’s timing diagram. . . 26

4.1 The testbench of the oscillator. . . 30

4.2 Delayed enabling signal triggers the oscillation. . . 31

4.3 Capacitor voltage in oscillation. . . 32

4.4 Comparator internal signals for upper threshold comparison in os-cillation. . . 34

4.5 Improved design of the oscillator. . . 35

4.6 The non-overlapping clock generator in the improved oscillator. . 36

4.7 The ramp capacitor voltage Vrcin oscillation. . . 36

4.8 Internal signals of the VthHcomparator in the improved oscillator. 37 4.9 The current generated from the bias current generator at nominal condition. . . 39

4.10 The capacitor ramp voltages in oscillation state at nominal condi-tion. . . 40

4.11 The output signals of the current mode comparator module in os-cillation state at nominal condition. . . 40

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LIST OF FIGURES xi

4.12 Top level of the proposed oscillator layout. . . 41

4.13 The logic module of the proposed oscillator layout. . . 42

4.14 The bias module of the proposed oscillator layout. . . 43

4.15 The current mode comparator module of the proposed oscillator layout. . . 44

4.16 Ramp voltages of the capacitors and output signals of the current mode comparator. . . 45

5.1 The original oscillator’s output waveform and frequency settling time. . . 48

5.2 The improved oscillator’s output waveform and frequency settling time. . . 48

5.3 The schematic simulation results of the proposed oscillator’s out-put waveform and frequency settling time. . . 49

5.4 The post-layout simulation results of the proposed oscillator’s out-put waveform and frequency settling time. . . 50

5.5 Temperature dependences of the implemented oscillators. . . 51

5.6 Supply voltage dependences of the implemented oscillators. . . 52

5.7 Histogram of 100 samples at −40◦C with 1.98 V supply of the orig-inal oscillator. . . 53

5.8 Histogram of 100 samples at −40◦ C with 1.62 V supply of the im-proved oscillator. . . 54

5.9 Histogram of 100 samples at −40◦ C with 1.62 V supply of the schematic simulation of the proposed oscillator. . . 54

5.10 Histogram of 100 samples at −40◦ C with 1.62 V supply of the post-layout simulation of the proposed oscillator. . . 55

5.11 The oscillators’ spectrums. . . 56

5.12 The oscillators’ phase noises. . . 57

5.13 Trimming range of the implemented oscillators. . . 59

5.14 VT variations of the implemented oscillators. . . 60

5.15 The output frequencies for different extractions of the nominal cor-ner. . . 61

6.1 Histogram of 100 samples at −40◦C with 1.62 V supply of the orig-inal oscillator. . . 68

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1.1 Constraints of the design. . . 3

2.1 Test settings for oscillators. . . 6

2.2 Simulation results of the original oscillator. . . 7

2.3 Specifications of the proposed design. . . 8

3.1 Truth table of the SR latch of this design. . . 20

5.1 Simulation results comparison between the original oscillator and the improved oscillator. . . 49

5.2 Simulation results comparison between the schematic and the lay-out of the proposed oscillator. . . 50

5.3 The comparison between different implementations’ Monte Carlo simulation results. . . 55

5.4 The noise simulation results’ comparison table. . . 57

5.5 Results comparison. . . 58

5.6 VT variations caparison. . . 61

A.1 Document history. . . 80

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Notation

Abbreviations

Abbreviation Description

BCG Bias Current Generator

CMC Current Mode Comparator

cmos Complementary Metal Oxide Semiconductor

CS Common Source

DFF D-Flip Flop

FoM Figure of Merit

INT Integrator

LSB Least Significant Bit

LUT Look-Up Table

MC Monte Carlo

opamp _{Operational Amplifier}

PVT Process, Voltage and Temperature PSS Periodic Steady State

RGC Regulated Cascode

TCR Temperature Coefficient of Resistance VCC Voltage Current Converter

VT Voltage and Temperature

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1

Introduction

In electronics a relaxation oscillator is a nonlinear electronic oscillator circuit that produces a non-sinusoidal repetitive output signal, such as a triangle wave or square wave [1]. The circuit consists of a feedback loop containing a switching device such as a transistor, comparator, op amp, or a negative resistance device like a tunnel diode, that repetitively charges a capacitor or inductor through a resistance until it reaches a threshold level, then discharges it again [2].

The period of the oscillator depends on the time constant of the capacitor or in-ductor circuit. [3] The active device switches abruptly between charging and dis-charging modes, and thus produces a discontinuously changing repetitive wave-form [2]. This contrasts with the other type of electronic oscillator, the harmonic or linear oscillator, which uses an amplifier with feedback to excite resonant os-cillations in a resonator, producing a sine wave [4].

1.1 Motivation and purpose

There was a given relaxation oscillator using RC architecture to generate square wave clock signal. This oscillator operates with 1.8 V supply voltage and is imple-mented with 0.18 µm technology. The given oscillator can output a square wave clock of 86 MHz with nominal process corner, 1.8 V supply and 25◦C tempera-ture. The given oscillator is shown in Fig. 1.1 and will be further described in Chapter 2 and 3.

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Ibias S1 S0 Ibias 1.8 V CRamp − + − + CMP0 CMP1 Vrc VthH VthL INV0 INV1 R S Q Q CLK CLK HitHigh HitLow ICharge IDischarge

Figure 1.1:The configuration of the original oscillator.

However, to obtain as good performance and robust system as possible, an im-proved performance is preferable. The oscillator itself can be tuned to operate in the frequency range of 20-100 MHz using digital control signals and this fits the current sensor implementation. The task is to look into oscillator principles to evaluate which circuit structure that is considered most appropriate to imple-ment in order to obtain low frequency variations over a large tuning range. A frequency variation in this project appears as a deviation to the mean output frequency. The deviation will degrade the supported systems, which are designed to operate at nominal frequency. The designs usually leave a flexible frequency range to operate with, and the frequency standard deviation can be compensated by digital parts of the system.

The frequency variation needs to be within a limited range for the stability of the system operation. As a static variation, frequency variation, or to be precisely, standard deviation could be due to temperature changes, process variations or supply voltage instability.

Noises in the oscillator are appeared to be phase noise, or jitters in time domain. Which are crucial performance parameters of normal oscillator. But due to the application of the oscillator, samples will only be taken when the signal is settled. The settled signals are so stable that the jitters of oscillators will not affect the sampling. Hence the noise performance of the oscillators are not main concern of this thesis.

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1.2 Problem statements 3

1.2 Problem statements

This thesis will cover the following questions.

• What other kinds of architectures can be used to achieve a relaxation oscil-lator?

• Which component of the design is the main reason for output frequency variation across different process, temperature and supply voltage corners? • Which devices of the components are more exposed to process, temperature

and supply changes?

The questions will be discussed and answered in the following chapters.

1.3 Constraints

This project is aiming to improve the existing design of the relaxation oscillator. Hence the design is limited with process technology, supply voltage, tempera-ture range and output signal type, as shown in Tab. 1.1. The design will be utilized in schematic level and a layout based on the schematic design will be per-formed. Hence the evaluation will be based on the simulations, which consists of schematic simulation and post-layout simulation.

Table 1.1:Constraints of the design.

Supply voltage (V) 1.62 - 1.98

Temperature (◦C) −_{40 - 85}

Process technology (nm) 180

Output signal form Square wave

Design form Schematic & Layout

Results sources Simulations

1.4 Methodology

The methodology includes preliminary literature survey to decide appropriate circuit design and state-of-the-art performance. Based on system specifications, the design parameters of the circuit blocks are derived. The implementations of different modules are carried out subsequently. The design is implemented by combining circuit techniques from different publications as well as adopting modifications of the original design. Simulations are performed with different process corners, supply voltages and temperatures.

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1.5 Scope of the dissertation

This thesis is organized as the following structure:

• Chapter 2 discusses the design specifications for the oscillator. The original oscillator’s simulation results are listed as well.

• Chapter 3 presents the working principles of different components inside the oscillators. This chapter is based on various publications and original oscillator’s circuit design.

• Chapter 4 presents the implementations of an improved version of the orig-inal oscillator and a new proposal of a relaxation oscillator.

• Chapter 5 presents results of the two implemented oscillators and a com-parison between different relaxation oscillators.

• Chapter 6 presents conclusions and discussions of the results. A wider perspective of this work is also concluded.

An appendix of the opponent’s comments and author’s replies is included at the final part of the report.

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2

Background

As mentioned in Section 1.1, the thesis is aiming to improve the existing design or propose a new implementation. Thus this chapter focuses on the original design and the specifications. The simulation results of the original oscillator based on schematic design are listed in this chapter. The worst corner of the frequency standard deviation is shown in histograms.

The distribution of the Monte Carlo simulation results are evaluated with the 3σ rule, which is used to measure samples’ deviations to the mean value of test results. To include all simulation results into 3σ range, a standard deviation needs to be adjusted. Hence a wide spread distribution of the simulation results will result in a large standard deviation of the output frequency, which needs to be avoided.

The proposed design should be able to easily integrate into the existing system. This requires some key features to be maintained, such as the trimming signal combined with the control code.

2.1 Original oscillator

The original oscillator has the configuration as shown in Fig. 1.1. It consists of two current sources charging and discharging the ramp capacitor CRamp, two

comparators connected with inverters and an SR latch as the output logic. It should be noticed that the two bias current mirrors are controlled by trimming codes outside the oscillator. The trimming code changes the amount of the charg-ing and dischargcharg-ing current, consequently adjusts the output frequency.

The trimming code ranges from −8 to 7 in decimal, but realized in two’s

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plement in the oscillator. In the original oscillator, the trimming code is a five bits two’s complement code. The five bits control code requires five branches of current mirrors. They are parallel connected MOSFETs and the numbers of MOSFETs in each branch are determined by 2n. A detailed description of the trimming control module is included in Section 3.2.3.

2.2 Simulation settings

The original oscillator and the proposed oscillator will be evaluated under tran-sient simulations and Monte Carlo simulations. Nominal cases trantran-sient simula-tions provide nominal output frequencies, settling time, duty cycles and current consumptions of the tested oscillators. The Monte Carlo simulations provide the output frequency standard deviations of the oscillators. The supply voltages are provided by ideal DC voltage source.

Simulation settings are shown in Tab. 2.1 below. It should be noted that trim-ming codes differ from each other for different purposes. That is the reason for "depends" in the table. When a tuning range of an oscillator is to be tested, the trimming code will be swept from −8 to 7. When an output frequency is to be tested, the trimming code will be fixed to 0.

The process corner 0 means typical corner. Different combinations of NMOSs and PMOSs corners are named after 1 to 12. The process corner 100 is for the recognition by the MC models. Hence the process corner 100 can be translated as "Monte Carlo model process corner setting".

Table 2.1:Test settings for oscillators. Simulation Transient Monte Carlo

Supply (V) 1.8 1.62, 1.98

Temperature (◦C) 25 -40, 25, 85

Process Corner 0 100

Trimming Code Depends 0

Apart from the VT settings and process corner settings, Monte Carlo simulations have more options than transient simulations. The variation setting is set to "all", which means process variations and mismatches are both simulated during the MC simulations. The sampling method is set to "random". The process variation is covered by the MC simulation model, hence VT variations are sufficient for MC corner settings.

It should be noticed that the process corner setting for the MC simulations are not enough to cover all process corner variations. Due to the limitations on resources, simulations for all process variations are not feasible. Hence a simplified MC pro-cess corner setting is used to estimate the oscillator’s performances. VT variations with MC simulations can not give identical results to the PVT simulations.

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2.3 Simulation results 7

2.3 Simulation results

The given design of the oscillator has the simulation results as shown in Tab. 2.2. As mentioned in Section 2.2, all voltage supplies are ideal.

The MC test simulates mismatches and process defects in the tested circuit and the simulation results are collected. Experimentally, the output frequency range in an MC test is larger than a test of all process corner sweep with different sup-plies and temperatures. Thus the trimming range can be determined through this test as well.

The current consumption is measured with transient test. The current is taken within several full clock cycles and averaged to calculate the average current con-sumption. The taken clock cycles are near the end of the simulation in order to acquire steady state current consumption.

The worst corner of the output frequency standard deviation occurs at the sce-nario of 1.98 V supply, −40◦

C. The distribution of the 100-points Monte Carlo simulation is shown in Fig. 2.1. It is clear that the 11.3 MHz standard deviation comes from this wide distribution in frequency domain. The target of the project is to achieve as low as possible frequency standard deviation while fulfilling other specifications.

Table 2.2:Simulation results of the original oscillator.

Current consumption (µA) 112.8

Output frequency tuning

range (MHz)

61.0 - 105.9

Output frequency (MHz) 85.68

Output settling time (µs) 2.14

Output duty cycle (%) 46.1

Standard deviation of output frequency (MHz)

11.3

VT variation (MHz) 7.06

Max/Min/Mean values of out-put frequency (MHz)

122.6 / 60.6 / 86.5

Apart from the frequency standard deviation, the frequency spread in the MC simulation shows a large range at output frequency. This is why a trimming system is required for the oscillator. The trimming system can provide a range to tune the oscillator in order to make the oscillator output frequency at 80 MHz. Since the PVT variations are realized by MC simulation model and the VT set-tings in this thesis due to the limited resources. These 100-points simulations for each VT combination corner can be seen as close estimations of an oscillator’s performances across PVT variations.

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Figure 2.1: Distribution of 100-points Monte Carlo simulation at −40◦

C with 1.98 V supply of the original oscillator.

2.4 Specifications

Design proposals need to be evaluated in the following perspectives: current con-sumption, area, start-up time, frequency standard deviation and duty cycle. The specifications of the proposed designs are shown in Tab. 2.3. It should be noticed that the following specification needs to be realized with the trimming code set to 0.

Table 2.3:Specifications of the proposed design.

Current consumption (µA) ≤₂₅₀

Area (mm2) ≤_0.02

Start-up time (µs) ≤_2.2

Frequency standard devia-tion (MHz)

≤_{6 @ 75 - 85 MHz}

Duty cycle (%) ≈₅₀

As a hard requirement, the target of decreasing the frequency standard deviation must be achieved. The other specifications could be deemed as acceptable when they are around the specifications.

The area estimation of those designs with only schematic levels are done in the Cadence layout tool LayoutXL. The estimation will be done with a utilization ratio of 70%, which could be easily achieved by careful planning and placement.

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3

Theory

This chapter will focus on the relaxation oscillator’s working principles, which involve both the oscillator and the sub-modules.

A conventional relaxation oscillator will be described first. Then different ponents of the original oscillator design will be elaborated. At last, the key com-ponents of the proposed design will be showed.

The original oscillator was designed based on the conventional voltage mode relaxation oscillator. Unlike common relaxation oscillators, the original design achieved an output frequency as high as 85 MHz. The high frequency output in-evitably leads to high frequency standard deviation. Thus a current mode relax-ation oscillator is proposed in this work, aiming to reduce the frequency standard deviation and keep the output frequency at a range of 75 - 85 MHz.

3.1 Conventional relaxation oscillator

As shown in Fig. 3.1 is a conventional voltage mode relaxation oscillator. The cir-cuit consists of bias currents IBs, a reference voltage VREF, comparators Comp.1,2

capacitors CRAMP1,2reset switches MNRST1,2, and a control logic circuit. When Q

and QBare high and low, MNRST1and MNRST2are off and on, respectively. The

CRAMP1 accepts IBand generates ramp voltage of VINT1. The Comp.1 compares

VINT1with VREF. When the VINT1reaches VREF, the Comp.1 detects it and Q and

QBtoggle low and high, respectively. By repeating above operation alternately

for CRAMP1and CRAMP2, the circuit generates a clock pulse [5].

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MNRST1 CRAMP1 + − VREF CRAMP2 MNRST2 − + Comp.1 − ₊ Comp.2 IB IB VDD VDD Logic QB Q VINT1 VINT2

Figure 3.1:Conventional relaxation oscillator schematic.

The control logic component is implemented with an SR latch, which is designed to reshape the output waveform from the two comparators as well as controlling the duty cycle of the output signal.

3.2 Original design of the oscillator

As shown in Fig. 3.2 is the oscillator design to be improved. The circuit con-sists of reference voltages VthHand VthL, bias current IBias, two current mirrors,

comparators CMP0,1, capacitor CRamp, switches S0,1 and an SR latch. The bias

current Ibiasis generated by current mirrors M1 and M2 with opposite direction.

Reference voltages are generated by a bias generation module, which provides the reference current for the current mirrors as well.

Comparing to the conventional design, this oscillator uses logic signal HitLow to set the SR latch due to the start-up voltage of the Vrcbeing logic high. Switches S0

and S1 are controlled by the clock signal output of the SR latch. The CLK signal is inverted to drive the switches, which are implemented by CMOS technology, i.e. S0 is implemented by PMOS and S1 is implemented by NMOS. Then the

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3.2 Original design of the oscillator 11

two current mirrors generate the bias current IBias to charge and discharge the

capacitor to generate a saw-tooth wave. The comparator will output a logic high signal when the positive input is higher than the negative input. The comparator CMP0 will output logic high when VthHis higher than Vrc, and CMP1 will output

logic high when Vrcis higher than VthL. These comparators’ output signals will

be inverted and work as set and reset signals to the SR latch.

A simple expression for the output clock signal can be concluded from Fig. 3.1

Tclk = Tclk_high+ Tclk_low= 1 fclk (3.1) Tclk_high= CRamp(VthH−VthL) |_I_Charge| (3.2) Tclk_low= CRamp(VthH−VthL) |_I_Discharge| (3.3) Ibias S1 S0 Ibias 1.8 V CRamp − + − + CMP0 CMP1 Vrc VthH VthL INV0 INV1 R S Q Q CLK CLK HitHigh HitLow ICharge IDischarge

Figure 3.2:Original design of the oscillator.

This oscillator works in the following sequence:

• An enabling signal is switched from logic low to logic high, triggering the bias module of the oscillator to start working. The Vrcis set to logic high

initially.

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the oscillator.

• The CRamp begins to discharge after the trimming control module is

acti-vated.

• When the Vrc touches the low threshold voltage VthL, the CMP1 output

signal toggles and HitLow changes to logic high, which set the SR latch output Q to logic high.

• The switch S1 turns off and S0 turns on. The Camp begins to charge after

the CLK signal toggling to logic high.

• When the Vrc touches the high threshold voltage VthH, the CMP0 output

signal toggles and HitHigh changes to logic high, which reset the SR latch output Q to logic low.

Then the oscillator keeps on oscillating until the enabling signal toggles to logic low. Which shuts down the oscillator.

The generated clock is used to take samples in the rest part of the circuit. Each sample will be taken at steady state, hence the jitter is not of concern in this application. Samples will be taken at their settled states, while the clock will be used at lower frequency to take the samples. Combining these two features together, clock jitters, or phase noises, of an oscillator is not one of the main pursuits of an oscillator design.

3.2.1 Bias generation module

The circuit has enabling signals E and E, bias currents IbnCand IbnRas the input

signals. Enabling signals Eo and Eo, bias current IbIch, bias voltages Vbp1 and

Vbp2, reference voltages VthHand VthLare the output signals of this circuit.

As shown in Fig. 3.3, The circuit can be divided into two parts. The current mirrors take constant reference currents IbnC and IbnRas reference inputs. The

bias voltage generator, which takes IbnCas the reference input, generates the bias

voltages for comparators, bias current IbIchand enabling signals Eoand Eofor the

rest parts of the oscillator.

The bias current IbIchis the reference current of the current mirrors that control

the charging and discharging of the capacitor CRamp in Fig. 3.2. The enabling

signals Eoand Eoare designed to have a time delay, which ensures that the

com-parator reference voltages and other pre-charging components of the oscillator are ready. The time delay is achieved by capacitor charging delay.The capacitor is implemented by connecting the PMOS PMC0 as a MOS capacitor, which needs to be charged and discharged to trigger the Schmitt trigger.

As for the capacitor connected MOSFET, The drain, source and bulk of the MOS-FET are connected to gether as one plate of the capacitor. The gate of the MOSMOS-FET functions as the other plate of the capacitor. Since the gate oxide is the thinnest dielectric available in an integrated circuit, it is imminently sensible to build ca-pacitors around it. All comprise gate and silicon conducting "plates" separated

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by the gate oxide as dielectric. All are nonlinear capacitors, whose value depends on the voltage across it [6].

The threshold voltage generator, which takes IbnR as reference input, generates

the reference voltages for comparators. The circuit uses a resistor R2 to compen-sate the temperature variation in the voltage divider. Similar resistor values of R2 and R1 are taken. As shown in Fig. 3.3, threshold voltages are set by series con-nected resistors R0 and R1. The two capacitors NMC0 and NMC1 are decoupling capacitors to stabilize the output threshold voltages.

Schmitt trigger

It should be noticed that the first stage of the enabling signals delay chain is a Schmitt trigger. It is implemented as shown in Fig. 3.4. A Schmitt trigger is used to avoid unsettled logic level to the inverters. As a analog to digital bistable device, the Schmitt trigger is widely used in multi-vibrators.

The Schmitt trigger in this design is an output inverted version of a normal one. As illustrated in [7], design parameters could be attained from

kM1 kNM1 =VDD−VHi VHi−VTN 2 , (3.4) kM0 kPM1 = VLi VDD−VLi− |VTP| 2 . (3.5)

The ki in the equations is defined as

ki = 1 2µCox W L i. (3.6)

VHiand VLiare the expected threshold voltage of the Schmitt trigger (i.e. starting

points of the triggering operations). VTN and VTP are the threshold voltage of

NMOSs and PMOSs. kNM0 and kPM0affect the real triggering points VHand VL.

The differences between the starting points and the transitions are marked as ∆VHand ∆VL. They can be expressed as

∆VH≈ VDD −_V_Hi− |_V_TP| kNM0 kPM0 + kNM0 kM0 , (3.7) ∆VL≈ − VLi −_V_TN kPM0 kNM0 + kPM0 kM1 . (3.8)

∆VHis defined as ∆VH= VH−VHi, while ∆VL= VL−VLi. The design parameters

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NM0 NM1 NMe0 NMe1 I bnC E E P M0 P M1 P Me0 P Me1 NM2 V bp1 V bp2 NM3 NM4 NM5 P Me2 I bI ch P MC0 Schmitt INV0 INV1 E o E o I bnR NM6 NMe2 NMe3 NM7 P M2 P Me3 R2 E E E P M3 NMC1 NMC0 R0 R1 1 .8 V V thH V thL Bias V ol tag e Gener ator Threshol d V ol tag e Gener ator F igure 3.3: Bias g ener ation mod ule design of the original oscilla tor .

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3.2 Original design of the oscillator 15 M1 NM0 PM0 M0 NM1 PM1 A Y 1.8 V 1.8 V

Figure 3.4:Schmitt trigger design of the current oscillator.

3.2.2 Comparator

The comparator in this oscillator is a component that compares two signals at the input ports and generates a logic signals accordingly at the output port. As shown in Fig. 3.5, the comparator consists of a differential amplifier, a common source amplifier and a buffer. The buffer turns the two-stage amplifier output into a logic signal driving the following inverters and the SR latch.

It should be noticed that the comparator aims to output a logic signal. Thus the gain of the first stage of the amplifier needs to be reasonable to avoid wrong operating region for the second stage NMOS. If the voltage difference at the first stage of the amplifier is not amplified larger than the threshold voltage of NM2, the second stage of the amplifier will work in sub-threshold region, which needs to be avoided in the comparator. However, a large gain in the first stage requires a large input pair, which introduces larger parasitic into the connecting node of CRampconsequently, resulting in worse speed performance. The slew rate of the

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NM0 NM1 PM0 PM1 Ibias1 NM2 Ibias2 NM3 PM3 NM4 PM4 1.8 V i- i+ Y a+

b-Differential Amplifier CS Amplifier _Bu_ffer

Figure 3.5:Comparator design of the original oscillator.

Having PMOS input first stage and NMOS input second stage maximizes the transconductance of the drive transistor of the second stage, which is critical when high-frequency operation is important [6]. The transconductance of the second stage can be expressed as

gNM2 =

r 2µnCox

W

LIbias2. (3.9)

By choosing PMOSs as the first stage input pair implies an NMOS will be the second stage transistor. Physically, the n-channel carrier has a larger mobility than the p-channel carrier. Hence, an n-channel input device has potentially larger conductance than a p-channel input device, resulting in larger gNM2.

The offset voltage of an opamp is composed of two components: the systematic offset and the random offset. The former results from the design of the circuit and is present even when all the matched devices in the circuit are identical. The latter results from mismatches in supposedly identical pairs of devices. The offset voltage VOScan be expressed as shown in [8]

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3.2 Original design of the oscillator 17 VOS≈ ∆Vt(PM0,PM1)+ ∆Vt(NM0,NM1)gNM0 gPM0 +Veff(PM0,PM1) 2 ∆ _W L N M0,N M1 _W L N M0,N M1 − ∆W_L P M0,P M1 _W L P M0,P M1 . (3.10)

In Equation (3.10), ∆Vt is the threshold mismatch, while ∆Veff is the effective

voltage driving the gate. For low noise and random input offset voltage, NM0 and NM1 should have small transconductances comparing to the input PMOS pair and longer channel lengths than the PMOSs [8].

3.2.3 Trimming control

The oscillator output frequency can be controlled by the current Ibiasas shown in

Fig. 3.2, which charges and discharges the capacitor. The frequency will change according to the changes of the bias current amount. The operating parts of this current mirror array are controlled by a series of switches, which are controlled by the trimming code ranged from −8 to 7 in decimal and implemented in 5-bits two’s complement. This trimming system is to ensure that the output frequency can be located near the desired frequency when the working condition changes. The circuit shown in Fig. 3.6 has the input signals E, E, Ib, T < 4 : 0 > and D. The

output signal is Ichg. It should be noticed that the signal Ibis the bias generation

module’s output signal IbIch. Enabling signal E and E are Eoand Eofrom the bias

generation module. The control signal D is from the output of the SR latch. As shown in Fig. 3.6, the circuit can be divide into three parts. The start-up cir-cuit copies the reference current and the current mirror array scales the current with factors of 2n. The logic component inverts the trimming signals T < 4 : 0 > to provide signals for both NMOS arrays and PMOS arrays. The decoupling ca-pacitors PMC0 and NMC0 are set to stabilize the gate voltages of the duplicated current mirrors. The part on the left are controlled by two switches. Each of them pulls up or down the decoupling capacitors’ top plates voltage when the enabling signal E is low. The whole circuit begins to operate when E is high. The current mirror array consists of NMOS arrays and PMOS arrays in series connection with switches which are controlled by the T < 4 : 0 >, E and E. Apart from the current mirrors, there is a pull-up switch forcing the output node logic high during the start-up phase. These two arrays are connected to the capacitor CRampin Fig. 3.2 to charge and discharge it. The switches NM14 and PM16 are

controlled by the Q signal of the logic module output, which is inverted by INV0. During the Tclk_highperiod, PM0-PM5 are responsible for charging the ramp

ca-pacitor CRampin Fig. 3.2. During the Tclk_lowperiod, NM0-NM5 are responsible

for discharging the ramp capacitor CRamp. In this way the feedback loop is

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1 .8 V P Me0 P M7<1:0> P M15<1:0> P M6<1:0> P M14<1:0> P MC0 P M5<9:0> P M13<9:0> P M4<15:0> P M12<15:0> P M3<7:0> P M11<7:0> P M2<3:0> P M10<3:0> P M1<1:0> P M9<1:0> P M0 P M8 P Me1 E E T2 < 4 > T2 < 3 > T2 < 2 > T2 < 1 > T2 < 0 > E I b INV2<4:0> INV1<4:0> T < 4 : 0 > T2 < 4 : 0 > T2 < 4 : 0 > P M16 NM14 INV0 D I chg NMe0 NMC0 NM6<1:0> NM13<1:0> NM5<9:0> NM12<9:0> NM4<15:0> NM1<15:0> NM3<7:0> NM10<7:0> NM2<3:0> NM9<3:0> NM1<1:0> NM8<1:0> NM0 NM7 E E T2 < 4 > T2 < 3 > T2 < 2 > T2 < 1 > T2 < 0 > S tart -up Circuit C urren t Mirror Arr ay Logic F igure 3.6: T rimming mod ule design of the original oscilla tor .

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3.2.4 SR latch

The traditional way of causing a bistable element to change state is to overpower the feedback loop. The simplest implementation accomplishing this is the well-known SR, or set-reset, flip-flop. This circuit is similar to the cross-coupled in-verter pair with NOR gates replacing the inin-verters. The second input of the NOR gate is connected to the trigger inputs (S and R) that make it possible to force the output Q and Q to a given state. These outputs are complimentary (except for the SR = 11 state). When both S and R are 0, the flip-flop is in a quiescent state and both outputs retain their values. (A NOR gate with one of its inputs being 0 looks like an inverter, and the structure looks like a cross-coupled inverter.) If a positive (or 1) pulse is applied to the S input, the Q output is forced into the 1 state (with Q going to 0) and vice versa: A 1-pulse on R resets the flip-flop, and the Q output goes to 0 [9].

As shown in Fig. 3.7, The design has two extra gates in order to achieve control of the SR latch as well as avoid unsettled logic signal during disable period. The unsettled logic signal will force the gates to consume constant power deciding the logic level. The output signal of the OR gate is the set signal to the latch, and the output signal of the AND gate is the reset signal. The truth table is shown below in Tab. 3.1. When the enabling signal E is logic high, the latch works as it is described. When E is logic low, the latch stays at the set state.

NOR0 NOR1 AND0 OR0 HitLow E E HitHigh Q Q S R

Figure 3.7:SR latch design of the oscillators.

In this oscillator design, we take the Q output as the switches control signal for the trimming control module. Due to the start up voltage of the capacitor CRamp

is logic high, hence NM0-NM5 in Fig. 3.6 need to be connected first to start the feedback loop. Or else the whole system can not be triggered. This requires the inputs to the SR latch should be SR = 01 when Vrcis logic high. The design meets

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Table 3.1:Truth table of the SR latch of this design. E HitLow HitHigh S R Q Q 1 0 0 0 0 latch latch 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 1 1 1 1 1 1 0 any any 1 0 1 0

3.3 Current mode oscillator

The proposed design is based on [5]. The key components will be illustrated in the following sections. The proposed current mode oscillator consists of a current generator, current mode comparators and SR latch. The SR latch is elaborated in Section 3.2.4. Hence theories of the bias current generator and the current mode comparators will be presented.

The current mode comparator can also be called current comparison circuit, which explains its function by words. However, it will be called current mode compara-tor in this thesis.

3.3.1 Block diagram

As shown in Fig. 3.8, the proposed current mode oscillator has an external ref-erence current input and square wave clock signal outputs, which can be either 80 MHz or 40 MHz. Bias current generator (BCG) Integrator with reset (INT) Voltage to current converter (VCC) Current mode comparator (CMC) Output logic Latch IRef Ibias1 Ibias2 Q Q VC VC Id2 Id1 Q Q Fout

Figure 3.8:The block diagram of the current mode oscillator.

The oscillator consists of bias current generator (BCG), integrator with reset (INT), voltage to current converter (VCC), current mode comparator (CMC) and output logic. The BCG generates bias currents IBias1and IBias2are sent to the INT and

CMC modules. INT generates ramp voltages VC and VCN. The ramp voltages

are then transferred to VCC and converted to currents ID1 and ID2. When the

converted current reaches IBias2, the latch toggles the internal logic and generates

a clock pulse. Finally the clock pulses are reshaped by the SR latch. A DFF is included in the output logic to divide the output frequency by a factor of two.

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3.3 Current mode oscillator 21

3.3.2 Circuit schematic

The configuration of the proposed oscillator is shown in Fig. 3.9. The trimming signals are used to control the current flow in the BCG module. They are marked with arrows cross the MOSFETs. For simplicity, the current mirror delivering the external reference to the regulated cascode current mirror’s input and bias is omitted. This omitted current mirror is implemented with a simple current mirror.

3.3.3 Cascode current mirror

As shown in Fig. 3.10 is the cascode current mirror which delivers the reference current with specified ratio to the current mode comparators. The circuit has IRef

as the input signal and Vbas the output signal. A trimming system is introduced

to this current mirror. The trimming system comes into effect by controlling the current flow of PM0, achieving a tuning range of 12 times to 27 times of the input reference current. The trimming signal is implemented by 4-bits two’s complement code, corresponding to a range of −8 to 7.

The bias current IBiasis equal to the reference current IRefto minimize the

system-atic error of the current gain [10]. NM0 is controlled by two switches NMe0 and NMe1. NMe0 is in charge of connecting the NM0 gate to the drain node, forcing NM0 into saturation region. NMe1 drags the gate of NM0 to ground when the E signal is logic low, forcing NM0 into cut-off region. NM11 to NM15 are used to make sure the drain nodes’ voltages of NM1 to NM5 are the same as the drain node’s voltage of NM0.

This circuit shows an increased output impedance in comparison to the simple current mirror or opamp, however, the usable output-voltage swing becomes nar-rower. By choosing optimum bias condition, this restriction can be somewhat relaxed [11]. The implemented structure is called a regulated cascode (RGC) cur-rent mirror.

Regulated cascode current mirror

To simplify the connection of Fig. 3.10, we can ignore the controlling switches and different ratios of devices. By rearranging the circuit, we can have the regu-lated cascode current mirror as shown in Fig. 3.11. The bias current is set to be equal to the input current IInavoid gain error.

NM2 and NM3 form a feedback loop which stabilize the drain node of NM1. This structure allows a very high gain without compromising the overall bandwidth [12]. To mitigate the effect of channel length modulation of NM1, its drain-source voltage has been fixed (Vds1constant) by using a feedback loop consisting of an

auxiliary amplifier (NM2 and bias current source) and NM3 as source follower [13]. The feedback mechanism upon which the stabilization is based works even if NM3 is driven into ohmic operating region, which extends the usable range for the output signal [11].

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Output logic T<3:0> I Ref biasI Q Q Q Q F out V SS V DD BC G INT0 C MC0 La tch C MC1 INT1 V C C0 V C C1 F igure 3.9: The configur ation of the proposed curren t mode oscilla tor .

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3.3 Current mode oscillator 23 NM0 NMe0 NMe1 NM1<11:0> NM2<7:0> NM3<3:0> NM4<1:0> NM5 NM11<11:0> NM12<7:0> NM13<3:0> NM14<1:0> NM15 NM6<11:0> NM7<7:0> NM8<3:0> NM9<1:0> NM10 NMe2<7:0> NMe3<3:0> NMe4<1:0> NMe5 P M0 P Me0 1 .8 V IRef E E IBias Vb E T < 3 > T < 2 > T < 1 > T < 0 > F igure 3.10: C ascode curren t mirror design of the oscilla tor .

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NM0 NM1 NM2 NM3 Ibias 1.8 V Iin Iout

Figure 3.11: Simplified model of the cascode current mirror design of the oscillator.

When we assume that the gate-source voltage of NM1 is constant, Vds1needs to

equal to Vgs1−Vth1to maximize the voltage swing of the output. When NM2 is

in strong inversion, we can acquire

Vds1= Vgs1−Vth1= Vgs2 (3.11) Vgs2= Vgt2+ Vth2 (3.12) Vds1= r 2Ibias β2 + Vth2. (3.13)

In the equations, β2is the transconductance coefficient of NM2. Vgt2is the

effec-tive voltage applying to the MOSFET gate control and calculation of the transis-tor’s drain-source current.

As shown in Equations (3.11) and (3.12), input voltage Vgs1 of NM1 has to be

two Vthhigher (if we assume NM1 and NM2 of same sizes) to achieve a possible

solution of the equation for Ibias and β2. This limitation needs to be kept for

better performance such as temperature-independent operating point [14] or low 1/f noise of the transistors.

When NM2 is in weak inversion while NM1 and NM3 are in strong inversions, the equations need to be redrawn due to lower limitation of Vgs2. A current flowing

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through a weak inversion transistor has the equation as shown in [15]

ID= I0×e

VGS

ζVT_. _(3.14)

Then Equation (3.11) can be redrawn

Vds1= Vgs1−Vth1= Vgs2= ζVth2×ln(Ibias

I0

). (3.15)

This condition can be fulfilled with any Vgs1larger than Vthif the devices are of

the same size.

Output swing limitation of the regulated cascode current mirror structure is that Vds1 has to be no lower than one threshold voltage to maintain the feedback of

the MOSFETs. Hence the lower bound for the output voltage is

Vout,min= Vth2+ Vdsat3. (3.16)

In the equation, Vth2 is referred to the threshold voltage of NM2 and Vdsat3 is

referred to the drain-source voltage of NM3 when it is in saturation region. This structure is not fully supply independent due to the slight change in Vgs2.

This change occurs because of the variation in the drain current of NM2.

3.3.4 Current mode comparator

As shown in Fig. 3.12 is the current mode comparator. Current mirror is replaced by the ideal current source for simplicity. As stated in Section 3.3, the current mode comparator is taken from [5]. The circuit has the input signals Q to control the switches NMe0 and NMe1, output signal Q to control the symmetric half circuit.

When starting with Q signal high and Q low, bias current Ibias1charges the

capac-itor connected MOSFET NMC0 and Ibias2flows through the resistor R0. With the

charge in NMC0 rising, the gate-source voltage Vgs1of NM0 increases. Hence the

current flows through NM0 partially. When the drain-source current Idof NM0

is equal to the bias current Ibias2, the output signal Q switches state and the input

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NMe0 NMC0 NM0 R0 NMe1 Ibias1 Ibias2 1.8 V Q Q Q

Figure 3.12:Current mode comparator design of the proposed oscillator.

The timing diagram of one clock cycle is shown in Fig. 3.13.

Q Q

Vgs0

Id0

Ibias2

T/2 t

Figure 3.13:Current comparison circuit’s timing diagram.

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3.4 Temperature coefficient 27 half clock cycle, NMC0 is charged by the bias current Ibias1. Hence Vgs0can be

expressed as a function of Tcycle, CNMC0and Ibias1

Q = Tcycle ×_I_bias1 2 , (3.17) Vgs0= Q CNMC0, (3.18) Vgs0= Ibias1×Tcycle 2CNMC0 . (3.19)

By rearranging the equation we can express the output frequency as

fclk= 1 Tcycle = Ibias1 2Vgs0×CNMC0 . (3.20)

This indicates the main sources of the frequency variations. Hence these compo-nents require attentions during the layout to minimize the PVT effects on devices.

3.4 Temperature coefficient

The implementations of the resistors in all the designs are p+_{polysilicon resistors.}

A total resistance R can be expressed as shown in [16]

R = RC+ Rsilicide+ Rbulk×

L

W+ Rinterface×

W0

W . (3.21)

In Equation (3.21), RCand Rsilicideare the effective contact and silicide resistance,

L and W are the length and width of polysilicon resistors, respectively. W0is a

normalization constant (e.g. = 1 µm) to guarantee the right dimensions of the full equation. As illustrated in [17], in a p+polysilicon application, the Rbulkand the

Rinterface decreases with the increase of temperature. Detailed affecting factors

to the different resistor consisting components are illustrated in [18]. The TCR is dominated by the TCR values of Rbulkand Rinterface, and the total TCR can be

expressed as TCR = 1 R dR dT ≈ 1 W× 1 R×[( ∂Rbulk ∂T ×L) + ( ∂Rinterf ace ∂T ×W0)]. (3.22)

Clearly, TCR is maily determined by Rbulk and Rinterface of the p+ polysilicon

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3.5 Noise

An ideal oscillator produces a perfectly-periodic output. In reality, however, the noise of the oscillator devices randomly perturbs the zero crossings. A small random phase quantity φn(t) can be used to describe the deviations to the ideal

zero crossings. The term φn(t) is called the "phase noise" [19].

Since the phase noise falls at frequencies farther from fclk, it must be specified at

a certain "frequency offset," i.e., a certain difference with respect to fclk. A 1-Hz

bandwidth of the spectrum at an offset of ∆f is considered, measure the power in this bandwidth, and normalize the result to the "carrier power." The carrier power can be viewed as the peak of the spectrum or as the power of A2/2. ’A’ in

the expression is the amplitude of the clock signal [19].

3.6 Conclusion

This chapter described the given oscillator and the proposed oscillator in detail. Some concerns regarding the oscillator stability are explained in order to better understand the simulation results later in Chapter 5. As stated in Section 2.4, the main focus of this thesis is reducing the frequency standard deviation across PVT corners to less than 6 MHz.

As stated in [20], comparators in the oscillator contribute to the frequency stan-dard deviation of oscillators. Hence a simple structure of a comparator is pre-ferred. The proposed current mode oscillator uses single MOSFET to function as a comparator. The compared signal is current instead of voltage, which helps to improve the stability of the oscillator. As shown in [5], a current mode oscillator can achieve low frequency standard deviation across PVT corners.

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4

Method

The implementations of the designs use 0.18 µm technology. The original oscilla-tor and the improved version are implemented in schematic level. The proposed current mode oscillator is implemented in both schematic and layout. The simu-lation results of different implementations are shown respectively in Chapter 5. During the simulation, the performances of the bias generation module and com-parators in the original design limits the possibilities to further improve the orig-inal oscillator. Hence a current mode oscillator is proposed and implemented.

4.1 Testbench

The following contents in this chapter involve the implementation and simula-tion of different oscillators. All the oscillators use the same testbench. The noise simulation in chapter 5 picks the high frequency output to analyze the phase noise. The connection of the testbench is shown in Fig. 4.1.

The supply source is an ideal DC voltage source and the enabling signal is imple-mented with DC source as well. The enabling signal generator has a delay time in the DC source setting to simulate the logic low disabling period of the circuit. The reference current is taken from a Verilog-A model which is a bandgap cur-rent generator producing 1 µA curcur-rent. Variations for diffecur-rent process corners, temperatures and supply voltages are modeled inside the module.

The oscillator has a trimming code generator taken from the Cadence built in library igwLib. The code generator can support up to 8 bits output. However, in these applications a maximum 5 bits are taken as the inputs of the oscillator. The trimming range for both the voltage mode oscillator and the current mode

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iBias Model Time to Freq Trimming Code + − VDD + − + − Iin VSS VDD E Trim E CK80 (fclk) CK40 CK80, CK40 Freq80, Freq40 Trim V_DD VSS

Figure 4.1:The testbench of the oscillator.

oscillator is from −8 to 7, converted to 5 bits or 4 bits two’s complement code respectively.

At the output stage, a frequency detector from library igwLib is used to determine the frequency of the output waveform. The frequency detector is also used to determine the frequency settling time.

4.2 Original oscillator

The original oscillator has a 10 ns disabling pulse to setup. The bias module and logic module are directly controlled by the outer enabling signal. The logic mod-ule is controlled by the outer enabling signal for the reason of canceling off state current consumption. Middle state signal levels will force the logic components to work constantly, wasting power during the circuit off period.

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4.2 Original oscillator 31

The original oscillator is simulated in schematic level and the simulation results are shown in Chapter 2. All the specifications for the proposed design are decided based on the original oscillator schematic simulation results. Hence the original oscillator’s post layout simulation will not be carried out.

The oscillator is stimulated to start working when the delayed enabling signal Eo

is generated from the bias module. Due to the decaps in different modules, dif-ferent components need to be charged up to start working. Thus the oscillation settles at 2.14 µs, as shown in Fig. 4.2. The Vrcvoltage driven by the trimming

controlled current mirror starts to oscillate after a long period of capacitor charg-ing. 0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 Time [µs] V ol tag e [V] Vrc Eo E

Figure 4.2:Delayed enabling signal triggers the oscillation.

As shown in Tab. 2.2, the oscillator has a deviation of 11.3 MHz at output fre-quency 85.7 MHz. The output clock signal will not be used directly. It will be divided by 8 instead to lower the transition time as well as the frequency stan-dard deviation. Hence the requirement on frequency deviation is not that strict at high frequency output.

Noise is not a concern in this application for the reason that the samples will only be taken when they are settled. Jitters will not affect the performance. However, noise simulations are included in the later sections as references.

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follow-ing sections. These issues are around the capacitor CRamp, involving comparator’s

speed and current mirror transistors’ working regions.

4.2.1 Start-up phenomenon

One of the problems lies on the capacitor voltage during the oscillation stage. As shown in Fig. 4.3, sharp ramps occur in both the charging and the discharging phases.

2.47

0

2.475

2.48

2.485

0.2

0.4

0.6

0.8

1 Time [µs]

V

ol

tag

e

[V]

V

rc

Figure 4.3:Capacitor voltage in oscillation.

This is due to the start-up phenomenon of the trimming control module. As shown in Fig. 3.3, drain nodes of NM6-NM0 and PM5-PM0 will be the same as their source nodes when switches NM14 or PM16 is in off state. NM14 and PM16 are controlled by the inverted Q signal from the SR latch. One of them will be turned off while the other be turned on. During the off state of the switches, all the connected nodes to the source nodes of these switches are floating.

Inevitably, the MOSFETs have to reestablish the correct working region to func-tion as current mirrors after the switches turning on. This phenomenon can be partially resolved by reducing the sizes of the two switches. Smaller switches have less capabilities to handle the current flows, hence the start-up phenomenon can be reduced.

However, smaller switches can not root out the start-up phenomenon. The solu-tion is provided in Secsolu-tion 4.3.

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4.3 Improved oscillator 33

4.2.2 Time delay

Limited by the comparator’s slew rate in different stages, the comparator can not react to the crossing points of Vrc and threshold voltage as fast as in ideal

scenario. As shown in Fig. 4.4b, an approximately 1 ns difference between the crossing point and the output of the comparator exists. All the names in the legend correspond to the nodes in Fig. 3.5.

This is the reason for the deviation of the triggering point. The variation of com-parator’s delay time results in frequency variation with voltage and temperature [20]. It is also showed in the figure that the rising phase of the b- node affects the pulse width going into the SR latch.

The variation of the delay time in the comparator combines with the sharp ramp in the capacitor voltage Vrcworsen the frequency standard deviation, resulting

in a noisy and unpredictable oscillator.

4.3 Improved oscillator

The improved oscillator focuses on the issues mentioned above. For solving the sharp ramps, a duplicate of the current mirrors inside the trimming module is implemented. The logical path of the circuit is simplified to decrease the com-ponents usage, which could lead to uncontrolled PVT variations. As shown in Fig. 4.5, the improved oscillator has two additional current mirrors to keep the MOSFETs staying in the correct working region.

The comparator’s inputs are swapped to achieve a simpler connection between different modules of the oscillator. Current supplies to the comparators are in-creased in order to achieve faster response. The current mirror ratio in the second stage is increased from one to four. The input pair of the comparator is reduced in sizes to achieve faster response as well.

The connections of the comparators are modified to simplify the signal path. This leads to slow responses of the comparators, since the rising and falling edges are flipped at original crossing points. Hence a modification to the capacitor value, which is determined by the gate area of the capacitor connected MOSFET, needs to be taken. The capacitor value reduction is combined with the threshold voltage divider modifications. As shown in Fig. 3.3, R0 is increased while R1 is decreased. The MOS capacitor size decreases to adjust the output frequency as well.

The control switches of the four current mirrors are controlled by CLK. Both S0 and S2 are implemented by PMOSs while S1 and S3 are implemented by NMOSs. During the S0 off state, S3 will be on to provide a current path to maintain PM5-PM0 in Fig. 3.6 at the correct working region, and the same way applies to NMOSs.

The original oscillator uses inverted CLK signal as the control signal for the cur-rent mirror switches, while the improved oscillator uses CLK directly to drive the switches of the current mirrors. This means the inverter INV0 in Fig. 3.6 can be

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2.215 2.22 2.225 2.23 2.235 0 0.5 1 1.5 2 Time [µs] V ol tag e [V] a+ b-Y i+

i-(a)Full-cycle’s oscillation.

2.221 2.222 2.223 2.224 2.225 2.226 2.227 0 0.5 1 1.5 2 Time [µs] V ol tag e [V] a+ b-Y i+ i-(b)Zoomed in view.

Figure 4.4: Comparator internal signals for upper threshold comparison in oscillation.

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4.3 Improved oscillator 35

skipped. The switches NM14 and PM16 can be directly connected to the SR latch output CLK. Ibias S1 S0 Ibias 1.8 V Ibias Ibias S2 S3 CRamp − + − + CMP0 CMP1 Vrc VthH VthL R S Q Q CLK CLK HitHigh HitLow ICharge IDischarge

Figure 4.5:Improved design of the oscillator.

The improved design of the original oscillator is proposed due to the simulation results of an intermediate implementation. By just swapping the inputs, deleting the inverters at the output stages of the comparators and maintaining other com-ponents unchanged, the oscillator showed a nominal output frequency at 61 MHz and a frequency standard deviation of 6.8 MHz.

4.3.1 Schematic simulation

As shown in Fig. 4.7, the ramp capacitor voltage is improved without any sharp ramps. Trimming control module is modified with extra current mirrors and a non-overlapping control signal generator. The non-overlapping circuit is uti-lized to avoid transparent window between switches S0, S1 and S2, S3. The non-overlapping signal generator is shown as Fig. 4.6. S0 and S2 are controlled by PhiP while S1 and S3 are controlled by PhiN. The time difference during the ris-ing phase is 128 ps, and 213 ps durris-ing the fallris-ing phase.

As shown in Fig. 4.7, the capacitor voltage exhibits a saw-tooth pattern waveform. This is achieved with the help of the duplicated current mirror in the trimming module.

The internal signals of the comparator CMP0 are shown in Fig. 4.8. All the names in the legend correspond to the nodes in Fig. 3.5. It should be noticed that the inputs are swapped to achieve inverted output signals from the comparators. Comparing to the original comparator, the modified comparator shows worse

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NOR0

NOR1 INV0

INV1 INV2 INV3 INV4

INV5 INV6 INV7 INV8 INV9

D

PhiN

PhiP

Figure 4.6:The non-overlapping clock generator in the improved oscillator.

2.470 2.475 2.48 2.485 0.2 0.4 0.6 0.8 1 Time [µs] V ol tag e [V] V_rc

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4.3 Improved oscillator 37 2.425 2.43 2.435 2.44 2.445 0 0.5 1 1.5 2 Time [µs] V ol tag e [V] a+ b-Y i+

i-Figure 4.8:Internal signals of the VthHcomparator in the improved

oscilla-tor.

performance in the perspective of output time delay. A simple conclusion could be drawn from the waveform that the slew rate limitation in the rising edge is the reason of the worse time delay. It is clear that the falling edge at the output of the original comparator is steeper than the rising edge of the improved comparator. In the simulation section in Section 5.2, the worsened time delay of the compara-tor does not worsen the frequency standard deviation. Further discussion will be presented in Section 6.5.

4.3.2 Limitations

The improved oscillator exhibits a good frequency standard deviation control when the output frequency is around 60 MHz. The standard deviation is 6.8 MHz at output frequency 61 MHz. However, The frequency standard deviation will rise to 8.5 MHz when the output frequency is increased to 79.2 MHz with smaller capacitor and changed thresholds.

In order to find out the theoretical performance limitation of the oscillator, the capacitor connected MOSFET CRampis replaced by an ideal capacitor in the

Ca-dence default library analoglib. The frequency standard deviation drops to 7.8 MHz, which does not meet the specification. A conclusion can be drawn that the fre-quency standard deviation comes from other modules in the oscillator, most prob-ably from bias generation module. This assumption is confirmed by the noise simulation later.

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The original and improved oscillators are based on the conventional comparator design, which are proved hard to be further improved. This kind of RC oscillator is limited by the comparator and passive components design. Based on capaci-tor connected MOSFET and p+ polysilicon resistor, a current mode oscillator is proposed and implemented based on the requirement on the frequency standard deviatio.

4.4 Current mode oscillator

A current mode circuit is able to operate faster than a voltage mode circuit [21], and effects of the comparator’s non-idealities can be minimized. The clock fre-quency changes due to the comparator’s non-idealities such as offset voltage and finite delay time. Therefore, it is difficult to obtain a stable clock frequency when we consider the effects of PVT variations [5]. Hence a current mode oscillator is proposed and implemented in order to minimize the comparators’ variations. Consequently, achieving the specification of low frequency standard deviation at high frequency output.

4.4.1 Implementation

The reference current input is generated by a bandgap device, which is not in-cluded in the design. Resistors are implemented with poly-silicon and capacitors are implemented with capacitor connected MOSFETs.

The capacitor value of NMC0 should consist dominantly of its own parasitic ca-pacitors. This requires that the size of NMC0 should be large enough in compari-son to NM0, as shown in Fig. 3.12.

This application is designed to have an output frequency of 80 MHz, unlike its prototype in [5], which operates at 32 MHz. Hence the bias currents are modified to satisfy the specification as well as stabilization. Ibias1: Ibias2is set to 1 : 2.

The CMC module is highly symmetric, hence the devices of this module are re-quired to place close to each other to minimize the mismatches during the layout phase. Analog signal wires are better placed far from fast changing digital signal wires, which disrupt the analog signals during the transmission.

The p+ polysilicon resistors’ values are estimated to be 135.6 kΩ with the sizes of 20 segments of 20 µm long and 1 µm wide, spacing between segments 250 nm. Size of NM0 is 2 µm width and 0.4 µm length.

The size of NMC0 is 6.9 µm width and length. NMC0 is approximately 60 times larger than NM0 in area, which makes the capacitor is dominantly decided by NMC0. Switches in the CMC module for Q and Q signals are 1 µm wide and 0.5 µm long. Reset switches have sizes of 0.5 µm widths and lengths.

For the bias generation module, all the NMOSs and PMOSs in the current mirrors have the sizes of 2 µm width and 2 µm length. Switches in the bias module are 1 µm wide and 1 µm long.

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Inverters in the design are implemented with a pair of NMOS and PMOS. The size of NMOS is 460 nm width and 180 nm length, while the size of PMOS is 985 nm width and 180 nm length. Other digital components are shown later in the layout part.

4.4.2 Schematic simulation

When the oscillator works at nominal corner, the trimming code is set to 0, which means the control code to the BCG is 0000. The expected current output from the BCG is 20 µA. As shown in Fig. 4.9, the BCG module outputs a current of 20 µA when the oscillator has a stable oscillation.

0

1

2

3

4 -25

-20

-15

-10

-5

0

5 Time [µs]

C

urren

t

[µ

A]

Figure 4.9:The current generated from the bias current generator at nominal condition.

As shown in Fig. 4.10, the gate voltages of VCC change periodically with the switches toggle on and off. This shows that the current mode comparator works as expected. The VC in the figure indicates the gate voltage of VCC1 in Fig. 3.9

and VCis corresponding to the gate voltage of VCC0.

At the same time, the switches’ control signals Q and Q are shown in Fig. 4.11. They are both output signals of CMC module and internal driving signals. To maintain the oscillation stable, the switches’ sizes are of great concern. A too small switch can result in the termination of the oscillation due to the unfinished

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2 2.005 2.01 2.015 2.02 2.025 0 0.2 0.4 0.6 0.8 1 Time [µs] V ol tag e [V] VC VC

Figure 4.10:The capacitor ramp voltages in oscillation state at nominal con-dition. 2 2.005 2.01 2.015 2.02 2.025 0 0.5 1 1.5 Time [µs] V ol tag e [V] Q Q

Figure 4.11: The output signals of the current mode comparator module in oscillation state at nominal condition.