Precision Amplifier for Applications in Electrical Metrology

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Institutionen för systemteknik

Department of Electrical Engineering

Examensarbete

Precision Amplifier for Applications in

Electrical Metrology

Examensarbete utfört i Elektroniksystem vid Tekniska högskolan i Linköping

av

Stefan Johansson

LiTH-ISY-EX--09/4205--SE

Linköping 2009

Department of Electrical Engineering Linköpings tekniska högskola Linköpings universitet Linköpings universitet SE-581 83 Linköping, Sweden 581 83 Linköping

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Precision Amplifier for Applications in

Electrical Metrology

Examensarbete utfört i Elektroniksystem

vid Tekniska högskolan i Linköping

av

Stefan Johansson

Handledare: Valter Tarasso

SP, Sveriges Tekniska Forsknings Institut

Karl-Erik Rydler

SP, Sveriges Tekniska Forsknings Institut

Examinator: Per Löwenborg

isy, Linköpings universitet

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Avdelning, Institution

Division, Department

Division of Electronics Systems Department of Electrical Engineering Linköpings universitet

SE-581 83 Linköping, Sweden

Datum Date 2009-02-13 Språk Language Svenska/Swedish Engelska/English Rapporttyp Report category Licentiatavhandling Examensarbete C-uppsats D-uppsats Övrig rapport

URL för elektronisk version

http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-16896

ISBN

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ISRN

Serietitel och serienummer

Title of series, numbering

ISSN

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Titel

Title

Precisionsförstärkare för tillämpning inom elektrisk metrologi Precision Amplifier for Applications in

Electrical Metrology Författare Author Stefan Johansson Sammanfattning Abstract

This master’s thesis addresses two main problems. The first is how to suppress a common mode voltage that appears for current shunts, and the second how to let a voltage divider work under an unloaded condition to prevent loading errors and thereby a decreased measurement accuracy. Both these problems occurs during calibration of power meters, and verification of current shunts and voltage dividers. To the first problem three alternative solutions are presented; prototype a pro-posed instrumentation amplifier circuit, evaluate the commercial available instru-mentation amplifier Analog Devices AD8130 or let the voltage measuring device suppress the common mode voltage. It is up to the researchers at SP to choose a solution.

To address the second problem, a prototype buffer amplifier is built and ver-ified. Measurements of the buffer amplifier show that it performs very well. At 100 kHz, the amplitude error is less than 20 µV/V, the phase error is less than 20 µrad, and the input Rpis over 10 MΩ. This is performance in line with the

required to make accurate measurements possible at 100 kHz and over that.

Nyckelord

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Abstract

This master’s thesis addresses two main problems. The first is how to suppress a common mode voltage that appears for current shunts, and the second how to let a voltage divider work under an unloaded condition to prevent loading errors and thereby a decreased measurement accuracy. Both these problems occurs during calibration of power meters, and verification of current shunts and voltage dividers. To the first problem three alternative solutions are presented; prototype a pro-posed instrumentation amplifier circuit, evaluate the commercial available instru-mentation amplifier Analog Devices AD8130 or let the voltage measuring device suppress the common mode voltage. It is up to the researchers at SP to choose a solution.

To address the second problem, a prototype buffer amplifier is built and ver-ified. Measurements of the buffer amplifier show that it performs very well. At 100 kHz, the amplitude error is less than 20 µV/V, the phase error is less than 20 µrad, and the input Rp is over 10 MΩ. This is performance in line with the

required to make accurate measurements possible at 100 kHz and over that.

Sammanfattning

Denna examensarbetesrapport behandlar två huvudsakliga problem. Det första är hur en common mode spänning som uppstår i strömshuntar ska undertryckas och det andra hur spänningsdelare ska förmås att arbeta olastat för att undvika belastningsfel och därmed minskad mätnoggrannhet. Båda dessa problem uppstår vid kalibrering av effektmätare och verifiering av spänningdelare och strömshuntar. Till det förstnämnda problemet föreslås tre alternativa lösningar; tillverka en prototyp till en anslagen kretslösning, evaluera den kommersiellt tillgängliga in-strument förstärkaren Analog Devices AD8130 eller låt det spänningsmätande instrumentet undertrycka common mode spänningen. Det är upp till forskarna på SP att välja en lösning.

För att lösa problem nummer två, byggs och verifieras en buffertförstärkarpro-totyp. Mätningar på den visar ett amplitudfel på mindre än 20 µV/V, ett fasfel på mindre än 20 µrad, och ett ingångs Rp på över 10 MΩ vid 100 kHz. Detta är

prestanda i linje med kraven för att möjliggöra precisa mätningar vid 100 kHz och däröver.

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Acknowledgments

First I would like to thank SP, Technical research institute of Sweden for giving me the opportunity to write this thesis, especially my supervisors Valter Tarasso and Karl-Erik Rydler. I would also like to thank many other employees at SP for giving me support and advices during this work, Ilya Budowsky at National Measurement Insitute Australia, NMIA, for the correspondence on the buffer amplifier and at last my examiner at Linköpings universitet Per Löwenborg.

I would also like to thank my near and beloved for their constant support.

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Introduction

This final year master’s thesis in Applied Physics and Electrical Engineering was carried out at SP, Technical Research Institute of Sweden.

1.1 Structure

After this introduction the background and theory chapters will give the reader a foundation needed to understand the contents of this thesis. Some of the expres-sions used in the background chapter are not explained until the theory chapter, so for some readers it might be a good idea to start with the latter. After this, the two problems occupy one chapter each and the design of a prototype and ver-ification of it occupies the two last chapters before the discussion and conclusions chapter.

References to sections, tables and figures within this report are written as plain numbers. The first digit represents the number of the chapter (or letter if appendix) and the second is a serial digit. Equations are referred to within common brackets ( ) and references to printed books, articles or websites that were used during research are written within square brackets [ ].

Large schematics and plots have been moved to appendix to not disturb the outline of this report.

1.2 Method

The first step in this project was to translate the accuracy of the measurement parameters stated in Section 2.4 into properties of amplifiers. After that the market was scanned for amplifiers meeting the requirements. Some examples of amplifiers with performance at least somewhat close to the desired are described in Section 4.2 and Section 5.2. When no amplifier with good enough performance was found development of new designs were started.

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4 Introduction

1.3 Resources

The main sources for this work have been scientific articles. Most of them have been PDF-files downloaded from databases e.g. IEEE Xplore. Documentation of existing amplifiers and components used in the design have been downloaded from web pages of hardware manufacturers. PSPICE models for components have also been downloaded from manufacturers web pages. There are a lot of books and articles on the topic of interest but since the performance needed is extraordinary, the amount of interesting literature is reduced substantially.

The simulation tool PSPICE and circuit layout application OrCAD Capture was widely used to evaluate performance of different amplifier topologies and monolithic integrated amplifiers. Later on when it was decided to build a pro-totype EDWin XP, was used to layout the printed circuit board (PCB). EDWin XP is a very powerful tool but has a quite complicated user interface. To measure the performance of the built prototype available measurement apparatus at SP was used and all data processing was performed in MathWorks MATLAB.

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Chapter 2

Background

The Technical Research Institute of Sweden, SP, section of electrical measure-ments, manufactures and sells current shunts and voltage dividers designed for accurate measurements in the power frequency range. Today the current shunts and voltage dividers are specified from DC up to a few kHz but there is a demand to specify them for higher frequencies. Limitations in the measurement system used at SP makes verification for higher frequencies impossible and as a step in the development of the measurement system there is a need for precision amplifiers.

2.1 Current Shunts

A current shunt is basically a resistor in which a certain current flows that corre-sponds to a specified voltage drop. This is a way to convert a current into a voltage which is easier to measure. The current shunts developed at SP consist of several high quality resistors mounted in a way that minimizes the effect of parasitics, the design is described in [19].

2.2 Voltage Dividers

Voltage dividers are used at SP to convert a high voltage to a lower one. It implements a common resistive voltage divider with several series resistors to share the power dissipation and a few features to improve the performance. Capacitive compensation of the phase angle due to capacitive loading of the output, together with a capacitive guard divider to minimize the effect of stray capacitances are examples of this. More information about the voltage dividers can be found in [18].

2.3 Why Amplifiers?

To be able to verify current shunts and voltage dividers, and calibrate power meters up to 100 kHz with high accuracy, equipment with very good performance

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6 Background

is needed. In the following sections the problems that occur for high frequency signals are described and possible solutions are briefly introduced.

2.3.1 Calibration of Power Meters

The configuration in Figure 2.1 is the present configuration used for calibration of power meters at SP. This system is described in more detail in [23]. DVM is an abbreviation for Digital Volt Meter.

Figure 2.1. Present configuration for calibration of power meters at SP.

This configuration is limited to 20 kHz due to the sample frequency of the DVMs. Another voltmeter is needed and for this purpose a two channel digitizer that can measure voltage up to 250 kHz with 24 bits resolution is available, see specifications in [7]. The new measurement configuration can be seen in Figure 2.2.

The problem with this configuration is that the two low terminals of the two channel digitizer are internally connected – the high terminal of the current part of the power meter and the low terminal of the voltage input will have the same potential. If the voltage source and current source are grounded, the current shunt is short-circuited. In other words, the two inputs of the digitizer must be separated. One way to do this is to use an instrumentation amplifier, see Section 3.3.4, and input the differential voltage to the high input of the digitizer, as viewed in Figure 2.3. To propose solutions to this problem is the first topic of this thesis.

The second topic of this thesis is how to make the voltage divider work under an unloaded condition. The relatively high output impedance of the voltage divider means that a very high input impedance load is needed to prevent loading errors making accurate measurements possible.

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2.3 Why Amplifiers? 7

Figure 2.2. Calibration of power meter using a digitizer. The two marked nodes will

have the same potential.

Figure 2.3. Calibration of power meter using a digitizer and amplifiers.

2.3.2 Verification of Current Shunts

A similar problem as described in Section 2.3.1 occurs when the amplitude and phase of current shunts is to be verified. Two shunts must lead the same current and are therefore connected in series. The upper of the two has known phase-and amplitude characteristics phase-and acts as a reference while the lower is verified,

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8 Background

see Figure 2.4. When the digitizer is used, instead of two DVMs, to measure the voltage over the two current shunts, the potential on the low side of the current shunts will be the same, making the verification impossible.

Figure 2.4. Verification of current shunts. The two marked nodes will have the same

potential.

To solve the problem an instrumentation amplifier can be used to input the differential voltage to the digitizer and suppress the common mode voltage that appears for the upper shunt. Figure 2.5 shows how this can be done.

Figure 2.5. Verification of current shunts with differential amplifiers.

2.3.3 Verification of Voltage Dividers

To verify the phase- and amplitude characteristics of voltage dividers, two voltage dividers are connected in parallel. This configuration will not give any problems with a common mode voltage since the voltage dividers share the reference point. The issue in this case is instead to let the voltage divider work under an unloaded condition and thereby prevent loading errors. This is achieved by adding a high input impedance amplifier between the current shunt and digitizer, see Figure 2.6.

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2.4 Performance Goals 9

Figure 2.6. Verification of voltage dividers with buffer amplifiers.

2.4 Performance Goals

The goal is to design or find amplifiers making verification with an accuracy ac-cording to Tables 2.1 and 2.2 possible at 100 kHz.

Table 2.1. Performance goals at 100 kHz for current shunts with 5 A input and 0.8 V

voltage drop.

Amplitude ≤ 10 µV/V Phase ≤100 µrad

Table 2.2. Performance goals at 100 kHz for voltage dividers with 240 V input and

0.8 V output.

Amplitude ≤ 20 µV/V Phase ≤200 µrad

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Chapter 3

Theory

This chapter will give the reader a good foundation of theory needed to understand the contents of this thesis. The reader is assumed to have basic knowledge in electrical science.

3.1 Properties of Amplifiers

There are some important amplifier properties and relations that must be well known by the reader. This section will present some of the most important prop-erties for this work.

3.1.1 Amplifier Model

A simple but still very useful model of an amplifier is shown in Figure 3.1. It is characterised by the input impedance, Rin, voltage amplification, Av, and the

output impedance, Rut. If a load resistance, RL, is connected in parallel with the

output, the transfer function of the amplifier can be derived using voltage division, see Equation (3.1), [15].

Figure 3.1. Amplifier model, [15].

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12 Theory Uout Uin = Av· RL RL+ Rout ⇒ Uout Ug = Rin Rin+ Rg · Av· RL RL+ Rout (3.1)

3.1.2 Input and Output Impedances

When a load is connected to an amplifier the output impedance becomes impor-tant. The amplifier must be able to provide enough current without a change in output voltage. The maximum output current is of course limited in all amplifiers. The output impedance of the amplifier in Figure 3.1 is equal to Rout.

To prevent loading errors the input, impedance must be sufficiently high. This is especially important in measurement technology to get accurate measurements. For the amplifier model in Figure 3.1 the input impedance is easily calculated. Ohm’s law directly gives Equation (3.2).

Zin=

Uin

Iin (3.2)

The input impedance of an amplifier can be modelled as a resitor, Rp, in parallel

with a capacitor, Cp. Due to the simple model Rp is often frequency dependent,

Rp(f). Equation (3.4) and (3.5) show how Rp(f) and Cp are calculated when Uin

and Iinare measured. See [16] for the equations in (3.3).

1 Z = Y = G + jB Zin= U_Iinin G= 1 Rp B = 2πfCp                    ⇒ (3.3) Rp(f) = 1 G= 1 Re(Y ) = 1 Re(_Z1) = 1 Re(Iin Uin) (3.4) Cp= B 2πf = Im(Y ) 2πf = Im(_Z1) 2πf = Im(Iin Uin) 2πf (3.5)

3.1.3 Offset Voltage and Bias Current

When an amplifier is fed with zero volts, the output should ideally be zero volts. Due to imbalances in the input stage, the output voltage can be slightly shifted from zero. The voltage that must be applied to give zero volts at the output is called offset voltage.

The ideal operational amplifier, see Section 3.2.1, has no input currents, but there are in reality small input currents, called input bias currents, that must be there to drive the amplifier. To minimize the effect of the input bias currents the input DC resistance should be kept the same for both inputs of the amplifier, [15].

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3.1 Properties of Amplifiers 13

3.1.4 Bandwidth

The bandwidth of an amplifier is usually defined as the frequency where the output voltage has dropped with a factor _√1

2, which corresponds to a drop of 3 dB, see

Figure 3.2. This definition is inappropriate for an amplifier with high performance and accuracy but gives a good hint of the performance when comparing different amplifiers, [15].

Figure 3.2. Definition of bandwidth, [15].

3.1.5 Slew Rate

Slew rate describes how fast an amplifier is. In other words, how big voltage swing it can provide under a certain time. When working with high frequencies and large voltage swings an amplifier with high slew rate is a must, [15].

slew rate= dU(t) dt max (3.6)

3.1.6 THD and SINAD

THD is an abbreviation for Total Harmonic Distortion and can be defined in several different ways. Here it is defined as a percentage of how large the power of the harmonics is relative the power of the fundamental frequency, see Equation (3.7). THD = n X i=2 Pi P1 (3.7) Signal-to-noise-and-distortion ratio, SINAD, is the ratio of the mean-square (RMS) value of the fundamental frequency to the mean value of the root-sum-square (RSS) of all other spectral components excluding DC, and is given in dB. SINAD is a good metrics of the dynamic performance of an amplifier just because it includes both noise and harmonics. Equation (3.8) defines SINAD.

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14 Theory

Under the same circumstances SINAD is equal to THD + N (Total Harmonic Distortion + Noise), with the difference that THD + N often is given as a per-centage, [10].

SINAD = 20 log Psignal

Pnoise+ Pdistortion

(3.8)

3.1.7 Differential and Single-Ended

The amplifier in Figure 3.1 is a single-ended amplifier. An amplifier with two inputs is called differential amplifier. It amplifies the difference between the two input signals, see Figure 3.3. A differential amplifier can have either one or two outputs, if there are two outputs the amplifier is called fully differential. Amplifiers with a differential input and a single-ended output are more common and very useful in many applications. The output voltage of such an amplifier can, for the ideal case, be expressed as in Equation (3.9). Where Av denotes the voltage amplification

and U1and U2the two voltage inputs, [15].

Figure 3.3. Differential amplifier.

Uout= Av·(U1− U2) (3.9)

3.1.8 Common Mode Voltage

The part of the input voltage that is the same of the two inputs of an differential amplifier is called common mode voltage (UCM) and is equal to the mean of the

inputs, see Equation (3.1.8), [15].

UCM =

U1+ U2

2 (3.10)

3.1.9 Differential Mode Voltage

The difference between the input signals is called differential mode voltage (UDM),

see Equation (3.1.9), [15].

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3.2 Operational Amplifier 15

3.1.10 Common Mode Rejection Ratio

As expressed earlier, an ideal differential amplifier only amplifies the differential voltage. But since an amplifier with zero common mode amplification does not exist, Equation (3.9) must be rewritten to Equation (3.12). Here AvDM is the

differential mode gain and AvCM is the common mode gain.

Uout= AvDM· UDM + AvCM· UCM (3.12)

The ability of a differential amplifier to reject common mode voltages is called common mode rejection ratio, CMRR, and is defined by Equation (3.13).

CM RR= AvDM

AvCM (3.13)

CMRR is usually given in dB according to Equation (3.14).

CM RRdB = 20 log

 AvDM

AvCM

(3.14) The common mode gain of a differential amplifier is normally an unknown parameter, this calls for a rewriting of Equation (3.14). When a common mode signal is applied to the differential amplifier the second part of Equation (3.12) is zero which gives Equation (3.15). Combining that and Equation (3.14) yields an easier way to calculate and measure CMRR, see Equation (3.16), [6].

Uout= AvCM · UCM ⇒ AvCM = Uout UCM (3.15) CM RRdB = 20 log  AvDM· UCM Uout (3.16)

3.2 Operational Amplifier

The operational amplifier (op-amp) is a common and very important building block in analogue electronics. It was introduced in the end of 1940’s, in other words about the same time as the transistor. The first op-amps were built from electron tubes. A monolithic integrated circuit op-amp using transistors was first designed by Bob Widlar at Fairchild semiconductors 1964. In the following years he designed many well known op-amps, one of them, the µA741 might be one of the most used op-amps ever, [13].

3.2.1 Operation of Ideal Op-Amps

The symbol of an op-amp is shown in Figure 3.4. It consists of a differential input pair, one inverting and one non-inverting input, and a single-ended output. Vcc

and Vee is the positive and negative power supply connections respectively. The

ideal op-amp have infinite input impedance, no offset voltage and zero output impedance. The bandwidth of the ideal op-amp is infinite and so is the open-loop

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16 Theory

Figure 3.4. Operational amplifier symbol.

gain. The ideal op-amp is far from reality, but it makes calculations of op-amp circuits easy and is often a sufficient model. The behaviour of an ideal op-amp is described by Equations (3.17) and (3.18).

Uout= Vcc for Uin+> Uin− (3.17)

Uout = Vee for Uin+< Uin− (3.18)

This behaviour makes the op-amp very suitable for comparator circuits, but might seem to be a strange behaviour of an amplifier. To get a proper amplifier function from an op-amp there is a need of feedback. The feedback circuit forces the op-amp to work in the active area between the two extreme values Vccand Vee, [6].

3.2.2 Feedback Circuits with Op-Amps

Op-amps are almost always used in feedback circuits. The principle is that a part of the output signal is coupled back to the input to cancel parts of it. This makes it possible to get a predictable gain of op-amp circuits. Feedback has many other benefits as well, for example increased linearity, which also leads to reduced distortion, [6]. Equation (3.19) shows the transfer function of a feedback circuit. Where Avo denotes the open loop gain of the amplifier and β the feedback factor.

Uout

Uin =

Avo

1 + βAvo (3.19)

When Avois large, or infinite, as for the ideal op-amp Equation (3.19) gives

Equa-tion (3.20). Uout Uin = limAvo→∞ Avo 1 + βAvo = 1 β (3.20)

This means that the total gain of the amplifier circuit is independent of the ampli-fier gain, as long as the open loop gain is high enough to satisfy Equation (3.20). The β network is usually resistors and or capacitors.

When analysing feedback circuits with op-amps, two rules are applied. Since the input impedance is infinite, there will be no current flowing into the op-amp, and due to zero offset voltage and infinite gain there will not be any voltage

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3.3 Amplifier Circuits 17

difference between the two inputs. This is expressed in Equations (3.21) and (3.22), [15].

I+= 0, I−= 0 (3.21)

U+= U− (3.22)

3.3 Amplifier Circuits

In this section a few amplifier circuits with op-amps are presented. Some of the circuits, or versions of them, are used later in the thesis.

3.3.1 Inverting Amplifier

Consider the circuit in Figure 3.5. It is an op-amp with feedback resistor R2and

an input resistor R1. This is a common inverting amplifier.

Figure 3.5. Inverting amplifier.

If the op-amp is seen as ideal the analysis of the circuit in Figure 3.5 is simple. Using Equation (3.22) yields that the voltage over R1 is Uin and Uout over R2.

The current through R1 and R2 is the same, according to Equation (3.21), and

Equation (3.23) can be stated using Ohm’s law to calculate the current thrugh the two resistors. Uin R1 = −Uout R2 ⇒ Uout Uin = −R2 R1 (3.23) The input impedance of the inverting amplifier is equal to R1 since the

non-inverting input of the op-amp is at zero volts. This makes it impossible to combine high gain and high input impedance, which is the main disadvantage of the invert-ing amplifier.

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18 Theory

3.3.2 Non-Inverting Amplifier

Figure 3.6 shows a non-inverting amplifier. The transfer function of this topology can be derived using the same rules as for the inverting amplifier, but the voltage at the input terminals comes from a voltage division between R2 and R1, see

Equation (3.24). Uin= R1 R1+ R2 · Uout ⇒ Uout Uin = R1+ R2 R1 (3.24)

The non-inverting amplifier has ideally infinite input impedance. In reality it is equal to the input impedance of the used op-amp.

If R2 is replaced by a short circuit and R1is removed, an amplifier with unity

gain is created. This special version of the non-inverting amplifier is called voltage follower or buffer amplifier.

Figure 3.6. Non-inverting amplifier.

3.3.3 Differential Amplifier

Differential amplifiers are, as discussed in Section 3.1.7, used to amplify the dif-ference between two signals. A common differential amplifier using one op-amp is shown in Figure 3.7. The transfer function of this circuit, Equation (3.25), is derived below using Equations (3.17), (3.18), Ohm’s law and voltage division.

Uin+= U1· R1R+R2 2

Uin+= Uin− U2−Uin−

R1 =

Uin−−Uout

R2            ⇒ U2− U1· _R₁R_+R2 ₂ R1 = U1· R2 R1+R2 − Uout R2 ⇒

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3.3 Amplifier Circuits 19

Figure 3.7. Differential amplifier with a single op-amp.

Uout=

R2

R1

·(U1− U2) (3.25)

To get a high CMRR there is a need for matching between the two resistors called R1and the two called R2. Even a small deviation between the resistors will

give a large decrease in CMRR. The CMRR of single op-amp differential amplifiers is carefully analysed in [17] where it is found that with 0.1 % tolerance resistors and unity gain a typical CMRR for this circuit is only 54 dB.

3.3.4 Instrumentation Amplifier

To get higher input impedance (and the same for both inputs) in the single op-amp differential amplifier, there is a need to implement input buffers. This can be done by just adding two voltage followers, one at each input. But a more clever solution is shown in Figure 3.8. The circuit is often called instrumentation amplifier (IA) because it is often used as a measurement amplifier. An instrumentation amplifier is characterized by high gain, high input impedance, and relatively high CMRR.

In this circuit the differential gain of the total amplifier can be adjusted with a single resistor (R1). The common mode gain is unity for the first stage, and

suppressed by the last amp. This circuit is not as sensitive as the single op-amp differential op-amplifier regarding resistor matching. The transfer function for a three op-amp is derived below, where I denotes the current through R1.

I=U2−U1 R1 U3= U1− R2I U4= U2+ R2I            ⇒ U3− U4= U1− U2−2R2I= U1− U2−2R2 U2− U1 R1 = = (U1− U2) 1 + 2R2 R1 (3.26)

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20 Theory

Figure 3.8. Three op-amp instrumentation amplifier

Combining the expression for the output voltage of a differential amplifier, Equa-tion (3.25), and the expression for U3− U4gives Equation (3.27).

Uout= R4 R3 (U3− U4) = R4 R3 1 + 2R2 R1 (U1− U2) (3.27)

High differential gain in the first stage together with unity gain (R4

R3 = 1) in

the differential stage will give a relatively high CMRR, [6]. Matching between the two input op-amps is nevertheless critical to achieve a really good CMRR. Also this circuits CMRR has been analysed in [17] where a CMRR of about 90 dB was reached for low frequencies.

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Chapter 4

Differential Amplifier

This chapter deals with the first problem of this thesis, described in Sections 2.3.1 and 2.3.2, how to suppress the common mode voltage that appears for current shunts during calibration of power meters and verification of current shunts.

4.1 Required Performance, Differential Amplifier

The first step towards a solution of this problem was to translate the measurement accuracy goals given in Table 2.1 into properties of a differential amplifier.

4.1.1 Common Mode Voltage Suppression

The common mode voltage that appears for the upper current shunt in Figure 2.4 must be suppressed. This can, as earlier described, be done by a differential am-plifier with a single-ended output. To get an amplitude error as small as 10 µV/V the CMRR must be very high. The common mode voltage, UCM, of the current

shunt is determined in accordance with Equation (3.10),

UCM =

U1+ U2

2 =

1.6 + 0.8

2 = 1.2 V (4.1)

Desired differential gain, AvDM, is unity and the output voltage

Uout= 0.8V ± 10 µV/V of 0.8 V. The output of a differential amplifier is according

to Equation (3.12),

Uout = 1 · 0.8 + AvCM·1.2 ⇒ AvCM ≤

0.8 · 10 · 10−6

1.2 (4.2)

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22 Differential Amplifier

This gives a CMRR of,

CM RRdB= 20 log  AvDM AvCM ≥ (4.3) ≥20 log 1.2 0.8 · 10 · 10−6 ≈103.5 dB (4.4)

Over 100 dB CMRR at 100 kHz is not easily achieved and will require a lot of effort.

4.1.2 Input Impedance

There are many versions of current shunts that SP is manufacturing. For example a 5 A shunt has resistance of 0.16 Ω, which corresponds to a voltage drop of 0.8 V. The minimum input impedance to get an amplitude error less than 10 µV/V and phase error less than 100 µrad at 100 kHz is calculated here. Figure 4.1 shows the model used for calculations, this model was discussed in Section 3.1.2. The transfer function from I to U is shown in Equation (4.5).

Figure 4.1. Model used when calculating input impedance.

Z =U I = Rshunt· Rp Rshunt+ Rp · 1 1 + jω ·RshuntRpCp Rshunt+Rp (4.5) Equation (4.6) is an approximation of the magnitude of the transfer function from I to U. It is a Maclaurin series of the first order of the magnitude of Equation (4.5). Rs has been factored out since it is the original impedance without an

amplifier. The term after 1 in the parentheses is the loading error caused by the amplifier. |Z|= U I ≈ Rshunt 1 −1₂2Rshunt Rp +R2shunt R2 p + (ωCpRshunt)2 (4.6) Rshunt

Rp is signaficantly larger than

R2

shunt

R2

p and (ωCpRshunt)

2

whereby they can be neglected and the minimum Rp can be calculated as below.

Rshunt Rp ≤10 µV V ⇒ Rp≥ Rshunt 10 · 10−6 = 0.16 10 · 10−6 = 16 kΩ (4.7)

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4.1 Required Performance, Differential Amplifier 23

The phase lag of Equation (4.5) is,

Φ = arctanω · RshuntRpCp Rshunt+ Rp ⇒ Cp= tan Φ(R shunt+ Rp) ωRshuntRp (4.8)

Equation (4.8) gives a maximum Cpof about 1 nF for Rp= 100 kΩ and Φ = 100 µrad.

This shows that the input impedance is not really a problem in this case since

Rp ≥ 16 kΩ and Cp ≤1 nF is easily achieved, even for high frequencies.

4.1.3 Slew Rate Calculation

The gain of the amplifier does not need to be high. Since the purpose is to take the difference between two signals and not really amplify them. This leads to the use of a unity gain amplifier. The input voltage to the amplifier is not very high either, what can cause a problem is high frequencies. The slew rate needed is calculated according to Equation (4.9), which is derived from Equation (3.6) when a sinusoidal signal is applied.

fmax=

Slew rate

2π ˆU ⇒ Slew rate= 2πfmax

ˆ

U (4.9)

If fmax is given in MHz, slew rate is in V/µs. To have some margin a

volt-age swing of URM S =1 V which gives ˆU ≈ 1.41 V at 100 kHz was used in the

calculation. This leads to a required slew rate of approximately 0.9 V/µs. Since many high performance op-amps on the market have a significantly higher slew rate than needed this will not be a big problem. However, the extreme requirements of linearity in phase and amplitude will lead to the requirement of a fast amplifier.

4.1.4 Bandwidth

The requirement of constant phase up to 100 kHz calls for a very high bandwidth of the amplifier. If no compensation is added and a first order (6 dB/octave) transfer function, A, is assumed, an amplifier with -3 dB point at 1 GHz is required. See the calculations below.

A= 1 1 + j ω ω1 ⇒ |A|= _r 1 1 +ω ω1 2 Equation (4.10) shows the phase lag of A.

ΦA= arctan  ω ω1 ≤100 µrad at 100 kHz ⇒ (4.10) ω1= 2π100 kHz tan(100 µrad) ≈1 GHz (4.11)

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Standard voltage feedback op-amps usually have a -3 dB bandwidth of about 1 MHz. There are amplifiers with much higher bandwidth, but to find one with as high bandwidth as 1 GHz is not possible. Some kind of compensation network must be implemented to keep the phase and amplitude more constant with frequency.

4.1.5 Table of Performance

Performance parameters of a differential amplifier that makes verification of cur-rent shunts and calibration of power meters according to Table 2.1 possible are listed in Table 4.1.

Table 4.1. Required performance of the differential amplifier at 100 kHz.

Parameter Value CMRR ≥103.5 dB

Amplitude error ≤ 10 µV/V Phase error ≤100 µrad

Slew Rate ≥0.9 V/µs

Rp ≥16 kΩ

Gain Unity

4.2 Commercially Available Amplifiers

The next step of this project was to scan the market for existing amplifiers that fulfilled the requirements. It was found to be a hard task. Below are some examples of amplifiers which performances have been tested in simulation using PSPICE.

4.2.1 AD8221

Analog Devices AD8221 is a high performance instrumentation amplifier which gain is set by an external resistor. The CMRR for this amplifier is high, over 110 dB, but only for quite low frequencies, and starts to fall at about 1 kHz. At 100 kHz the CMRR has fallen to about 75 dB. The phase start to fall at about 1 kHz and deviates several degreases from zero at 100 kHz and should in other words need a lot of compensation to fit in the thought application.

This amplifier is too far from the requirements to motivate further investiga-tion.

4.2.2 AD8130

Analog Devices AD8130 is a differential receiver amplifier generally used as a high speed differential line driver, but is also used as a high speed instrumentation amplifier. The AD8130 is typically specified, [5], to have a CMRR of 100 dB at least up to 300 kHz but when the minimum specification is considered the value

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4.3 Custom Design 25

falls to 88 dB. The simulation model, which according to Analog Devices models the minimum performance, shows a CMRR that stays at about 94 dB up to 10 kHz where it starts to fall. The bandwidth of this amplifier is very good, it has -3 dB bandwidth of 250 MHz minimum, [5]. The phase response is, according to simulation, very linear and deviates 1.99 mrad at 100 kHz. But this value is not good enough for this application and some kind of compensation is required, described in Section 4.3.1. Not in the same range as for the AD8221 though.

AD8130 has very good performance and no real competitors have been found from other manufacturers. If the CMRR is somewhat better then the minimum specification and the phase is compensated, this amplifier would be a simple and cheap solution to the common mode problem.

Further investigation of this amplifier is motivated.

4.3 Custom Design

Since no amplifier was found on the market that could assure performance that would fulfil the specifications in Table 2.1 development of a new design was started to see how far such would reach.

4.3.1 Bootstrapped Three Op-Amp Instrumentation

Am-plifier

The CMRR of a regular three op-amp instrumentation amplifier is not good enough for this application, see Sections 2.4 and 3.3.4. However, this is a good circuit to start with but some modifications are required. Many different circuits were considered during the development work and the best alternative is presented in [6], see Figure A.1. It is a standard three op-amp instrumentation amplifier where the two input op-amps have bootstrapped power supplies. The common mode voltage is buffered by a fourth op-amp and fed to a small floating split supply to the two input op-amps. This circuit removes the input common mode signal from the input op-amps because they do not see any voltage swing due to common mode signals at their input relative their power supply. The CMRR of this circuit was simulated to as much as 130 dB at 100 kHz and considerably higher for low frequencies, see Figure B.1. But this is with ideal resistors without any matching errors and no parasitic capacitances that will appear when a printed circuit board is designed. The choice of op-amp is critical in this circuit. It must have high speed, high bandwidth, and high CMRR to reach the required performance. The two input op-amps must also be well matched to not degrade the CMRR. MAX477, [14], by Maxim is well suited for this task. It is a voltage feedback op-amp with very high bandwidth and low gain and phase errors.

The amplitude and phase response of this circuit was not good enough from the beginning and some kind of compensation was required. An op-amp with a capacitor in the feedback network was added after the instrumentation amplifier to bend the phase back towards zero and the gain towards one. The value of this capacitor was tried out with repeated simulations. The compensation part of the

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amplifier can be seen in Figure 4.2. This is a non-inverting amplifier with an added

Figure 4.2. Compensation stage of the instrumentation amplifier.

capacitor. There are also two resistors in parallel at the non-inverting for both inputs to have the same DC input resistance. This reduces the effect of the input bias currents, see Section 3.1.3 for more details. The ideal transfer function of this circuit is derived below.

Uout Uin = R29// 1 jωC9 R29+ R28 = R29+ R28+ jωC9R29R28 R29 (4.12) When there is a big difference between R29and R28, equations for the ideal

op-amp does no longer apply and it is possible to achieve a gain lower than unity for the non-inverting amplifier. The amplifier stage in Figure 4.2 has a gain of 0.99990 to compensate the gain of 1.0001 in the instrumentation amplifier. There are no reasons to trim the resistance values further in simulation since more trimming is a must when the circuit is built anyway, due to resistor matching and parasitics.

As mentioned above, the performance of the three op-amp instrumentation amplifier with bootstrapping is good in simulation with ideal components. The simulated CMRR can be seen in Figure B.1 and satisfies to the requirement. The amplitude and phase response also stays within the requirement but not with a very large margin. The phase deviates 95 µrad from zero and the amplitude shows an error of 8 µV/V at 100 kHz.

The biggest problem with this circuit is that it is very sensitive to unbalanced parasitic capacitances at the input of the differential stage, as little as 0.1 pF degrades the CMRR with as much as 57 dB. Matching of the resistors in the differential stage must also be kept at µV/V level to reach the goals. The influence of parasitics can be lowered by keeping the resistance values low giving a smaller

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RC product and thus higher pole frequency. But too low resistance values tend

to lower the overall CMRR, the reason for this has not been found.

The reasons mentioned above are what make this amplifier hard to implement, but an experienced engineer has overlooked the design and thinks that it is possible to keep the parasitics low enough to meet the performance requirements. Careful symmetric PCB layout and precise component matching is a must.

4.3.2 Instrumentation Amplifier Using CCCII

CCCII is short for the second generation of current controlled conveyors. A current conveyor is a analogue building block with very high bandwidth since it is not limited by feedback as op-amps, [24]. The transfer function of CCCIIs is shown below, [12].   iy Vx iz  =   0 0 0 1 Rx 0 0 p 1     Vy ix Vz   (4.13)

CCCIIs are available in two versions, one with a Z+ output and one with a

Z- output, p in Equation (4.13) indicates witch one the relation apply to. The

interesting thing about current conveyors is that they can implement an amplifier without the use of any resistors. The gain is instead set by the bias current Io

which controls the intrinsic resistance, Rx, of port x. This makes it possible to

build an amplifier with transistors only and thereby avoid all resistor matching problems.

In [11] an instrumentation amplifier using CCCIIs is presented. Since there are no discrete CCCIIs available (only Texas instruments OPA861 that can work as a CCCII+ are known by the author, Texas Instrument was contacted but they do not market any CCCII-) on the market the circuit must be build from scratch. So was done in OrCAD Capture using transistor models and schematics for the CCCIIs presented in [12]. The schematic of this circuit can be seen in Figure A.2 and a block schematic in Figure 4.3. Equtaion (4.14) shows the transfer function of this instrumentation amplifier.

Vo= 2R x3

Rx1+ Rx2

(V1− V2) (4.14)

This circuit has very high CMRR, 140 dB for low frequencies and still above 100 dB up to almost 200 kHz. Neither the phase nor the amplitude response are within the requirements, but a compensation circuit as described in Section 4.3.1 can solve that problem. The high CMRR and no influence of mismatched resistances make this circuit very interesting. The problem is that a custom integrated circuit layout is probably needed. The schematic includes at least 30 transistors (some optimization of the circuit showed can be done) and a discrete layout with that high numbers of components will cause a lot of parasitics and the performance will be heavily degraded. A custom IC layout is out of range for this work and is also way to expensive.

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Figure 4.3. IA with three CCCIIs.

4.4 Digitizer in Differential Mode

It was found that the digitizer, National Instruments PXI-5922, that is to mea-sure the voltage after the amplifier, see Section 2.3.1, can be used with the two channels coupled as one differential. According to the first version of the detailed specification of the PXI-5922, [7], the CMRR should typically stay over 90 dB up to 200 kHz. With this in mind measurements was carried out at the PXI-5922. The results from these measurements are presented in Table 4.2.

Table 4.2. Measured CMRR of PXI-5922 in differential mode.

Frequency [kHz] CMRR [dB] Nom. input imp., fs

1 94.5 1 MΩ, 1 MHz

100 76.1 1 MΩ, 5 MHz

The results was not as good as expected, some deviation can be accepted since the CMRR specification shows the typical performance and these tend to be a bit optimistic. But over 15 dB difference is more than acceptable. After some investigation it was found that National Instruments has changed the specifications of the PXI-5922, see [9]. The updated CMRR specification is shown in Figure 4.4, which corresponds much better to the measurements.

The phase and amplitude properties of this solution would be very good since no additional error from an amplifier is added to the measurement. This solution does however require that an additional digitizer is bought.

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4.5 Comparasion Between Different Options 29

Figure 4.4. Specified CMRR for the PXI-5922 in differential mode, [9].

4.4.1 Digital Instrumentation Amplifier

One option that not has been discussed earlier would be to convert the analogue signals to digital and implement an instrumentation amplifier in the digital do-main. This would also require a digital to analogue conversion after the amplifier to be able to input the signal to the digitizer. This, if it is not possible to tweak the digitizer and make it possible to input digital signals. The number of ADCs and DACs must be kept at as low level as possible to maximize the performance. Each conversion will add errors to the signals.

Another option to reach the CMRR requirement would be to improve the common mode suppression ability of the digitizer by optimizing the hardware.

These two options have not been fully investigated why the performance of them is not known and hard to predict.

4.5 Comparasion Between Different Options

It is very hard to tell in advance how good an amplifier like the one presented in Section 4.3.1 will perform when built. One solution for SP would be to use two digitizers, the CMRR performance is not as good as wanted and this will give an amplitude error. But since no additional amplifier is added in the measurement chain it will be possible to perform phase measurements on current shunts with very high accuracy since the CMRR does not affect the phase of the signals that is to be measured.

A less expensive solution would be to implement the purposed circuit in Section 4.3.1 or to try Analog Devices AD8130. But both these solution will increase the phase and amplitude error which will result in decreased measurement accuracy. It is up to the researchers at SP to choose the solution they prefer.

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Chapter 5

Single-Ended Amplifier

This chapter deals with the second problem of this thesis, described in Sections 2.3.1 and 2.3.3. The voltage dividers in the power meter calibration and verification of voltage dividers circuit must work under an unloaded condition to prevent loading errors and thereby decreased measurement accuracy. This can, as shown in the same sections, be done by adding a buffer amplifier (i.e. gain = 1) between the voltage divider and the digitizer. The buffer amplifier must be as transparent as possible to affect the measurement in an as small range as possible. Very high input impedance is a must to provide an unloaded condition and prevent loading errors or large amplitude inaccuracy will be a fact in the measurement.

5.1 Required Performance, Single-Ended

Ampli-fier

The goals in measurement accuracy that is desired by SP were listed in Table 2.2. These parameters can be translated into performance requirements of the amplifiers in a similar way as for the differential amplifier. Slew rate and bandwidth are calculated in the same way as for the differential amplifier so these are left out here. See Sections 4.1.3 and 4.1.4. The output impedance, DC-errors and temperature dependency should be kept to a minimum, so should the THD and noise.

5.1.1 Input Impedance

The input impedance required to get an amplitude error less than 20 µV/V and phase error less than 200 µrad at 100 kHz is calculated here. A similar model as for the differential amplifier is used, see Figure 5.1.

In Section 4.1.2 an approximation of the magnitude of the transfer function was calculated and it is shown again in Equation (5.1) with the difference that the parameters are according to Figure 5.1.

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32 Single-Ended Amplifier

Figure 5.1. Input impedance model.

|Z|= U I ≈ Rdiv 1 −1₂2Rdiv Rp +R2div R2 p + (ωCpRdiv)2 (5.1) The higher output impedance of the voltage divider (200 Ω compared to 0.16 Ω) gives a smaller difference between the error terms. But Rshunt

Rp is still significantly

larger than R2_shunt R2

p and (ωCp Rshunt)

2

whereby they can be neglected also here. The minimum Rp can thereby be calculated as below.

Rdiv Rp ≤20 µV V ⇒ Rp≥ Rdiv 20 · 10−6 = 200 20 · 10−6 = 10 MΩ (5.2)

Cpis also calculated in the same manner as in Section 4.1.2, see Equation (5.3).

Cp=tan(Φ)(R

div+ Rp)

ωRdivRp (5.3)

The significantly higher output impedance, Rdiv, gives a maximum Cpof less than

2 pF, which is impossible to achieve. But since the voltage dividers are designed to compensate for the capacitive load this will not be problem and a Cp of about

10 pF is acceptable, see [18].

5.1.2 Table of Performance

The performance parameters of the single ended buffer amplifier are listed in Table 5.1.

Table 5.1. Required performance of the single ended amplifier at 100 kHz.

Parameter Value

Rp ≥10 MΩ

Slew Rate ≥0.9 V/µs

Amplitude error ≤ 20 µV/V Phase error ≤200 µrad

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5.2 Commercially Available Buffer Amplifiers 33

5.2 Commercially Available Buffer Amplifiers

There is of coarse also a market of buffer amplifiers. But to fulfil the performance needed in this application is not trivial. Some of the best buffer amplifiers are specified to have a gain flatness of 0.1 dB and a phase error of 0.02 degrees at 100 kHz, which is about 350 µrad. Together with these two requirements the input resistance must be kept high enough and the DC-errors and temperature dependency as low as possible.

Simulations of Analog Devices AD8079, which is one of the better buffer ampli-fiers on the market, [2], shows a gain error of 0.37 % at 100 kHz which is a bit less than the specification of 0.1 dB but much larger than the requirement of this ap-plication. The phase response has, according to the simulation, dropped 530 µrad at 100 kHz, which is a bit more than the 350 µrad specified by the manufacturer. Analog Devices AD8079 is too far from the requirements to motivate further investigation.

5.3 Custom Design

A buffer amplifier design that has very good performance was published in [1]. A somewhat updated schematic of this amplifier can be seen in Figure A.3. It implements a form of bootstrapping, in a similar manner as the bootstrapped instrumentation amplifier in Section 4.3.1. The bootstrapping corrects the ampli-tude and phase error of the op-amps. The amplifier can be considered as three different stages that are explained step by step in the following paragraphs, see Figure 5.2.

Figure 5.2. Sketch of the buffer amplifier.

The input stage makes sure that the input resistance and capacitance are kept at high and low level respectively, due to the FET transistors. Figure 5.3 shows the input stage. The FET input stage is a source follower that has a gain slightly below unity, [6]. The op-amp circuit directly after is there to correct the gain error of the FET stage and provide the bootstrap voltage to the first correction stage. This circuit has a transfer function equal to Equation (4.12) but with a gain, Av,of 1.02 and a pole frequency, fpole, of 81.2 MHz to compensate some of

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Figure 5.3. Input stage of the buffer amplifier.

the bandwidth limitations in the op-amp.

After the input stage there are two compensation stages that correct most of the amplitude and phase error of the input stage. They are regular voltage followers but with bootstrapped power supplies. The output of the input stage serves as bootstrap voltage, shifted ±4.9 V (± 5.6 V ∓ 0.7 V) for the positive and negative respectively, to the first compensation stage. This is done by the zener diodes. Above the zener diodes there is a current regulation diode J505 from Vishay to reduce the voltage dependency of the zener voltage. The voltage from the zener diodes controls the bipolar transistors that provide the power supply voltage to the voltage followers.

As long as the voltage followers do not see any difference from the power supply to the input there will just be a copy of the voltage from the input to the output. For higher frequencies, when the output from the input stage starts to drop due to the limited bandwidth and there will be a difference from the input to the power supply. The amplifier will then have a higher output voltage to be able to satisfy Equation (3.22), that the voltage is the same at the non-inverting and inverting input respectively. This is how the correction works.

A slightly different way to look at the correction is to see the two correction steps as stages producing feedforward signals that are added absolutely to the

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Figure 5.4. Vector diagram of correction principle.

output signal of the input stage. This is illustrated by the vector diagram in Figure 5.4. The ideal function would be two equal vectors, i.e. Vin= Vout. But

since the amplifier will give both amplitude and phase error the first output, Vout1,

differs both in magnitude and angle compared to Vin. The two following outputs

Vout2 and Vout3 correct Vout1 back to Vin almost perfectly.

The last op-amp is there to provide most of the output current when the buffer amplifier is to drive a significant current. Assuming that the voltage is the same at the input of the last op-amp and the output node (Vin= Vin1= Vin2) the values

of the resistors are chosen according to Equation (5.4). See Figure 5.5, where R44

represent the load of the buffer amplifier and Vout−opis the output of the op-amp

(U21). Vout−op−Vin R48 = Vin R44 Vout−op− Vin=Vin_RR45 51    ⇒ R45 R51 = R48 R44 (5.4)

5.3.1 Simulation Results

Simulations of this circuit in PSPICE show that the result of the correction is excellent. Omitting the output stage an amplitude error of less than 0.2 µV/V and phase error less than 1 µrad, can be achieved with proper component selection and a load of 1 MΩ when Analog Devices AD817 is used as op-amp. The frequency dependent input resistance, Rp stays at 20 MΩ up till about 1 MHz where a

discontinuity occurs and the resistance changes to a negative value. More details about component selection is given in Chapter 6. Simulation plots are available in Figures B.2 and B.3.

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Figure 5.5. Output stage of buffer amplifier.

5.4 Comparasion Between Different Options

To avoid loading errors when measuring on voltage dividers there is, as explained, a need of a buffer amplifier. Since the buffer amplifier published in [1] performs so well in simulation it is likely to reach the requirements even in reality. The simulations show results that are many times better than the best commercial available buffer amplifier found.

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Chapter 6

Design of Buffer Amplifier

The simulation results of the buffer amplifier published in [1], further described in Section 5.3, were so convincing that a decision was made to manufacture a prototype with this topology. It was decided to use surface mount devices (SMD) to minimize the signal paths and achieve good high frequency properties. The first version of the buffer amplifier prototype is called version 1.0.

6.1 Component Selection

To carefully select the components is essential. The op-amps are especially im-portant in this circuit since they directly will affect the performance of the buffer amplifier. The small error that many other components, e.g. resistors, cause will be corrected in the correction stages of the amplifier. Anyhow, to reach as good performance as possible resistors, with low tolerances have been used in critical places.

6.1.1 Op-amp Used in Version 1.0

To fulfil the requirements and work in this application the op-amp must be very fast, have low noise and handle a large power supply span. Low input bias currents and thus offset voltage is also important, so is the offset voltage drift with tem-perature. The requirement that the op-amp is fast, a lot faster than the 0.9 V/µs calculated in Section 4.1.3, makes the amplitude and phase requirements reach-able. Simulations with different op-amps have shown that a slew rate of at least 60 V/µs is a must to fulfil the requirements. To have some margin the op-amps that were considered to use in the design have higher slew rate.

Analog Devices AD817, [3], has a slew rate of 350 V/µs and very wide supply range from ±5 to ±15 V. But the DC-performance of this amplifier is not that good with an offset of 0.5 mV typically and 10 µ V/℃ drift. Simulations of the buffer amplifier with this op-amp did however show really good performance. The phase and amplitude responses stayed well under the requirements. Rp, the frequency

dependent input resistance, was calculated in simulation according to Equation 37

Precision Amplifier for Applications in Electrical Metrology

Institutionen för systemteknik

Department of Electrical Engineering

Examensarbete

Precision Amplifier for Applications in

Electrical Metrology

Precision Amplifier for Applications in

Electrical Metrology

Examensarbete utfört i Elektroniksystem

vid Tekniska högskolan i Linköping

av

Abstract

Sammanfattning

Acknowledgments

Contents

List of Figures

List of Tables

Chapter 1

Introduction

1.1

Structure

1.2

Method

1.3

Resources

Chapter 2

Background

2.1

Current Shunts

2.2

Voltage Dividers

2.3

Why Amplifiers?

2.3.1

Calibration of Power Meters

2.3.2

Verification of Current Shunts

2.3.3

Verification of Voltage Dividers

2.4

Performance Goals

Chapter 3

Theory

3.1

Properties of Amplifiers

3.1.1

Amplifier Model

3.1.2

Input and Output Impedances

3.1.3

Offset Voltage and Bias Current

3.1.4

Bandwidth

3.1.5

Slew Rate

3.1.6

THD and SINAD

3.1.7

Differential and Single-Ended

3.1.8

Common Mode Voltage

3.1.9

Differential Mode Voltage

3.1.10

Common Mode Rejection Ratio

3.2

Operational Amplifier

3.2.1

Operation of Ideal Op-Amps

3.2.2

Feedback Circuits with Op-Amps

3.3

Amplifier Circuits

3.3.1

Inverting Amplifier

3.3.2

Non-Inverting Amplifier

3.3.3

Differential Amplifier

3.3.4