LiUMIMO : A MIMO Testbed for Broadband Software Defined Radio

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Institutionen för systemteknik

Department of Electrical Engineering

Examensarbete

LiUMIMO: A MIMO Testbed for Broadband

Software Defined Radio

Examensarbete utfört i Datorteknik vid Tekniska högskolan i Linköping

av

Johan Fältström Fredrik Gidén

LITH-ISY-EX--08/4263--SE

Linköping 2008

Department of Electrical Engineering Linköpings tekniska högskola

Linköpings universitet Linköpings universitet

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LiUMIMO: A MIMO Testbed for Broadband

Software Defined Radio

Examensarbete utfört i Datorteknik

vid Tekniska högskolan i Linköping

av

Johan Fältström Fredrik Gidén

LITH-ISY-EX--08/4263--SE

Handledare: Di Wu

isy_{, Linköpings universitet}

Johan Eilert

Examinator: Dake Liu

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Avdelning, Institution Division, Department

Division of Computer Engineering Department of Electrical Engineering Linköpings universitet

SE-581 83 Linköping, Sweden

Datum Date 2008-12-16 Språk Language Svenska/Swedish Engelska/English ⊠ Rapporttyp Report category Licentiatavhandling Examensarbete C-uppsats D-uppsats Övrig rapport ⊠

URL för elektronisk version

http://www.da.isy.liu.se http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-ZZZZ ISBN — ISRN LITH-ISY-EX--08/4263--SE Serietitel och serienummer Title of series, numbering

ISSN —

Titel

Title Svensk titel_{LiUMIMO: A MIMO Testbed for Broadband Software Defined Radio}

Författare

Author Johan FältströmFredrik Gidén

Sammanfattning Abstract

In order to keep up with the increasing demand on speed and reliability in modern wireless systems, new standards have to be introduced. By using Multiple Input Multiple Output technology (MIMO) and Orthogonal Frequency Division Mul-tiplexing (OFDM) technologies the performance can be increased dramatically. Forthcoming standards such as WLAN 802.11n, WiMax and 3GPP LTE are all taking advantage of MIMO technology. To perform realistic tests with these stan-dards it is often not enough to run software simulations in for example Matlab. Instead, as many real world parameters as possible need to be included. This can be done using a testbed, like the LiUMIMO, that actually transmits and receives data through the air.

The LiUMIMO is designed as a Software Defined Radio (SDR), only the RF front end and the data log are implemented in hardware, while all signal processing will be performed in Matlab.

Nyckelord

Keywords matlab in the air, mimo, radio forensics, SDR, Software defined radio, LTE, WiMAX, LiUMIMO, FPGA

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Abstract

In order to keep up with the increasing demand on speed and reliability in modern wireless systems, new standards have to be introduced. By using Multiple Input Multiple Output technology (MIMO) and Orthogonal Frequency Division Mul-tiplexing (OFDM) technologies the performance can be increased dramatically. Forthcoming standards such as WLAN 802.11n, WiMax and 3GPP LTE are all taking advantage of MIMO technology. To perform realistic tests with these stan-dards it is often not enough to run software simulations in for example Matlab. Instead, as many real world parameters as possible need to be included. This can be done using a testbed, like the LiUMIMO, that actually transmits and receives data through the air.

The LiUMIMO is designed as a Software Deﬁned Radio (SDR), only the RF front end and the data log are implemented in hardware, while all signal processing will be performed in Matlab.

Sammanfattning

På grund av ökad efterfrågan på högre hastigheter och mer robusta trådlösa sy-stem måste nya standardarder introduceras. Genom användning av Multiple Input Multiple Output teknologi (MIMO) och Orthogonal Frequency Division Multiplex-ing (OFDM) kan prestandan ökas markant. Kommande standarder som WLAN 802.11n, 3GPP LTE och WiMAX drar alla nytta av MIMO teknologi. För att kunna göra realistiska tester med dessa standarder räcker det oftast inte med att göra mjukvarusimuleringar, i tex Matlab. För att kunna ta med så många verkliga faktorer som möjligt krävs en testbed, tex LiUMIMO, som både skickar och tar emot data genom luften.

LiUMIMO är designad som en Software Deﬁned Radio (SDR), bara radio delen och dataloggningen är implementerade i hårdvara, medan alla signalbehandling utförs i Matlab.

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Acknowledgments

First of all we like to thank Professor Dake Liu for giving us the opportunity to work with this project. We also would like thank our supervisors Di Wu and Johan Eilert for the tremendous amount of help they have given us during this project. A special thank to Dr. Anders Nilson (Junior) for trusting us to use his boards and code and for all the help. Other persons at the Division of Computer Engineering that deserves special thanks for contributing to our work, making this project possible, are Andreas Eihlar and Anders Nilsson (Senior). Our opponents Christian Östman and Anna Forsberg also deserve our thanks for being able to stand by with such a short notice. Finally we would like to thank our friends and families for all the support and understanding during this project.

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6.3.1 ADC Synchronization . . . 33 6.3.2 ADC/SDRAM . . . 35 6.3.3 DAC/SDRAM . . . 35 6.3.4 ETH/ SDRAM . . . 35 6.4 Hardware . . . 37 6.4.1 SDRAM Interface . . . 37 6.4.2 Ethernet Interface . . . 39 6.4.3 ADC Interface . . . 40 6.4.4 DAC Interface . . . 41 6.5 Hardware Control . . . 43 6.5.1 SPI . . . 44 6.5.2 ARM-bus Interface . . . 44 6.6 System Control . . . 45 7 Testing 47 7.1 Ethernet Test . . . 47 7.1.1 Receive . . . 47 7.1.2 Transmit . . . 48 7.2 SDRAM Test . . . 48

7.3 Ethernet - SDRAM Test . . . 49

7.3.1 Simulations . . . 49 7.3.2 Hardware . . . 50 7.4 ADC Test . . . 51 7.4.1 Packing Algorithm . . . 51 7.4.2 ADC Test . . . 52 7.5 DAC Test . . . 52 7.5.1 Simulation . . . 52

7.6 Full System Test . . . 53

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Contents xi

8 Results 57

9 Future work 59

9.1 Matlab In the Air . . . 59

9.1.1 Transmit . . . 59

9.1.2 Packet Detection . . . 59

9.1.3 DFE - Digital Front End . . . 59

9.2 Real-time Data Streaming . . . 59

Bibliography 61 A Flow Charts 63 B Registers 67 C Interfaces 69 D System Control 71 E Clock Domains 72

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Chapter 1

Introduction

1.1 Motivation

Multiple Input and Multiple Output (MIMO) and Orthogonal Frequency Division Multiplexing (OFDM) technologies have been widely used in wireless communica-tions to increase the spectrum efficiency. There have been an enormous amount of literatures published regarding the theory of OFDM and MIMO. However, the-oretical work using Matlab or C++ simulations are usually based on a number of assumptions and a much simplified model. The best way of validating the theory is by real-world experiments. Therefore, works [9], [10], [11] and [12], described in Chapter 3 have been done on building testbeds using OFDM and MIMO tech-nologies. Different from running Matlab simulations, which are almost for free, building and maintaining a high-quality testbed usually costs a lot of money. It also requires different kinds of knowledges, which is usually absent from the aca-demics. From the efficiency aspects, there is a need to include as many real-world system parameters as possible while minimizing the cost and system complexity. This motivates us to build a compact and configurable testbed to carry out both the data log and real-time demo of a MIMO-OFDM based Software Defined Radio (SDR) system.

1.2 Problem Description

This thesis is related to the ongoing research of MIMO-implementations at the Division of Computer Engineering, Linköping University and aims for a fully func-tional MIMO-testbed. The testbed, when fully developed, should be able to carry out Radio Forensics, “Matlab In the Air” as well as real-time demo. The system will be designed as a Software Deﬁned Radio and will support diﬀerent MIMO standards such as: WiMAX, 3GPP LTE and WLAN 802.11n. Data transfers be-tween a PC and the on board SDRAM memory will be supported by an Ethernet connection. Furthermore the system will be able to send and receive data through an RF-module.

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2 Introduction

The main objectives are design of several interfaces to perform data log: • SDRAM-interface

• Ethernet interface

• ADC/DAC to SDRAM-interface

1.3 Limitations

Creating a fully functional MIMO-testbed from scratch is a risky and time con-suming work, it usually takes several man years. We will therefor use a control board, made by Dr. Anders Nilsson, and some of his code for communication between the diﬀerent units.

Since this is an SDR, the focus will not be on implementing certain standards. The testbed will support Radio Forensics and some parts of the Matlab In The Air feature. Fully working Matlab In the Air and Real-time data streaming will be left for future development.

1.4 Abbreviations

MIMO Multiple Input Multiple Output OFDM Orthogonal Frequency Multiplex-ing FPGA Field Programmable Gate Array RF Radio Frequency DAC Digital to Analog Converter ADC Analog to Digital Converter SDR Software Deﬁned Radio

1.5 Terminology

An N × N MIMO-system refers to a system using N transmitting antennas and N receiving antennas.

0x in front of a number refers to a hexadecimal numbers, for example 0x123. Names written in italic refers to signals used by the interfaces in the FPGA, for example signal_name. The I/O ports of the interfaces can be seen in Appendix C.

Signal names with an overline refers to signals that are active low. For example signal_name.

1.6 Reading Guidelines

Chapter 2: gives some basic knowledge about MIMO-technology and diﬀerent

communication standards using MIMO. This chapter is important to get the big picture of why this testbed is developed.

Chapter 3: contains a study of MIMO-testbeds designed by other research teams. Chapter 4: gives an overview of the diﬀerent tasks supported by the testbed.

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1.6 Reading Guidelines 3

Chapter 5: is more or less a reference for Chapter 6, giving a brief description

of the components used in the system.

Chapter 6: is the most important part of the thesis, explaining the design of our

MIMO-testbed in detail.

Chapter 7: describes how the functionality of the system was tested and what

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Chapter 2

Background

2.1 SDR - Software Defined Radio

With today’s fast growth in communications, it has become important to be able to modify radio devices in an easy and cost-efficient way [1]. One easy way to do this is to move the signal processing into software and keep the Radio Frequency (RF) frontend in hardware, the result of this is called Software Defined Radio (SDR). The best, and most accurate, definition of an SDR is “Radio in which some or

all of the physical layer functions are software defined”[2]. In this way, when it is

needed to modify the radio for a different standard, only the software need to be changed while the RF frontend remains the same. This makes SDRs very flexible, easy and cheap to upgrade compared to ordinary radios. A typical SDR architec-ture can be seen in Figure 2.1. The RF frontend is responsible for transmitting and receiving the signals at the correct frequencies as well as the up/down conver-sion to/from Intermediate Frequency (IF). The AD/DA-converters converts the signals from analog to digital or from digital to analog. The signal processing, that is made in software, is responsible for all signal manipulations for example modulation and demodulation. Of course, in a “true” SDR all parts can be fully programmed, but today there are several limitations that makes this impossible. For example ADC/DAC based on today’s technology can not handle the universal requirement of bandwidth, dynamic range and the sample frequencies defined by the “true” SDR with reasonable cost and power consumption. Instead, the SDR implementations that are commercially successful always come from a trade-off between cost and flexibility. This is usually a combination of programmable and fixed-functional units.

2.2 MIMO - Multiple Input Multiple Output

Multi-antenna or Multiple Input Multiple Output (MIMO) based wireless tech-nologies has been an active research area for decades. It is proved that they can greatly enhance the spectrum eﬃciency by utilizing various degrees of freedom

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6 Background

Figure 2.1: Typical SDR architecture

ing several antennas at both the transmitter and receiver). However, they usually require massive computational power. Until recently, semiconductor technology was not able to accommodate MIMO-baseband processing in mobile handsets. Not only because of the amount of performance and power consumption can not be met, but also because of the limited number of antennas that can be placed in a small handset. Owing to the further scaling of the CMOS process, more and more broadband standards have adopted MIMO as an important feature to boost the performance.

Generally speaking, in wireless systems there are several possible antenna con-ﬁgurations:

• SISO: Single Input Single Output (Figure 2.2a)

• SIMO: Single Input Multiple Output (Figure 2.2b) • MISO: Multiple Input Single Input (Figure 2.2c) • MIMO: Multiple Input Multiple Output (Figure 2.2d)

SISO is of course the most common antenna conﬁguration, using one antenna at the transmitter and one at the receiver. SIMO and MISO conﬁgurations are widely used in for example Digital TV and WLAN.

(a) SISO (b) SIMO

(c) MISO (d) MIMO

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2.2 MIMO - Multiple Input Multiple Output 7

Several widely used MIMO transmission schemes are: • STBC - Space Time Block Coding

• Spatial Multiplexing • Beamforming

2.2.1 STBC - Space Time Block Coding

Space Time Block Coding (STBC) was introduced during the 90’s, but did not become popular until the Alamouti coding was introduced [15]. The Alamouti code is a coding scheme for transmitting data over two antennas. The symbols are transmitted as pictured in Table 2.1. An Alamouti coded system sends two symbols over two time frames. The system is said to have rate-1, meaning that the data rate is neither decreased nor increased. Instead, this makes the transmission very reliable since the same information is sent twice. STBC-systems using a larger number of transmitting antennas can never achieve rate-1, they have to decrease the data rate in order to maintain orthogonality.

Table 2.1: Simple Space Time Block Coding. * Conjugate

2.2.2 Spatial Multiplexing

Spatial Multiplexing means that the system takes advantage of multipath and sends independent information on different antennas [9]. This creates several “vir-tual wires” which increases the throughput of the system. When sending a stream of data over an N × N MIMO-system, using spatial multiplexing, the data stream is first divided into N shorter streams. Each data stream will be transmitted on an individual antenna [8]. The transmitted signals are then mixed in the air (channel) since they are using the same frequency spectrum. More efficient use of the frequency spectrum is one of the MIMO-systems great advantages. Transmit-ting data over an N × N antenna system only uses 1/N of the nominal frequency spectrum. The cost is then moved from spectrum to hardware.

The channel between the transmitter and receiver can be described as a ma-trix , using training symbols. At the receiver side, the receiver ﬁrst identiﬁes the mixing channel matrix. Then the individual transmitted streams are separated and estimated to recreate the original data. A N × N MIMO-system can the-oretically increase the throughput N times. However, in reality the increase in

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8 Background

performance depends on numerous things such as RF-condition and distance be-tween transmitter and receiver. The throughput will therefor never reach the ideal values.

Spatial multiplexing can be performed even though the transmitter has no channel knowledge. This is done by an open-loop system. That can be described mathematically by y = Hs + n, where y is the received signal, s the sent signal, H the channel matrix and n the noise.

If the transmitter has channel knowledge then it is called a closed-loop system. In a closed loop system the transmitted symbols are precoded. Mathematically the closed loop system can be described by y = HW s + n, here W is the precoding matrix and y, H, s and n are the same as above. The closed-loop system gives better performance at lower complexity compared to the open-loop system.

Figure 2.3: Basic spatial multiplexing in a 2x2 MIMO-system

2.2.3 Beamforming

In a multiple antenna system signals can be transmitted from different antennas with different strength. Beamforming technology weights the transmitting power on the antennas. This transmits the signal in the direction of the receiver and away from interference. This improves the Signal to Noice Ratio (SNR). There are two different classes of beamforming, Direction Of Arrival (DOA) and Eigen-beamforming. The DOA-based beamforming is based on a physical direction and Eigenbeamforming is based on a mathematical direction. For the various different incoming signals in DOA-based beamforming, a direction of arrival can be esti-mated using signal processing. From these estiesti-mated DOAs a weighting vector is constructed and used by the antenna system to receive or transmit the desired signal and suppress undesired signals such as noise. Eigenbeamforming uses the channel-impulse response from each antenna element to construct weights that fulfills a certain criteria such as SNR. While DOA-based beamforming requires line of sight, or at least environments with limited local scattering around the transmitter, Eigenbeamforming is more suitable for realistic conditions.

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2.3 OFDM 9

2.3 OFDM

Orthogonal Frequency Division Multiplexing (OFDM) is a promising technology for its capability to convert a frequency selective channel into a number of ﬂat fading subchannels. Due to the property that subcarriers are orthogonal to each other, the guard bands are no longer necessary, which greatly increases the spec-trum eﬃciency.

When increasing the data rate in a single carrier system, the duration of a bit or a symbol is reduced. The system then becomes more sensitive to interference. In an OFDM-system the symbols are divided over diﬀerent subcarriers. The signals in the subcarriers can be overlapped in frequency since they are orthogonal. If orthogonality is maintained, it will still be possible to recover the symbols at the receiver side.

Before sending an OFDM symbol, each subcarrier is independently modulated using Quadrature Amplitude Modulation (QAM). An OFDM signal is equivalent to the inverse discrete Fourier transform of the data sequence. This makes the implementation of OFDM transmitters and receivers easy, see Figure 2.4.

Figure 2.4: Basic OFDM, FFT - Fast Fourier Transform, IFFT - Inverse Fast Fourier Transform

2.4 MIMO-standards

There are several diﬀerent MIMO-standards available. This testbed will support the ones described in this section.

2.4.1 W-LAN 802.11n

802.11n is a proposed amendment to the IEEE 802.11-2007 wireless networking standard. The most important change in 802.11n, compared to previous standards, is the support for MIMO, up to 4 × 4 MIMO, which will increase the through-put signiﬁcantly [5]. Other major improvements in 802.11n will be the usage of beamforming, the increased number of OFDM subcarriers (from 48 to 52) and fast Modulation and Coding Scheme (MCS). MCS recommends the speed of the next packet to be sent. This is useful when the conditions changes in a short time. Some optional conﬁgurations are also introduced: reduced guard interval between transmissions (from 800 ns down to 400 ns) and the bandwidth of the channels can

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10 Background

be doubled (from 20 MHz to 40 MHz). The increased bandwidth is only available under certain circumstances, such as good conditions. STBC can be used to make devices with only one antenna take advantage of the multiple antennas on the access point.

The main speciﬁcations of 802.11n standard are: • Maximal throughput: 600 Mbps

• Typical throughput: 74 Mbps • RF-bands: 2.4 GHz and 5 GHz • Channel width: 20 MHz or 40 MHz • MIMO-support: 4 × 4 antennas

• Range: 70 m indoor and 250 m outdoor

2.4.2 3GPP LTE

To meet the increasing mobile data usage, Third Generation Partnership Project, 3GPP, have started a project called Long Term Evolution, LTE [3].

The main goals for LTE are: • increase the peak data rate • reduce latency

• minimizing cost and power consumption while ensuring backward-compatibility • spectrum ﬂexibility

• improve spectrum eﬃciency

Different antenna configuration are used for the uplink and the downlink [4]. The reason for this is to keep the cost for the terminals (mobile phones) low since there are many more terminals than base stations. In the downlink, two transmit antennas are used at the base stations and two receive antennas are used at the terminals. Configurations with four antennas are also being considered. In the uplink, from the terminals to the base stations, MU-MIMO (Multi-User MIMO) is used. By using this, the base stations still use multiple receive antennas, but the mobile terminals only require one transmit antenna. This reduces the cost for the mobile terminal a lot.

The main speciﬁcations of the LTE standard are: • Peak data rate, 20 MHz spectrum

– Downlink 100 Mbps – Uplink 50 Mbps

• Mobility support up to 500 km/h, optimized for 0-15 km/h • coverage at 5-100 km, slight degradation after 30 km • spectrum ﬂexibility: 1.25, 2.5, 5, 10, 15, 20 MHz

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2.4 MIMO-standards 11

2.4.3 802.16e - WiMAX

802.16, or WiMAX (Worldwide Interoperability for Microwave Access), is a telecom-munication standard that provides high speed data over a wide area [6]. There are two reﬁned versions of the original 802.16 standard, 802.16d and 802.16e. These two standards are used for diﬀerent applications and are optimized for these. The 802.16d standard is used to replace ordinary wired DSL. The 802.16e standard is a mobile version of WiMAX and it is used to provide high speed data at a lower cost. It is OFDM based and it supports a variety of signal-processing techniques, for example spatial multiplexing. It provides data rates up to 15 Mbps at a distance of 2-4 km. More advanced versions of this standard have 2 × 2 and 4 × 4 MIMO support[7].

The main speciﬁcation of the 802.16e standard are: • Typical throughput: 15 Mbps • RF-bands – Europe 3.5 GHz – Asia 2.3 GHz – USA 2.5 GHz • Channel width: 10 MHz • MIMO-support: Up to 4 × 4 antennas • Range: Typical 3 km

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Chapter 3

Testbeds

3.1 Overview

The diﬀerence between testbeds, demonstrators and prototypes is somewhat hard to distinguish [10]

• A demonstrator is often used to show customers the implementation of a new idea, concept or standard. The functionality and design time are often more important than scalability.

• A prototype is the initial realization of a research idea or standard. It is used as a reference or a proof of concept that can be used for further improvements of the product.

• In academics, a testbed is mainly used for research, for example in veriﬁcation of ideas and/or algorithms in a more realistic environment.

There are not many complete testbeds available on the market, and some of them do not include RF-frontends which makes it hard to implement a real physical channel through the air. Due to the lack of good commercial testbeds, a few research teams have chosen to develop their own ones.

3.2 Existing Testbeds

In literature, there have been a few testbeds published. Among them, the Eric-sson LTE testbed and Signalion testbed are from the industry, while the Vienna testbed and ETH testbed come from the academics. Generally speaking, industrial testbeds are usually much more complex than those from the academics because of the high standard needed for commercialization. Academic testbeds are usually simple and lacks a lot of key features that are vital in the industry while of no interest to the academics for publication purposes.

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14 Testbeds

3.2.1 Ericsson LTE Testbed

An LTE MIMO testbed for fast prototyping is published by Ericsson AB [11] which consists of the following parts:

• An application server

• A radio base station

• A host.

The platform is completely programmable, apart from some radio parts. To control the testbed, a graphical user interface (GUI) is used.

The system is very flexible and supports a variety of different antenna configu-rations: SISO, SIMO, 2 × 2 MIMO and 4 × 4 MIMO. When one transmit antenna is used, the testbed supports data rates up to 80 Mbps with a bandwidth of 20 MHz in the downlink. When four transmit antennas are used it supports up to 300 Mbps in the downlink. The main advantage with this testbed is that it is almost completely programmable. As stated above this allows support for many different antenna configurations.

3.2.2 Signalion HIL Prototype (HaLo)

Signalions MIMO prototype is based on Hardware-In-the-Loop (HIL) simulations [12]. HIL starts by taking the most critical functionality out of simulation into the real world, in a wireless system this is the radio channel. After each successful simulation more and more parts of the system are moved from software to the prototype, in the end this gives a complete real-time prototype. Signalions HaLo prototype consists of one transmitter and one receiver which uses two antennas each. This setup limits the transmission to be unidirectional. The transmissions are done in the license-free frequency bands at 2.4 GHz and 5.1-5.8 GHz with a maximum bandwidth of 60 MHz. The maximum sampling frequency is 80 MHz. The HaLo system has an average transmission rate of 108 Mbps while transmitting with spatial multiplexing in a small room. In larger rooms, transmission rates at 48 Mbps can be achieved. One advantage with this testbed is the simplicity, the system is more or less plug and play. Another is the use of HIL simulations that in the end generates a complete prototype. The disadvantage is that the communication is unidirectional.

3.2.3 Vienna MIMO Testbed

Vienna MIMO testbed is developed by the Institute of Communication and Radio Frequency Engineering at Vienna University of Technology. The system consists of six main parts:

• Transmit PC

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3.2 Existing Testbeds 15

• Channel

• Analog receiver-frontend • Receiver PC

• User PCs

The transmit PC and the receive PC are connected to the user PCs via a Local Area Network (LAN). The user controls the transmit PC via a Matlab interface on the user PC. This solution makes it easy for several research teams to share the same testbed for diﬀerent experiments. The transmit PC digitally up-converts the incoming complex baseband data samples. The system supports up to 50 Msps (Mega samples per second) on four channels. For the RF channel, either channel emulators or a physical channel through the air can be used. The physical channel through the air support up to 4 × 4 antennas at the frequency 2.45 GHz. The maximum transmission bandwidth is 6.25 MHz, which makes this a narrowband testbed. The receiver PC is using a maximum sample rate of 6.25 MHz for converting the incoming IF signal down to digital baseband data samples. This limits the maximum system bandwidth further down to approximately 6 MHz. The advantages with this testbed is the Matlab interface that give multiple users access to the same hardware and the ability to support any modulation standards. The disadvantages on the other hand is the limited bandwidth.

3.2.4 ETH Zürich Testbed

ETH (Eidgenössische Technische Hochschule) in Zürich has implemented a Real-Time Multi-Terminal MIMO-OFDM Testbed [13]. This testbed supports up to 4 × 4 antenna conﬁgurations, channel bandwidth of 20 MHz and data rates up to 4 × 52 Mbps. It uses 12 bit AD- and 14 bit DA-converters with the sample rate of 80 Msps. The RF-chain has a superheterodyne design and supports frequencies of 2.4 GHz and 5.2 GHz. The testbed is operated directly from a Matlab interface. Two access points and three terminals are used for testing. No physical channel is used, testing is only done using channel modulators. Advantages with this testbed are the support for both frequencies of 2.4 GHz and 5.2 GHz, support for multiple coding standards and the real-time feature. The disadvantage is mainly that it has only been tested using channel modulators and no physical channel in the air.

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Chapter 4

LiuMIMO

4.1 Overview

The goal of LiuMIMO is to build a flexible platform that allows different kinds of tasks ranging from radio forensic, Matlab-In-Air (MIA) and real-time demo to be carried out using the same platform. Consisting of RF transceivers, ADC/DAC units, an ARM processor and a large FPGA, the testbed can be configured to accommodate the tasks mentioned above.

4.1.1 Radio Forensics

Radio Forensics basically means listen to some radio frequency, record the data and try to identify what has been received. The LiUMIMO is able to receive incoming data transmitted at the license free frequency bands (2.4 GHz and 5.1-5.8 GHz). The recorded data are sent to a PC for processing in Matlab. Processing includes packet detection, channel estimation and demodulation.

Figure 4.1: Radio Forensics using LiUMIMO 17

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18 LiuMIMO

4.1.2 MIA - Matlab-In-Air

Matlab In the Air is mainly for verifying Matlab level algorithm simulations. This mode assumes that the baseband transmitter (Tx), as well as the baseband receiver (Rx) are implemented in Matlab. It also requires the LiUMIMO to access a real radio channel.

The incoming bits are first processed offline in Matlab. Then the output of the transmitter are transfered to the LiUMIMO Tx from the PC. The data is stored in the on board memory. The LiUMIMO Tx converts the digital data to analog baseband signals and then up converts them to RF signals. The signals are propagated through the air, possibly with multiple reflections, to the LiUMIMO Rx board. At the Rx board the incoming analog RF signals will be down converted into analog baseband signals and then into digital baseband. The received digital data can be transfered back to the PC via Ethernet. Finally the signal is processed offline in Matlab. This completes the whole MIA-chain.

Figure 4.2: Matlab In the Air using LiUMIMO

4.1.3 Real-Time Demo

During the prototyping of a baseband transceiver, step by step, more functions can be moved out from the Matlab simulation into the Register Transfer Level (RTL) implementations. Finally, the complete baseband signal processing chain can be accommodated by the FPGA which will allow real-time demo of the system in case there is enough logic and memory in the FPGA. According to our under-standing, given that an advanced FPGA is used, a 2 × 2 MIMO-OFDM (LTE and WiMAX) system with middle-level performance (limited complexity) can be well accommodated by the LiUMIMO.

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4.1 Overview 19

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Chapter 5

Components

5.1 Hardware

The hardware used in the system are described below.

5.1.1 FPGA

Overview

An FPGA is a fully programmable circuit used to implement functions in hardware. FPGA-architectures are often built by 4-input lookup table cells. The way of constructing LookUp Tables (LUT) can roughly be divided in three standards:

• SRAM based

• EEPROM/ﬂash based • fused based solutions

The logic blocks are connected through an interconnect framework. In order to program logic into the FPGA a Hardware Description Language (HDL), such as VHDL or Verilog, can be used. The beneﬁt using FPGAs is that they are reprogrammable, which makes it ﬂexible and easy to upgrade.

Figure 5.1: Basic FPGA building block

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22 Components

Avnet Virtex-4 LX Evaluation Board

The Xilinx Virtex-4 FPGA is attached to an evaluation board from Avnet. Besides the FPGA the board contains an Ethernet connection, AvBuses (used by the SDRAM Expansion module and the control board) and clock generator.

Key parameters for the Xilinx Virtex-4 FPGA: • Up to 200k logic cells.

• Up to 960 user I/Os, 20 I/O standards • Up to 11 Mbits embedded block RAM • DCM support

• Embedded multipliers, 18x18 MAC (Multiply and Accumulate) • Soft processor support

5.1.2 SDRAM

Synchronous Dynamic Random Access Memory (SDRAM) is a DRAM with a synchronous interface. The memory core of an SDRAM and a DRAM are more or less the same, it is the interface to the outside world that are the main diﬀerence [14].

An SDRAM is built up by banks, rows and columns. All banks are identical and have a ﬁxed number of rows and columns. The address is used to point out a certain row and column in one of the banks. Each column has the same width as the memory’s data width. For example if the memory has a data width of 16 bits, each column is 16 bits wide. A memory cell inside a SDRAM can store either ’1’ or ’0’. These cells are made from one transistor and one capacitor. Since the capacitors leak, all cells have to be refreshed with a certain time interval so that the cells do not lose their information due to the leakage. Figure 5.2 shows a clear view of the internal structure of an SDRAM.

Figure 5.2: The internal structure of an SDRAM

Read and write operations in the SDRAM are done in a burst manner. The burst length is set during the initialization of the memory. This means that for

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5.1 Hardware 23

every write command that is given to the SDRAM it will make n consecutive writes, where n is the burst length. In the same way, n consecutive reads will be done with one read command. This is what makes the SDRAM fast compared to for example a DRAM. Another

number related to the SDRAM’s speed is the CAS (Column Address Select) latency. The CAS latency tells how many cycles it takes for the data to be available after a read command is given.

SDRAM Expansion Module

This system uses an SDRAM memory expansion module from Avnet. On this

ex-pansion module there are two SDRAM memories from Micron (2×MicronMT 48LC16M16), each 16 bits wide and can store 32 MB. From the outside they are seen as one 32

bits wide memory that can store 64 MB.

5.1.3 Ethernet

Ethernet is the family of Local Area Network products covered by the IEEE 802.3 standards [16]. There are several Ethernet types such as 10 Mbps Ethernet, Fast Ethernet and Gigabit Ethernet. The Ethernet standard consists of two OSI (Open Systems Interconnection Basic Reference Model) layers, see Table 5.1, the Physical layer and the Data Link layer. The physical layer (PHY) is the one closest to the actual cable. It gets data from the Media Access Control (MAC) in the Data Link layer and translates it into a bitstream to be sent over the cable.

Table 5.1: The seven Layer OSI-model

For communication between the PHY and the MAC there is a Media Inde-pendent Interface (MII). The MII uses a number of control signals to control the transmitting and receiving of data through the PHY. The signals are listed in Table 5.2.

The data is sent using frames. Each frame can send a maximum of 1.5 kB data. A basic Ethernet frame contains seven diﬀerent ﬁelds seen in Figure 5.3.

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24 Components

Table 5.2: The signals from the Media Independent Interface

• PRE: Preamble (7 Byte), an alternating pattern of zeroes and ones used for synchronization.

• SOF: Start-of-frame delimiter (1 Byte), alternating zeroes and ones ending with two ones. Telling the receiver that the next byte is the start of the destination address.

• DA: Destination Address (6 Byte), telling which machine that should receive the packet.

• SA: Source Address (6 Bytes), telling from which machine that sent the packet..

• Length/Type (2 Byte): contains either the length of the data bytes or the type ID of the frame.

• Data (Max 1500 Byte): The data ﬁeld.

• FCS: Frame Check Sequence (4 Byte), 32 bit Cyclic Redundancy Check (CRC)

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5.1 Hardware 25

Fast Ethernet

Fast Ethernet is an Ethernet standard that has a maximum data rate of 100 Mbps. The MAC gets two 25 MHz clocks, tx_clk and rx_clk, from the MII and receives/transmits four bits every clock cycle. In practice, the actual data rate is lower than 100 Mbps because of the preamble and header sequences.

5.1.4 AD/DA-Converter

AD-converter

An AD-Converter (ADC) converts an analog signal into digital values. The basic concept is that the voltage of the incoming signal is compared to a reference voltage. Depending on the ratio between the incoming signal and the reference a different number of digital bits are set high. Key parameters of an ADC are sample rate and resolution. The sample rate, or sample frequency, determines how many samples that are taken from the continuous analog signal every second. The resolution is simply the number of different digital outputs the ADC can give. The resolution is often expressed in number of bits. For example a 3-bit ADC can give eight different output levels.

There are several diﬀerent types of ADCs, the most common are: • Flash ADC

• Successive-approximation ADC

• Sigma-Delta ADC

• Pipeline ADC (Subranging quantizer)

Flash ADCs use several comparators. When the voltage is increased, more comparators turns to one, giving all ones for the highest voltage level. Flash ADCs are very fast but requires a large area on the chip and consume a lot of power.

Successive-approximation ADCs compare the incoming voltage with the output of an internal DAC until it gets a good approximation.

Sigma-Delta ADCs oversample the incoming signal and uses feedback from the digital output via a DAC. The output from the internal DAC is subtracted from the incoming signal and integrated to achieve noise shaping. The eﬀective number of bits can therefor be signiﬁcantly higher than than the actual bits.

PipelineADCs convert the incoming signal in several steps. In the first step a rough conversion is made. In the second step the the difference between the converted and the original signal is determined by a DAC. Then the difference is converted through the whole pipeline chain. In the last step the results are combined and error correction applied. This solution gives high resolution and only need a small area on the chip.

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26 Components

DA-converter

A DA-converter (DAC) converts digital values into a continuous signal. The basic concept of the DAC is that every binary value on the input represent a voltage on the output. When the output voltage changes at a high speed the output becomes near a continuous signal.

The most common types of DACs are • Pulse width modulating DAC

• Interpolating DAC

Pulse width modulation is the simplest DA-conversion technique. A train of pulses that varies in duty time is sent out. The pulses goes through a low pass ﬁlter and the output signal becomes a voltage proportional to the pulse width.

Interpolating DACuses oversampling to be able to use a low resolution DAC internally and then uses an interpolation ﬁlter to increase the eﬀective update rate.

Analog Devices AD9863

AD9863 is an integrated converter for communication applications. It has dual 12 bits DACs as well as dual 12 bits ADCs. The dual 12 bit converters can be used as a 24 bit converter when running the ADC/DAC in half duplex mode.

The ADC uses a pipelined architecture with 9 pipeline steps. Each step, except the last, consists of a low resolution ﬂash ADC and a MDAC (multiplying DAC). The rx-path (ADC) supports up to 50 Msps.

The DAC uses an interpolating current output DAC. Booth channels includes two FIR-ﬁlters making the DAC able to interpolate 1x, 2x or 3x. Th tx-path (DAC) supports an input data rate of up to 160 Msps and a sample rate of maxi-mum 200 Msps.

5.1.5 RF-Module

The RF module is the part that does the actual transmitting and receiving. Since this is an SDR, the modulation is already done in software. This module basically performs the up and down conversions. This circuit consists of a receive path and a transmit path. In the receive path the signal first passes through an Low Noise Amplifier (LNA) that is matched to the antenna. The received signal is then down converted from the RF band to IF band with a mixer. At the same time the signal is split into an I and a Q part. The difference between the I and the Q signals is that they are shifted 90◦in phase. In Figure 5.4a a simple schematic of a receiver

can be seen.

In the transmit path the I and Q signals ﬁrst pass through the mixers to get up converted from the IF frequency band to the RF band. The diﬀerence between the frequencies in the mixers are, as in the the receive path, 90◦ in phase. Then

they pass through an LNA before they go to the antenna. In Figure 5.4b a simple schematic of a transmitter can be seen.

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5.1 Hardware 27

(a) Receiver (b) Transmitter

Figure 5.4: Transmitter and receiver

Maxim MAX2829

This system uses the MAX2829 transceiver from Maxim. It supports both the 2.4-2.5 GHz and the 4.9-5.875 GHz frequency bands, and most important it has MIMO support. One of the requirements for MIMO applications is that all receivers must have a constant relative local oscillator phase [18]. The same requirement holds for all transmitters. To fulﬁll this requirement, all transceivers must have the same external reference source and the MAX2829 must be programmed to enable the MIMO support. The transceiver can be programmed to either transmit or receive data by setting a bit in an internal register. The programming of the registers in the MAX2829 is done with an SPI (Serial Peripheral Interface) bus, see Section 5.2.1.

5.1.6 ARM7-Processor

ARM7 is a family of 32-bits RISC (Reduced Instruction Set Computer) micropro-cessor cores, optimized for low power and low cost. ARM7-promicropro-cessors are mainly used for mobile consumer products, such as mobile phones and portable media players. Main features of the ARM7 family:

• Small dye size and low power consumption

• High code density

• Supports many operating systems, such as Windows CE, Palm OS and Linux.

• Up to 130 MIPs (Million Instructions Per second)

Atmel AT91

Atmel AT91 series is based on the ARM7TDMI processor core. AT91 uses a 32 bit von Neumann architecture with a 16 bit instruction set. The External Bus Interface (EBI) supports 8- or 16-bit data width.

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28 Components

5.2 Communication

5.2.1 SPI - Serial Peripheral Interface Bus

Many devices in the system must be configured to work as intended. For example the AD/DA converters need to be programmed for half duplex and the RF-boards need to be programmed to transmit or receive. All these devices can be configured via an SPI bus. Each device has its own Chip Select (CS) signal but they all share the same data lines. The SPI bus works in full duplex and communicates in master/slave mode, see Figure 5.5. The master is the one that starts the transmission. During one SPI clock cycle the master first sends one bit to the slave and the slave reads that bit. Then the slave sends one bit to the master and the master reads that bit and so on.

Figure 5.5: Basic SPI structure with one master and two slaves.

5.2.2 EBI - External Bus Interface

The ARM7-processor communicates with other units over an EBI (External Bus Interface). A principle schematic of the EBI can be seen in Figure 5.6 below.

Write

A write over the EBI is done in the following way: at the falling edge of the clock the Chip Select signal is set low and at the same time the register address is applied. After the chosen number of wait sates, on the rising edge of the clock, the Write Enable (WE) signal is set low and the data is applied.

Read

Reading is done in a similar manner as the write operation. On the falling edge of the clock the CS signal is set low and the address applied. After the chosen number of wait states the Read Enable (RD) signal is lowered.

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5.2 Communication 29

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Chapter 6

System

Figure 6.1: The Avnet board and the control board.

6.1 System Overview

LiUMIMO testbed is based on an evaluation board from Avnet, containing a Xilinx Virtex-4 FPGA. The board uses an external 64 MB memory expansion module. To send data back and forth from/to the SDRAM an Ethernet connection is used. A custom made control board, made by Dr. Anders Nilsson, is attached to the evaluation board. The control board has an ARM-processor and two AD/DA-converters. The actual transmission and receiving is done by two Maxim radio

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32 System

modules attached to the control board. The transceiver has two antennas and can work either as a transmitter or a receiver at a time. Users can control the system from a PC using a terminal interface to communicate with the ARM-processor.

An overview of the hardware can be seen in Figure 6.2 below.

Figure 6.2: System overview

6.2 Hardware/Software partitioning

The system can be divided into two parts, the part controlled by software and the part controlled by hardware. However the borders are a bit ﬂoating.

The software in the ARM processor controls the communication with the FPGA as well as the hardware on the control board. The control functions, such as starting transmissions and sending data from PC etc, are also implemented in software.

The hardware controlled parts of the system are the SDRAM- and Ethernet-interfaces as well as the interface between the AD/DA-converters and the SDRAM.

6.3 Clock Domains and Timing

The system contains three diﬀerent clock domains communicating with each other, see Figure 6.3. A more detailed view of all clocks and their origin can be seen in Appendix E.

• 40 MHz from the AD/DA-converters • 100 MHz from the FPGA board • 25 MHz from Ethernet PHY

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6.3 Clock Domains and Timing 33

This makes the system vulnerable to timing issues. Providing synchronizations between the diﬀerent clock domains have been a great part of the work.

Figure 6.3: The three diﬀerent clock domains in the system

6.3.1 ADC Synchronization

The clocks to the two ADCs are extracted from the same crystal. The clock from the reference crystal is fed through a clock generator which outputs a 40 MHz clock. This clock is then given as inputs to the two ADCs. However, the path to the two ADCs are not equally long. This means that the two ADCs are running at the same frequency but with a phase diﬀerence. The clocks from the ADCs,

ad_clk1 and ad_clk0, which are used in the FPGA, can therefore not be expected

to have the same phase.

There can also be some unknown delay since the clocks are not routed through clock pins on the FPGA. This makes the signals travel across the board to reach the clock banks, and the phase between the clocks may come to differ even more. The first attempt to synchronize the incoming data was done by using flip-flops, see fig. 6.4. This solution generated some problems. If ad_clk1 is delayed compared to ad_clk0 then the data from ADC_1 might be clocked out by ad_clk0 while it is still changing the data on the input.

For example, let a counter be the input and assume that discharging a data bit takes longer time than driving it high. When the counter reaches the value 0x7FF the next value to be clocked in should be 0x800. However, if there is some phase diﬀerence between the clocks all data bits may not have had the time to change before the clock edge arrives. This might give an error like 0x7FF goes to 0xFFF, see Table 6.1.

(a) Incorrect timing (b) Correct timing

Table 6.1: Timing problem example when data goes from 0x7FF to 0x800 To avoid this kind of timing problem the data from the ADCs must be properly

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34 System

Figure 6.4: Synchronization using ﬂip-ﬂops

synchronized with respect to one of the clocks. The solution was to use two FIFOs reading and writing at the same frequency. First data is written in from the ADCs into two separate FIFOs using the ad_clk0 and ad_clk1 respectively. Then, when there is data present in both FIFOs, the data will be read out simultaneously at the positive edge of the ad_clk0 clock. This synchronizes the data and prevent such timing issues as described above.

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6.3 Clock Domains and Timing 35

6.3.2 ADC/SDRAM

After the data from the ADCs have been synchronized it should be written to the SDRAM. This operation has to cross clock domains, from 40 MHz to 100 MHz. Every 40 MHz clock cycle there will be 48 bits of incoming data, and every 100 MHz clock cycle 32 bits of data can be written to the memory.

The handshaking between the ADC-interface and the SDRAM-interface begins with the ADC-interface setting the sdram_wren signal high. This is done when there is one burst ready to be written to the memory. When the SDRAM is ready it sends out sdram_wr_ready to ADC-interface and a burst is written to the memory. To make the handshaking complete, the ADC-interface takes down the

sdram_wren.

Figure 6.6: Crossing clock domains between ADC and SDRAM

6.3.3 DAC/SDRAM

Transmitting data from the SDRAM to the DACs contains the same clock domain changes and data rates as described in Section 6.3.2.

When transmitting data from the SDRAM to the DACs, the DAC-interface sends out a request for data to the SDRAM by setting the sdram_rden high. When the SDRAM is ready it sets the sdram_data_valid high, and a whole packet is written into the FIFO. To complete the handshaking, the DAC-interface lowers the sdram_rden when the sdram_data_valid is high.

6.3.4 ETH/ SDRAM

The SDRAM is running at 100 MHz, using a clock generated inside the FPGA. The Ethernet interface is using two external clocks at 25 MHz from the MII.

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36 System

Figure 6.7: Crossing clock domains between SDRAM and DAC

Transmit

When transmitting data, the MAC is running at the tx_clk from the MII. In the beginning of every packet the MAC tells the SDRAM-interface to start writing data into the FIFO. The SDRAM-interface responds when it has received the request, making the handshaking complete. Since the SDRAM reads 32 bits at 100 MHz (3.2 Gbps) and the Ethernet send four bits at 25 MHz (100 Mbps), the SDRAM writes one packet at the time to the FIFO. Then it waits for a new data request. This prevents overﬂow in the FIFO.

Receive

When receiving data, the MAC is running on the rx_clk. The data arrives four bits at the time at 25 MHz and when the MAC has received 32 bits the data is written to the FIFO. After a whole burst has been received and written to the FIFO the MAC sets sdram_wren high, telling the SDRAM-interface to write the burst from the FIFO. Since the SDRAM reads out data from the FIFO much faster than the Ethernet data arrives, there is no risk to overﬂow the FIFO.

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6.4 Hardware 37

6.4 Hardware

6.4.1 SDRAM Interface

In order to make the communication with the SDRAM easier an interface was needed. That is because multiple commands are needed to perform one operation. The SDRAM from Micron used in this system accepts the commands shown in Table 6.2.

Table 6.2: Commands accepted by the SDRAM.* If Address bit ten (A10) is low all banks are precharged, if A10 is high only the selected bank will be precharged. ** see 6.9. An x here means that the signal is don’t care.

The interface internally uses a Finite State Machine (FSM) that applies the correct commands to the SDRAM, see Figure A.3 in Appendix A, depending weather a write, a read or an autorefresh is done. The write and read addresses are generated inside the interface, this because all the data will be stored and read from consecutive addresses. Every time a write burst is completed the internal write address will be incremented by four. In the same way, the internal read address will be incremented by four after each finished burst. This, since only the address to the first 32 bits data is needed by the SDRAM, the other three remaining addresses in the burst are calculated internally in the SDRAM from the first address.

Initialization

To initialize the SDRAM several commands are sent to the memory in a given order and in the end, the mode register is programmed. This is done by an FSM, see Figure A.2 in Appendix A. In the mode register the user can set the burst length, burst type, CAS latency and operating mode. The mode register is programmed according to Figure 6.9. During the initialization the following conﬁguration is set:

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38 System

• burst type: sequential

• CAS latency: 2

• operating mode: normal operation

• write burst mode: programmed burst length

Figure 6.9: Micron SDRAM mode register

Write

To write to the SDRAM the user need to set the sdram_wren signal high. The interface set the get_data signal high so that the other units in the system knows when to apply data to the interface. Get_data will remain high for all of the four 32 bits data needed to complete a burst. If only one burst are supposed to be written to the memory, the sdram_wren signal must be lowered when the

get_data signal goes high. If more bursts are to be written, sdram_wren can be

kept high.

Read

To read from the SDRAM the user need to set the sdram_rden signal high. When this is done 90 bursts of four 32 bits data will be read out from the SDRAM. This amount of data corresponds to the size of one Ethernet package, see Section 6.4.2.

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6.4 Hardware 39

When the data is available at the output sdram_dout the sdram_data_valid sig-nal goes high. The sdram_data_valid sigsig-nal will remain high at least four consec-utive clock cycles, since that is a complete burst. It might stay high longer, since 90 consecutive bursts are read out from the memory, with pauses for autorefresh and row or bank changes.

Autorefresh

The SDRAM need to refresh its contents after some time. The interface uses a counter to keep track on when it is time to do an autorefresh. Autorefreshes can only be done when the SDRAM is idle or after a complete burst is written to or read from the memory. Before an autorefresh can be done, all active rows must be precharged.

6.4.2 Ethernet Interface

For transmitting and receiving data via the Ethernet protocol, a MAC-layer is needed. The Ethernet connector at the Avnet evaluation board includes the PHY-layer. Using the MII, the FPGA is provided with a number of signals from the PHY see Table 5.2 The MAC-layer is a sublayer to the data link layer according to the OSI-model se Table 5.1.

The system needed a simple interface to send and receive data to and from the PC. The protocols used are IPv4 as network layer and UDP at transfer layer, according to the OSI-model. Internet Protocol version 4 (IPv4) is the most com-mon network protocol, widely used in practically all internet communication. User Datagram Protocol (UDP) is a protocol that does not require any handshaking before sending data. It does not give any response whether the packet has reached its destination or not. In our case that is not a problem because the risk of losing packets between the PC and the evaluation board is small. This solution was chosen in order to keep the interface simple and not add unnecessary overhead to the system. The Ethernet header as well as the IPv4-header and UDP-header is stored in a block RAM in the FPGA together with the preamble sequence.

Initialization

To initialize the Ethernet it has to be reseted for 600 µs. When the reset is released the PHY performs an auto-negotiation with the PC in the other end of the cable. The auto negotiation mode is set by jumper settings on the Avnet Evaluation board. When the device is using the auto-negotiation mode it automatically sets the highest performance mode. In our case 100 Mb/s full duplex (Fast Ethernet).

Transmit

When the ARM tells the Ethernet interface to start sending data to the PC, a whole packet of data (1440 B) is ﬁrst read from the SDRAM into the FIFO. When there is data in the FIFO the Ethernet starts sending the preamble sequence. This solution prevents the Ethernet to start sending before the SDRAM is ready

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40 System

to provide data. A counter in the FPGA controls which data to send. After the preamble sequence, alternating ones and zeros, a sync bit is sent, then the header starts. When the whole header has been sent the interface reads 32 bits of data from the FIFO and sends it, four bits at the time, over four clock cycles. This goes on until the end of the packet. In order for the PC to accept the incoming packet a correct 32 bit CRC (Cyclic Redundancy Check) must be generated and sent at the end of each packet. During the whole transmission, from the start of the header, a CRC is generated continuously inside the FPGA. When the last data in a packet has been sent the CRC is ready, and written to the output.

Receive

When the user starts receiving data from the PC the Ethernet starts listen to the incoming data_valid signal. When data_valid goes high there is valid incoming data. The ﬁrst incoming data are the preamble sequence. The MAC waits for the sync signal and headers, when the header ends the actual data is starting. The data arrives four bits at the time, and are saved to a 32 bit temporary register. When 32 bits has arrived the temporary register is written to the FIFO. This goes on until the packet ends. After a whole packet has been received, the system starts waiting for valid data again.

6.4.3 ADC Interface

The ADCs need to be connected to the SDRAM memory so that data received from the antennas can be stored. There are two major problems when connecting the ADCs to the SDRAM. The first one is that they work in different time domains. The solution to this problem is discussed in Section 6.3.2. The second difference is that from each antenna one sample is 24 bits. In total 48 bits need to be stored into the memory to get a complete sample. The SDRAM has a data width of 32 bits. To solve this problem, a packing algorithm is needed. The idea is to store the first 24 bits sample from the first antenna and directly after store the first 24 bits sample from the second antenna. Then store the second 24 bits sample from the first antenna and then the second 24 bits sample from the second antenna and so on. If the samples are named Iij and Qij, where i∈[1,2] tells which antenna the

sample is taken from and j∈[1,n] is the time index for the sample, the following sequence will be obtained when reading the data from the memory: I11 Q11 I21

Q21I12...I1n Q1n I2n Q2n.

To get the wanted sequence the 48 bits were stored in three 16 bits wide FIFOs: 1. FIFO0 stores I11 and Q11(11:8), where (11:8) stands for the four MSBs of

Q1.

2. FIFO1 stores the remaining eight bits of Q11, Q11(7:0), and I21(11:4).

3. FIFO2 stores I21(3:0) and Q21.

To get the data in the order described earlier in this section the data need to be read out from two FIFOs at the same time and in a certain order.

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6.4 Hardware 41

1. Read from FIFO0 and FIFO1 2. Read from FIFO2 and FIFO0 3. Read from FIFO1 and FIFO2

Figure 6.10 gives a clearer overview on how the packing is done.

Figure 6.10: Overview of how the data is packed between the ADCs and the SDRAM

In Figure 6.11 a principle schematic of hardware used in the data packing is shown. To control which FIFOs to read from and in which order they should be concatenated in the register connected to the SDRAM, a counter is used. The value of the counter is then decoded to give the correct read enable signals to the three FIFOs and the correct control signals to the two multiplexers.

6.4.4 DAC Interface

When transmitting, data need to be read from the SDRAM and pass through the DAC. The same problem as with the ADCs occur here, two different time domains and two different data widths. The solution to the different time domains are discussed in Section 6.3.3. Another packing algorithm is needed to get the correct data format to the DACs. When sending data to the DAC 240 samples, the size of an Ethernet package, are read from the SDRAM into a FIFO. From that FIFO data is read and stored in four 24 bits registers, REG0, REG1, REG2 and REG3, since each antenna need 24 bits.

1. The ﬁrst 24 bits, I11and Q11, are stored in REG0. The remaining eight bits

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42 System

Figure 6.11: Principle schematic of the hardware used in packing the data between the ADC and SDRAM

2. The next cycle the following 32 bits are read out from the FIFO and they correspond to the remaining four bits of I21(3 : 0) and Q21which are stored

in REG1. The remaining 16 bits I12 and Q12(11 : 8) are stored in REG2.

3. The next 32 bits are read out from the FIFO. The ﬁrst eight bits are the remaining Q12](7 : 0) and they are stored in REG2. The remaining 24 bits

are I22and Q22 and they are stored in REG3.

FIFO0 stores the samples with index 1 and FIFO1 stores the samples with index 2. In step 3, REG0 and REG1 are written into FIFO0 and FIFO1 respectively. Then it starts over from step 1 by reading out data from the FIFO and store it in REG0 and REG1, as described above. In that step, REG2 and REG3 are written to FIFO0 and FIFO1 respectively. This continues until all data are read from the SDRAM. See Figure 6.12 for a clearer view on how the packing is done. To control FIFO0 and FIFO1 a counter is used. The counter value is then decoded to provide the correct control signals to the multiplexers, the enable signals to the registers and the correct write enable to FIFO0 and FIFO1. Figure 6.13 shows a principle schematic over the hardware used when packing the data.

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6.5 Hardware Control 43

Figure 6.12: Overview of how the data is packed between the SDRAM and the DACs

Figure 6.13: Principle schematic of the hardware used in packing the data between the DAC and SDRAM

6.5 Hardware Control

The diﬀerent hardware, such as AD/DA-converters, radio-boards etc. are initial-ized from the software in the ARM through the SPI. The start signals to transmit and receive are also generated in the ARM and written to registers in the FPGA through EBI, described in Section 5.2.2.

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44 System

6.5.1 SPI

The SPI works as described in Section 5.2.1. The SPI-address is generated in the ARM and goes through a hardware decoder on the control board. The address is decoded in such way that the chip select signal for the addressed unit is set. Then data is sent out through the SPI to the selected unit.

Figure 6.14: Programming through SPI

ADC/DAC

The ADC/DACs are programmed to perform as speciﬁed below: • Duplex: Half

• Resolution: 24 bits • Bias: External bias

To change between AD and DA the rx/tx mode is changed.

6.5.2 ARM-bus Interface

The ARM-bus interface is an interface between the ARM7-processor and the FPGA. It is used to set values in control register for diﬀerent units in the sys-tem. Each register is 16 bits wide and has a unique address, see Appendix B. In the FPGA the following registers are available:

• RADIO_0: This register is used to control the MAXIM2829 radio boards. • RADIO_1: This register is used to control the SPI address.

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6.6 System Control 45

• CONTROL: This register is used to set various ﬂags telling if the system is receiving or transmitting via Ethernet and if the system is receiving or transmitting using the radio boards.

• PACKETS: Sets the number of packets to be transmitted.

The EBI need to be conﬁgured to work properly, this is done by a function written in C inside the ARM7-processor. The EBI is conﬁgured as follows:

• Data bus width: 16 bits data bus width • Number of wait states: 8

• Page size: 1 MB page size, active bits in base address 12 (bits 31-20) • Number of cycles added after transfer: 7

• Chip Select: enabled • Base address: 0x4000

When the FPGA acknowledge that the WE from the EBI is set low, it generates a pulse from that signal. On the rising edge of that pulse, the data is written to the addressed register.

When the FPGA has received the RD from the EBI it will place the value of the addressed register on the EBI data bus.

The clock used when reading and writing to the FPGA registers is the same 80 MHz clock that the ARM7-processor is using. To prevent timing issues introduced by the diﬀerence in clock and data routing, wait states and the number of cycles after a transfer is set as high as possible.

Reading and writing are done by functions written in C. The read function takes the address as input while the write function takes data and address as inputs.

6.6 System Control

To communicate with the system the only thing needed is a computer with an USB port and a program that can talk with a COM port. On the control board there is an mini-USB connection that allows connection to a PC. The computer sees this connection as a COM-port. To communicate with this COM-port, HyperTerminal is used. HyperTerminal need to be conﬁgured properly before the connection is established. When the connection is setup, commands to the system can be given from the PC, see Appendix D.

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