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A Thesis submitted to the Faculty and the Board o f Trustees o f the Colorado School o f Mines in p a rtia l f u lf illm e n t o f the requirements fo r the degree o f Master o f Science (Physics).
S i g n e d A , J f> Anthody L, MorroMorroni
Golden, Colorado December 18, 1973 Robert W. M c A llis te r Q a R§rlph B. Bowersox Golden, Colorado December 18, 1973
AHTHUK LAKES LIBRAK1 COLORADO SCHOOL OF MIMES
GOLDEN. COLORADO
T-1609
ABSTRACT
This th e sis describes some o f the necessary c ir c u its fo r use in a multichannel analyzer; in p a rtic u la r those c ir c u its needed in a pulse height analyzer and Mossbauer data analyzer are described. The c ir c u its th a t concern a pulse height analyzer are a s e ria l s h if t re g is te r memory, a tim ing and synchronization c ir c u it , and an analog pulse s tre tc h e r c ir c u it . The c ir c u its th a t could be used in a Mossbauer data analyzer are a p a ra lle l s h if t re g is te r memory, a tim ing and synchronization c ir c u it , and a memory address se le c to r A high frequency voltage fo llo w e r c ir c u it is also described; th is c ir c u it could be used as a b u ffe r stage or in a sample and hold a p p lic a tio n . F in a lly , the im ple mentation o f these c ir c u its in both types o f analyzers is discussed.
TABLE OF CONTENTS
1 In tro d u c tio n . 1
2. S olid State S h ift Register Memories 4
Theory o f Operation. 4
S h ift Registers 4
S h ift Register Memories 5
General Purpose S h ift Register Memory Card 6
D escription o f the Memory Card. 6
IC S h ift re g is te r 10 IC Counter. 12 Level T ra n sla to r 14 In tro d u c tio n . 14 D escription o f Operation. 14 Design Considerations 16
Appll cations o f the General Purpose Memory 18
S e ria l Memory 18
P a ra lle l Memory 20
3. Timing and Synchronization C irc u it. 22
In tro d u c tio n 22
Pulse Height Analyzer. 23
C ir c u it Requirements. 23
C ir c u it Operation 23
Mossbauer Data Analyzer. 30
C ir c u it Requirements. 30
C ir c u it Operation 30
4. Analog Pulse S tre tch e r. 35
In tro d u c tio n 37
Basic Pulse S tretcher C ir c u it. 37
T-1609
Pulse S tretcher Theory, 37
v Super Diode C ir c u it 38
D escription o f Basic Pulse S tretcher C irc u it. 39 P ra c tic a l Pulse S tre tch e r Operational Design. 40 Two Stage Pulse S tre tch e r C ir c u it. , 46
F ir s t Stage 46
F ir s t Stage Output B u ffe r 47
Second Stage. 49
F ir s t Stage Clear and Reset C ir c u it 51
Output B uffer 56
Summary 57
Testing the Pulse S tre tch e r. 59
Determination o f the Minimum Input Pulse Width. 59 Determination o f the Decay Time fo r the Stretched
Pulse. 60
Determination o f L in e a rity , 61
Summary 70
5. Memory Address S elector 71
In tro d u ctio n 71
Operating Sequence 73
C ir c u it Operation. 74
6. High-Frequency Voltage Follower 82
In tro d u c tio n 82
Frequency Compensation o f the SN72702 Operational
A m p lifie r 83 Lag Compensation. 83 Lead Compensation 87 Voltage Follower C ir c u it 90 D escription 90 Computer Modeling 94 Results. 110
7 D escription o f a Pulse Height Analyzer. I l l
8. D escription o f a Mossbauer Data Analyzer. 115
B ibliography. 119
Appendix, 120
7 8 11 15 24 25 26 31 32 37 37 38 39 41 48 50 52 S h ift Register Memory Card Logic Diagram
Memory Card Layout
Required S h ift Register Wave Forms Level T ranslator
Timing and Synchronization C ir c u it (Pulse Height Analyzer) - Logic Diagram.
Timing and Synchronization C irc u it (Pulse Height Analyzer) - Layout
Pulse Train Sequence fo r Pulse Height Analyzer Timing and Synchronization C ir c u it (Mossbauer Data Analyzer) - Logic Diagram.
Pulse Train Sequence fo r Mossbauer Data Analyzer Capacitor Diode Pulse S tretcher,
Input-O utput Voltage o f Capacitor Diode Pulse S tretcher.
Super Diode C ir c u it.
Basic Pulse S tretcher C irc u it. F ir s t Stage (Pulse S tre tch e r), F ir s t Stage Output B uffer. Second Stage
F ir s t Stage Clear and Reset C irc u it.
T-1609
17. Output B u ffe r. 57
18. Block Diagram o f Complete Pulse S tre tch e r. 58 19. Input-O utput Voltage o f Pulse S tre tch e r. 59 20. Equivalent C ir c u it w ith Stray Capacitance E ffe cts, 61
21 Fast Rise Time L in e a rity Graph 66
22. Exponential Rise-Time Pulses L in e a rity Graph 69
23. Memory Address S elector Logic Diagram. 75
23-A. Memory Address S elector Layout 76
24. Clock Wave Form. 80
25. Inverted S h ift Frequency 80
26. Simple Lag Compensation C irc u it. * 83
27. Phase S h ift vs. Frequency. 84
28. Modified Lag Compensation C ir c u it. 85
29. Gain vs. Frequency - Modified Lag Compensation 85 30. Schematic Diagram - SN72702 Operational A m p lifie r, 86
31 Lead Compensation C ir c u it. 87
32. High Frequency Voltage Follower. 89
33. Simple High Frequency Voltage Follower 90
34.* Voltage Follower - Frequency Compensation Computer
L is tin g . 95
35. Computer-Generated Response o f Voltage Follower. 96
36 (a -1 ), Computer Output. 97 - 108
37. Block Flow Diagram - Pulse Height Analyzer 112 38. Block Flow Diagram - Mossbauer Data Analyzer 116
TABLES
1 S h ift Register AC C h a racte ristics. 12
2. S erial Memory Organization 19
3. Data Set 1-A (Fast Rise Time Pulse L in e a rity Data) 64 4. Data Set 1-B (Fast Rise Time Pulse L in e a rity Data) 65 5. Data Set 2 (Exponential Rise Time Pulse
L in e a rity Data), 4 68
6. Example o f Ripple-Through. 78
7 Truth Table, J-K F lip -F lo p 79
T-1609
V
ACKNOWLEDGMENTS
I would lik e to express my sincere appreciation to Dr. R. W. M c A llis te r f o r his patience, help, and a v a ila b ilit y in guiding my th e sis work. I want to thank the Physics Department o f the Colorado School o f Mines and Morroni E lectronics fo r defraying the costs o f my work. I thank Mr. Charles 0. Hook fo r proofreading and typing my th e s is , and Mr. Robert A. Morroni and Mr. James A. L i l l o f o r the e x c e lle n t drawings. F in a lly , I would lik e to e s p e c ia lly thank my parents fo r th e ir constant encouragement and patience, fo r w ith o u t them th is work would never have been completed.
CHAPTER 1 INTRODUCTION
This th e sis tre a ts the development o f some o f the c ir c u its required fo r a multichannel analyzer I n i t i a l l y these c ir c u its were to be applied to a Mossbauer data analyzer fo r research th a t Dr Joseph A. Moyzis, J r , was conducting at the tim e. The organization o f the memory, tim ing and synchronization, and memory address se le cto r are a ll based upon the c r it e r ia o f Dr. Moyzis. Approximately midway in the development o f the Mossbauer data analyzer, Dr Moyzis l e f t the Colorado School o f Mines; consequently, there was no longer a need fo r a Mossbauer data analyzer.
The pulse height analyzer research and design was sta rte d in an e f f o r t to develop a useful to o l and to minimize the time lo s t in the development o f the Mossbauer data analyzer. The memory c o n fig u ra tio n , pulse s tre tc h e r, and the tim ing and synchronization c ir c u it have been developed and tested fo r the pulse height analyzer The pulse height analyzer is to have 100 channels capable o f s to rin g 105 counts per channel w ith inp u t pulses from 0 to 10 v o lts high and 0.5 ys wide.
Chapter 2 deals w ith s o lid s ta te s h if t re g is te r memories. This type o f memory was selected because o f it s low cost and high f l e x i b i l i t y . The memory.may be used e ith e r as a small s e ria l type memory or a.s a
large p a ra lle l type memory. The memory has the c a p a b ility o f a d d itio n
T-1609 2
o f counts, su b tra ctio n o f counts, readout fo r an analog d is p la y , and readout fo r a numeric d is p la y . F in a lly , there is an explanation o f how the memory is applied in a Mossbauer data analyzer and in a pulse height analyzer.
Chapter 3 describes the tim ing and synchronization c ir c u its fo r a pulse height analyzer and a Mossbauer data analyzer These c ir c u its provide the two-phase clocks fo r the memory, the preset load command, and the count enable command. The tim ing and synchronization c ir c u it f o r the pulse height analyzer allows a maximum o f one count to be added in to the memory per address; th is c ir c u it is compared w ith the tim ing and synchronization c ir c u it fo r the Mossbauer data analyzer, which ac cumulates more than one count in the memory per address The tim ing and synchronization c ir c u it allows the memory to be d ig it a lly synchro nized w ith other c ir c u its fo r added s t a b ilit y .
The pulse s tre tc h e r c ir c u it is described in Chapter 4. This c ir c u it , which is used only in a pulse height analyzer, accepts a 0 to 10 v o lt pulse o f 0.5 ys minimum duration and stretches i t fo r 0.2 ms m aintaining a lin e a r re la tio n s h ip between the input and output voltages
. The memory address s e le c to r, as described in Chapter 5, was
designed fo r use in a Mossbauer data analyzer. This c ir c u it selects the the p a rt o f the memory w ith in which data are to be stored. The c ir c u it cycles the memory at a high s h if t frequency u n til the s ta r t lo c a tio n in the memory is reached; the c ir c u it then cycles the memory a t a slower s h if t frequency through the addresses where data are to be stored; f i n a l l y the c ir c u it cycles the remaining addresses in the memory at
the high s h if t frequency. This c ir c u it minimizes delays inherent in using one p a rt o f a large s h if t re g is te r memory.
Chapter 6 discusses a high frequency voltage fo llo w e r This c ir c u it was developed fo r the pulse s tre tc h e r c ir c u it ; however, the f in a l version o f the pulse s tre tc h e r did not require the high frequency voltage fo llo w e r. This c ir c u it accepts a 0 to -5 v o lt signal and has a bandwidth o f 5 MHz.
Chapter 7 is a block d e s c rip tio n o f a pulse height analyzer and shows the a p p lic a tio n o f the c ir c u its th a t have been developed fo r the pulse height analyzer. The d e scrip tio n also explains the c ir c u its th a t have to be developed to make a working pulse height analyzer
Chapter 8 deal's w ith a Mossbauer data analyzer and explains how the c ir c u its th a t have been developed would be used in a Mossbauer data analyzer. The d e scrip tio n also o u tlin e s the c ir c u its needed to make a complete Mossbauer data analyzer.
T-1609
CHAPTER 2
SOLID STATE SHIFT REGISTER MEMORIES
Theory o f O peration:
S h ift R egisters: A s h if t re g is te r can be analyzed as a series
§
o f J-K f lip - f lo p s . Figure 1 gives a block diagram o f a s h if t re g is te r composed o f J-K f l ip - f lo p s , and the waveform fo r the s h if t pulse.
J QZ Z K QZ S h ift Pulse i+_______ • Figure 1
The operation o f a s h if t re g iste r-b e g in s a t p o in t 1 o f the s h if t pulse; a t th is p o in t the slave is is o la te d from the master. At p o in t 2 the values o f QA and QA from f l i p - f l o p A are entered in to the master o f f l i p - f l o p B by way o f the J and K inputs o f B. This sequence also occurs in the remaining f l ip - f lo p s , each receiving the data from the previous stage. At p o in t 3 the J and K inputs are disabled, and the values o f J and K are locked in to the master. At p o in t 4 the inform ation stored in the master is tra n s fe rre d in to the slave. The QB and OB’ outputs o f the B f l i p - f l o p
now assume the value th a t QA and QA had before the s h if t pulse a rriv e d . Data are entered in to the s h if t re g is te r through the J and K inputs o f f l i p - f l o p A in a manner s im ila r to the way th a t data are entered in to f l i p - f l o p B from f l i p - f l o p A. Data are read out o f the s h if t re g is te r through the QZ and QZ outputs o f f l i p - f l o p Z, Therefore, in the operation o f a s h if t re g is te r data which are entered in to the s h if t re g is te r are remembered fo r as many s h if t pulses as there are f l i p - f l o p s , and these data c o n s titu te the output o f the la s t f l i p - f l o p .
S h ift Register Memories: A s h if t re g is te r can be used as a drum type memory device when the s h if t re g is te r is connected in a re c irc u la tin g loop. This re c irc u la tio n is accomplished by connecting the la s t f l i p - f l o p 's outputs, QZ and QZ, to the J and K inputs o f the A f l i p - f l o p . When con nected in th is manner the data, which have gone through the e n tire memory and are now at QZ and QZ, reenter a t the beginning o f the memory, The data then re c irc u la te through the memory.
The primary d i f f i c u l t y w ith a memory o f th is type is the entry and r e tr ie v a l o f the data stored w ith in the memory. This d i f f i c u l t y is
overcome by in s e rtin g in the feedback loop o f the s h i f t re g is te r a device to read out o f or w rite in to the s h i f t re g is te r. This device allows the data to be entered in to , changed w ith in , and read from the memory,
This type o f memory does not allow the random access o f any address, as would be possible w ith a random access memory. The s h if t re g is te r memory must in general be cycled whenever an address is to be accessed. In large s h if t re g is te r memories the inherent delays become a real problem. The means to circumvent th is problem are explained in the section e n title d Memory Address S elector,
T-1609 6
General Purpose S h ift Register Memory Card:
D escription o f the Memory Card: The s h if t re g is te r memory card is illu s t r a t e d in Figure 2. The design o f the memory is based on a binary coded decimal (BCD) form at. The memory uses fo u r 5 1 2 -b it s h i f t re g is te rs and one up-down presetable counter as the computation device. At some lo c a tio n in one s h if t re g is te r one o f the fo u r necessary BCD b its which c o n s titu te a decimal number is stored. The fo u r s h if t re g is te rs then store one complete decimal d i g i t in BCD.
The s h if t re g is te rs require a two-phase clock in p u t. The two-phase clock s h ifts the re g is te r and also enables the read and the w rite opera tio n . The output clock is $1; data are read out from the s h if t re g is te r on a lo w -to -h ig h tra n s itio n o f the $1 clock. The inp u t clock is $2; data are read in to the s h if t re g is te r on a low -to-high tra n s itio n o f the $2 clock. External to the memory there is a tim ing and synchroniza tio n c ir c u it th a t generates the two-phase clock pulses. These pulses are timed according to the a p p lic a tio n th a t the memory must serve.
The outputs o f the s h if t re g is te rs 1-1, 1-2, 1-3, and 1-4 are connected to the A, B, C, and D preset inputs o f the counter, 1-5. The-A, B, C, and D outputs o f the counter are fed back to the inputs o f the s h i f t re g is te rs , 1-1, 1-2, 1-3, and 1-4 re s p e c tiv e ly .
By placing the counter in the feedback loop fo r the re c irc u la tin g s h if t re g is te r , data can be entered in to , cleared from, changed w ith in , and read out o f the s h i f t re g is te r.
Data- are entered in to and changed w ith in the s h if t re g is te r in the fo llo w in g sequence. A lo w -to -h ig h tra n s itio n o f the output clock $1 causes the values o f the n-th b its from I -1 , 1-2, 1-3, and 1-4 to appear
s~ <u to - P V- c O O O O CD 3 O O O O -M O > > > > 4-> w u r • • M— • r - (_> O Q <3* II II II II CVI 4-> *r— CD Q +-> 2 : Z 1 r — •r— jr r CD \ 03 < C < t 4—4 CD LO CO tO D i ZD — 1 * 4-> CO ra C M 4— 4 c s r — C M L O L O L O L O C D L O r — r— c ; c s c z m 0 O O O 0 O O C M s - + - > + - > ^ 3 - < 3 - ■=3' > > 1• r — O O C O C O c o C O r - » r ^ . r ^ » t o 4— 4 O CD C D s : 2 : s : 2 : T ~ s c • 0 • L O L O «« CD r — 1— 5 ~ r > ~ S I 0 0 t o 0 0 t o C M r — t o + 1 c c CD O ) 1 t o C O II 11 II II 11 II 11 11 II II II II II 4— 4 t t J 4 - > Q - a . - a C M C O L O t o r ^ » C O r — C M C O 0 Q i - • 1— • r ~ • r — 0 3 1 1 1 1 1 1 1 1 1 1 1 0 O O S - r ~ J S C D *— 1 1— 4 ►— I »— « ►—I 4— 4 4— 4 C tL C il c c > > I o 1 3 O O Q sL 2 0 COJ) — <)_ stQ o r o \ / o \ f < \ / ® \ / cb M CO V ° i <tc!> O O (D cM O I > a V S . " 1 H c r co 3 -> c /-> t * 0 <X 0
-czz
- d Z • - C Z 3 - H H H ' <Hi-CM vO O lo <C CD I O Q In I I oS(T 3" lO <r H - r J d Z h ^ d z i T d Z l J - < E ? o CSJ J I M r ac o CO j H r <D c QC d i H x o -cx ->. Run**? ( v » o aa. O £ ) ■> -yvsn? ->■ uwon <| V ) © ? ■^•(MmOCJ -J ■> OQa -yz«t> ■> i<t> S h if t Register M em or y C ar d L o g ic D ia gr am F ig u reT-1609 8 i 7 H O Q e ~ - a i p 3 ~ « i c\j f7W0l r< X 10 O s > CP «0 I o o -> S . O o CQ 0 O -c 0 0 -J 0-3 c 3 o a -h C 3 0 3 O -C u 0 _c "0 o o -t- o a _ i _ j 3 o <n 3 O 3 C + C O o
O }< I® IO | Q | < ICO icJ JQo o o —^ _i J
M em or y C ar d L a y o u t F ig u re 2-A
a t the outputs. These fo u r outputs, which c o n s titu te one decimal d i g i t , are used to load the preset counter. The counter w i l l now e ith e r count up (add counts) or count down (su b tra ct counts) according to a predeter mined command from an external sw itch. A fte r a predetermined time the inp u t clock $2 then loads in to 1-1, 1-2, 1-3, and 1-4, the fo u r BCD outputs o f the counter. The s h if t re g is te r then s h ifts to lo c a tio n n+1 and the sequence begins again.
To c le a r memory requires only th a t the c le a r be enabled in the counter. Then, as the re g is te r s h if t s , only zeros can be entered
because the c le a r holds the output o f the counter a t zero. Consequently, only zeros are w ritte n in to the s h i f t re g is te r.
I f there is no count pulse (command) present the preset counter's output w i l l assume the value o f the preset in p u t. The counter w ill not change value, and the s h if t re g is te rs w ill behave as a re c irc u la tin g memory. This mode is ideal fo r storage o f in fo rm a tio n , as w ell as fo r reading out o f the memory. The read-out process is non-destructive and allows fo r the sampling o f data w hile the memory is c y c lin g .
Included on the memory card are two means fo r data o u tp u t; there are a continuous output and a latched output. When enabled the continuous output reads out the instantaneous value o f the counter in BCD. This type o f output would ty p ic a lly be used fo r a cathode ray tube (CRT) d isp la y. Here the continuously changing output from the counter w ill be applied to the inp u t o f a d ig ita l-to -a n a lo g converter, and the output o f the d ig ita l-to -a n a lo g converter w ill then give a c o n tin u a lly changing analog output o f the memory. The latched output assumes the value o f the counter output when the la tch pulse is .re c e iv e d , and stores th is
T-1609 10
value u n t il the next la tc h pulse is received. When the la tc h output is enabled the value o f the counter output a t the time o f the la tc h pulse is then provided. This type o f readout would be used fo r a numerical tube or te le typ e o utput, where the output must be present fo r a period o f time longer than is required by a CRT d isp la y.
Both the latched and the continuous output are o f a bussed
c o n fig u ra tio n . In unbussed memories th a t require many cards there are necessarily fo u r output wires from each card. By using the output bus and strobing the output gates o f the memory card there are only fo u r output lin e s fo r the e n tire memory and one strobe lin e fo r each card. This reduces the backpanel w irin g and s im p lifie s the actual hand w irin g . The output gates fo r the memory are ope n -co lle cto r 2 -in p u t NAND gates, One in p u t o f the NAND gate is from the counter, in the case o f the continuous o utput, or from the la tc h , in the case o f the latched output. The other in p u t to the NAND gate is one o f the strobe inputs fo r the card. When the strobe in p u t is a t lo g ic level "1" then the output o f the NAND gate is the complement o f the other input to the gate. When the strobe in p u t is a t lo g ic le ve l "0" then the output o f the NAND gate is a t lo g ic le ve l "1" independently o f the other in p u t. The open c o lle c to r gates can have th e ir outputs p a ra lle le d to give the w ire AND-function. This fe a tu re allows implementation o f the BCD output bus and reduces the o u tp u t-lin e requirement. The output is the complement o f the BCD code.
IC S h ift R e g iste r: The s h if t re g is te r chosen fo r the memory a p p lic a tio n is a M o no lith ic Memories, Inc. MM3405. I t i s a 512 b i t re c irc u la tin g dynamic s h if t re g is te r. This integrated c ir c u it features
a wide operating frequency range o f 30 Hz to 4 MHz. The slow s h if t frequency in many a p p lica tio n s is q u ite advantageous. The MM3405 is a s ilic o n gate metal oxide semiconductor device; however, i t is e a s ily in te rfa c e d w ith the standard TTL lo g ic by use o f some external re s is to rs . The w r ite /re c ir c u la te and read co n tro ls and chip s e le c t gates were not used in the present a p p lic a tio n . An im portant c h a ra c te ris tic o f the s h i f t re g is te r in designing in te rfa c e c ir c u its to TTL lo g ic is the large clock capacitance o f 80 p f This a ffe c ts the le ve l tra n s la to rs because they must be capable o f d riv in g ca p a citive loads.
Conditions of Test
Input rise and fall times: 10 nsec
Output load is 1 TTL gate Timing Diagram
BIT 1 BIT N DATA OUT 0 n OUTPUT CLOCK 02 INPUT CLOCK DATA IN I —
►jtowi>4-CLOCK REP RATE
WRITE/RECIRCULATE CHIP SELECT 1 CHIP SELECT 2 tc,+_H - i h - w +5 | 1 ' » +5 READ 0 J \ F igure 3
T-1609 12
The Timing Diagram fo r the s h i f t re g is te r is given in Figure 3 ^ Clock pulses shown here are produced by the Level T ra n sla to r,
A d d itio n a l AC c h a ra c te ris tic s f o r the s h if t re g is te rs are given in Table 1^
A.C. Characteristics
T Case = - 5 5 ° C t 0 + 8 5 ° C ; V CC = -^ V ± 5 % ; VDD = - 5 V ± 5 % ; V|LC = (Vcc -1 4 ) to (Vcc -1 7 ); Rl = 3K; C L = 20pf; 1 TTL Load; 36% Duty Cycle unless otherwise noted.
SYM BO L TEST M IN . MAX. UNIT C O N D ITIO N S
FREQUENCY CLOCK & DATA REP RATE 200 Hz @25°C Note 1
2 MHz
t<^>pw CLOCK PULSE WIDTH 0.180 10 fi sec
tyd CLOCK PULSE DELAY 30 nsec
t ; tf CLOCK PULSE TRANSITION 1 Atsep
tow DATA WRITE (SET-UP) TIME 100 nsec
tDH DATA TO CLOCK HOLD TIME 20 nsec
-ta+;ta- CLOCK TO DATA OUT DELAY 250 nsec
*R—>
tcS-
‘WR-CLOCK TO “ READ” OR “CHIP SELECT” OR “WRITE/ RECIRCULATE” TIMING 0 nsec tR+; tcs+ *WR + CLOCK TO “READ” OR “CHIP SELECT” OR “WRITE/ RECIRCULATE” TIMING
0
nsec
Cin INPUT CAPACITANCE 5 pF @ 1 MHz; V = V CC; V=250mV p-p
C o u t OUTPUT CAPACITANCE 5 PF @ 1 MHz; V =V CC; V=250mV p-p
C ( f ) CLOCK CAPACITANCE 80 PF @ 1 MHz; V = V CC; V=250mV p-p
Table 1
One a d d itio n a l fa c to r c o n trib u tin g to the se le ctio n o f these s h if t re g is te rs is the cost per b i t . The cost o f one cent per b i t makes the s h i f t re g is te r memory very a ttr a c tiv e , and the fa c t th a t the memory does not perm it random access can be to le ra te d .
IC Counter: The counter used in the feedback loop o f the s h if t re g is te r is a Texas Instruments SN74192, which is a synchronous 4 - b it up/down counter. The SN74192 is a preset counter, required in the memory
a p p lic a tio n in which the s h if t re g is te r must load the counter. The
counter is also an up/down counter, which gives the memory the c a p a b ility o f both adding counts in to and subtracting counts from the memory. This is p a r tic u la r ly useful in a pulse-height analyzer because i t provides a convenient method fo r su b tra ctin g background counts, subtracting
spectra, e tc.
The high c le a r in p u t forces a ll outputs to be low, independently o f the count and preset inputs. The counter has both borrow and carry outputs fo r e a s ily cascading the stages. There are two count inputs provided. The d ire c tio n o f counting is determined by which count inp u t is pulsed. The SN74192 g re a tly increases the f l e x i b i l i t y o f the memory fo r the nominal cost o f $1.92.
T-1609 14
Level T ra n s la to r:
In tro d u c tio n : The s h if t re g is te rs require a two-phase clock input fo r s h if t in g , data in p u t, and data output. The lo g ic determining the tim ing and synchronization o f the two-phase clock depends upon the ap p lic a tio n o f the s h if t re g is te r. The use o f the tr a n s is to r - tr a n s is to r lo g ic (TTL) fo r the two-phase clock would li m i t the output voltage o f th is c ir c u it to standard TTL le v e ls , approximately 0 v o lts and +5 v o lts , The MM3405 s h if t re g is te rs require a two-phase clock voltage swing o f -10 v o lts to +5 v o lts . This necessitates the use o f a le ve l tra n s la to r which w ill tra n s la te the TTL le ve ls o f 0 and +5 v o lts to -10 and +5 v o lts re s p e c tiv e ly . The clock inp u t fo r an MM3405 has a predominently re a ctive in p u t whose capacitance is 80 p f
D escription o f Operation: The level tra n s la to r is shown in
Figure 4. 1-1 represents a standard TTL gate. The actual in p u t o f the le ve l tra n s la to r is Q - l; the operation is more e a s ily fo llo w e d , however, by in clu d in g the gate in the discussion. When the input o f 1-1 is at lo g ic level "1" the output o f 1-1 is a t lo g ic level "0" Logic level "0" is approximately 0 v o lts . With 0 v o lts applied to it s base Q-l conducts. T ra n sisto r Q-l is the source o f s u ffic ie n t cu rre n t to saturate tra n s is to r Q-2, When tra n s is to r Q-2 sa tu ra te s, i t applies -9 .5 v o lts to the base o f the complementary e m itte r fo llo w e r consisting o f Q-3 and Q-4. The output voltage is approximately -10 v o lts under these conditions.
I f the in p u t o f 1-1 is a t lo g ic level "0" the output o f 1-1 is at lo g ic le ve l "1" Logic le ve l "1" is approximately equal to +5 v o lts , and +5 v o lts applied to the base o f tra n s is to r Q-l w ill tu rn o f f Q-l
io cc cc 0) <o CD to o •r— O. .>> o o s: co ii r— <d c. <o w o s- o o o> <D O- *r— -o C S- r - O OJ rj *r— •!-CD Q - o o a ii i a *o *+-E l O a a a o o o m o o «— r-II r-II r-II CM CO I I I ccac cc 1 0 DC CM CM r^ . O LO t o c o CD ZD LO o o 0 0 0 0 s : c l. Q . O -0 -0 s CZ S I II II II II r— CM CO 1 1 1 1 c r c r c r c r L e ve l T ra n s la to r F ig u re
T-1609 16
With tra n s is to r Q-l o f f there is no base cu rre n t fo r Q-2; Q-2 is consequently turned o f f The c o lle c to r o f Q-2 is now a t +5 v o lts . The +5 v o lts is applied to the base o f the complementary e m itte r fo llo w e r, g ivin g an output voltage o f the level tra n s la to r o f approxi mately +5 v o lts .
The complementary PNP-NPN e m itte r fo llo w e r allows the level
tra n s la to r to a c tiv e ly p u ll the output to e ith e r +5 v o lts or -10 v o lts .
Design C onsiderations: R esistor R-2 is 470 ohms and has a p o te n tia l d iffe re n c e o f 4.5 v o lts across i t when tra n s is to r Q-l is conducting. The c o lle c to r cu rre n t o f Q-l is approximately 10 mA.
Q-2 is an NPN, high speed, saturated sw itching tra n s is to r. Q-2 is a type number MPS3646, which has switching times o f 25 ns fo r time to turn on and 35 ns fo r time to turn o f f The forward cu rre n t gain h^e has a minimum value o f 30.
For tra n s is to r Q-2 w ith a base current o f 10 mA and an h^e o f 30, s a tu ra tio n re s u lts fo r
50ft < R-3.
Another c o n s tra in t on tra n s is to r Q-2 is the maximum c o lle c to r cu rre n t. This cu rre n t is 300 mA; R-3 has to be large enough th a t th is cu rre n t l i m i t is not exceeded. The value o f R-3 in the actual c ir c u it is 150 ohms, which s a tis fie s both o f the above co n stra in ts,
The capacitors C-l are used to bypass the power supply lin e s , These provide tra n s ie n t operating cu rre n t to the tra n s la to r which could not be provided by the power supply because o f in d u ctive leads They also reduce feedback between stages and reduce the tendency to
o s c illa te . Without diode D - l, the output o f the level tra n s la to r has some rin g in g fo llo w in g a pulse tra n s itio n . Diode D-l is inserted between the output o f the level tra n s la to r and the -10 v o lt supply and decreases the amount o f rin g in g . I f the output o f the level tra n s la to r f a lls
below -10 v o lts in p o te n tia l the diode D-l is forward biased and conducts The rin g in g , which would go below -10 v o lts , forward biases diode D -l; the diode consequently q u ic k ly drains the energy out o f the s tra y capacitance and inductance which are causing the rin g in g .
R esistor R-4 is suggested by the manufacturer o f the s h if t
re g is te rs as an in te rfa c in g stage between the level tra n s la to rs and the s h if t re g is te rs ' clock inputs.
The complementary e m itte r fo llo w e r Q-3 and Q-4 w i l l have to charge the clock capacitance o f the s h if t re g is te rs through re s is to r R-4. The R-C charging time w i l l determine the number o f s h if t re g is te rs th a t may be driven by the level tra n s la to r. From Figure 3 and Table 1 the maximum allowable clock pulse tra n s itio n time is 1 ys fo r a
tra n s itio n o f the clock o f 90% o f the fin a l voltage. A 90% tra n s itio n corresponds to approximately three R-C time constants. Therefore
3{R- 4HCc lo c k H n } < 1 v s ’
where C ] ^ = 80 p f / s h if t re g is te r , n = the number o f s h if t re g is te rs , and R-4 = 100 a. Consequently, n is approximately equal to 40, and the le ve l tra n s la to r should be able to d riv e about 40 s h if t re g is te rs ,
T-1609 18
A pplications o f the General Purpose Memory:
S erial Memory: In a s e ria l BCD memory data may be stored in a h o rizon ta l stack. The A b i t o f each coded decimal d ig it is stored in s h if t re g is te r 1-1; s im ila r ly , the B b it is in 1-2, C is in 1-3, and D is in 1-4.
To store a fiv e decimal d ig it number in the s e ria l memory the 10° decimal d i g i t is stored in b its 1 o f s h if t re g is te rs I -1 , 1-2, 1-3, and 1-4; s im ila r ly , the 101 d i g i t is in b its 2, the 102 d i g i t is in b its 3, the 103 d ig it is in b its 4, and the 10^ d i g i t is in b its 5 o f the s h if t re g is te rs I -1 , 1-2, 1-3, and 1-4. The address number 0 con s is ts o f b i t numbers 1 through 5 o f the fo u r s h if t re g is te rs . B it numbers 6 through 10 c o n s titu te address number 1, etc.
A memory o f 100 addresses capable o f s to rin g a fiv e d ig it number in each address requires one memory card. The size o f the memory is determined by the size o f the s h if t re g is te rs used on the card. For 5 1 2 -b it s h if t re g is te rs the above memory has 12 extra b its which can be used to store a d d itio n a l data.
Table 2 b e tte r illu s t r a t e s the s e ria l memory c o n fig u ra tio n . In actual operation i f a count is to be added in address 1, then when s h if t re g is te r b i t #6 is reached and the output clock has loaded the preset counter, a pulse is applied to the inp u t o f the counter, increasing decimal b i t 10° by 1 The in p u t clock then loads the new b i t #6 in to the s h i f t re g is te rs . The carry output o f the counter then is sensed as to whether a count should be added to the b i t #7, the 101, o f address #1 I f so, the above process is fo llo w e d ; i f n o t, there is no pulse to the counter, and the value o f b i t #7 does not change.
TABLE 2
S erial Memory Organization
S h ift Register 1-1 1-2 1-3 1-4 BCD-A B it # BCD-B BCD-C BCD-D Address .Address 496 497 498 499 500 Address #99
T-1609 20
A s im ila r procedure is follow ed to su b tra ct counts; however, the borrow is now sensed ra th e r than the carry.
The tim ing and generation o f the pulse is c a rrie d out by the tim ing and synchronization c ir c u it .
P a ra lle l Memory: In a p a ra lle l BCD memory the data are stored in a v e rtic a l stack. This memory c o n fig u ra tio n requires more than one
memory card. I t requires one memory card per decimal d ig it o f the number to be stored. Therefore, i f a number o f order fiv e is to be stored, then fiv e memory cards are needed.
Each card in the memory stores one complete d ig it . 1-1 stores the A b i t , 1-2 the B, 1-3 the C, and 1-4 the D. The 10° are stored in card 1, the 101 in card 2, the 102 in card 3, 103 in card 4, and 104 in
card 5. Address #0 comprises b its #1 on a ll cards, address #1 comprises b its #2 on a ll cards, e tc.
The cards are chained together to form the v e rtic a l stack. The size o f the number to be stored is determined by the number o f cards; the number o f addresses is determined by the size o f the s h if t re g is te r.
• This memory c o n fig u ra tio n presents the various d ig its o f a number stored in a given address sim ultaneously. The count pulses are applied to the in p u t o f the u n it's decade memory card. The te n 's decade memory card receives it s in p u t from e ith e r the borrow output o f the u n it's card i f the counts are to be subtracted or the ca rry output o f the u n it's card i f the counts are to be added. This scheme is continued fo r as many decades as necessary in the memory.
The strobe output fe a tu re is p a rtic u la r ly useful fo r th is memory c o n fig u ra tio n . The number o f cards needed to store a large number d ic ta te s the necessity fo r a bussed output.
This memory co n fig u ra tio n allows fo r e a s ily expanding the memory c a p a b ility , th a t is , the magnitude o f a number th a t can be stored. This expansion is accomplished by simply adding more cards to the memory, The expansion o f the address c a p a b ility o f the memory requires the a d d itio n o f more s h if t re g is te rs to each card. This is the same type expansion d i f f i c u l t y as would be found in a s e ria l a p p lic a tio n o f the general purpose memory.
The p a ra lle l memory co n fig u ra tio n is useful fo r large memories because the time needed to load the memory is on the order o f 50 ns fo r a fiv e d i g i t number. This time is determined by the response time of the SN74192 decade counters. The time needed to load a s im ila r number in a s e ria l memory is 2.5 ys, This time is determined by the maximum s h i f t ra te o f the MM3405 s h i f t re g is te rs ,
T-1609
CHAPTER 3
TIMING AND SYNCHRONIZATION CIRCUIT
In tro d u c tio n :
As indicated in the section e n title d S h ift R egisters, the two- phase clock determines the reading in to and w r itin g out o f memory. The most accurate and r e lia b le means fo r generating the two-phase clock signals is d ig it a lly . This method, as opposed to a method which re lie s upon an R-C tim ing network to generate the tim ing and synchronization necessary fo r the s h if t re g is te rs , is more precise and allows fo r d e fin ite time synchronization.
The in p u t to the tim ing and synchronization c ir c u it is a master
clock. This clock provides the pulses th a t the tim ing and synchronization c ir c u it counts in order to generate the c o rre c t pulse tr a in fo r the
s h f f t re g is te rs . Any e rro r introduced by the master clock may change the read-in tim e, or w rite -o u t tim e, etc. This e rro r w ill not change the synchronization given by the pulse tr a in .
Pulse Height Analyzer:
C ir c u it Requirements: Figure 5 shows a tim ing and synchronization c ir c u it appropriate fo r a p p lic a tio n in a pulse height analyzer The fu n c tio n o f th is c ir c u it is to generate the proper pulse tra in fo r the two-phase clo ck, preset load command, count enable command and the add/subtract 1 count to memory command. A c h a ra c te ris tic o f the pulse height analyzer is th a t only one count per address may be added per cycle o f memory. The tim ing and synchronization c ir c u it must provide f o r th is fe a tu re .
The pulse tr a in sequence is depicted in Figure 6. The required sequence is one in which the low -to-high tra n s itio n o f the $1 clo ck, the output clock o f the s h i f t re g is te r , occurs w ith in the command to load the preset counter. The count enable and the add 1 count occur a fte r the preset counter has been loaded. The count in p u t and the preset load are disabled when the $2 c lo c k , the inp u t clock o f the s h if t
re g is te r, makes it s low -to-high tra n s itio n .
C ir c u it Operation: The in p u t to the c ir c u it is the square wave generated by the master clock. This square wave is a 10 .MHz signal
th a t is applied to the in p u t o f I - l - B , J-K f l i p - f l o p . The J and K inputs o f the f l i p - f l o p are connected to the +V This connection makes the f l i p - f l o p change states on each clock pulse. The B output o f I - l- B is the clock inp u t fo r another J-K f l i p - f l o p , I - l - A , also connected to toggle. I - l- B divides the master clock by two, and I - l- A divides the output o f B. by two; the output o f the master clock is , th e re fo re ,
T-1609 24 O -o -o o Q r - 2 2 Z U - < < < £ 1 • Z Cl • r + > - P 4-> r - 3 3 3 UL_ O - CL C L c c c 2 ^ M M t—1 1 1 1 1 •3 s r CO c o o o 0 M -c o c m 0 C L * 3 - »sf r v . O 2 : z : s 2 "3" t o c o ( / ) 00 IX ) I I II II 11 II r— CO CO r— I 1 1 1 1 1—1 ►—1 •—• •—1 CJI o cn cr> i o e 3 o o tn E V o IcQ < *o LU O +-> 4-> Ol to C o C L T im in g an d S y n c h ro n iz a tio n C ir c u it (P u ls e H e ig h t An a ly z e r) - L o g ic D ia gr am F ig u re
h-2 3 O o Ul 2 2 <C X o
Jj
Ul <9 <9 Z Ui I-z 3 o o Q < o _ J Hlu t/t UJ CC a . rtf ^ 'S. a: £ _j o H o c\J -0. *fl «£ u o 3 o a. to h3 X U . U l O z <9 Ck > 5? <o < w _ _ so - ff"' o < -wo 6 ■St. ■r>= 0 J*5 © ■ ■ ZS t ' A -■ o- ■CO 04 to 3-■ O -N .T im in g an d S y n c h ro n iz a ti o n C ir c u it (P u ls e H ei g h t A n a ly ze r) - La yo ut F ig u re 5 -AT-1609 26 H 4-> 4-> =3 r— <U O C 3 Q . CO O 3 Q. 4 -> “O <U <— O C 3 -O S-o CO o •—• o < c a . P u ls e T ra in S eq ue nc e Fo r P ul se H e ig h t A n a ly z e r F ig u re
I-4-C is a NAND gate used as an in v e rte r; i t in v e rts the signal from the master clock. The output signal from the master clock is here a fte r re fe rre d to as C
The preset load command must have enabled the counter's preset load when the $1 clock makes a low -to-high tr a n s itio n . I t is therefore advantageous fo r the preset load to be enabled s lig h t ly before the low- to -h ig h tra n s itio n o f the $1 clock and remain fo r a period o f time a fte r th is tra n s itio n . The counter inp u t must also be disabled throughout th is time. The Boolean expression fo r the $1 clock can be seen from Figure 5 to be
$1 = C • B • A.
The preset load command is , in Boolean form, Preset Load = B • A.
The count enable has an external input which comes from an external counter. This in p u t is named "Channel 0-99 OK." This in p u t is from a counter which determines whether the memory is in the f i r s t 100 addresses or not. The lo g ic has been expressly designed fo r a 100 channel analyzer. The Boolean expression fo r the count enable is
Count Enable = A • D,
where D represents "Channel 0-99 OK." When D is "1 ", the count enable is A; when D is "0 ", the count enable is "1"
The count to be added in to the memory must occur a fte r the preset is loaded and the counter is enabled. This co n d itio n must be present regardless o f whether the count is a new count entering memory or the ca rry or borrow output fo r the other d ig its ,
T-1609 28
The pulse which adds 1 count is the output o f I-2 -A , a 4 -in p u t V
NAND gate. The external in p u t to th is gate is labeled "OK add 1 count." This in p u t represents e ith e r a new count to be added to the u n its or a ca rry to or borrow from other d ig its . The lo g ic a l expression fo r add 1 count i s , i f "OK add 1 count" is labeled E,
Add 1 count = C • B • A • E.
When E = "1" the Add 1 count = C • A • B, and when E = "0" the Add 1 count = "1"
The $2 c lo c k , the in p u t clock f o r the s h i f t r e g is te r , must occur a fte r the Add 1 count pulse. This sequence allows the new value o f the counter to be loaded in to the s h i f t re g is te r. A fte r the $2 pulse the s h i f t re g is te r s h ifts to the next b i t ; the $1 clock pulse, consequently, should fo llo w the $2 clock pulse c lo s e ly in tim e. The $2 clock pulse in Boolean form is as fo llo w s :
$2 = C • A • B.
The to ta l clock sequence fo r the tim ing and synchronization c ir c u it is depicted in Figure 6.
The actual c ir c u it has a 540 p f capacitor to ground a t the output o f I-4-C . This capacitor is used to compensate fo r the delays through the J-K f lip - f lo p s . The ty p ic a l propagation delay fo r an SN7473 J-K f l i p - f l o p is 25 ns. For example i f B - "1 ", A = "1 ", and C = "0 ", then $2 = C • A • B - "1" On the "0" to "1" tra n s itio n o f the master clock C changes to "1 ", ty p ic a lly 10 ns a fte r the master clock tra n s itio n i f no ca p a cito r C-l is present. Therefore, a t time t = 10 ns Z - "1 ", A = "1" and B = "1 ", and $2 = "0" The $2 clock makes the tra n s itio n from "1" to
"0" a t t = 10 ns. At t = 25 ns the B output o f I - l- B makes it s tra n s itio n from "1" to "0" Therefore, a t t = 25 ns C = "1 ", A = "1 ", B = "0"
and $2 = "1" The $2 clock th e re fo re makes an unallowable tra n s itio n and is in the wrong sta te from t = 10 ns to t = 25 ns w ith no capacitor C-l present.
%.
The 540 p f capacitor C-l holds the output o f I-4-C a t "0" or "1" u n t il the J-K f lip - f lo p s have changed th e ir outputs. This capacitor compensates fo r the propagation delays through the f lip - f lo p s and elim inates the p o s s ib ility o f fa ls e outputs because o f the propagation delays through the various inte g ra te d c ir c u its ,
T-1609 30
Mossbauer Data Analyzer:
C ir c u it Requirements: Figure 7 shows the tim ing and synchronization c ir c u it appropriate to a MSssbauer Data Analyzer. The c ir c u it must pro vide e s s e n tia lly the same tim ing and synchronization th a t is necessary in a pulse height analyzer. A Mossbauer analyzer remains a t one address and counts fo r a period o f tim e, however; then the memory indexes, and the system counts a t a new address, The tim ing and synchronization
c ir c u it fo r a Mossbauer analyzer is , th e re fo re , not re s tric te d to 1 count per address per cycle o f memory, as is true fo r a pulse height analyzer
Figure 8 gives the time sequence fo r the pulse tr a in used to synchronize the memory o f a Mossbauer analyzer.
C lr c u it O peration: Pulses from the master clock are applied to the in p u t o f I - l - A which is a J-K f l i p - f l o p . The QA output o f the f l i p - flo p provides the count pulses fo r 1-2, a decade counter
The A and D outputs o f 1-2 are applied to the in p u t o f I-4 -B , a 2 -in p u t NAND gate. The output from I-4-B is one o f the inputs to I-4 -C , the other in p u t is a "X I0" in p u t. The "X I0" in p u t increases the s h if t frequency by a fa c to r o f 10 and completely disables the memory in p u t. This in p u t is used in conjunction w ith the memory address s e le c to r to decrease the cycle time through memory.
The combination o f 1-2 and I - l- A provides the long count time a t one address. The count time is 18 pulses out o f 20 master clock pulses,
The count enable is high when the counter is disabled. The Boolean expression fo r the count enable is
Q . <U O +■> Q r— c u_ =5 < «C 1 O r -0 - -0 •r— ■M +-> r — 0) =J r j U_ ■o O . a . fO c c X o *—« i—i 1 a> 1 i o CM CO o CM O X cr> CTi O X x X 2 2= !T*p CO 00 CO ( /) II II II II ,_CM CO I 1 1 1 ►—« *—» K-H o X OJ o LxJ O D _ O . T im in g an d S y n c h ro n iz a tio n C ir c u it (M o ss b a u e r D at a An a ly z e r) - L o g ic D ia gr am F ig u re
C lo c k T-1609 32 O ' c 3 i ? ► r— r C\J < Sl * o JD <o ta q; o c Cd CO UJ in +-> 4-> +-> 4-> 3 a) E 3 C L to 3 C L +•> <U o c 3 S_ o o a. Pul se T ra in S eq ue nc e Fo r M o ss b a u e r D at a A n a ly z e r F ig u re
The co n d itio n A • D = 1 occurs only when the counter is a t the BCD representation fo r the number 9. The counter counts a lte rn a te clock pulses, I t counts on a h ig h -to -lo w tra n s itio n o f it s in p u t pulse. I - l- A changes sta te on each clock pulse because it s J and K inputs are connected to lo g ic le ve l "1" Since I - l- A has a h ig h -to -lo w tra n s itio n fo r every other clock pulse, the decade counter remains in each sta te fo r two master clock pulses, Therefore fo r pulses number 18 and 19 from the master clock A = D = "1 ", and fo r other pulses in the group o f 20, A • D = "0"
For pulses number 18 and 19 in each group o f 20, A D = "0 ",
the count enable is equal to "1 ", and the counter is disabled. I f in p u t "X I0" is "0" then regardless o f the other in p u t fo r I-4-C the count enable is equal to "1 ", and the counter is disabled. I f "X I0" is "1" then during pulses 18 and 19 the count enable is equal to "1 ", and the counter is disabled; during the other 18 pulses in the group
A • D = 1, count enable is equal to "0 ", and the counter is enabled. Consequently, the counter is enabled fo r 18 out o f every 20 pulses o f the master clo ck, and i t is disabled fo r the remaining 2 pulses in 20. . The output s h if t re g is te r clock $1 and the in p u t s h if t re g is te r clock $2 must occur during the time when the counter is disabled. Furthermore, the $2 must precede the $1 clock w ith in the time span o f the disable counter pulse. The preset load pulse has to occur through out the time span o f the $1 clock pulse, but not any longer than the disable pulse fo r the counter.
The Boolean expression fo r $1, the output s h if t re g is te r c lo c k , is $1 = C • [AQ] • [Count Enable] • 1
T-1609 34
I-3 -A and I-3-B are fo u r-in p u t NAND gates; the fo u rth in p u t is connected to "1" This connection e ffe c tiv e ly makes the gates th re e -in p u t gates I f the count enable is equal to "1 ", as could be e x te rn a lly set by making the "X10" = "0 ", then the $1 clock is simply equal to C [AQ]. With $1 equal to C" • [AQ] the s h if t re g is te r w i l l s h if t ten times fa s te r because the decade counter 1-2 no longer has to count to 9 fo r the count enable to equal "1"
The preset load is given by the expression
Preset Load = [AQ] • [Count Enable],
This expression ensures th a t the "0" to "1" tra n s itio n o f the $1 clock pulse occurs e n tir e ly w ith in the preset load command.
The in p u t s h if t re g is te r clock $2 has the fo llo w in g Boolean expression:
$2 = 0 • [AQ] • [Count Enable] • 1
The only d iffe re n ce between the $1 clock and the $2 clock lie s in the interchange o f AQ and AQ in the lo g ic expression. This fa c to r ensures th a t the pulses w i l l occur c lo s e ly in time and also th a t the $2 clock w i l l precede the $1 clock in time.
CHAPTER 4
ANALOG PULSE STRETCHER
In tro d u c tio n :
An analog pulse s tre tc h e r is a c ir c u it which stretches in time a sh o rt duration in p u t pulse w h ile m aintaining the h e ig h t, i. e . vo lta g e , o f the in p u t pulse. This c ir c u it is required in a pulse height analyzer Design in p u t pulse duration is approximately 0.5 ys. Design range fo r in p u t pulse height is 0 to +10 V
In the 100 channel pulse height analyzer the pulse s tre tc h e r is needed because the stretched pulse must be compared to a lin e a r ramp. The lin e a r ramp is generated from the same clock th a t is d riv in g the memory. The lin e a r ramp generator must be synchronous w ith the memory, A c ir c u it th a t generates such a ramp w ith automatic compensation to co
r n
sure lin e a r it y is o u tlin e d by D. M. Brockmanv 1 in "E le c tro n ic s " Vol 46, No. 2. When the stretched pulse voltage and the lin e a r ramp voltage are equal, one count is added to the then current address in memory, The lo c a tio n in memory is determined by the height o f the ramp and hence by the height o f the in p u t pulse.
The 100 channel pulse height analyzer has a memory cycle time o f 0.2048 ms; th is is calculated on the basis o f a s h if t frequency o f
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2.5 MHz and re g is te r capacity o f 512 b its .
The voltage range o f the in p u t pulse is 0 to +10 v o lts , and the pulse height analyzer has 100 channels; th e re fo re , the width o f each channel is 0.1 v o lt.
The requirements o f the pulse s tre tc h e r are th a t i t must accept an in p u t pulse o f voltage 0 to +10 and width o f 0.5 ys; the output pulse must not decay by 0.1 v o lt in 0.2048 ms; the output voltage must bear a
Basic Pulse S tretcher C ir c u it:
Pulse S tretcher Theory: A simple c ir c u it th a t could be used fo r an analog pulse s tre tc h e r is a capacitor and diode, as depicted in Figure 9.
A p o s itiv e pulse o f height V is applied to the in p u t. Because the capacitor cannot instantaneously change i t s charge, the r ig h t p la te o f the capacitor i n i t i a l l y ris e s to the same p o te n tia l as the l e f t . As the p o te n tia l o f the r ig h t p la te increases, the diode becomes forward biased and conducts. This action then brings the r ig h t p la te o f the ca p a cito r to ground p o te n tia l, charging the cap a cito r to the voltage V
o f the pulse. ^
When the in p u t pulse returns to ground, the ca p a cito r again cannot instantaneously change i t s charge; consequently, the r ig h t p la te is now a t a p o te n tia l o f -V. The diode is reverse biased and the output voltage
m
o f the pulse s tre tc h e r is -V. A time sequence a t the in p u t and output o f th is c ir c u it is depicted in Figure 10. V Input Output Figure 9 +V Input 0 +V Output 0> -V Figure 10
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A disadvantage o f th is c ir c u it arises from the c h a ra c te ris tic s o f a semiconductor ju n c tio n diode. The current through the diode is an
For small forward-biased voltages the cu rre n t through the diode is small and as a re s u lt i t takes a long time fo r the diode to bring the r ig h t p la te o f the capacitor to ground p o te n tia l
The basic pulse s tre tc h e r c ir c u it u t iliz e s the simple ca p a cito r- diode pulse s tre tc h in g c ir c u it ; however, i t divorces i t s e l f o f the dependence upon the diode's exponential behavior.
Super Diode C ir c u it : A super diode c ir c u it uses an operational a m p lifie r and a diode to sim ulate a diode w ith an extremely low turn-on voltage and high sw itching speed. Figure 11 shows such a c ir c u it .
The operational a m p lifie r has an open-1oop voltage gain G, which is ty p ic a lly 10u. The n o n -in ve rtin g in p u t o f the operational a m p lifie r is grounded. C h a ra c te ris tic o f negative feedback is a small p o te n tia l d i f ference or e rro r voltage between the non-in ve rtin g and in v e rtin g inputs I f a p o s itiv e pulse voltage 6v is applied to the in v e rtin g in p u t, the c ir c u it id e a lly w i l l apply $v to the anode o f the diode and -G[<$vJ to exponential fu n ctio n o f the voltage across the d io d e ,(4)
Input
x
the cathode o f the diode. In p ra c tic e G[<5v] may be much greater than the s a tu ra tio n output voltage o f the operational a m p lifie r; i f so, the o u t put voltage o f the operational a m p lifie r w i l l be lim ite d to i t s s a tu ra tio n value. Having a p o te n tia l o f (1 + G)sv across i t , the diode is forward biased. The turn-on voltage fo r a s ilic o n diode is approximately 0.6 v o lt . Therefore the minimum 6v th a t w ill s tro n g ly tu rn on the diode is
6v - J -;| = yqv = 6 x 10 5 v o lt.
The diode in th is c ir c u it is s tro n g ly turned on a t 6 x 10"5 v o lt ra th e r than 0.6 v o lt as would be tru e fo r a diode alone.
I f the voltage applied to the in v e rtin g in p u t is -6v then the anode o f the diode is at p o te n tia l -Sv and the cathode a t p o te n tia l G[6v].
The diode is reverse biased by a voltage o f (G + 1 )6v; consequently, only a small reverse leakage cu rre n t is allowed in the diode fo r a small
reverse voltage 6v being applied to the in p u t o f the c ir c u it .
D escription o f the Basic P ulse-Stretcher C ir c u it : The basic pulse s tre tc h e r c ir c u it is shown in Figure 12.
Input
IX— Output
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The tra n s is to r is connected as an e m itte r fo llo w e r. Pulses to be stretched are applied to the base o f th is tra n s is to r. The e m itte r f o l lower is a b u ffe r stage which provides enough current to charge the cap a cito r q u ic k ly . The DC o ffs e t c h a ra c te ris tic o f the base e m itte r ju n c tio n w ill not a ffe c t the operation o f the pulse s tre tc h e r because the s tre tc h in g capacitor AC couples the in p u t b u ffe r to the re s t o f the c ir c u it .
The operational a m p lifie r and diode form a super diode. This is the charging diode through which the capacitor is charged.
The operation o f th is c ir c u it resembles th a t of a simple ca p a cito r- diode pulse s tre tc h e r, except th a t the super diode has an extremely small turn-on voltage.
P ra c tic a l Pulse S tre tch e r Operational Design: Figure 13 shows the pulse s tre tc h e r. Added components are necessary to reduce non-ideal e ffe c ts th a t d e tra c t from o v e ra ll c ir c u it operation.
The in v e rtin g input bias cu rre n t fo r the operational a m p lifie r is supplied by re s is to r R-4, which is necessary because th is in p u t is c a p a c itiv e ly coupled. R esistor R-4 is s lig h t ly sm aller than required fo r proper b ia s, so th a t in the absence o f an inp u t pulse the feedback diode is conducting. Because the feedback diode is turned on, negative feedback keeps the e rro r signal a t approximately 0 v o lts . This feature ensures th a t the r ig h t p la te o f capacitor C-l is quiescently a t ground p o te n tia lj
Capacitor C-2 is a frequency compensation ca p a cito r. The use o f a non-frequency compensated operational a m p lifie r allows the designer to
o 4-> C L Q _ § O. o o r>. r>. CM z 00 II O CM O O O O to CO O CO +-> CM r— CM r— 1 1 1 o CM CM CM > CO CO 0 0 o o o CM LO LO i n r— 1 ii ii ii II r— CM CO I I I > a o q 1 *o 4 M 4 -C L -C L E O r— CO o o I— CM . II II II r— CM CO I I I u u u cs cs a a s: o CO II II . II II r - C M ( 0 I I I I o c a : cc cc CO +-> o > CM +. CO Ol
