Sound Level Measurement System
E
XAMENSARBETEUTFÖRTIE
LEKTRONIKSYSTEM AV TORE JOHANSSONT
OREJ
OHANSSONLiTH-ISY-EX--06/3964--SE
E
XAMENSARBETEUTFÖRTIELEKTRONIKSYSTEM VIDL
INKÖPINGSTEKNISKAHÖGSKOLAAV
T
OREJ
OHANSSONLiTH-ISY-EX--06/3964--SE
S
UPERVISOR: K
ENNYJ
OHANSSONISY, L
INKÖPINGU
NIVERSITETE
XAMINER: M
ARKV
ESTERBACKAISY, L
INKÖPINGU
NIVERSITETPresentationsdatum
6 nov 2006
Publiceringsdatum (elektronisk version)
Institution och avdelning Institutionen för systemteknik Department of Electrical Engineering
URL för elektronisk version
http://www.ep.liu.se/exjobb/isy/2006/3964
Publikationens titel
Sound Level Measurement System
Författare
Tore Johansson
Sammanfattning
The purpose of this master thesis work is to design a device that measures the loudness of sound for different frequencies. This device is divided in three parts; a microphone that captures the sound, one A/D converter that samples the sound and one FPGA which analyse the data using an FFT algorithm. LEDs connected to the FPGA are used to indicate different output levels. A db(A) filter is applied that weights each frequency, before the different outputlevels are measured for each frequency.
This system is supposed to be a subsystem to a larger system that is developed in a company. However, because of the risk that competitors might be able to guess the next product move of the company, the company is anonymous in this report. All the components used are paid for by the company and in return the company gets an idea of the complexity of the system and a basis for future design decisions.
Antal sidor: 40
Nyckelord
FFT, VHDL, sound level, FPGA
Språk
X Svenska
Annat (ange nedan)
Antal sidor Typ av publikation Licentiatavhandling X Examensarbete C-uppsats D-uppsats Rapport
Annat (ange nedan)
ISBN (licentiatavhandling) ISRN LiTH-ISY-EX--06/3964--SE
Serietitel (licentiatavhandling)
TABLE OF CONTENTS
1 Introduction
1
1.1 Background . . . 1 1.2 Overview . . . 2 1.3 Reading Guideline . . . 3 1.4 Design Tools . . . 32 Work plan
5
2.1 Time Plan. . . 5 2.1.1 System Specification . . . 5 2.1.2 Research. . . 5 2.1.3 Implementation . . . 6 2.1.4 Testing . . . 6 2.1.5 Documentation. . . 6 2.2 Workflow . . . 63 System Specification
9
3.1 System Requirements . . . 9 3.2 Design focus . . . 104 Matlab Model
11
4.1 Overview . . . 11 4.2 FFT Algorithm. . . 12 4.2.1 Bitswap . . . 12 4.2.2 Butterfly. . . 13 4.3 X-Square . . . 145 VHDL Models
17
5.1 First VHDL Model. . . 17 5.1.1 Problems . . . 17 5.2 Second VHDL Model . . . 19 5.2.1 Scaling . . . 19 5.2.2 Twiddle Factor. . . 20 5.2.3 Problems . . . 20 5.3 Third VHDL Model . . . 21 5.3.1 RAMs. . . 215.3.3 Problems . . . 23
6 Final Model
25
6.1 Multiplier . . . 26 6.2 Safe Scaling . . . 27 6.3 Test. . . 28 6.4 Schematic. . . 29 6.5 Output . . . 29 6.6 A/D Converter . . . 30 6.7 Microphone . . . 317 Result and Discussion
33
7.1 Conclusion . . . 337.2 Results . . . 33
7.3 Future Work. . . 34
Abbreviations
FFT Fast Fourier Transform
VHSIC Very High Speed Integrated Circuit VHDL VHSIC Hardware Description Language FPGA Field Programmable Gate Array RAM Random Access Memory
ISY Department of Electrical Engineering A/D Analog to Digital
LED Light Emitting Diode
ASIC Application Specific Integrated Circuit ROM Read Only Memory
1
1
INTRODUCTION
1.1 BACKGROUND
The purpose of this master thesis work is to design a device that measures the loudness of sound for different frequencies. This device is divided in three parts; a microphone that captures the sound, one A/D converter that samples the sound and one FPGA which analyse the data using an FFT algorithm. LEDs connected to the FPGA are used to indicate different output levels. A db(A) filter is applied that weights each frequency, before the different output levels are measured for each frequency.
This system is supposed to be a subsystem to a larger system that is devel-oped in a company. However, because of the risk that competitors might be able to guess the next product move of the company, the company is anony-mous in this report. All the components used are paid for by the company and in return the company gets an idea of the complexity of the system and a basis for future design decisions.
1.2 OVERVIEW
In Fig. 1.1 an overview of the design steps is presented. The main task is to implement a FFT algorithm, which is first done using MATLAB. This model is later translated to VHDL and later refined in several steps. When a synthe-sizable version of the VHDL model is ready, all remaining parts, such as the A/D converter, are implemented. In each design step tests are performed to guarantee a correct behaviour before next step is taken.
Figure 1.1: The different design steps
MATLAB Model
VHDL Model
A/D Converter and LEDs
Final Tests
Chapter 1 – Introduction 3
1.3 READING GUIDELINE
The first chapter is an introduction to the thesis. Chapter 2 describes the plan-ing of the work and workflow. The specification of the system is outlined in Chapter 3. The following chapters, 4 and 6, explains the implementation process and the final model. Eventual future work and conclusions are dis-cussed in Chapter 7.
1.4 DESIGN TOOLS
ModelSim was used for simulation of the VHDL versions of the system, and Precision was used to synthesize the different versions. These two programs are included in Hdl Designer (described in more detail in [4]), which was also used for writing the code and to organize different subsystems. MATLAB
(described in more detail in [5]) was used to simulate the MATLAB model and to generate test data. All documentation was made using Adobe FrameMaker.
5
2
WORK PLAN
2.1 TIME PLAN
The work was divided in five major parts; system specification (1), research (2), implementation (3), testing (4) and documentation (5). A ruff time plan for the project was made in the beginning as outlined in Fig. 2.1.
Figure 2.1: Time plan
2.1.1 SYSTEM SPECIFICATION
In the system specification phase, a specification was decided in consultation with the customer and the examiner Mark Vesterbacka. This to make sure that the work would not be too demanding or too easy and also to make sure that the customer is satisfied with what he gets from the project.
2.1.2 RESEARCH
Some research was made before the implementation part. This was mostly studies of the FFT algorithm. The different computer tools that were used during the implementation process were studied in this phase as well.
1 2 3 4 5
2.1.3 IMPLEMENTATION
As expected, the implementation phase was the most time consuming part of the project. All coding, debugging and hardware implementation were done here. During this implementation process several meetings with my supervi-sor Kenny Johansson were organized, who provided feedback on different design aspects.
2.1.4 TESTING
During the test phase the system was tested with both test data from MATLAB
and also on the target hardware. These tests are discussed in more detailed in later chapters. Several test were also performed during the implementation period, which explains why the phase used exclusively for test is relatively short.
2.1.5 DOCUMENTATION
The last month was used exclusively for documentation of the system and the work process. Also several comments were added in the final version of the VHDL code to help eventual future work. All documentation were made in FrameMaker and templates from ISY were used for the layout.
2.2 WORKFLOW
A top down design approach was used, starting with a MATLAB model which later was refined several times until a final working design was achieved. In order to have an efficient method when working a specific workflow was used that shows how each version of the system is tested and if needed changed. This workflow is described in Fig. 2.2. Each VHDL model passes through several stages, such as simulation and synthesis. If a stage fails, a new VHDL model is designed and the procedure starts over.
Chapter 2 – Work Plan 7 Figure 2.2: Workflow Yes Yes Yes Yes Yes No No No No No Simulation successful? Synthesizeable?
Area requirements fulfilled?
Synthesis
Works with hardware?
Requirements fulfilled?
Done! New VHDL model
9
3
SYSTEM SPECIFICATION
3.1 SYSTEM REQUIREMENTS
For the system to have basic functionality the following system requirements must be fulfilled.
• Implementation of a FFT in VHDL with a resolution of at least 512 points.
• An A/D converter, with a connected electret microphone, should be used to sample the sound.
• The sound should be sampled with a sampling rate of 20 kHz.
• The system should detect at least 4 different sound levels, and use LEDs to indicate these.
• The system should fit in a Virtex-II XC2V1000 FPGA.
If these system requirements are implemented and fully functional the fol-lowing extra requirements should be considered if time allows.
• Measurements of sound levels over time.
• Change hardware target so that an ASIC is used instead of a FPGA. • Weigh different frequencies with a dB(A) filter before measuring sound
3.2 DESIGN FOCUS
The system requirement are only behavioral requirements. However, there are also some different design aspects that should be considered when imple-menting the system. These design focuses are listed below.
• Low area use.
• Low power consumption. • Low cost.
Low area and low power consumption use is in some degree attained by using smart coding strategies. Low cost however is only affected by the choice of components, in this case the A/D converter and the FPGA.
11
4
MATLAB MODEL
4.1 OVERVIEW
The purpose of developing a MATLAB model of the system is first of all to make sure that the algorithms that are used are understood correctly. Its out-put data are later compared with the outout-put data from the VHDL model of the system. This will also make it possible to compare data from the VHDL model with the built in FFT algorithm in MATLAB, which should guarantee a correct implemented system.
Figure 4.1 shows the main steps in the MATLAB model. Since there are no data from an A/D converter present, the Generator is required to generate test data for the FFT.
Figure 4.1: Overview of the MATLAB model
Butterfly
Generator Bitswap X2
Plot of designed FFT Plot of MATLABs FFT
The Sort, Butterfly and X2 are all part of the FFT algorithm and are explained
in more detail in Chapter 4.2.
4.2 FFT ALGORITHM
The algorithm that is implemented is an FFT which stands for Fast Fourier
Transform. Its purpose is to compute the Discrete Fourir Transform (DFT) of
a signal, which is defined as
, (4.1) where N determines the resolution of the DFT. However, this sum is far too complex to calculate directly when calculating the DFT since the number of operations required is proportional to 2N2. When an FFT algorithm is used
instead to compute the DFT, the number of operations that is required is pro-portional to only NlogN. The used FFT Algorithm is described in [1]. 4.2.1 BITSWAP
The first step of the FFT algorithm that is used in this system is to sort the input data using the BITSWAP method which is demonstrated in Table 4.1. In this example N is 8 and the length of the binary representation of the indi-ces is 3. The index of a sample is first translated into binary (second column), then the bits are reversed (third column), and in the last step they are trans-lated back from binary (fourth column).
Index Binary Swaped
Binary Sorted Index
0 000 000 0 1 001 100 4 2 010 010 2 3 011 110 6 4 100 001 1 5 101 101 5
Table 4.1. Demonstration of BITSWAP DFT x n{ [ ]} XN[ ]k x n[ ]e–j 2( π N⁄ )kn
n=0
N 1–
Chapter 4 – MATLAB model 13
When all N samples have been sorted according to this method the data are ready for the next step, the butterfly.
4.2.2 BUTTERFLY
The butterfly operation is the most complex part of the FFT algorithm since it involves several complex multiplications and additions. Also, a twiddle fac-tor is used which requires access to one sine and one cosine function. Fig. 4.2 shows how the multiplications and additions are performed. In this example
N, which determines the resolution, is 4. Note that all input samples are sorted
with bitswap before they are processed by the butterfly.
Figure 4.2: Butterfly operation
The twiddle factor is defined as
, (4.2)
where k and p are integers and are determined according to Fig. 4.2. When N is 2z there are z steps in the butterfly. So an FFT with a resolution of 512,
which is used in the MATLAB model, requires 9 steps. This means that a total of 4608 twiddle factors are used and 18432 multiplications (one complex multiplication uses four normal multiplications in this system) are required to compute the FFT. Hence an efficient method to generate the twiddle factors is
---essential. The first method that was implemented to generate the sine and cosine values was a Maclaurin series of order two. In order to obtain more accurate results all input values above are mapped down to a value between 0 and . Hence, the computation have to be changed. How this is done is shown Table 4.2 and is described in more detail in [2].
In the table
(4.3)
ul means the upper limit and ll means lower limit. Later this use of Maclaruin
series was set aside for a more efficient method, which is described in the next chapters.
4.3 X-SQUARE
This last step is necessary in order to transform the complex output data from the butterfly to energy levels for the different frequencies. The imaginary and
Octant sin(x) cos(x) sin(x) cos(x) cos(–x´) sin(–x´) cos(x´) –sin(x´) sin(–x´) –cos(–x´) –sin(x´) –cos(x´) –cos(–x´) –sin(–x´) –cos(x´) sin(x´) –sin(–x´) cos(–x´) Table 4.2. Octant mapping
π 4 ---π 4 ---0 x π≤ <4 ---π 4 --- x π≤ <2 ---π 2 --- x 3π≤ <---4 3π 4 --- x≤ <π π x 5π≤ <---4 5π 4 --- x 3π 2 ---< ≤ 3π 2 --- x 7π≤ <---4 7π 4 --- x 2≤ < π
x′ ul x,when there is a negation before x´–
x ll,when there is no negation before x´– =
Chapter 4 – MATLAB model 15
real part for a frequency are first squared and then summed. Normally the square root of this sum is computed, however this is left out in this and later version of the system. This is possible since the constants that are compared with the output data, to detect the different output levels, are squared before saved in the VHDL code.
17
5
VHDL MODELS
5.1 FIRST VHDL MODEL
The first VHDL model is almost a direct translation of the MATLAB model. Its purpose is to have a simple basic model of the system that is easy to com-pare with the MATLAB model. This model is later refined in several steps during the work process.
In Fig. 5.1 an overview of the system is presented. All processes are executed in the order indicated by the numbers in the Fig. 5.1. First, the data is gener-ated and then the data is sorted in BITSWAP. In the third process, the Butter-fly, all butterfly multiplications are performed. The X2 is used to square the
real and imaginary parts, and finally in process five the output data is saved to a file. In this model, the memory is implemented with two arrays, one for the real part and one for the imaginary part. After step four the data are ready, and in step five the data are saved to a file in order to make it possible to compare it with data from the MATLAB model or the built in FFT function in MAT-LAB.
To represent the data internally, the data type real is used, which is easy to use when simulating a system because no consideration to scaling is necessary. 5.1.1 PROBLEMS
Since this is just a first model of the system it is far from complete. Several steps are needed in order to get a synthesizable version of reasonable size. The main limitation of this model is the fact that real numbers are used to rep-resent data instead of binary numbers. Even though it is possible to synthesize
real numbers, if the correct libraries are included, the size would probably be way beyond the size of the target FPGA.
Another big problem with this model is that everything happens in the same clock cycle which makes this version really slow.
Figure 5.1: Overview of the first VHDL version
Mem Generator BITSWAP Butterfly X2 1 2 3 4 5
Chapter 5 – VHDL models 19
5.2 SECOND VHDL MODEL
This second model has two major differences compared with the first model. These are the addition of SinCos generators used by the Butterfly and the change of data type that is used to represent data in the process. In Fig. 5.2, which gives an overview of the system, these SinCos generators are con-nected directly to the Butterfly process. The rest of the processes in Fig. 5.2 are similar to the ones in the previous model. The size of the data buses are also shown in the figure. The change of data type requires a scaling process which is explained in Section 5.2.1.
Figure 5.2: Overview of the second VHDL version
5.2.1 SCALING
The next step in the refinement of the system is to change the representation of data from real numbers to binary numbers. The data type std_logic_vector is used which not only enables addition and subtraction but also multiplica-tion. With this data type there is however a risk of overflow. This risk is diminished by introducing scaling in the butterfly process. In this version a rather primitive method is used that scales the data after each multiplication with 7 bits.
In Fig. 5.3 this process is illustrated, where two numbers both with a word length of 51 bits are multiplied and the result with a word length of 58 bits is reduced to 51 bits again.
Generate 1 2 4 5 SinCos Data Data 51 bit 51 bit Data 31 bit RAM 51*1042 BITSWAP 3 5 Butterfly 51 bit Data Data 51 bit X2 Generator 10 b it SinCos Generator 10 b it 14 b it 14 b it
Figure 5.3: Scaling at multiplication
5.2.2 TWIDDLE FACTOR
In the previous model, Maclaurin series were used to compute the twiddle factors. To do this easy, real numbers are needed, so in this version a different approach is necessary. One commonly used way to handle this problem is to have a ROM memory with all coefficient data. This solution has the advan-tage of being simple, but to store all data one extra component is needed. Of course all data could be saved in the FPGA, but the space that would be required for the storage would be much larger than the available space. A third way to handle this problem is to use a special algorithm to compute each sine and cosine value. Such an algorithm was proposed in [2], and it is implemented in this system. All VHDL code needed for the sine and cosine functions are generated with a special tool provided by Kenny Johansson. The size of these included components are relatively small. One cosine and sine generator occupies the equivalent area of one 16x16 bit multiplier. Since all multiplication are performed in one clock cycle, and all multiplications require two twiddle factors, two SinCos components are included.
5.2.3 PROBLEMS
There are still some necessary changes needed in order to obtain a synthesiz-able version of the system. First of all, the built in block RAMs that are avail-able in the FPGA must be used instead of the arrays, which is used at the moment. A pipelined architecture is also needed to obtain a reasonable throughput.
51-bits
51-bits 58-bits 51-bits 7-bits MSB
LSB Next
Chapter 5 – VHDL models 21
5.3 THIRD VHDL MODEL
In the FPGA that is used there are several RAMs available onchip. These are included as components in the VHDL code and there is also code for simula-tion of these memories. In version three of the system the usage of these memories is the major change compared with the second version. Also the number of bits used to represent data is changed from 51 bits to 32 bits. This is to make the use of the memories simpler. Some essential changes in the architecture are made as well.
An overview of the system is illustrated in Fig. 5.4. Only one group of RAMs are present in the figure, but there are three more equal RAM groups con-nected. The Memory Controller is the other addition to this model and it han-dles all communication with the RAMs on one side and the other processes on the other.
5.3.1 RAMS
In Fig. 5.4 the memory control unit is located in the centre. This process han-dles all communication with the RAMs on one side and all the data process-ing units on the other side. This control unit is necessary since different processes can not write data to the same signal in VHDL (a signal is a datatype in VHDL), e.g., same RAM. Each RAM has 256 addresses and a word length of 16 bits, which means that two RAMs are necessary to obtain the required word length of 32 bits. With a resolution of 512 the required memory for the FFT algorithm is 512 complex numbers. In Equation 5.1 the required number of RAMs is computed to eight, which means that all availa-ble RAMs in the original target FPGA will be used.
(5.1) The memory control unit also has different interfaces for the communication with each data processing unit.
Bits used RAM size
Figure 5.4: The third VHDL version of the system
5.3.2 PIPELINING
To increase the throughput of the FFT a pipelined architecture is introduced. This means that each process is divided into several steps that are executed one after another. As shown in Fig. 5.5, the operations in the butterfly process are divided into three steps. The memory controller communication, which occur between the butterfly steps, is normally divided in four parts during write and read operations. Since different processes are executed in different speeds, several synchronized clocks are generated.
In the first step, the memory address for the data that is needed is sent to the memory controller, which fetches the data from the memory and makes it
SinCos Data WERamX 32 bit Memory 3 5 Butterfly 32 bit Data Data 32 bit Generator 10 b it SinCos Generator 10 b it 14 b it Controller X2 4 14 b it Sampling & 1 BITSWAP Generator D a ta 3 2 b it WE EN RST 32 bit 16 bit 16 bit WE EN RST 0 0 1 1 WERamX RamXa 4096 bit RamXb 4096 bit 32 bit Data
4x
Chapter 5 – VHDL models 23
available for the butterfly process before it processes the next step. Also dur-ing the first step, the two sine and cosine generators are provided with the correct data so that the twiddle factors are computed and ready before the next step.
Figure 5.5: Demonstration of pipelining
All multiplications and additions are performed in step 2. This solution is far from optimal since the multiplications are heavy operations. This makes this version quite slow even though it is much better than the previous versions. In step 3, all control signals are updated and also signals are sent to the memory controller, which writes the computed data to memory.
5.3.3 PROBLEMS
As mentioned above, all multiplications are performed during one clock cycle. This makes the throughput quite low since a high clock frequency is not possible. Overflow is still an issue with this model since safe scaling is not yet introduced. A scaling strategy similar to the one described previously is used here. The only different is that a different number of bits are used to reduce the wordlength after a multiplication.
An interface for communication with the A/D converter is also not finished, which means that test data still has to be generated internally. Hence any real hardware test is not possible.
Step 1 Step 2 Step 3 Step 1
Butterfly
25
6
FINAL MODEL
There are several ways in which the final version differs from the third model of the system. First of all this version is fully synthesizable and its design is improved regarding occupied chip area, speed and low power. Only four RAMs are necessary, as seen in Fig. 6.1, compared to eight in the previous model. This is possible because the word length is reduced from 32 to 16 bits. Safe scaling is also introduced, which means that overflow is no longer possi-ble. One way to save area is to share resources between the different proc-esses. One resource that is shared in this version is the multiplication function. Both the butterfly and the x-square process uses this function. In the previous version two different sine and cosine generators were used, however in this version only one is necessary since a pipelined architecture is intro-duced for the multiplier as well. Code for communication between the FPGA and the A/D converter is added to the Sampling & BITSWAP process, which makes it possible to use this version with real sampled data. Indication of dif-ferent output levels are made possible via LEDs on the development board, on which the FPGA is located.
The overview in Fig. 6.1 contains several changes compared with the over-view of the third model of the system. First of all parts outside the FPGA are added. These are the A/D converter, the analog circuit (which includes the microphone) and the LEDs. The Multiplication process is also new and is used by many other processes, as seen by all the data buses connected to it.
6.1 MULTIPLIER
Sharing resources is vital for a design with demands on low area. Therefore only one multiplier is implemented in this version and it is used continuously by the butterfly and the x-square process. The size of the input data is 16 bits, and the size of the output to the other processes is 32 bits. The input data is, except for the twiddle factors, obtained directly from the memory controller, which makes the design even smaller. Since the twiddle factors are only 14 bits they are extended with two zeroes at the end before the multiplication.
Figure 6.1: Overview of the final version of the system
D a ta WERamX 8 bit Memory Butterfly SinCos Generator 1 0 b it Controller X2 4 Sampling & 1 BITSWAP WE EN RST 0 1 RamXa 4096 bit
4x
Data 16 bit Multiplication 3 Data Data Address Address 8 bit 8 bit D a ta Address Data 16 bit 3 2 b it 16 bit 3 2 b it 16 bit 14 bit d o u t sh d n d c lo c k A/D ADS8320 LEDs 16x16 Data 16 bitFPGA
Analog circuitChapter 6 – Final Model 27
6.2 SAFE SCALING
The benefit of safe scaling compared to the previously implemented scaling operations is the elimination of the risk for overflow. However, with a safe scaling the resolution is lower, since more bits are removed after each multi-plication. The difference between old scaling and safe scaling is illustrated in Fig. 6.2 where the difference in resolution shows clearly. In the old scaling version the data that exceeded the maximum allowed data size (which is FFFF in hexadecimal) was reduced to the maximum allowed data size. In safe scaling, since overflow is impossible, this is not a problem. This scaling method is a version of the scaling method described in [3].
Figure 6.2: Safe scaling vs Old scaling
If an addition with two binary numbers is guaranteed to not exceed the word length, both numbers have to be divided by two. Now each butterfly opera-tion does not only include addiopera-tion but includes multiplicaopera-tion as well, with all numbers complex. So a careful mathematical approach is required to guar-antee the correct behaviour. In a butterfly operation, X1 and X2 are the two
operands, and is the twiddle factor. Equation 6.1 shows the range of the results for this operation without scaling.
(6.1)
To obtain safe scaling the result must be less or equal to one. Hence a multi-plication with one half is necessary, as shown in Equation 6.2.
(6.2) The real and the imaginary parts are processed and saved separately so each
W1 X1 ≤1 X2 ≤1 W1≤1 X1+X2W1 ≤2 1 2 --- X1+X2W1= 2---X1 1+12---X2W1 ≤1 FFFF FFFF freq freq
Safe scaling Old scaling
0000 0000
butterfly operation is divided into the two following operations.
(6.3) (6.4) Using these equation will yield safe scaling, so overflow is not possible in this final version. Actually, because of the pipelined architecture of the butter-fly, these two equations are performed in six clock cycles to improve per-formance.
6.3 TEST
To guarantee the correct behavior of this model it was tested with data gener-ated by MATLAB. The result was later compared with the output from the
MATLAB model. Since the MATLAB model does not have safe scaling imple-mented the amplitude differs, but otherwise the plot of the test data should be the same.
One of these tests is presented in Fig. 6.3. A pure sine signal was used as input data for this test and the difference, apart from the amplitude scale, is so small that it is not even noticeable. For this application this simple observa-tion will do.
Figure 6.3: Plots for the tests with a pure sine signal for both the models Re 1 2 ---X 1 1 2 ---X 2W1
+ = 2---Re X1 1 +12---Re X( )Re W2 ( 1) 1–2---Im X( )Im W2 ( 1)
Im 1 2 ---X 1 1 2 ---X 2W1
Chapter 6 – Final Model 29
6.4 SCHEMATIC
In Fig. 6.4 the schematic of the system is presented. The dotted line marks what is on the development board. The A/D converter and the microphone are wired on to an expansion board. Since the A/D converter is surface assem-bled, a circuit board is necessary in order to connect it. This circuit board was etched and soldered in Admittansen by Thommy Jakobsson.
Figure 6.4: Schematic of the system
6.5 OUTPUT
To indicate different output levels from the x-square process, where the dif-ferent output levels are detected, LEDs are used. The LEDs most easily avail-able are in fact two 7-segment displays on the development board, which is acceptable since this is only a prototype. A more suitable solution might have been a bar of LEDs, however the implementation of 7-segment displays and a bar of LEDs is similar.
On the left display, as shown in Fig. 6.5, one of the LEDs indicate that the system is running. This indication was implemented to help with debugging.
Virtex-II FPGA ADS8320 V re f V In + V In – V cc D cl o ck D o u t S H D N G N D Vcc M ic GND 1.5 V 3.3 V
The right 7-segment display is used to indicate seven different sound levels, number one indicates the lowest level and number seven the highest level.
Figure 6.5: The two 7-segment displays on the development board
6.6 A/D CONVERTER
The A/D converter that is used is an ADS8320 from BURR-BROWN. This is a small 16 bit converter with a serial interface. There are many advantages for this A/D converter compared with its competitors. First of all, because of its serial interface, the size is small which makes the total required area for the system smaller. The power consumption is also low, in the range of 0.3 mW and 1.8 mW. Since the operation voltage can differ between 2.7 V and 5 V this A/D converter is ideal for portable and battery-operated systems. Table 6.1 shows data for this A/D converter.
The A/D converter uses a reference voltage to decide the value of the input voltage. Vin– is connected to ground, Vin+ to the microphone and Vref is connected to the reference voltage of 1.5 V. With a resolution of 16 bits between 0 V and 1.5 V the sensitivity of the least significant bit is small, only 2.3.10–5 V.
The A/D converter is controlled via the Sampling & BITSWAP process in the FPGA. One clock signal DCLOCK is generated and one SHDN signal which, when low, tells the A/D converter to generate output data via Dout. This
com-Sampling rate <100kHz max Power consumption 1.8 mW at 100 kHz
Package MSOP-8
Interface Serial Supply voltage 2.7 V to 5 V
Table 6.1. Data for ADS8320 1 2 3 4 5 6 7 Running
Chapter 6 – Final Model 31
munication is roughly described in Fig. 6.6. When SHDN goes low the A/D converter takes a sample and the most significant bit of the sample value is put on Dout after 2.5 DCLOCK clock cycle.
Figure 6.6: Communication between the A/D converter and the FPGA
6.7 MICROPHONE
The microphone that is used is an electret microphone. This microphone also has an integrated preamplifier, which makes it simple to connect it to an A/D converter.
An anti-aliasing filter between the microphone and the A/D converter is not necessary due to the frequency characteristic of the microphone. At the Nyquist frequency the magnitude obtained from the microphone is well below 3 dB, which should prevent aliasing effects with a satisfactory degree.
SHDN DCLOCK Dout
MSB Start sampling
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7
RESULT AND DISCUSSION
7.1 CONCLUSION
A system of this type is quite easy to implement since the complexity is rela-tively low. Despite this there are several things that, when looking back, could been made different. For example more time should have been spent on optimization of the algorithms before they were coded. Fewer multiplications could have been used and this would have contributed to a lower power con-sumption.
Also, safe scaling should have been introduced earlier since a lot of time were spent on trying to get the first type of scaling to work smoothly. The problem with the first type of scaling is that it was hard to decide how many bits that should be removed. This was difficult since it was hard to know how much overflow that was acceptable.
7.2 RESULTS
The result of this master thesis is a working prototype of the system. Sound is sampled with a sampling rate of 20 kHz via an A/D converter. Later the sound data is analysed with the FFT and different output levels are indicated. This prototype has been demonstrated for the customer, who was satisfied with the result and will use it for future design decisions.
7.3 FUTURE WORK
Almost all requirements on the system were fulfilled. However some require-ments are still not implemented. These are listed below.
• The main thing that still remains to be implemented is the db(A) filter. However this filter is easy implemented with the existing structure. In the x-square process a weight multiplication can be added. All that is needed is weight data that describes the frequency characteristic for the filter, which could, on this FPGA, be programmed in a RAM on start.
• Measurements over time is also possible to implement quite easily. All that is required is a couple of counters and a memory.
• If the design is to be changed for an ASIC as target hardware instead of the FPGA, some changes are necessary. The Memory Control process has to be rewritten for the available memories, and all output ports must be changed as well.
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REFERENCES
[1] S. Söderkvist and L-E. Ahnell, Tidsdiskreta Signaler och System. Tryckeriet E. Larsson AB, 1994.
[2] L. Wanhammar, K. Johansson, and O. Gustafsson, “Efficient sine and cosine computation using a weighted sum of bit-products,”European Conf. Circuit
Theory Design, Cork, Ireland, Aug. 28–Sept. 2, 2005, vol. 1, pp. 139–142.
[3] T. Widhe, Efficient Implementation of FFT Processing Elements. Tryckeriet UniTryck, Linköping, 1997.
[4] Hdl Designer, by Mentor Graphics, http://www.mentor.com/products/ fpga_pld/hdl_design/hdl_designer_series/.
