An FPGA based MPPT and monitoring system

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Degree project

An FPGA based MPPT and

monitoring system

suitable for a photovoltaic based microgrid

Author: Rongpeng Zheng Supervisor: Pieternella Cijvat Examiner: Pieternella Cijvat Date: 19-05-28

Course code: 2ED34E, 15 hp Topic: Electrical Engineering

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Summary

Nowadays there is increasedinterest in microgrids based on renewable sources, containing for example photovoltaic (PV) cells and wind power. These microgrids may work in stand-alone mode ("islanding") or be

connected to the main grid. In both modes of operation, power quality must be monitored and controlled.

This report focuses on microgrids and aims to implement a monitoring system for microgrids, based on FPGA. Based on the monitoring system, two applications could be achieved, firstly a PAS-MPPT algorithm in a DC-DC boost converter to improve the maximun power point tracking, secondly switching of grid mode, including detection of the grid mode (stand-alone or connected to the main grid) as well as switching. Simulation results prove that Verilog programs in FPGA are suitable to be used in microgrids.

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Abstract

Microgrids containing photovoltaic (PV) cells and wind power gain more and more interest. These microgrids may work in stand-alone mode ("islanding") or be conncted to the main grid. In both modes of operation, power quality must be monitored and controlled.

This report focuses on microgrids and aims to implement a monitoring system based on FPGA. In the monitoring system, two applications can be achieved, firstly a PAS-MPPT algorithm in a DC-DC boost converter to improve the maximun power point tracking of a PV unit, and secondly a detection and switching system of the grid mode - stand-alone or connected to the main grid. Simulation results prove the Verilog programs in FPGA are suitable to be used in microgrids.

Keywords: Microgrids, Monitoring System, Maximum Power Point Tracking (MPPT), Stand-alone Mode, Grid-connected Mode, FPGA, Verilog HDL.

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1. Introduktion

1.1. Background

A microgrid is an integrated platform consisting of a low-voltage (LV) distributed system with distributed energy resources (Fig. 1), for example, microturbines, fuel cells, photovoltaic (PV) cells, and corresponding storage units such as flywheels, energy capacitors and batteries. Besides, it also has requirements such as different loads. For the characteristics of the microgrid, it can be connected to a low voltage level, which means that it is usually at a low voltage, and its total installed microgenerated capacity is lower than the MW range, but it is also possible that part of the medium voltage (MV) network is attached to the microgrid for interconnection [1]. However, microgrids are also suitable to provide local electric power, in case there is no national or regional grid or in case of interrupted power supply. On this basis, the microgrid should have the ability to handle both grid-connected and islanded state.

Fig. 1. Microgrid as a LV grid [1]

With the popular trend of microgrids, some parameters in microgrids need to be monitored for improving their the operation and design [2], such as the power delivered from the microgrid, the generated power of distributed energy resource and the power quality.

There are many control algorithms used in microgrids, such as maximum power point tracking(MPPT) [3] for PV systems, regulating a DC-DC boost

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converter, or when the microgrid is in stand-alone mode, applying voltage-frequecy (V/f) control, e.g in a DC-AD inverter, or lastly active power and reactive power control (PQ control) in a DC-AC inverter when the PV system is in grid-connected mode [4]. However, the prerequisite of monitoring some parameters and using those algorithms is that they need sensors for collecting information from the microgrid. Thus, implementing a monitoring system for the microgrid is extremely necessary. It could collect instantaneous voltage, current, frequency from the microgrid.The central controller would get this information, use some equations to get some monitoring parameters and give corresponding control signals to some devices in the microgrid through control algorithms.

Based on the monitoring system, some control algorithms in microgrids can be implemented. For example, traditional MPPT needs average output current and voltage from PV arrays to generate pulse width modulation (PWM) signals with corresponding duty cycle to quickly track the maximum power point and ensure the PV system makes full use of its generation power. Another example is a MPPT in wind-turbine generation system [5]. This algorithms needs to detect wind velocity and rotor speed of the wind turbine from sensors to judge how the wind turbine input torque changes so that the MPPT makes the wind turbine track the maximun power point and maintain the ideal torque.

About the control center, the field-programmable gate arrays (FPGA) chip is a good choice for its scalability, programmability and integration. Scalability of FPGA chips is one of the advantages in microgrids, as modules in FPGA chips are able to be reused when it satifies the requirements of input and output. Parameters in programs are easy to change. For those reasons, FPGA chips could be used in some extension to microgrids including larger

microgrids and control algorithms could handle multi-channel control. Another advantage is that FPGA chips are programmable so that they could update or improve the control algorithms at any time and be a testing platform by programming [6]. In addition, FPGA chips could integrate the functions of many kinds of components which makes the cost of

implementations less than digital signal processors (DSP) which just focuses on digital processing [7].

1.2. Limitations

The report focuses on implementing a monitoring system for microgrids. Based on the monitoring system, there are some control algorithms that can be achieved, such as a piecewise adaptive step MPPT (PAS-MPPT) in [3] and stand-alone mode detection and switching based on FPGA. However, a microgrid is a large system which is hard to build in hardware so that this report will test the Verilog programs in FPGA by co-simulation of Simulink and Modelsim. The model of microgrids in Simulink is limited to a grid-connected PV system, which has the basic components as that in micorgrids.

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Due to time restrictions, other algorithms such as V/f control, PQ control and wind power control are not implemented.

1.3. Purpose and objectives

The aim of the report is to implement a monitoring system with a PV system as example, and use data from the monitoring system to achieve the PAS-MPPT algorithm. Moreover, stand-alone mode detectionas well as switching based on FPGA is to be implemented.

In order to achieve the above objectives, the following research questions will be answered:

(1) Based on microgrids connection, PV system guidelines and applied algorithms, which information needs to be monitored?

(2) Using the PV system as an example, how can the PAS-MPPT algorithm be implemented and how does it perform?

(3) Can the stand-alone mode detectionas well as switching be implemented? (4) How to build the FPGA programs in Verilog HDL?

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2. Monitoring system

2.1 Basic components of a PV based microgrid

Fig. 2. A model of a microgrid based on a PV system [3]

Shown in Fig. 2 is model of a PV-based microgrid. It clearly shows the basic components, such as solar array, battery storage, DC-DC boost converter, DC-AC inverter, loads and utility grid1. For each part of the PV system, PV array would produce power from solar energy whose maximun power could be tracked by MPPT in the DC-DC boost converter. After the DC-DC boost converter, the DC volatge would be provided to the battery storage and the DC-AC inverter. The battery, in parallel to the DC-DC boost converter,

1_{Wind power is not included in Fig. 2, however, if the wind power unit is including an AC-DC converter}

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could absorb or inject active power by a bidirectional DC-DC converter. In the DC-AC inverter, there are two control algorithms, V/f control in standalone mode and PQ control or synchronous generator control in grid-connected mode. Then, the whole PV system would provide three phase volatge and current to the point of commom coupling (PCC) which is the point connecting the utility grid, load and the microgird. Finally, there is a breaker between the PCC and utility grid to make the microgird into stand-alone system when the electricity from the microgird is not satisfying the requirements of connecting utility grid.

2.2 Guideline for photovoltaic system monitoring

In [2], there is a guideline about how to judge if the design goals are met and to improve the system design and operation through monitoring parameters of a PV system. According to the a table of Recorded Parameters for Analytical Monitoring, this report conbines with the Fig. 2 to get table I. There are many parameters that need to be monitored for analysising the PV system. This can be done by current trasformers and voltage transformers.

Table I: Monitor parameters based on system model

PARAMETER SYMBOL UNIT

Array output voltage Vpv V

Array output current (total)

Ipv A

Converter output current Idc A Converter output

voltage

Vdc V

Current input to battery storage

Isi A

Current output from battery storage

Iso A

dc line voltage (battery voltage)

Vbatt V

Inverter/rectifier dc current (+/-)

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2.3 An piecewise adaptive step MPPT

The principle of the piecewise adaptive MPPT(PAS-MPPT) is explained clearly in [3]. The MPPT needs two parameters: array output voltage(Vpv) and array output current (Ipv) which are shown in Table I. The priciple of PAS-MPPT will be explained in section 3 of the report.

2.4 V/f control

When the PV system is in stand-alone mode, the PV system lose the surport voltage and frequency from the untility grid. Therefore,the load needs to follow the frequency and voltage of the microgird which needs to maintain frequency and voltage at PCC. In [4], it is explained how to achieve V/f control. From Fig. 3, the algorithm needs the instantaneous voltage(vta, vtb, vtc) and the instantaneous current (ica, icb, icc) at point of common coupling (PCC) to get the power from DC-AC inverter (PAC measured), the frequency

(fa, fb, fc) from three phase DC-AC inverter and the average current and power delivered to the DC-AC inverter (PDC).

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2.5 P-Q control

When the PV system is in grid-connected mode, PQ control is used to improve the system performance so that the system could set the perfect active power and reactive power from the PV system output and maintain the system operation in the reference active and reactive power. In [4], the active power (P) and reactive power (Q) could be defined by the following equations:

（1）（2） Thus, the system needs the instantaneous voltage (vta, vtb, vtc) to get their RMS value (Vt) at PCC and instantaneous current (vca, vcb, vcc) as the output of the PV system to get their RMS value (Vc) after the DC-AC inverter. The α in equation (1) and (2) is the phase angle between Vc and Vt. The PQ control diagram is shown below. The system could set the value of Pref as well as Qref and finally maintain the ideal output active and reactive power.

Fig. 4. The PQ control diagram [2]

2.6 Other monitoring parameters

There are other parameters for the microgrid (PV system) that can be monitored, listed in Table II.

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Table II: Other monitoring parameters

Other monitoring parameters

Explanation

Ppv Output power from PV arrays Pdc Output power from DC-DC booster

converter

Rate_boost Power conversion efficiency of DC-DC booster converter

Pbatt Battery power

Pii Power delivered to DC-AC inverter Ica_rms RMS value of output current in the A

phase from DC-AC inverter

Vca_rms RMS value of output voltage in the A phase from DC-AC inverter

Vta RMS value of voltage in the A phase at PCC

P The output active power of the whole PV system

Q The output reactive power of the whole PV system

S The output apparent power of the whole PV system

cosα Power factor of the whole PV system Rate_power_inverter Power conversion efficiency of DC-AC

inverter

Rate_loss The loss rate of the whole PV system Pload Load power consumption

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3. PAS-MPPT for the PV system

The detailed priciple has been explained in [3]. This part will show the basic priciples of PAS-MPPT.

3.1 PV array characteristics

The basic simplified boost circuit of the PV array is shown below in Fig. 5:

Fig. 5. Simplified boost converter in PV system

Then, Eq.(3) below shows how the ducy cycle affects the PV output power (Ppv):

(3) R’L is the load resistance and RL is the resistance of the PV array. When the

duty cycle(D) of PWM signal is changed and a different PWM signal would be sent to the IGBT, the power of the PV array (Ppv) will be changed. When the D is a proper value, R’L will match RL so that Ppv will be the maximum

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3.2 Piecewise and adaptive step theory in PAS-MPPT

The Ppv-D curve and dp/dD curve are shown in Fig. 6 Here, Ppv is the output power of PV arrays and D is the duty cycle of PWM which is sent to DC-DC boost converter. The Ppv-D curve shows the relationship between the output D from PAS-MPPT and the output power of PV arrays. Then, the dp/dD curve is the derivative curve from the Ppv-D curve. When D is increased from 0 to 1, the dp/dD increase firstly, which is the B area but far away from A area. When D continues to be increased, the second derivative of P-D curve, Δ2_P/ΔD2_{is less than 0. From this point to the second}

intersection point with M, the area is B area and close to A area. The A area is limited by second and third intersection point with M. After the A area, there are the same way to judge different area. According to different area judgement, the calcution of the adaptive step of duty cycle is different in these three areas in Fig. 7 ΔDmax is a large fixed step and ΔD0 is a small

fixed step. Based on this control algorithms, the speed of tracking would be quickly baceuse of the large fixed step and the maximun point would be precise without large oscillation because of the small step in A area.

Fig. 6. Three areas: A,B and C [5]

B, C area but far away from A B, C area but close to A A area

Fig. 7. The adaptive step of duty cycle [5]

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3.3 The flow chart of PAS-MPPT

Below is the flow char of PAS-MPPT. The PAS-MPPT of Verilog programs would be based on Fig. 8 [3].

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4. Stand-alone mode switch

In [8], there are some recommended practices for a utility interface of photovoltaic (PV) systems:

(1) RMS voltage Vta/Vtb/Vtc at PCC, any one should be 88-110% of the rated voltage at the interface (in the simulation program, the RMS voltage at the interface is 220V).

(2) When encountering voltage problems, the PV system will not enter the island mode immediately which is dependent on the current voltage in Table III. Table III is based on 120V, but this report uses 220V as a reference. Cycles is the voltage acquisition period of 1 Vt (PCC voltage). For example, when V<50%, if it has not returned to normal within the specified 6 cycles, the PV system will enter the stand-alone mode.

Table III : Response to abnormal voltage [8]

Voltage (at PCC) Maximum trip time

V<50% 6 cycles

50%≤V<88% 120 cycles

88%≤V≤110% Normal operation 110%<V<137% 120 cycles

V≥137% 2 cycles

(3) The system output frequency and grid input frequency should be 59.3-60.5Hz. If it exceeds 6 cycles or is out of range, it will enter the stand-alone mode.

(4) If it is due to a grid fault and enters an island, it is necessary to detect that the grid Vsa and frequency fsa have been in normal operation for at least 5 minutes before the grid is restored.

(5) If the PV system is faulty, Vta/Vtb/Vtc+fa/fb/fc can be restored to the grid after returning to the specified value for at least 5 minutes.

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5 FPGA

In this part, the whole structure of the FPGA and each module will be shown. The RTL view diagrams show the connection of each module and the

interconnection of each module. In addition, the block diagrams display the input and output of each module.

5.1 Top-down design of FPGA

In Fig. 9, there is the module division for the FPGA which also shows the call level. MPPT_test_tops is the top level and can call other mudules. The second level inculdes clk_divider, sensor_out, fpga_calculation, fifo_tops, MPPT module, pwm_gen and islandcheck.The clk_divider module is used to generate different clock signals which are provided to other modules for sampling, calculating and controlling the output signals. Sensor_out module is used to receive the information from sensors. The fpga_calculation module is used in calculating some parameters which need to be calculated from the sensor information, such as the power of PV arrays (Ppv). The fifo_tops (first input first output) could control the data flow in order and make the output data steady. MPPT module is including the PAS-MPPT algorithm which calls the multi_core for calculating the power of PV arrays (Ppv). The pwm_gen could generate PWM signals with different duty cycle and it uses triangual signals as fundamental wave. The island_chek can judge the power quality from sensors and detemine if make the PV system should get into stand-alone mode.

Fig. 9. Top-down design of the FPGA

In Fig. 10, the relationship between different modules is shown, including the data width and data flow. Analog sensor from Simulink will send the digital value to the FPGA chip. Two parameters, Ipv and Vpv of the PV arrays, will go through the fifo_tops for controling the data flow to FPGA. Then, the power calculation would receive the Ipv and Vpv from fifo_tops module and send the power value of the PV arrays to MPPT. Finally, the FPGA will generate PWM signals to the DC-DC boost converter,

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stand-alone mode detection as well as switching and show all the parameters, collected by analog sensors and calculated to chipscope to monitor values changed in the Fig. 10.

Fig. 10. The FPGA block diagram

In Fig. 11, the synthesized register-transfer level (RTL) view for the FPGA cjip shows the connection of each module and the data flow from the whole system.

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5.2 Modules in the FPGA

In this part, more details will be shown about Verilog programs and the RTL view of each module.

5.2.1 Sensor out

This module is used to get the Ipv and Vpv from simulink. The Verilog program is shown in Appendix 1. Its internal connection diagram is shown in Fig. 12.

Fig. 12. The block diagram of Vpv and Ipv diagram

5.2.2 MPPT_module

The block diagram and the RLT view diagram of MPPT_mode is shown in Fig. 13. Its Verilog program is in Appendix 2.

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Fig. 13 (b). The RLT view diagram of MPPT_module

5.2.3 The fifo_tops module

The block diagram of the fifo_tops module is shown in Fig. 14. Its Verilog program is in Appendix 3.

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Fig.14 (a) The RLT view diagram of fifo_tops module.

5.2.4 The clk_divider module

The block diagram and the RLT view diagram of the clk_divider module is shown in Fig. 15. Its Verilog program is in Appendix 4.

Fig. 15 (a) The block diagram of the clk_divider module.

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5.2.5 The pwm_gen module

The RLT view diagram of the the pwm_gen module is shown in Fig. 16. Its Verilog program is in Appendix 5.

Fig. 16. The RLT view diagram of the pwm_gen module

5.2.6 The fpga_calculation module

The block diagram and a part of RLT view diagram of the the

fpga_calculation module is shown in Fig. 17. Its Verilog program is in Appendix 6.

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Fig.17 (b) A part of the RLT view diagram of the fpga_calculation module

5.2.7 The sensor_out module

The block diagram and a part of the RLT view diagram of the the sensor_out module is shown in Fig. 18. Its Verilog program is in Appendix 7.

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Fig.18 (b) A part of the RLT view diagram of the sensor_out module.

5.7.8 The islandcheck module

The block diagram and a part of the RLT view diagram of the the

islandcheck module is shown in Fig. 19. Its Verilog program is in Appendix 8.

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6. Simulation

Because a real environment to test the project is lacking, co-simulation of Simulink and Modelsim is used in this report. The simulation method is explained below.

Firstly, a model of a three phase grid-connected PV system is built in Simulink. It is shown in Fig. 20 and is based on Fig. 2.

Fig. 20. A model of a three phase grid-connected PV system

In the simulink model, the PAS-MPPT and synchronous generator control are used for tracking maximun power point and making the voltage output of the PV system follow the untility voltage. The simulation conditions are T = 25 ℃, S = 1000 W/m2 _{at t=0s, S = 1200 W/m}2 _{at t=0.05s and S = 1400}

W/m2 at t=0.09s. It is assumed that PV cells have an efficiency of 16-17% and an area of 50 m2. Thus, the maximum power from the PV is 8000W, 10000W and 12000W. After the first simulation, the sensor data from simulink would be collected to the FPGA chip.

Then, three functions can be achieved, monitoring system, PAS-MPPT and stand-alone dection as well as switching.

For the monitoring system, the FPGA can get the sensor information from the simulink which will go through fpga_calculation and sensor_out module. Then the FPGA would send those data to Chiscope. The sensor information and parameters in Section 3 will be shown in Chiscope.

For PAS-MPPT, the same algorithm is used in Simulink and the FPGA so the output duty cycle of PWM signals in the FPGA would be approximately the same as in Simulink. The output duty cycle and the input Ipv and Vpv

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correspond in time. Thus, this step provides the right sensor information to the FPGA. Then, the output file of PWM signals in the FPGA can be saved and be used in the Simulink model without PAS-MPPT. In this way, comparing the Ppv-t curve will prove whether the PAS-MPPT programs in FPGA is effective.

For stand-alone detection and switching, the corresponding value from sensors in section 4 can be changed in modelsim and it can be checked whether the programs work. After resetting the programs, the value of

voltage Vta or frequency fa in a signal phase at PCC is changed at t=3300 ns. Moreover, the rated RMS voltage of the model at PCC is 220V. Then the modelsim simulation will show the cnt, signal and breaker, which are counting the acquisition clocks, showing the unnormal situation and

disconnecting from the utility grid respectively. There are 6 situations to test the module below [8]:

(1) Vta <50%*220V: After 6 acquisition clocks, if the Vta collected by each sensor is still <50%*220V, then the signals of Signal_1 =1 and breaker =1 are given. (Signal_1=1 means that the detected fault is Vta <50%*220V, initial Signal_1 =0)

(2) 50%*220V<=Vta <88%*220V: After 120 acquisition clocks, and if the Vta collected by each clock is still within the range of 50%*220V and 88%*220V, then Signal_2 =1 and breaker =1.

(3) 110%*220V<Vta <137%*220V: After 120 acquisition clocks, if the Vta collected by each clock is still within the range of 110%*220V and

137%*220V, then Signal_3 =1 and breaker =1.

(4) Vta >=137%*220V: After 2 acquisition clocks, if the Vta collected by each clock is still more than 137%*220V, then Signal_4 =1 and breaker =1. (5) fa<59.3Hz or >60.5Hz: After 6 acquisition clocks, if each clock is still outside the specified range, then Signal_5 =1 and breaker =1 will be given. (6) Restore to grid-connected mode: When Vta and fa are within the

specified range for 5 minutes, then Signal_6 =1, breaker =0 and Signal_1~5 =0.

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7. Results and analysis

In this section, some simulation results are shown based on the method of section 6.

7.1 Monitoring system

The figures below show some parameters shown in Chipscope.

Fig. 21. Output Power of the PV arrays (Ppv)

Fig. 22. Active Power of the PV system (P)

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From fig. 21-23, output power of the PV arrays, the active power and reactive power of the PV system can be minitored by FPGA and the curves can be shown in Chipscope.

7.2 PAS-MPPT algorithm in PFGA

From the first simulation in simulink, Fig. 24 is obtained which shows the duty cycle of PWM signal (D), power (Ppv), voltage (Vpv) and current (Ipv) of the PV arrays.

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From the second simulation, with the PWM file from the FPGA, Fig. 25. is obtained.

Fig. 25. Second simulation result in simulink,with the FPGA From these figures, the reponding time is 0.02s from the beginning at S = 1000 W/m2. Then, the S is changed to 1200W/m2, suddently but the

maximun power point tracking is very fast so that it is hard to see what is the exact time it takes to track. Comparing these two figure, the result of second simulation shows a little bit more ripple which is caused by the harware of the FPGA and is unavoidable. The oscillation error is approximately 50W which is just 0.5% at S = 1000 W/m2. Moreover, the efficiency of the tracking maximum power point is 99.4% at S = 1000 W/m2. In conclusion, this method to test the programs in FPGA is feasible and obtains the approximate same result as the software simulation. That means the PAS-MPPT in FPGA will work in a real system.

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7.3 Stand-alone mode detection and switching

In this part, there are six figures from modelsim corresponding to six situations in section 6.

From the Fig. 26, the o_cnt1 starts to count the 6 acquisition clocks, but the the value of Vta is still less than 50%*220V so the o_signal1 and o_breaker turn to 1 which mean the abnormal situation is Vta is less than 50%*220V and the breaker in the untility side would be switched off with the help of a ralay.

Fig. 26. Simulation result of Vta <50%*220V

From the Fig. 27, the o_cnt2 starts to count the 120 acquisition clocks, but the value of Vta is still within the range of 50%*220V and 88%*220V so the o_signal2 and o_breaker turn to 1.

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From the Fig. 28, the o_cnt3 starts to count the 120 acquisition clocks, but the value of Vta is still within the range of 110%*220V and 137%*220V so the o_signal3 and o_breaker turn to 1.

Fig. 28. Simulation result of 110%*220V<Vta <137%*220V

From the Fig. 29, the o_cnt4 starts to count the 2 acquisition clocks, but the value of Vta still exceeds 137%*220V so the o_signal4 and o_breaker turn to 1.

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From the Fig. 30, the o_cnt5 starts to count the 6 acquisition clocks, but the value of fa is still out of the boundary so the o_signal5 and o_breaker turn to 1.

Fig. 30. Simulation result of fa<59.3Hz or >60.5Hz

From the Fig. 31, based on the Fig. 26, the value of Vta is normal at 5500 ns. Then, the o_cnt6 starts to count the 1000 acquisition clocks which is on behalf of five minutes. When the value of Vta is still normal after 1000 acquisition clocks, the o_signal6 turns to 1 but o_breaker turns to 0.

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8. Discussion and conclusion

Based on the good simulation results, the research questions are solved in different sections of the report.

Section 2 solves the problem about how to implement a monitoring system in microgrids with the example of a PV system. Guidelines show the information that needs to be monitored in PV plants. Some control algorithms, such as MPPT, V/f control and PQ control, ask for some

parameters as inputs. Those sensor information and parameters compose the monitoring system in the microgrid. In the presented implementation, Chipscope shows those parameters in figures.

Scetion 3 explains how to achieve the PAS-MPPT based on the monitoring system and make full use of the generation power in microgrids with the example of the PV system. Firstly, this section shows the characteristic of PV arrays and how the duty cycle of PWM signals affects the output power. Then, the piecewise and adaptive step theory are explained in detail. Finally, the flow chart of PAS-MPPT can guide how to write the Verilog programs. Therefore, comparing with the figures of the first simulation with MPPT, the figures of Ppv show the Verilog programs work successfully and can be used in a real system.

Section 4 shows some standards about when grid-connected microgrids should be switched off. There are four situations with regard to the abnormal voltage at PCC and one situation for abnormal frequency. The FPGA chip can get the sensor information from the microgrid, judge whether the system should be disconnected from the utility grid and how long it takes. As the results of simulations show, the FPGA chip can detect the islanding

requirements or restoring requirements and send the breaker signal to switch off or on the grid-connected mode. However, due to time constraints in the project, V/f control in the PV model is not implemented so the system can not recover the voltage and frequency in the normal range automatically. Section 5 shows how to implement the above functions in the FPGA chip. The top-down design shows the modules and their calling level. The block diagram shows the relationship between modules. Moreover, the Verilog programs and block diagrams of each module show how to implement the Verilog programs in the FPGA chip.

In conclusion, the monitoring system is implemented and two application, MPPT and stand-alone detecion as well as switching, are achieved. The Verilog programs in the FPGA chip can be used in real microgrids because of the good simulation results. In the future, the Verilog programs in the report could be resued or more programs can be added for monitoring more parameters or implementing more control algorithms to update the microgrid system.

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8. Appendices

Appendix 1: The Verilog code of Ipv and Vpv Appendix 2: The Verilog code of MPPT_module Appendix 3: The Verilog code of fifo_tops Appendix 4: The Verilog code of clk_divider Appendix 5: The Verilog code of pwm_gen Appendix 6: The Verilog code of fpga_calculation Appendix 7: The Verilog code of sensor_out Appendix 8: The Verilog code of islandcheck

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Appendix 1 The Verilog code of Ipv and Vpv

module sensor_out2( i_clk, i_rst, o_Ipv, o_Vpv ); input i_clk; input i_rst; output signed[15:0]o_Ipv; output signed[15:0]o_Vpv; Ipv Ipv_u( .i_clk (i_clk), .i_rst (i_rst), .o_dout(o_Ipv) ); Vpv Vpv_u( .i_clk (i_clk), .i_rst (i_rst), .o_dout(o_Vpv) ); endmodule

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Appendix 2 The Verilog code of MPPT_module

module MPPT_module( i_clk, i_rst, i_PV_current, i_PV_voltage, o_PV_power, o_PV_max, o_PV_current, o_PV_voltage, o_state ); input i_clk; input i_rst; input signed[15:0]i_PV_current; input signed[15:0]i_PV_voltage; output signed[31:0]o_PV_power; output signed[31:0]o_PV_max; output signed[15:0]o_PV_current;

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output signed[15:0]o_PV_voltage; output [1:0]o_state; //power multi_core multi_core_u( .a(i_PV_current), // input [15 : 0] a .b(i_PV_voltage), // input [15 : 0] b .p(o_PV_power) // output [31 : 0] p ); reg signed[31:0]r_PV_k1; reg signed[31:0]o_PV_max;

always @(posedge i_clk or posedge i_rst) begin if(i_rst) begin o_PV_max <= 32'd0; r_PV_k1 <= 32'd0; end else begin r_PV_k1 <= o_PV_power; if(o_PV_power>o_PV_max) o_PV_max <= o_PV_power; else o_PV_max <= o_PV_max;

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end end wire signed[31:0]Uk; wire signed[31:0]Pk; assign Uk = i_PV_voltage; assign Pk = o_PV_power; reg signed[15:0]dU = 16'd1; reg signed[15:0]dU0= 16'd1; reg signed[31:0]Pk1; reg signed[15:0]Uk1; reg signed[15:0]Uref; //adaptive step reg[19:0]cnt;

always @(posedge i_clk or posedge i_rst) begin if(i_rst) begin cnt <= 20'd0; end else begin

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if(cnt>=20'd35000) cnt <= 20'd35000; else cnt <= cnt+20'd1; end end reg[1:0]o_state;

always @(posedge i_clk or posedge i_rst) begin if(i_rst) begin Pk1 <= 32'd0; Uk1 <= 16'd0; Uref <= 16'd0; o_state <= 2'd0; end else begin Pk1 <= Pk; Uk1 <= Uk;

if(Pk>=Pk1 & Uk>Uk1) begin

Uref <= Uref +

{dU0[15],dU0[15],dU0[15],dU0[15],dU0[15],dU0[15],dU0[15:6]}; o_state <= 2'd0;

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end

if(Pk>=Pk1 & Uk<=Uk1) begin Uref <= Uref - {dU0[15],dU0[15],dU0[15],dU0[15],dU0[15],dU0[15],dU0[15 :6]}; o_state <= 2'd1; end

if(Pk<Pk1 & Uk>Uk1) begin Uref <= Uref - {dU0[15],dU0[15],dU0[15],dU0[15],dU0[15],dU0[15],dU0[15 :6]}; o_state <= 2'd2; end

if(Pk<Pk1 & Uk<=Uk1) begin Uref <= Uref + {dU0[15],dU0[15],dU0[15],dU0[15],dU0[15],dU0[15],dU0[15 :6]}; o_state <= 2'd3; end end end assign o_PV_voltage=Uref; assign o_PV_current=dU0 ; reg signed[31:0]Power_diffe; reg signed[7:0] Current_diff;

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always @(posedge i_clk or posedge i_rst) begin if(i_rst) begin dU <= 16'd1; dU0 <= 16'd1; Power_diffe <= 32'd0; Current_diff <= 8'd0; end else begin Power_diffe <= o_PV_max-r_PV_k1; Current_diff <= i_PV_current[15:8]; if(cnt<20'd4000) begin if({Power_diffe[31-4:16-4],4'd0}>16'd10) dU0<= {16'd16}; else dU0<= {Power_diffe[31-4:16-4],4'd0}; end else begin dU0<= {Power_diffe[31-4:16-4],4'd0}; end end end endmodule

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Appendix 3 The Verilog code of fifo_tops

module fifo_tops( i_clkw, i_clkr, i_rst, i_I, i_U, o_I_fifo, o_U_fifo ); input i_clkw; input i_clkr; input i_rst; input signed[15:0]i_I; input signed[15:0]i_U; output signed[15:0]o_I_fifo; output signed[15:0]o_U_fifo; reg flag; reg[7:0]cnt;

always @(posedge i_clkr or posedge i_rst) begin

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begin cnt <= 8'd0; flag<= 1'b0; end else begin if(cnt == 8'd200) cnt <= cnt; else cnt <= cnt + 8'd1; if(cnt == 8'd200) flag<= 1'b1; else flag<= 1'b0; end end fifos fifos_u1 ( .rst (i_rst), // input rst .wr_clk (i_clkw), // input wr_clk .rd_clk (i_clkr), // input rd_clk .din (i_I), // input [15 : 0] din .wr_en (1'b1), // input wr_en .rd_en (flag), // input rd_en

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.full (), // output full

.almost_full (), // output almost_full .empty (), // output empty

.almost_empty() // output almost_empty );

fifos fifos_u2 (

.rst (i_rst), // input rst

.wr_clk (i_clkw), // input wr_clk .rd_clk (i_clkr), // input rd_clk .din (i_U), // input [15 : 0] din .wr_en (1'b1), // input wr_en .rd_en (flag), // input rd_en

.dout (o_U_fifo), // output [15 : 0] dout .full (), // output full

.almost_full (), // output almost_full .empty (), // output empty

.almost_empty() // output almost_empty );

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Appendix 4 The Verilog code of clk_divider

module clk_divider( i_clk, i_rst, o_clock1, o_clock2, o_clock3 ); input i_clk; input i_rst; output o_clock1; output o_clock2; output o_clock3; reg[15:0]cnt;

always @(posedge i_clk or posedge i_rst) begin

if(i_rst) begin

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end else begin

cnt <= cnt+16'd1; end

end

assign o_clock1 =i_clk;

assign o_clock2 =i_clk;//~cnt[0]; assign o_clock3 =~cnt[0];//cnt[10]; endmodule

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Appendix 5 The Verilog code of pwm_gen

// pwm-gen top level module pwm_gen( i_clk1, i_clk2, i_rst, i_Uref, o_data_triangular, o_data_Udw, o_PWM1, o_PWM2 ); input i_clk1; input i_clk2; input i_rst;

input signed[9:0] i_Uref;

output signed[9:0]o_data_triangular; output o_data_Udw; output o_PWM1; //Pwm output o_PWM2; //Pwm wire[9:0]o_data_triangular; wire o_data_Udw; triangular_gen triangular_gen_u( .i_clk (i_clk1), .i_rstn (~i_rst), .o_data_triangular (o_data_triangular), .o_data_Udw (o_data_Udw) ); Pwm_sub Pwm_sub_u( .i_clk (i_clk2), .i_rstn (~i_rst), .i_data_Udw (o_data_Udw), .i_data_triangular (o_data_triangular), .i_Uref (i_Uref), .o_PWM (o_PWM1), .o_PWM1 (o_PWM2) ); Endmodule //triangular_gen module triangular_gen( i_clk,

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i_rstn,

o_data_triangular, o_data_Udw );

parameter Vtriangular = 10'd1000; //Vtriangular = fc/(2*ftri)

input i_clk;

input i_rstn;

output[9:0]o_data_triangular; //triangular

output o_data_Udw; //increase|decrease

reg[9:0]o_data_triangular; reg counter;

always@(posedge i_clk or negedge i_rstn) begin if(~i_rstn) begin o_data_triangular <= 10'd0; counter <= 1'b0; end else begin

if(!counter && o_data_triangular < Vtriangular) begin

o_data_triangular <= o_data_triangular + 1'b1;

end

else if(o_data_triangular == Vtriangular) begin

counter <= 1'b1;

o_data_triangular <= o_data_triangular - 1'b1;

end

else if(counter && o_data_triangular < Vtriangular && o_data_triangular != 0)

begin

o_data_triangular <= o_data_triangular - 1'b1;

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end else if(counter && o_data_triangular == 0)

begin counter <= 1'b0; o_data_triangular <= o_data_triangular + 1'b1; end else begin o_data_triangular <= 10'd0; end end end

assign o_data_Udw = counter; endmodule

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// Pwm_sub module Pwm_sub( i_clk, i_rstn, i_data_Udw, i_data_triangular, i_Uref, o_PWM, o_PWM1 ); parameter IDLE = 4'd0; parameter STATE1 = 4'd1; parameter STATE2 = 10'd79; parameter STATE3 = 10'd50; input i_clk; input i_rstn; input i_data_Udw; input[9:0]i_data_triangular; input[9:0]i_Uref; output o_PWM; output o_PWM1; reg o_PWM; reg[9:0]rbuf_triangular; reg[9:0]rbuf_uref; reg[3:0]Current_State; reg iscount; reg[9:0]Count1; reg[9:0]Count2;

always@(posedge i_clk or negedge i_rstn) begin if(~i_rstn) begin Count1 <= 10'd0; end else begin if(Count1 == STATE2) begin Count1 <= 10'd0; end else if(iscount) begin Count1 <= Count1 + 1'b1;

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end else if(!iscount) begin Count1 <= 10'd0; end end end

always@(posedge i_clk or negedge i_rstn) begin if(~i_rstn) begin Count2 <= 10'd0; rbuf_uref <= 10'd200; end else begin if(Count2 == STATE3) begin Count2 <= 10'd0; rbuf_uref <= i_Uref; end

else if(Count1 == STATE2 && iscount) begin Count2 <= Count2 + 1'b1; end else if(!iscount) begin Count2 <= 10'd0; end end end //PWM

always@(negedge i_clk or negedge i_rstn) begin if(~i_rstn) begin o_PWM <= 1'b0; rbuf_triangular <= 10'd0; Current_State <= IDLE; iscount <= 1'b0; end else begin case(Current_State) IDLE:begin rbuf_triangular <= i_data_triangular;iscount <= 1'b1;

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Current_State <= STATE1; end

STATE1:begin

Current_State <= IDLE; if(i_data_Udw == 0 && rbuf_triangular >= rbuf_uref)

begin

o_PWM <= 1'b1; end

else if(i_data_Udw == 1 && rbuf_triangular <= rbuf_uref)

begin o_PWM <= 1'b0; end end default:begin Current_State <= IDLE; end endcase end end

assign o_PWM1 = ~o_PWM; endmodule

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Appendix 6 The Verilog code of fpga_calculation

module fpga_calculation( i_clk, i_rst, i_Ipv, i_Vpv, i_U_dc, i_I_dc, i_Iso, i_Isi, i_Iii, i_Ibatt, i_Vbatt, i_ia, i_ib, i_ic, i_va, i_vb, i_vc, i_fa, i_fb, i_fc, i_vta, i_vtb,

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i_vtc, i_Ila, i_Isa, o_Ppv, o_Pdc, o_Rate_boost, o_Pbatt, o_Pii, o_Icarms, o_Vcarms, o_Vtarms, o_P, o_Q, o_S, o_alpha, o_Rate_power_inverter, o_Rate_loss, o_Pload, o_Pg ); input i_clk; input i_rst; input signed[15:0]i_Ipv; input signed[15:0]i_Vpv; input signed[15:0]i_U_dc; input signed[15:0]i_I_dc; input signed[15:0]i_Iso; input signed[15:0]i_Isi; input signed[15:0]i_Iii; input signed[15:0]i_Ibatt; input signed[15:0]i_Vbatt;

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input signed[15:0]i_ia; input signed[15:0]i_ib; input signed[15:0]i_ic; input signed[15:0]i_va; input signed[15:0]i_vb; input signed[15:0]i_vc; input signed[15:0]i_fa; input signed[15:0]i_fb; input signed[15:0]i_fc; input signed[15:0]i_vta; input signed[15:0]i_vtb; input signed[15:0]i_vtc; input signed[15:0]i_Ila; input signed[15:0]i_Isa; output signed[31:0]o_Ppv; output signed[31:0]o_Pdc; output signed[31:0]o_Rate_boost; output signed[31:0]o_Pbatt; output signed[31:0]o_Pii; output signed[31:0]o_Icarms; output signed[31:0]o_Vcarms; output signed[31:0]o_Vtarms; output signed[31:0]o_P; output signed[31:0]o_Q; output signed[31:0]o_S; output signed[31:0]o_alpha;

//rate of power loss in the DC-AV Inverter output signed[31:0]o_Rate_power_inverter; output signed[31:0]o_Rate_loss; output signed[31:0]o_Pload; output signed[31:0]o_Pg; // Ppv of PV arrays multi_core multi_core_u( .a(i_Ipv), // input [15 : 0] a .b(i_Vpv), // input [15 : 0] b .p(o_Ppv) // output [31 : 0] p );

// Pdc of the output power of the DC-DC booster converter multi_core multi_core_u2(

.a(i_U_dc), // input [15 : 0] a .b(i_I_dc), // input [15 : 0] b .p(o_Pdc) // output [31 : 0] p

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);

//rate of power loss in the DC-DC booster converter

//--- Begin Cut here for INSTANTIATION Template ---// INST_TAG divider divider_u3 (

.clk(i_clk), // input clk .sclr(i_rst), // input sclr .rfd(), // output rfd

.dividend(o_Pdc), // input [31 : 0] dividend

.divisor({o_Ppv[31],o_Ppv[31],o_Ppv[31],o_Ppv[31],o_Ppv[31],o _Ppv[31],o_Ppv[31:6]}), // input [31 : 0] divisor

.quotient(o_Rate_boost), // output [31 : 0] quotient .fractional()

); // output [31 : 0] fractional // Pbatt battery power

multi_core multi_core_u4( .a(i_Ibatt), // input [15 : 0] a .b(i_Vbatt-16'd1720), // input [15 : 0] b .p(o_Pbatt) // output [31 : 0] p );

// Pii input to the DC-AC Inverter multi_core multi_core_u5( .a(i_Iii), // input [15 : 0] a .b(i_U_dc), // input [15 : 0] b .p(o_Pii) // output [31 : 0] p );

//a相输出 RMS 电流 Ica_rms//FPGA 资源限制，只能 matlab 计算好了， FPGA显示 wire signed[15:0]Icarms; Icarms Icarms_u( .i_clk(i_clk), .i_rst(i_rst), .o_dout(Icarms) ); assign o_Icarms={Icarms[15],Icarms[15],Icarms[15],Icarms[15],Icarms[15],Icarms [15],Icarms[15],Icarms[15],Icarms[15],Icarms[15],Icarms[15],Icarms[15],Ic arms[15],Icarms[15],Icarms[15],Icarms[15],Icarms};

// Vca_rms the output RMS voltage value of the A phase wire signed[15:0]Vcarms;

Vcarms Vcarms_u( .i_clk(i_clk), .i_rst(i_rst), .o_dout(Vcarms)

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); assign

o_Vcarms={Vcarms[15],Vcarms[15],Vcarms[15],Vcarms[15],Vcarms[15], Vcarms[15],Vcarms[15],Vcarms[15],Vcarms[15],Vcarms[15],Vcarms[15], Vcarms[15],Vcarms[15],Vcarms[15],Vcarms[15],Vcarms[15],Vcarms}; // Vta the RMS voltage value of the A phase at PCC

wire signed[15:0]Vtarms; Vtarms Vtarms_u( .i_clk(i_clk), .i_rst(i_rst), .o_dout(Vtarms) ); assign o_Vtarms={Vtarms[15],Vtarms[15],Vtarms[15],Vtarms[15],Vtarms[15],Vta rms[15],Vtarms[15],Vtarms[15],Vtarms[15],Vtarms[15],Vtarms[15],Vtarms [15],Vtarms[15],Vtarms[15],Vtarms[15],Vtarms[15],Vtarms};

// active power P of the PV system wire signed[15:0]P; P P_u( .i_clk(i_clk), .i_rst(i_rst), .o_dout(P) ); assign o_P={P[15],P[15],P[15],P[15],P[15],P[15],P[15],P[15],P[15],P[15],P[15],P[ 15],P[15],P[15],P[15],P[15],P};

// reactive power Q of the PV system wire signed[15:0]Q; Q Q_u( .i_clk(i_clk), .i_rst(i_rst), .o_dout(Q) ); assign o_Q={Q[15],Q[15],Q[15],Q[15],Q[15],Q[15],Q[15],Q[15],Q[15],Q[15],Q[1 5],Q[15],Q[15],Q[15],Q[15],Q[15],Q};

// apparent power S of the PV system assign o_S = o_P+o_Q;

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//power factor cosα wire signed[15:0]alpha; alpha alpha_u( .i_clk(i_clk), .i_rst(i_rst), .o_dout(alpha) ); assign o_alpha={alpha[15],alpha[15],alpha[15],alpha[15],alpha[15],alpha[15],alph a[15],alpha[15],alpha[15],alpha[15],alpha[15],alpha[15],alpha[15],alpha[15] ,alpha[15],alpha[15],alpha};

//rate of loss power in the Inverter divider divider_u4 (

.dividend(o_Pii), // input [31 : 0] dividend

.divisor({o_Pdc[31],o_Pdc[31],o_Pdc[31],o_Pdc[31],o_Pdc[31],o_ Pdc[31],o_Pdc[31:6]}), // input [31 : 0] divisor

.quotient(o_Rate_power_inverter), // output [31 : 0] quotient .fractional()

); // output [31 : 0] fractional

// rate of loss power in the PV system wire signed[31:0]Rate_loss;

divider divider_u5(

.dividend(o_Pii), // input [31 : 0] dividend

.divisor({o_Ppv[31],o_Ppv[31],o_Ppv[31],o_Ppv[31],o_Ppv[31],o _Ppv[31:5]}), // input [31 : 0] divisor

.quotient(Rate_loss), // output [31 : 0] quotient .fractional() ); // output [31 : 0] fractional assign o_Rate_loss=100-Rate_loss; // Pload wire signed[31:0]Pload; multi_core multi_core_u10( .a(i_Ila), // input [15 : 0] a .b(o_Vtarms), // input [15 : 0] b .p(Pload) // output [31 : 0] p

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); assign o_Pload={Pload[30],Pload[30:0]}+Pload; // Pg from grid wire signed[31:0]Pg; multi_core multi_core_u11( .a(i_Isa), // input [15 : 0] a .b(o_Vtarms), // input [15 : 0] b .p(Pg) // output [31 : 0] p ); assign o_Pg={Pg[30],Pg[30:0]}+Pg; endmodule

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Appendix 7 The Verilog code of sensor_out

module sensor_out( i_clk, i_rst, o_Ipv, o_Vpv, o_U_dc, o_I_dc, o_Iso, o_Isi, o_Iii, o_Ibatt, o_Vbatt, o_ia, o_ib, o_ic, o_va, o_vb, o_vc, o_fa,

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o_fb, o_fc, o_vta, o_vtb, o_vtc, o_Ila, o_Isa ); input i_clk; input i_rst; output signed[15:0]o_Ipv; output signed[15:0]o_Vpv; output signed[15:0]o_U_dc; output signed[15:0]o_I_dc; output signed[15:0]o_Iso; output signed[15:0]o_Isi; output signed[15:0]o_Iii; output signed[15:0]o_Ibatt; output signed[15:0]o_Vbatt; output signed[15:0]o_ia; output signed[15:0]o_ib; output signed[15:0]o_ic; output signed[15:0]o_va; output signed[15:0]o_vb; output signed[15:0]o_vc; output signed[15:0]o_fa;

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output signed[15:0]o_fb; output signed[15:0]o_fc; output signed[15:0]o_vta; output signed[15:0]o_vtb; output signed[15:0]o_vtc; output signed[15:0]o_Ila; output signed[15:0]o_Isa; Ipv Ipv_u( .i_clk (i_clk), .i_rst (i_rst), .o_dout(o_Ipv) ); Vpv Vpv_u( .i_clk (i_clk), .i_rst (i_rst), .o_dout(o_Vpv) ); /////////////////////////////////////////////////// U_dc U_dc_u( .i_clk (i_clk), .i_rst (i_rst), .o_dout(o_U_dc) ); I_dc I_dc_u( .i_clk (i_clk), .i_rst (i_rst), .o_dout(o_I_dc) ); Iso Iso_u( .i_clk (i_clk), .i_rst (i_rst),

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.o_dout(o_Iso) ); Isi Isi_u( .i_clk (i_clk), .i_rst (i_rst), .o_dout(o_Isi) ); Iii Iii_u( .i_clk (i_clk), .i_rst (i_rst), .o_dout(o_Iii) ); /////////////////////////////////////////////////// Ibatt Ibatt_u( .i_clk (i_clk), .i_rst (i_rst), .o_dout(o_Ibatt) ); Vbatt Vbatt_u( .i_clk (i_clk), .i_rst (i_rst), .o_dout(o_Vbatt) ); /////////////////////////////////////////////////// ia ia_u( .i_clk (i_clk), .i_rst (i_rst), .o_dout(o_ia) ); ib ib_u( .i_clk (i_clk), .i_rst (i_rst),

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.o_dout(o_ib) ); ic ic_u( .i_clk (i_clk), .i_rst (i_rst), .o_dout(o_ic) ); va va_u( .i_clk (i_clk), .i_rst (i_rst), .o_dout(o_va) ); vb vb_u( .i_clk (i_clk), .i_rst (i_rst), .o_dout(o_vb) ); vc vc_u( .i_clk (i_clk), .i_rst (i_rst), .o_dout(o_vc) ); /////////////////////////////////////////////////// fa fa_u( .i_clk (i_clk), .i_rst (i_rst), .o_dout(o_fa) ); fb fb_u( .i_clk (i_clk), .i_rst (i_rst),

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.o_dout(o_fb) ); fc fc_u( .i_clk (i_clk), .i_rst (i_rst), .o_dout(o_fc) ); /////////////////////////////////////////////////// vta vta_u( .i_clk (i_clk), .i_rst (i_rst), .o_dout(o_vta) ); vtb vtb_u( .i_clk (i_clk), .i_rst (i_rst), .o_dout(o_vtb) ); vtc vtc_u( .i_clk (i_clk), .i_rst (i_rst), .o_dout(o_vtc) ); /////////////////////////////////////////////////// Ila Ila_u( .i_clk (i_clk), .i_rst (i_rst), .o_dout(o_Ila) );

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Isa Isa_u( .i_clk (i_clk), .i_rst (i_rst), .o_dout(o_Isa) ); endmodule

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Appendix 8 The Verilog code of islandcheck

module islandcheck2( i_clk, i_rst, i_vta,i_fa, o_signal1, o_signal2, o_signal3, o_signal4, o_signal5, o_signal6, o_breaker, o_cnt1, o_cnt2, o_cnt3, o_cnt4, o_cnt5, o_TIME ); //1 parameter Vlvl1 = 110;//放大了 8 倍 //2 parameter Vlvl2 = 193;//放大了 8 倍,8*0.88*220 //3 parameter Vlvl31= 242;//放大了 8 倍,8*110%220V parameter Vlvl32= 301;//放大了 8 倍,8*137%*220

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input i_clk; input i_rst; input signed[15:0]i_vta; input signed[15:0]i_fa; output o_signal1; output o_signal2; output o_signal3; output o_signal4; output o_signal5; output o_signal6; output o_breaker; output[7:0] o_cnt1; output[7:0] o_cnt2; output[7:0] o_cnt3; output[7:0] o_cnt4; output[7:0] o_cnt5; output[15:0]o_TIME; reg o_signal1 = 1'b0; reg o_signal2 = 1'b0; reg o_signal3 = 1'b0; reg o_signal4 = 1'b0; reg o_signal5 = 1'b0; reg o_signal6 = 1'b0; reg r_signal1 = 1'b0; reg r_signal2 = 1'b0; reg r_signal3 = 1'b0; reg r_signal4 = 1'b0; reg r_signal5 = 1'b0; reg r_signal6 = 1'b0; reg o_breaker = 1'b0; reg[7:0]o_cnt1 = 8'd0; reg[7:0]o_cnt2 = 8'd0; reg[7:0]o_cnt3 = 8'd0; reg[7:0]o_cnt4 = 8'd0; reg[7:0]o_cnt5 = 8'd0; reg[15:0]o_TIME = 16'd0;

(77)

//1

always @(posedge i_clk or posedge i_rst) begin if(i_rst) begin r_signal1 <= 1'b0; r_signal2 <= 1'b0; r_signal3 <= 1'b0; r_signal4 <= 1'b0; r_signal5 <= 1'b0; r_signal6 <= 1'b0; o_signal1 <= 1'b0; o_signal2 <= 1'b0; o_signal3 <= 1'b0; o_signal4 <= 1'b0; o_signal5 <= 1'b0; o_signal6 <= 1'b0; o_breaker <= 1'b0; o_cnt1 <= 8'd0; o_cnt2 <= 8'd0; o_cnt3 <= 8'd0; o_cnt4 <= 8'd0; o_cnt5 <= 8'd0; o_TIME <=16'd0; end else begin //1 if(i_vta < Vlvl1) begin o_cnt1 <= o_cnt1+8'd1; if(o_cnt1>= 8'd5) begin r_signal1 <= 1'b1; end else begin r_signal1 <= 1'b0; end end else begin o_cnt1 <= 8'd0; r_signal1 <= 1'b0; end //2

(78)

begin o_cnt2 <= o_cnt2+8'd1; if(o_cnt2>= 8'd119) begin r_signal2 <= 1'b1; end else begin r_signal2 <= 1'b0; end end else begin o_cnt2 <= 8'd0; r_signal2 <= 1'b0; end //3

if(i_vta >= Vlvl31 & i_vta<Vlvl32) begin o_cnt3 <= o_cnt3+8'd1; if(o_cnt3>= 8'd119) begin r_signal3 <= 1'b1; end else begin r_signal3 <= 1'b0; end end else begin o_cnt3 <= 8'd0; r_signal3 <= 1'b0; end //4 if(i_vta>Vlvl32) begin o_cnt4 <= o_cnt4+8'd1; if(o_cnt4>= 8'd1) begin r_signal4 <= 1'b1; end else begin r_signal4 <= 1'b0; end end else begin o_cnt4 <= 8'd0;

(79)

r_signal4 <= 1'b0; end //5 if(i_fa<=59 | i_fa>=61) begin o_cnt5 <= o_cnt5+8'd1; if(o_cnt5>= 8'd5) begin r_signal5 <= 1'b1; end else begin r_signal4 <= 1'b0; end end else begin o_cnt5 <= 8'd0; r_signal5 <= 1'b0; end //6

if(i_vta == 220 & (i_fa>59 & i_fa<61)) begin o_TIME <= o_TIME+16'd1; if(o_TIME>= 16'd1000) begin r_signal6 <= 1'b1; end else begin r_signal6 <= 1'b0; end end else begin o_TIME <= 16'd0; r_signal6 <= 1'b0; end o_signal1 <= r_signal1; o_signal2 <= r_signal2; o_signal3 <= r_signal3; o_signal4 <= r_signal4; o_signal5 <= r_signal5; o_signal6 <= r_signal6;

(80)

if(r_signal1==1'b1 | r_signal2==1'b1 | r_signal3==1'b1 | r_signal4==1'b1 | r_signal5==1'b1)

o_breaker <= 1'b1; if(r_signal6 ==1'b1) o_breaker <= 1'b0; end end endmodule

(81)

(82)

Fakulteten för teknik

An FPGA based MPPT and monitoring system

Degree project