IGCT Transient Analysis and Clamp Circuit Design for VSC valves

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Degree project in

IGCT Transient Analysis and Clamp Circuit Design for VSC valves

SANCHIT SINGH

Stockholm, Sweden 2012

XR-EE-E2C 2012:014 Electrical Engineering Master of Science

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IGCT Transient Analysis and Clamp Circuit Design for VSC valves

Author Sanchit Singh

Company Supervisor Senior Specialist. Ingemar Blidberg

Examiner and Supervisor at Institute Prof. Hans-Peter Nee

Master Thesis

Department of Electrical Energy Conversion School of Electrical Engineering Royal Institute of Technology (KTH)

Stockholm, Sweden 2012

XR-EE-E2C 2012:014

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Abstract

I

^Ntoday’s high power VSCs (Voltage Source Converters), IGBTs (Insulated Gate Bipolar Transistors) are the dominant semiconductors. These converters are in general modular multilevel based and contain several building blocks that are series connected. Each of these building blocks in turn con- sist of several series connected IGBT valves. One of the advantages of using modular multilevel based VSCs is the ability to switch each building block at a lower frequency compared to the average total switching frequency of the converter. IGBTs generally have lower switching losses than other semiconductors, however, their on-state losses are higher because of a larger on-state voltage. Furthermore, series connection of IGBTs devices imposes voltage sharing complications that are generally difficult to deal with. A solution to this problem is to increase the amount of series connected building blocks and thus avoid series connection of semiconductors. To lower the semiconductor on-state losses, ei- ther the IGBTs are replaced by improved IGBT and drives or an alternative semiconductor that is more suited for modular multilevel topologies can be used. In this thesis, an alternative semiconductor called IGCT (Integrated Gate-Commutated Thyristor) is studied; more specifically RC-IGCT (Reverse Conducting IGCT). An analytic analysis is conducted to grasp the switching behavior, furthermore, a simulation model in Pspice^R is proposed for confirming the analytic analysis. This model is also used for parameter sweeps of clamp circuit components from which a table is created. This table can be used for comprehending the effects of changing values on the switching transient and also for the design of clamp circuit components. However, a numerical and a graphical method together with the Pspice^R model are proposed for designing the clamp circuit. It is found that the graphical method is far more intuitive and revealing than the numerical. If further accuracy is required, then the graphical method can be used in tandem with the numerical. A fault case analysis of the clamp circuit is conducted in order to reveal how failures in the clamp components affect the semiconductors and other components in a building block. Some of these failures are more destructive than others. The IGCT building block states and current paths are discussed and finally series connection of IGCTs is considered.

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Sammanfattning

I

^Dagens högeffekt VSC:er (Voltage Source Converter), IGBT:er (Insulated Gate Bipolar Transistor) är dominanta halvledare. De här omvandlare är generellt modulär multi-nivå baserade och innehåller flertal block som är seriekopplade. Varje block i sin tur består av ett antal seriekopplade IGBT:er. En av fördelarna med att använda modulär multi-nivå omvandlare är möjligheten att kunna switcha enskilda block med lägre frekvens än den totala medelfrekvensen av omvandlaren. IGBT:er har generellt lägre switchförluster än andra halvledare, dock har de oftast högre ledförluster. Seriekoppling av IGBT:er är komplicerad ur spänningsdelnings perspektive samt svårare att hantera än tillämpningar utan seriekoppling. En lösning till detta problemet är att öka antal block i omvandlare, vilket leder till att seriekoppling kan undvikas. För att lösa det andra problemet med höga ledförluster kan man antingen ersätta IGBT:er med förbättrade versioner eller så kan man använda alternativa halvledare. I det här exjobbet, en alternativ halvledare som heter IGCT (Integrated Gate-Commutated Thyristor) studeras;

mer specifikt RC-IGCT (Reverse Conducting IGCT). En analytisk analys genomförs för att få insikt i switchförloppen samt en simuleringsmodell förslåss för att bekräfta den analytiska analysen. Denna föreslagna modellen används även till parametriska simuleringar av klampkrets komponenter för att skapa en tabell. Tabellen används för att förstå hur ändringar i komponentvärden påverkar switchför- loppen samt även används för att designa klampkrets komponenter. En design procedur som använder sig av en numerisk metod och en grafisk method tillsammans med simuleringar föreslåss. Man kom- mer fram till att grafiska metoden är helt klart mer intuitiv samt mer avslöjande än den numeriska metoden. Om mer noggrannhet önskas, kan grafiska metoden tillsammans med numeriska metoden användas. Ett felfall analys genomförs för att ta reda på hur felen i klampkretsen påverkar de övriga komponenterna i blocken. Vissa av dessa fel är mer destruktiva än andra. IGCT block tillstånd och strömbanor diskuteras och slutligen seriekopping av IGCT:er undersöks.

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Acknowledgments

The completion of this master thesis has only been possible through support from numerous individuals. I would like to take the opportunity to express my gratitude towards the following individuals:

• Professor Hans-Peter Nee for accepting the supervision of this thesis.

• Senior Specialist Ingemar Blidberg at ABB HVDC for:

– Accepting me for this thesis.

– Providing support, constructive feedback and discussions in both the report and thesis work.

• Annika Lokrantz at ABB HVDC for providing with detailed and constructive feedback on the report.

• Jim Liljekvist at ABB HVDC for:

– showing interest in my thesis.

– Being there to listen to my thoughts and ideas.

– Providing with constructive comments and his own ideas.

I would also like to thank the members of the department for making the work experience pleasant and enjoyable.

Lastly, I would like to thank my family for providing moral support and motivation throughout my education at KTH.

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Introduction

I

^Nthe early days of electrical engineering, DC (Direct Current) system was the only type of transmission system known to mankind and it was in use between 1870s and 1880s. In the late 1880s, the AC (Alternating Current) transmission system emerged and overwhelmed DC. Even though AC-system has been the norm for quite some time now, DC-system has continued to evolve in the shadows. From 1930s and onwards, a rising demand for power paved the way for HVDC (High Voltage Direct Cur- rent) as an alternative for transmission of high power from remote localities[1]. Today at ABB, HVDC is promoted in two different forms, HVDC Classic and HVDC Light¹.

HVDC Light is a self-commutated VSC (Voltage Source Converter) based technology. It is a successful and environmental friendly way of designing a power transmission system. HVDC Light is specially beneficial when it comes to supplying power to offshore platforms, connecting offshore wind farms, improving grid reliability, city infeed and powering islands[1]. As of now, the converter stations use state of the art turn-on/turn-off IGBT (Insulated-Gate Bipolar Transistor) as valves (see Figure 0.1 for a simplified diagram of a HVDC with VSC).

IGBT Valves

Figure 0.1.: Simplified single-line diagram for HVDC with voltage source converters[2].

Some benefits of HVDC Light over conventional HVDC Classic are[1, 2]:

• Compact and light-weight design.

• Rapid control of both active and reactive power independently of each other to keep voltage and frequency stable.

• Reactive power can be controlled at terminals without being dependent on dc transmission voltage level.

• Converters can be placed almost anywhere in the AC system.

1Siemens has an equivalent product called HVDC Plus.

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2 Introduction

• Permits black start; i.e. converter can behave as a synchronous generator.

• Converters demand no reactive power.

• There is no restriction on minimum network short-circuit capacity.

• No relevant electromagnetic fields.

Taking the above mentioned benefits of HVDC Light into consideration, one can conclude that it has a promising future as can alternative to the conventional HVDC system. The reason why HVDC Light hasn’t completely replaced HVDC Classic is due to technical limitation at very high power transmission, cost effectiveness and because losses are still higher at the same power level.

HVDC Light Generations

HVDC Light has been in constant development since 1997. The generation number simply represents improvements in terms of cost and loss reduction made in the development of HVDC Light since the last generation.

Generation 1

Generation 1 technology emerged in 1997[3]. It is based on two-level topology (see Figure 0.2 for a simplified diagram of a two-level converter topology) and promises converter losses of no more than 3%[4]. To keep the current ripple low, a high switching frequency is used and filters are required to damp harmonic distortions.

+

-

Ud

Figure 0.2.: Simplified single-line diagram of a Two-level converter.

Generation 2

Generation 2 emerged in 2002 and is based on a three-level topology (see Figure 0.3 for a simplified diagram of a three-level converter topology)[4]. This technology permits a lower switching frequency (thus reducing switching losses) and promises converter losses of no more than 1.8% at the cost of in- creased component cost[3]. The conversion reduces the stresses on the filter compared with generation 1 due to improved harmonic generation.

Generation 3

Generation 3 was introduced in 2005; this generation promised losses of no more than 1.4%, but this technology utilized the two-level converter topology once again[4]. Loss reduction was achieved by optimized IGBT and drive, and OPWM (Optimized Pulse-Width Modulation) with lower switching frequency. Thus, harmonic generation was kept at the same level as generation 2.

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Introduction 3

Ud +

-

Ud

Figure 0.3.: Simplified single-line diagram of a Three-level converter.

Generation 4

It is based on MMC²(Modular Multilevel Converter) (seeFigure 0.4 for a simplified diagram of a MMC topology). It promises reduced switching losses, with total converter losses down to 1%. Almost no filtering is required and it is easily scalable to high voltages. One of the main reasons for lowered switching losses and filtering stresses is that, that even though the effective switching frequency of the converter is very high, each building block is switched at a much lower frequency[5].

- +Ud

Ud

Figure 0.4.: Simplified single-line diagram of a MMC.

2ABB calls its MMC for CTL, because it is a little different in some aspects[5].

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4 Introduction

Trend Today

Today, work is underway in this field to minimize the losses of HVDC Light further and at the same time increase the power capacity such that it is comparable to HVDC Classic. This goal can be achieved by using numerous methods. One such method is to replace today’s IGBT valves with improved IGBT valves and control strategies or use a different semiconductor.

Purpose

The purpose of this thesis is to study an alternative semiconductor called IGCT (Integrated Gate- Commutated Thyristor) for the converter valves. Only recently, developments in the field of IGCTs have improved the Safe Operating Area (SOA)[6] and made IGCT an attractive candidate as valves in the converters. ABB HVDC have limited experience in handling IGCTs and one significant part of the study is to comprehend IGCT; its basic structure and functionality.

The category of IGCT that this thesis will mainly discuss is called RC-IGCT (Reverse Conducting Integrated Gate-Commutated Thyristor). The study will contain the following aspects:

• The turn-on and turn-off behavior.

• The effect of surrounding electrical components on the switching transients on MMC building block level.

• Optimizing the clamp circuit for a given maximum DC-capacitor voltage and turn-off load current.

• Study of behavior in fault cases.

• Understanding states and current paths of an IGCT MMC building block.

• Considering series connection of IGCTs.

Scope

To meet the goals of the study, following steps will be taken:

• Get sufficient knowledge of the layout of a typical GCT.

• Comprehend the turn-on and turn-off behavior of the GCT part using semiconductor physics.

• Find a suitable program for simulation of the RC-IGCT with its clamp circuit.

• Comprehend the commutation process between IGCT and diode using heuristic reasoning and confirmation using simulations.

• Conduct an analysis to determine the model robustness and accuracy.

• Understand how changes in the clamp circuit parameters and stray inductances affect transient behavior through parameter sweeps.

• Use the information from the above step to determine the criteria for optimum performance.

• Determine the optimum clamp circuit parameters for a given DC-voltage and maximum turn-off load current.

• Use simulation to determine how the performance of IGCT circuit is affected during different clamp circuit fault cases.

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Introduction 5

• Consider an IGCT MMC building block and discuss the commutation process, the different states and current paths.

• Understand how IGCT can be series connected and discuss the advantages and disadvantages of doing so.

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CHAPTER 1 IGCT Introduction

T

^HEIGCT is introduced including why it is considered to be a suitable candidate as a valve in the modern day converter valves, its internal structure and the different categories of IGCTs available today. Furthermore, a study is conducted in order to understand the switching behavior of the GCT part of the IGCT. Lastly, switching waveform terminology and definitions are introduced

1.1. Considering IGCT as Valve

IGCT is a power semiconductor that can be considered as an improvement to the more common Gate Turn-off Thyristor (GTO). IGCT was commercially introduced in 1997 and its main application domains were Industrial Drives, Traction and Energy Management. After just 5 years of its introduction, IGCT established itself as the power semiconductor of choice for high power level applications, because of lower costs, higher reliability and efficiency[7]. In general, IGBT’s are more cost effective at high powers and high frequencies. Free Wheeling Diodes (FWD) are fast and IGBT losses are, in comparison with other devices such as GTO and IGCTs, low. However, IGCTs are better suited for still higher powers but lower switching frequencies[8]. The superiority of IGCTs is noticeable at higher powers. In the on-state, IGCT generally has a smaller on-state voltage and hence lower losses in this mode compared to an IGBT of the same voltage and current class. Lower switching frequencies are required due to higher turn-on and turn-off energies of IGCTs.

High power applications require series connection of semiconductor devices since these devices can block only a limited amount of voltage. Even though, there has been some success earlier with series connection of IGCT’s in high power applications[9], it is still considered to be a more difficult venture in comparison with series connection of IGBTs[10]. This is one of the reasons as to why IGCT hasn’t established itself asTHE power semiconductor of choice for VSC valves. Recent trends however are pointing towards dismissing series connection of power semiconductors altogether[11] and instead use many more cells³in the MMC (seeFigure 0.4). In MMCs, lower switching frequencies are employed and voltage step is scalable in individual converters. Furthermore, preliminary loss calculations[12]

point towards IGCT being an attractive valve for this category of converters.

1.2. IGCT Basics

1.2.1. Structure

GCT refers to the semiconductor press-pack component. The additional I in the abbreviation has its origin from the special fabrication which involves integrating gate unit in a very low inductance arrangement. IGCT is fabricated like a GTO and allows for unity gain turn-off of the thyristor structure.

3Also called MMC building block.

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8 Chapter 1. IGCT Introduction

In the vertical direction, it utilizes exclusive techniques such as buffer-layer and transparent emitter for loss reduction. The buffer-layer technology is implemented in many power semiconductors (GCTs, GTOs, power diodes and IGBTs). This technologies allows for 30% reduced thickness at the same forward voltage, thus, on-state losses and turn-off losses are reduced significantly. Typically, buffer-layer devices require larger trigger currents at turn-on, to avoid this problem transparent anode emitter technology is used. At turn-off this technology allows for equivalent performance as through conventional anode shorts. Additionally the structure allows for monolithic integration of an anti-parallel diode in the same wafer[8, 13, 14] (see Figure 1.1).

Diode GCT

n



p

n



n

_

n

p

p

Figure 1.1.: Schematic of the separation region of GCT and its diode part[13].

There are several categories of IGCTs available today[15]:

RC-IGCTs reverse conducting IGCTs with anti-parallel diode integrated in the same wafer⁴(seeFigure 1.2).

RB-IGCTs reverse blocking IGCTs

A-IGCTs asymmetric IGCTs that neither allows for reverse conduction or reverse blocking.

Figure 1.2.: RC-IGCT with its gate-unit mounted on the same circuit board[16].

4This thesis will focus mainly on this type.

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1.2. IGCT Basics 9

1.2.2. GCT Operation

1.2.2.1. Turn-on

In the turn-on mode, GCT behaves exactly like a thyristor (or a GTO). This operation principle can be understood by considering the equivalent two-transistor model given inFigure 1.4⁵. The p⁺n⁻p and n⁺pn⁻regions represent PNP and NPN transistors respectively. The anode of the GCT is connected to p⁺ region, which is the emitter of the PNP transistor. The collector of the PNP is connected to the gate of the NPN transistor and vice-versa, because ofn⁻ region neighboring the p region. The cathode of the GCT is connected to then⁺region, which is the emitter of the NPN transistor[13].

This two-transistor model has two stable states, ON and OFF, which are determined by the gate control. When a current is supplied to the gate to turn on the GCT, the gate current flows to the cathode This turns on the NPN transistor and its collector current will now flow from the anode through the J₁junction. TheJ₁ junction is the emitter of the PNP transistor, therefore, the collector current of the PNP is then the base current of the NPN. The two transistors are connected in positive feedback allowing for a self-sustaining state called latch-up. This state is reached because the large current flowing between the anode and cathode is able to inject enough carriers into the base regions to keep the transistors saturated without the need of continuous gate current flow[17, 18] (Figure 1.4 illustrates the different stages of the turn-on process using the two-transistor equivalent circuit). Typical turn-on time for a GCT is about ≈ 10µs[19].

A

G

 C

p nbuffer n^base pbase n^

J1 J2 J3

Figure 1.3.: One-dimensional structure of GCT.

G

Stage 1 Stage 2 Stage 3

G A

C

J1

J2

J3 G

A

C

J1

J2

J3

A

C

J1

J2

J3

Figure 1.4.: Two-transistor equivalent model of the GCT and its turn-on stages.

5This model can be derived from the basic one-dimensional structure inFigure 1.3.

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10 Chapter 1. IGCT Introduction

1.2.2.2. Turn-off

The turn-off mode, however, differs from that of a GTO. A GTO is turned off by negative current injection into the NPN base. Once the base current is reduced to a certain level, the collector current and hence the PNP base current reduces. This in turn, reduces the collector current of the PNP, leading to a further reduction in the base current of the NPN base[17]. This positive feedback process turns-off the GTO. The majority of the anode current flows out from the cathode and only a fraction of anode current flows out from the gate that is why the turn-off gainβ_{o f f} = I_A/I_G of the GTO is of the order 3 ∼ 5[19].

To turn-off a GCT, all the anode current is diverted to the gate, causing the cathode current to decrease rapidly. At the time cathode current decreases to a level close to zero, the minority carriers associated with the gate-cathode junction(J₃) are removed. At zero cathode current, minority carrier injection fromn⁺ side into the p base seizes[17]. Now, the GCT is an open base PNP transistor (Figure 1.5 illustrates the turn-off process using the two-transistor equivalent circuit). Typical turn-off time of a GCT is about ≈ 20µs [19].The time it takes for the current to commutate to the gate is of the order

∼ 1µs. This short time constricts the maximum allowable stray inductance of the gate unit. A typical value of the stray inductance of the gate-unit assumingV_G= 20V and d i

d t = 1000A/µs, is L_s< V_G

d i/d t = 20

1000· 1µs = 20nH (1.1)

This tight constraint on the stray inductance is one of the reasons why the gate unit is required to be integrated in a low-inductance arrangement with the GCT[13].

Since all the current flows from the anode to the gate the turn-off gainβ_{o f f} of the GCT is unity. The unity gain is advantageous because it significantly shortens the storage time⁶ compared to that of a GTO. Other advantages of unity gain are improvement in the SOA of the GCT and the abridged need for snubber circuits[13].

Stage 1 Stage 2 Stage 3

G A

C

J1

J2

J3 G

A

C

J1

J2 Open-base

J2

J3 G

A

C

J1

J2

J3

Figure 1.5.: Two-transistor equivalent model of the GCT and its turn-off stages.

6Time required to remove minority carriers from the p-base.

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1.3. IGCT Transient Waveform and Terminology 11

1.3. IGCT Transient Waveform and Terminology

The typical waveforms of the turn-on and turn-off transients are given inFigure 1.6. The terminology used in the figure is explained below:

V_D static on-state voltage, typically the dc-link capacitor voltage in a building block.

I_T is the constant forward load current.

I_{T GQM} is the maximum current that the IGCT can turn-off.

d i_T

d t is the rate of rise of the forward load current.

V_{D SP} is the first peak of the IGCT (seeFigure 1.6); depends upon its characteristics and stray inductances.

V_{D M} is the second peak of the IGCT (seeFigure 1.6); depends upon external clamp circuit.

CS is the electrical command signal sent to the gate unit (GU).

SF is the electrical status-feedback signal.

t_don is the turn-on delay time. Similarly,t_{d o f f} is the turn-off delay time.

t_{don SF} turn-on status-feedback time. Similarly,t_{d o f f SF} is the turn-off status feedback time.

t_r is the anode voltage fall time.

Figure 1.6.: Typical IGCT turn-on and turn-off waveforms[15].

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CHAPTER 2 Analytic Circuit Analysis

T

^ESTcircuit used for transient analysis is introduced. Later, a thorough theoretical analysis of the clamp circuit is covered; including optimizing the clamp circuit for a given DC capacitor voltage and maximum turn-off load current.

2.1. Circuit Introduction and Terminology

To test the turn-on and turn-off transients, and for finding suitable clamp circuit parameter values, a standard test circuit is used. This circuit can be found in the data sheets for IGCTs and is commonly used for switching events occurring in a Voltage Source Inverter (VSI), be it a 2-level or 3-level topology.

This circuit with all the stray inductances is given inFigure 2.1⁷including standard terminology for the components. The terminology is further explained below[15]:

C_{D CLink} is the dc-link capacitor, which is the main energy storage unit in a building block of a MMC.

L_i2 is the stray inductance of theC_{DC Li nk}.

F W D is the free-wheeling diode (FWD), which is the anti-parallel diode of the second IGCT, commonly found in a half-bridge topologies.

L_i1 is the choke inductance used for limitingd i_T/d t through the FWD.

R_s is the clamp resistor, it is used to dissipate the energy stored inL_i1. L_s is the stray inductance ofR_s.

C_CL is the clamp capacitor, used for clamping the over-voltage caused by the largeL_i1. V_CL is theC_{C L}voltage.

D_CL is the clamp diode. Used for conducting the energy stored inL_i1 toR_sandC_{C L}. D U T is the Device Under Testing (DUT), in our case, it is the IGCT.

L_CL is the overall stray inductance of the loopC_{C L}-D_{C L}-D U T -F W D.

L_load is the load inductance.

R_load is the load resistance.

7In essence, this circuit is a buck-converter[18].

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14 Chapter 2. Analytic Circuit Analysis

Rs

DCLink

C

DCL DUT

FWD

Lload

LCL 1

Li

Rload

Ls

2

Li

CCL

Figure 2.1.: Test circuit for the IGCT including all the modeled stray inductances.

2.2. Motivation for the Clamp Circuit

As mentioned previously, the circuit in Figure 2.1 is mainly used for studying turn-on and turn-off transients but it can also be used for finding suitable values for the clamp circuit parametersL_i1, R_s and C_{C L} using computer simulations. But then the question arises, why is there a need for a clamp circuit?

For simplicity let’s assume that the only stray inductance in the test circuit isL_{C L} and that the only components used inFigure 2.1 are C_{DC Li nk},D U T , F W D and L_{l oad}. CapacitorC_{DC Li nk}is charged to the levelV_D, IGCT isn’t conducting and the load currentI_T is free-wheeling through FWD. From our discussions insubsection 1.2.2, we know that the rate of turn-on of the IGCT isn’t controllable, hence, when we turn-on the IGCT the d i_T/d t is much larger than what the FWD is designed for. This limit forces us to use a choke inductorL_i1 to turn-off FWD at a rate that it can withstand. However, an inductor in series with the IGCT causesV_{D SP} to be unnecessarily large at IGCT turn-off and can inflict damage to the component. We need to clamp this over-voltage somehow, which is achieved by using a capacitor C_{C L}. Inductor L_i1 stores magnetic energy when the IGCT is conducting and this energy needs to be dissipated somewhere, otherwise it will oscillate betweenC_{C L}andL_i1. A clamping resistorR_s is required for dissipating this energy and a clamping diode D_{C L} is needed to make sure that current through the FWD during its turn-off is limited mainly byL_i1and not justL_{C L}(Figure 2.2 illustrates the the need for inclusion of components in steps). The inclusion of the clamp circuit increases the component count per building block, which is considered to be one of the disadvantages of using IGCT as valve.

2.3. Transient Analysis

2.3.1. Turn-on

In order to proceed with the analysis of the test circuit an understanding of the waveforms given in Figure 1.6 is needed at circuit level. We begin by considering the turn-on waveforms. Initially, let’s assume thatC_{C L} is charged to the same voltage asC_{DC Li nk} , no current is flowing through the clamp circuit components and the load current is free wheeling through FWD. Then at some time

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2.3. Transient Analysis 15

DCL

Lload Clamp over-voltage

CCL DCLink

C

DUT

FWD

1

Li

Rload

Damp oscillations/Burn energy

Fix FWD turn-off Rs

CCL DCLink

C

DUT

FWD

1

Li

Rload

Rs

CCL DCLink

C

DUT

FWD

1

Li

Rload Limit FWD turn-off di/dt

DCLink

C

DUT

FWD

Lload 1

Li

Rload DCLink

C

DUT

FWD

Lload

Rload

Figure 2.2.: Motivating clamp circuit. This figure illustrates the need for inclusion of components in steps in an IGCT circuit.

t₀, a command signal is sent to the IGCT to turn it on. After a short time delay, depending upon the characteristics of the IGCT, the voltage over it drops rapidly and once it has fallen to ≈ 0.1VD, the current commutation process starts. The current through FWD starts to drop at the rate that is mainly limited byL_i1 , while the current through the IGCT increases at the same rate. Figure 2.3 illustrates the commutation process. From the figure we find that:

i_{F W D}= i_T − i_u (2.1)

Commutation currenti_u increases from 0 to I_T at the same time i_{F W D} decreases from I_T to 0. The rise rate ofi_u (or equivalently, fall rate ofi_{F W D}) is determined by the largest inductance in the loop.

In this case, it isL_i1that is the largest inductance.

The current overshoot in the turn-on waveform of IGCT has to do with the reverse recovery current I_RMof FWD, which in turn depends to some extent on the characteristics of the diode and the fall rate ofd i_{F W D}/d t or equivalently rise rate of d i_u/d t through IGCT.

2.3.2. Turn-off

The turn-off process is more complex. Initially, let’s assume that the IGCT is turned on and is conducting full load current. Clamp capacitorC_{C L}is charged to the same voltage asC_{DC Li nk}so thatD_{C L} is turned off. At some timet₀, a command signal is sent to the IGCT to turn it off. Voltage over IGCT rises rapidly while the current drops at the rate limited only byL_{C L}. The peak voltageV_{D SP} defined inFigure 1.6 is dependent on the stray inductance L_{C L}, the forward recovery voltageV_{F R}ofD_{C L}and the characteristics of the IGCT[15]. Figure 2.4 illustrates the simplified commutation process. From the figure we find that:

i_{D U T} = i_T − i_u₁ (2.2)

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Rs

DCLink

C

DCL DUT

FWD

Lload

LCL 1

Li

Rload

CCL

iu

iT 2

Li

iFWD

Figure 2.3.: Redrawn test circuit during commutation from FWD to IGCT excluding some stray inductances for simplicity.

Commutation currenti_u

1 increases from 0 toI_T whilei_{D U T} decreases fromI_T to 0⁸. From the figure we can also notice that it is only L_{C L} that limits the d i/d t of the commutation current. Capacitor C_{C L}initially gets charged byi_u

1 and oncei_T has commutated over to FWD, the currents in the clamp circuit is governed by the equivalent parallel resonance circuit ofFigure 2.6⁹. Figure 2.5 illustrates the currents in the test circuit after commutation. The capacitor voltage appears over IGCT, sinceD_{C L} is conducting. The voltage overshootV_{D M} is the maximum charge voltage ofC_{C L}; the value ofV_{D M} depends highly on the chosenR_s,C_{C L},L_i1and stray inductances. OnceD_{C L}stops conducting, which occurs when i_L_i1 decreases at the rate that is governed by the parallel resonance circuit to zero, the voltage across the IGCT oscillates down toV_D. Capacitor voltage v_{C L} decays with a time constant τ = R_sC_{C L}until it reaches the same static value as the IGCT. The total time it takes for the capacitor to discharge toV_D depends on the chosenR_s,C_{C L},L_i1 and stray inductances.

2.4. Clamp Circuit Energy Losses

A huge choke inductor can always be found in IGCT circuits to limit the turn-offd i/d t of FWD and this inductor stores a significant amount of magnetic energy depending on the transient mode of the circuit. At IGCT turn-off, the stored magnetic energy from the on-state of the IGCT is given by:

E_R

s= I_T²L_i1

2 (2.3)

While, at IGCT turn-on , the stored magnetic energy from the reverse recovery of the FWD is given by:

E_R

s= I_RM² L_i1

2 (2.4)

8the effects of the IGCT tail current is neglected here since it is quite small and shouldn’t have any significant influence on the clamp circuit.

9Seesection 2.7 for an explanation of why the clamp circuit can be approximated as a parallel resonance circuit after the current commutation from IGCT to FWD.

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2.5. Selecting Choke InductorL_i1 17

Rs

DCLink

C

DCL ^DUT

FWD L^load LCL

1

Li

Rload

CCL

u1

i

T 2

Li

iDUT

Figure 2.4.: Redrawn test circuit during commutation from IGCT to FWD excluding some stray inductances for simplicity.

Rs

DCLink

C

DCL

DUT

FWD Lload

LCL 1

Li

Rload

CCL

iT 2

Li

1

Li

i

CCL

i

Rs

i

Figure 2.5.: Currents in the test circuit after commutation from IGCT to FWD.

Both of these energies are burned inR_s. This is true for a simple loss calculation model, however, according to[20] not all of this magnetic energy is burned in R_s some of it is burned in the semiconductors and some is restored back to theC_{DC Li nk}.

2.5. Selecting Choke Inductor L

_i1

To ensure safe turn-off of FWD,L_i1 needs to be dimensioned appropriately. To do that, we consider the circuit inFigure 2.3 again. Using Kirchoff’s Voltage Law (KVL) through the i_u current loop of the figure, we get:

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V_{D max}− Li2

d i_{T max} d t − Li1

d i_{T max} d t − LC L

d i_{T max}

d t = 0 ⇒ (2.5)

L_i1> −L_i2− L_{C L}+ V_{D max} d i_{T max}/d t

whereV_{D max}is the maximumC_{DC Li nk}voltage that will be used andd i_{T max}/d t is the maximum turn- off decay rate allowed for the FWD, this is usually specified in corresponding data sheets. As one can notice from the equation above. The value ofL_i1 is influenced only by stray inductances, maximum C_{DC Li nk} voltage and thed i_{T max}/d t of FWD. It is independent of the maximum turn-off current. As we’ll see later on in this chapter, the values ofR_sandC_{C L}are influenced by the turn-off current.

2.6. Selecting Clamping Diode

When selecting D_{C L} for the clamping circuit, the Forward Recovery V_{F R} of the diode needs to be taken into account. This over-voltage has a direct effect on the voltage across the IGCT during turn- off. This effect can be understood by having another look atFigure 2.4. In the figure, the effect of L_{C L} is an increase inV_{D SP} and since the commutation currenti_u1flows through bothL_{C L} and D_{C L} the voltage across D_{C L} also contributes to a increase inV_{D SP}. TheV_{F R} depends mainly on the voltage class, diameter of the wafer, the temperature and the forwardd i/d t .

In summary, D_{C L} should be chosen such that it has the smallestV_{F R} possible and at the same time should be of the same voltage class as the IGCT[15].

2.7. Selecting R

_s

and C

_{C L}

2.7.1. Analytical Relationships

Since the test circuit contains stray inductances and diodes it can be very difficult to find an analytic solution using circuit differential equations. One has to turn to simulations for a more reliable circuit behavior. It is however possible to find analytic relationships during IGCT turn-off to aid in dimen- sioningR_sandC_{C L}¹⁰by making a few assumptions[21]. From these assumptions we get the simplified circuit given inFigure 2.6.

The circuit in Figure 2.6 is actually a parallel resonance circuit. A thorough analysis of this circuit is given inAppendix A. We are interested in only a few characteristics of this circuit. According to Figure 1.6 and subsection 2.3.2, we are interested in the following specific characteristics:

• The timet_maxit takes forv_{C L}to reach its maximum value. This is equivalent to the time it takes for IGCT to reachV_{D M}.

• The maximum value ofC_{C L}voltageV_max, whereV_max= V_{D M}.

• The timet_{e nd} it takes for theL_{C L}current to become zero. This is relevant because we want to know the time it takes forD_{C L}to turn-off[15].

10The value ofL_i1is fully dependent on the current decay rated i_T/d t that the FWD is designed to withstand, as discussed insection 2.5.

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2.7. SelectingR_s andC_{C L} 19

R

s 1

L

i

C

CL

1

Li

i

CCL

i

Rs

i

v

CL

Figure 2.6.: The simplified clamp circuit based on the assumptions above.

All of the above mentioned characteristics can be extracted fromAppendix A, they are included here for convenience:

4C_{C L}R²_s

L_i1 > 1 (2.6)

t_max= 1 ω_d tan⁻¹

ω_d σ

(2.7)

V_max= i_T s L_i1

C_{C L}e⁻

ωdσ tan⁻¹_ωd

σ

(2.8) t_{e nd} = π

ω_d − tmax (2.9)

where,

ω_d =q

ω²_n− σ² (2.10)

ω_n= 1

pL_i1C_{C L} (2.11)

σ = 1

2R_sC_{C L} (2.12)

From the above relationships, we can deduce that t_max is independent of the turn-off voltage and current, it only depends onL_i1,C_{C L} andR_s. SinceL_i1is decided by the maximum current derivative as discussed insection 2.5 we only have two degrees of freedom here. The voltage V_max = V_{D M} is proportional to the turn-off current, by decreasingC_{C L}, we can decreaseV_{D M} at the cost of changing the values oft_maxandt_{e nd}.

2.7.2. Parameter Optimization

Clamp circuit parameter values,R_s andC_{C L} must be chosen with respect to some optimization constraints. In order to find a mathematical representation for these constraints, we need to identify the

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SOA limitations. During IGCT turn-off, we are interested in minimizingV_{D SP},V_{D M} andto f f −mi n, in order for the IGCT to meet the specified SOA[15]. The time to f f −mi nis given by:

to f f −mi n= t_{on−mi n}+ 2t_{B D} with: t_{on−mi n}≥ I_{T GQM}+ I_RM

d i_T/d t + t_{d yn} (2.13) The equations are derived usingFigure 2.7. These limitations are directly related to the clamp circuit.

However, there are also limitations due to the IGCT itself. This is due to the fact that the GCT needs some minimum time to reach its steady-state[15].

Figure 2.7.: Minimum dead timest_{on−mi n}andto f f −mi n[15]

To minimizeV_{D SP} the clamp stray inductanceL_{C L}needs to be minimized. We have little control over L_{C L} from electrical design point of view. However,V_{D M} depends almost entirely on the parameter values of the clamp circuit. Same is true forto f f −mi n; inEquation 2.13 the term ^I^{T GQM}_{d i} ^+I^RM

T/d t td yn in many cases andt_{d yn}also depends almost entirely on the clamp circuit[15].

To minimizeV_{D M}we first need to find a mathematical representation for it, this is given inEquation 2.8.

Next, sincet_{d yn}is directly related toto f f −mi n, we need to find a mathematical representation for it as

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2.7. SelectingR_s andC_{C L} 21

well. Timet_{d yn}as defined inFigure 2.7 can be considered as the sum of two intervals. The first interval t_{e nd} as given inEquation 2.9 and the second t_{C L}is the discharge time of the RC-circuit created byR_s andC_{C L}. This time interval is defined as:

t_{C L}= −τ ln

1 −P e r 100

(2.14) which is derived from the basic RC-circuit discharge relationship v_{C L} = v_{C L}(0) e⁻^τ^t , where τ = R_sC_{C L}andP e r is the percentage voltage drop. Thus, the mathematical representation of t_{d yn}is:

t_{d yn}= t_{e nd}+ t_{C L}= π ω_d − 1

ω_d tan⁻¹

ω_d σ

− τ ln

1 −P e r 100

(2.15) From NLP (non-linear programming) theory[22], we know that a general minimization problem can be written in the form:

mi nx f(x) (2.16)

subject to: g(x) ≤ 0

where x is a vector,f (x) is the function to be minimized¹¹and g(x) are the constraints. In our case,

x= R_s C_{C L} T

(2.17) f(x) = V_max= i_T

s L_i1 C_{C L}e⁻

σ(x) ωd (x)tan⁻¹

_{ωd (x)}

σ(x)

(2.18)

g(x) = (2.19)

=







1 −4C_{C L}R²_s L_i1 π

ω_d(x)− 1

ω_d(x)tan⁻¹

¨ω_d(x) σ (x)

«

− R_sC_{C L}ln

1 −^{P e r}₁₀₀

− t_{e nd Re q}







≤ 0 0

wheret_{e nd Re q} is the maximumt_{d yn}allowed. The problem inEquation 2.16 can be solved graphically or numerically. In the graphical method one can choose a data set of allowedR_sandC_{C L}and then plot a range of contours off (x) and g (x). A few contour values should be sufficient to get an approximate optimum. Since it was already mentioned that simulations need to be conducted in order to include the effects of stray inductances, an approximate optimum is all that may be required. Furthermore, it is much easier to comprehend if the optimum is a global or a local minimum. A program with user friendly graphical user interface (GUI) is developed to apply the graphical method¹². In the numerical method Matlab’sfmincon function can be used to solve the problem. This function is specially designed to solve non-linear optimization problems written in this form. There are however some disadvantages with this method:

• An initial guess is required for the program to run.

• The problem to be solved usingfmincon needs to be convex in order to guarantee a global minimum solution.

11also called an objective function.

12seechapter 4 for an elaborate example of using this program.

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2.7.3. Minimum Transient Time Limitation

It can be of interest to know the minimum value oft_{d yn}that can theoretically be achieved for a given IGCT with a given maximum peak repetitive voltage (V_{D RM}) and a specific load currenti_T, sincet_{d yn} directly affects t_{on−mi n} and to f f −mi n as discussed in the previous section. One way to extract this value is to considerEquation 2.17, Equation 2.18, Equation 2.19 and interchange the last constraint in Equation 2.19 with the objective function of Equation 2.18; t_{e nd Re q} is removed and instead we have a V_{maxRe q}= V_{D RM}. So now the new optimization functions are:

x= R_s C_{C L} T

(2.20) f (x) = t_{e nd}+ t_{C L}= t_{d yn}= π

ω_d(x)− 1

ω_d(x)tan⁻¹

¨ω_d(x) σ (x)

«

− RsC_{C L}ln

1 −P e r 100

(2.21)

g(x) =







1 −4C_{C L}R²_s L_i1 i_Ts L_i1

C_{C L}e⁻

σ(x)

ωd (x)tan⁻¹_{ωd (x)}

σ(x)

− V_{maxRe q}







≤ 0 0

(2.22)

This problem can be solved using the graphical method. However, this method is very sensitive to the initial guess; there are a lot of local minimum candidates and it can be very difficult to find an initial guess that gives the optimum solution. A recommended method is to use the graphical one as mentioned in the previous subsection.

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CHAPTER 3 Circuit simulations

A

simulation model for the test circuit used in this thesis is introduced. Next, the theoretical analysis ofchapter 2 is confirmed including the effects of stray inductances. Lastly, parameter sweeps are used to create a table that aids in comprehending the effects of changing parameter values on the switching transients.

3.1. Selecting Simulation Program

Once a theoretical base has been established one needs to confirm theory with practice. The cheapest alternative is to use computer simulations. A first step is to find an appropriate program to conduct simulations in. A study was conducted to find a suitable program for simulations of the test circuit.

The results of the study is summarized inTable 3.1.

The choice of the program was based on the following criteria:

• Familiarity with the program is recommended but not a necessary condition.

• The program should allow for running multiple simulations with different component values, also called Parameter Sweep.

• The program should have support for transient analysis.

• It is highly desirable for the program to be widely accepted for power electronics simulations.

With this characteristic, simulations will be reliable and consistent.

Taking the above criteria into consideration we can conclude that Pspice^R is the suitable candidate.

Table 3.1.: Summary of the survey of suitable simulation programs. Orange marked header represents the program of choice.

Matlab^R Pspice^R Microcap^R Simplorer^R PSCAD^R

Adv- antages

Disadv- antages

Adv- antages

Disadv- antages

Adv- antages

Disadv- antages

Adv- antages

Disadv- antages

Adv- antages

Disadv- antages Easy to

plot graphs and set axis scaling

using code.

First simulation

in SimPower

Systems toolbox gave in- consistent

results.

First simulation gave results that were deci- pher- able and consis-

tent.

Not much control over the

style of plotting and scaling of

axis.

Is spice based and easier to use than Pspice^R.

Hierarchial models are not possible to create

in Micro- cap.

Contains a lot of features that both Matlab^R

and Pspice^R provide.

Model for IGCT isn’t available.

Unfamiliar with this program.

23

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24 Chapter 3. Circuit simulations

Possible to run simulations in a for-loop

and change

more than on parameter every itera- tions.

Is meant for system

analysis, only simple power electron-

ics models

are available.

Parameter sweep can be used to iterate values of components, is almost as pow- erful as Matlab^R.

There are no models available for power electron-

ics components in Pspice^R library.

Easy to change plotting style and scaling of axis.

Possible to pause simulation and change

values of compo-

nents.

Meant for system analysis and not for detailed analysis of

circuit compo-

nents.

There is a possi- bility to check curve forms in

real time using

“Scope”

in simulink

library.

Not possible to pause simulation

and change

values.

Many IEEE re- searchers

have used P-spice for creating models

for power

electronics compo-

nents.

Not possible to pause the simulation

and change

values.

Other advan-

tages are similar

to Pspice^R.

Other disadvantages are similar to Pspice^R.

Simulations in real

time are pos-

sible.

Not as popular

as Pspice^R

for transient analysis of

small to medium electrical

circuits.

Familiar with this program.

Has a reputa-

tion of being a

good tool for

transient analysis of small- medium sized electri-

cal circuits.

Real time simulation results are

not possible.

There is no need

for special licenses to create

new models.

Familiar with this program.

Special license is needed

for creating

new models.

3.2. Modeling Test Circuit

Once a simulation platform has been selected a suitable simulation model needs to be considered. The main purpose of the simulations is to confirm the theoretical analysis ofchapter 2 and also examine the effects of stray inductances inFigure 2.1. For this category of simulations, modeling the exact turn-off behavior of the IGCT isn’t of utmost importance. Thus, IGCT can be modeled as an ideal switch with defined turn-on and turn-off transient times[15].

3.2.1. GCT Model

In Pspice^R an ideal switch with editable model is calledSbreak. The editable parameters are R_on, R_{o f f},V_onandV_{o f f}. The total voltage across IGCT during conduction is given by[18]:

IGCT Transient Analysis and Clamp Circuit Design for VSC valves

IGCT Transient Analysis and Clamp Circuit Design for VSC valves

SANCHIT SINGH

IGCT Transient Analysis and Clamp Circuit Design for VSC valves

Author Sanchit Singh

XR-EE-E2C 2012:014

Abstract

I

Sammanfattning

I

Acknowledgments

Table of Contents

Introduction

I

Purpose

Scope

CHAPTER 1

IGCT Introduction

T

1.1. Considering IGCT as Valve

1.2. IGCT Basics

n

n

n

n

1.3. IGCT Transient Waveform and Terminology

CHAPTER 2

Analytic Circuit Analysis

T

2.1. Circuit Introduction and Terminology

2.2. Motivation for the Clamp Circuit

2.3. Transient Analysis

2.4. Clamp Circuit Energy Losses

i

i

2.5. Selecting Choke Inductor L

2.6. Selecting Clamping Diode

2.7. Selecting R

and C

R

L

C

i

i

i

v

CHAPTER 3

Circuit simulations

A

3.1. Selecting Simulation Program

3.2. Modeling Test Circuit