Event counter:

Event counter:

Problem formulation

• Cross talk

– Close integration of analog and digital parts – Several thousands of pixels

– The counter is the most complex digital component

Discriminator

Counter Pre-amplifier

Pulse shaper

Detector Comaprators

Analog

Digital

Implementation

alternatives (N-counter)

=1

S

S

event

Linear Feedback Shift Register (LSFR)

+ Readout comes for free

± Synchronous

- C

=N(C

+p

·C

)

Asynchronous counter

event ...

D D D D

+ C

= (C

+C

) 

2

~(C

+C

)

± Asynchronous

- Expensive readout

Idea

 





j j clk

ff

eff C C C C

C   ^  ^ 





Event counter

D_out

Pre-scalar

D_out Event counter

I) II)

-bits

-bits p-bits

p



 

Decrease in accuracy Counter architecture

235413±251 235400±251

events=D

events=D

*2

Relation between LFSR width and SNR

 

 





 

 





 

 





 

 





 





 







 





1

10 10 SNR

2

10 10 12 1

log

deg

SNRout

p





Relation between

C _eff and SNR

Current and di/dt for the

hybrid counter

Results

Table 1. Comparisons between power supply current and di/dt for a type I and type II counter.

Type I Type II Ratio (I/II)

Max current 13.3 mA 2.4 mA 5.54

Mean current 2.5 mA 0.66 mA 3.79

Mean current peaks 6.5 mA 0.91 mA 7.21

Conclusion

• The counter architecture decrease the current peaks by a factor of 7

– Power consumption is 4 times lower – Readout is almost 2 times faster

• The design rules enables the designer to weigh the

SNR value against the digital switching