Stand-alone Data Acquisition Board for optical links

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IT 15036

Examensarbete 30 hp Juli 2015

Stand-alone Data Acquisition Board for optical links

Georgios Ntounas

Panagiotis Stamatakopoulos

Institutionen för informationsteknologi

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Teknisk- naturvetenskaplig fakultet UTH-enheten

Besöksadress:

Ångströmlaboratoriet Lägerhyddsvägen 1 Hus 4, Plan 0 Postadress:

Box 536 751 21 Uppsala Telefon:

018 – 471 30 03 Telefax:

018 – 471 30 00 Hemsida:

http://www.teknat.uu.se/student

Abstract

Stand-alone Data Acquisition Board for optical links

Georgios Ntounas Panagiotis Stamatakopoulos

Data acquisition is one of the most important processes used in order to gather and digitize information. The purpose of this project is the design of a Stand-alone Data Acquisition Board specialized for optical communication. Printed Circuit Board (PCB) design is one of the most demanding fields in electronics system design, especially when it includes high speed signals such us the connection of a Double Data Rate RAM memory. Throughout this report we present in detail the steps that we followed so as to create a complete PCB design. The very first step in this process is to acquire the necessary background that one need to understand in order to create PCBs, background that is briefly covered in the report. In addition, there is a detailed description of the criteria based on which we chose the components of the board, as well as of the interconnection of each component. Finally throughout the report we present some of the basic rules that PCB designers need to follow in order to ensure signal integrity, which is vital for the proper operation of the system.

Examinator: Wang Yi

Ämnesgranskare: Leif Gustafsson Handledare: Pawel Marciniewski

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Acknowledgements

We would like to express our sincere thanks towards our supervisor Pawel Marciniewski and our reviewer Leif Gustafsson. It is certain that without their experience and their guidance we would not be able to complete the purpose of this project.

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List of Figures

1.1 3D Model of the final Layout. . . 7

2.1 Through Hole Components . . . 8

2.2 Surface-mount components. . . 8

2.3 Multilayer Board. . . 8

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2.4 Zynq-7000 Architecture . . . 11

2.5 The Zynq Processing System . . . 11

3.1 ZedBoard . . . 15

3.2 PicoZed . . . 16

3.3 Mezzanine . . . 17

5.1 High Level Overview . . . 18

6.1 Ethernet Transceiver Block Diagram . . . 19

6.2 USB PHY Block Diagram . . . 21

6.3 Micro SD Card Block Diagram . . . 23

6.4 SFP Block Diagram . . . 25

6.5 HDMI LC filters . . . 30

6.6 Block Diagram of Basic Power Architecture . . . 32

6.7 Current cosumption in Xilinx Power Estimator . . . 33

6.8 LTM4644 Schematic Diagram . . . 35

6.9 LMZ31710 RVQ 42 Schematic Diagram . . . 36

6.10 MGT Regulators Schematic Diagram . . . 37

6.11 Complete Power Architectire Block Diagram . . . 37

6.12 Ramp-up Output Voltage Response . . . 39

6.13 Resistors for Boot Mode Selection . . . 40

7.1 Reflection of a single pulse . . . 44

7.2 Diﬀerential signals connected deep in XC7Z030 chip . . . 45

7.3 Zcalc Software . . . 46

7.4 The layer stack manager interface from Altium . . . 46

7.5 The thermal pad in 2D and 3D view . . . 47

7.6 Layers 3, 4 and 5 underneath the DDR . . . 49

7.7 Routes of the DDR in diﬀerent layers with length matching . . . 50

7.8 Two test points and one of the two fiducials . . . 51

7.9 A mounting Pad . . . 52

7.10 The ROM configuration resistors footprint . . . 53

7.11 Power and DONE LED . . . 53

7.12 The clear ground plane for the ADC . . . 54

7.13 The top layer is on the left, the right is layer five . . . 55

8.1 3D view of the final design . . . 57

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List of Tables

1 List of I/O Peripheral Interfaces . . . 12

2 Zynq-7000 family members . . . 12

3 XC7Z030-1FBG484C Specification . . . 13

4 Ethernet Pin Assignment . . . 20

5 USB Pin Assignment . . . 21

6 DDR3 Memory Pin Assignment . . . 22

7 SD Card Pin Assignment . . . 24

8 GTX Transmit and Receive Diﬀerential Signals . . . 25

9 Control Signals of SFP/SFP+ Modules . . . 26

10 Nim Modules Pin Assignment . . . 27

11 HDMI Transmitter Pin Assignment . . . 28

12 HDMI Transmitter Power Domains . . . 29

13 Zynq-7000 Power Supply Voltages . . . 31

14 Component Supply Voltages . . . 31

15 XC7Z030 Current Consumption per Rail . . . 33

16 Boot Mode Pins . . . 40

17 Flash Memory Pin Assignment . . . 41

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1 Introduction

Data acquisition is one of the most important processes in experimental physics gathering and digitizing information on physical phenomena. ”In experimental and applied particle physics, nuclear physics, and nuclear engineering, a particle detector, also known as a radiation detector, is a device used to detect, track, and/or identify high-energy particles, such as those produced by nuclear decay, cosmic radiation, or reactions in a particle accelerator” [1]. Particle detectors deliver a vast amount of data, which after a quick in-flight pre-selection needs to be collected on discs for further analysis. Large detectors, such as the PANDA, under construction at GSI, Darmstadt, Germany, consist of many detector subsystems, responsible for data streaming. Hence, multiple data sources, such as digitizers, are distributed over a large area of the detector system.

Currently constructed or available data collection systems, which, as we mentioned, are subsystems responsible for the collection and stream of data in particle detectors, are suited for large scale experiments, customized to unique environ- ments of diverse laboratories and as a result they are not easily portable. It should also be noted that data collection using optical links has become increasingly pop- ular, recently, due to their high bandwidth and mechanical flexibility. Considering all the above, an easy to use optical data collector, which can serve communication over Ethernet for a small experiment or test, would be much appreciated.

The purpose of this project is the design and construction of a small Data Acquisition Board, capable of bi-directional communication, with 4 front-end data converters over optical links. The interface will act as a data collector and server for a PC, connected over Gigabit Ethernet or USB. The interface will feature a Xilinx ZYNC FPGA with a dual core ARM9 embedded system running Linux.

In case more complex data processing or extended data storage space is required, the board will support up to 512 MB RAM and a Micro SD slot. In the following figure, we present a 3D model of the final layout of the board:

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Figure 1.1: 3D Model of the final Layout.

2 Background

”Printed circuit boards (PCBs) are electrical systems, with electrical properties as complicated as the discrete components and devices mounted to them” [2]. The design of modern electronic systems requires the interconnection of multiple devices with a large number of inputs and outputs, on the smallest possible footprint. In this part of the report we will mention some of the most important background information that the reader needs, in order to cope with the rest of the document, as well as some of the basic terminology that is used.

At the beginning of PCB design technology, the interconnection of components was made only on one surface of the board. Thru-hole components were used, with pins intended to be inserted into plated holes in the PCB, while the copper tracks were routed on the other side of the board. In figure 2.1a we can see the top view of a very simple circuit, while in figure 2.1b the respective side view, where the component pins are plated into the PCB.

The construction of surface mount components enabled us to place them on both surfaces, reducing significantly the size of the board. The interconnection of components that are placed on diﬀerent layers (top and bottom surface) is being implemented using vias, which are plated holes that allow signals to pass through the board [3]. In figure 2.2 we can see two capacitors on diﬀerent layers, connected through a via:

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(a) Top View (b) Side View Figure 2.1: Through Hole Components

Figure 2.2: Surface-mount components.

The demand for more complicated systems in conjunction with the requirement for reduced board size led to multilayer boards, which contributed to the design of even denser boards. As can be seen in the following picture, there are multiple internal layers, in order to connect components through vias.

Figure 2.3: Multilayer Board.

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2.1 Electromagnetic Interference and Compatibility

PCB design is a major field of electronics design, in which both the high speed signals and compact size requirements have resulted in numerous rules that must be followed, in order to ensure signal integrity. As we know from basic physics, a changing current in one circuit may produce an induced current in another [4].

Even a changing current that flows through a conductor (or a trace) can generate current in a second nearby conductor (or trace). The unintentionally produced current, caused by electromagnetic induction, is only one example of unintentionally released electromagnetic energy that can aﬀect electronic circuits. Phenomena as the above, of disturbance due to electromagnetic induction or radiation, are called Electromagnetic Interference (EMI) [5].

Besides induced and radiated noise, an electronic system may suﬀer from unintended changes in signals that pass through the wires. These changes may aﬀect the performance of another part of the system. This kind of emissions that pass through the conductors of a device and the rules that must be followed in order to eliminate them, are referred to as Electromagnetic Compatibility (EMC) [6].

There are several rules that PCB designers follow, in order to prevent the interference in electronic systems [7]. Especially in our board, which consists of a plethora of high speed signals, such as Double Data Rate communication, the demand for reduced EMI/EMC is vital for the proper operation of the system.

Based on the rules that designers follow, the actual placement of the components, as well as the routing of the layout is carried out, thus it is critical to mention the ones that influenced the Data Acquisition Board’s design most.

2.1.1 Decoupling Capacitors

A major concept in PCB design is decoupling. Power supplies, which are responsible for providing power to the board, introduce some ripple at their output and as a result they cannot supply the components with absolute steady voltages. These unintended changes in voltage (noise) may aﬀect the normal operation of integrated circuits. The high switching frequency of circuits, resulting in an abrupt draw of current from the rail and as a consequence a voltage drop on it, is also a factor that creates noise on the power rails. In order to prevent these phenomena, decoupling capacitors are used, which filter out the high frequency noise, by

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providing electric charge. Decoupling capacitors should be placed as close to the power pins of a chip as possible, so as to minimize current loops (the path from power to ground). Whenever there is a voltage drop on a power rail, decoupling capacitors ”release” their electric charge, filtering out the created noise. Thus, it can be thought as a tiny battery, placed really close to the power pins, able to provide with a short amount of charge, whenever there is a voltage drop on the rail.

2.1.2 Ground System

Ground is the return path of the current. A good grounding system is valuable for proper system functionality. Many designers concentrate on how the current is supplied to the circuits, underestimating the importance of its return path to ground. In order to eliminate electromagnetic emissions, a good grounding system should provide low inductance, which is achieved by maximizing the ground area [8]. For this reason, most of the documentation suggests to spend an entire layer for ground, which is not always feasible.

Another important rule, when it comes to ground, is to isolate all sensitive analog signals from the ”noisy” digital ones. The most eﬃcient technique, in order to achieve that, is to partition the design into sections, routing all the analog signals on the analog part and the digital ones on the respective digital part [9]. A critical point to mention is that the two planes should be connected at a specific location on the board, which is usually under the Analog-to-Digital converter, since it has pins connected both to the analog and the digital plane.

2.2 Zynq-7000 All Programmable System-on-Chip (SoC)

The most important component of the board is a Zynq-7000 All Programmable System-on-Chip (SoC) from Xilinx, thus it is worth mentioning some related background information about it. These Integrated Circuits (IC) combine an ARM dual Cortex-A9 processor system with Xilinx 7-series FPGA. Thus, they oﬀer the flexibility of an FPGA along with the processing power of an ASIC [10]. The internal ZYNQ architecture comprises two parts: the Programmable Logic (PL) equivalent to an FPGA and the Processing System (PS), which is the ARM processor [10].

They can be used independently, powering down the part that is not used, or to-

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gether, exploiting the Advanced eXtensible Interface (AXI) industry standard to interconnect them.

Figure 2.4: Zynq-7000 Architecture

We need to highlight that the PS includes not only the ARM processor but a collection of processing resources, composing the Application Processing Unit (APU), as well as memory interfaces and peripheral interfaces. In figure 2.5 we present a block diagram of the PS.

Figure 2.5: The Zynq Processing System

As illustrated, there is a number of external interfaces that can communicate

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directly with the PS using the Multiplexed Input/Output (MIO) pins [10]. These pins form separate banks on the ZYNQ (the PS MIO Banks), on which we are going to connect the USB and Ethernet communication, the SD card as well as the flash and DDR3 memories. In the following table we can see a list of all I/O peripheral interfaces.

I/O Interface Description

SPI (x2) Serial Peripheral Interface I2C (x2) I2C bus

CAN (x2) Controller Area Network

UART (x2) Universal Asynchronous Receiver Transmitter GPIO General Purpose Input/Output

SD (x2) For interfacing with SD card memory USB (x2) Universal Serial Bus

GigE (x2) Ethernet

Table 1: List of I/O Peripheral Interfaces

The I/O Banks are divided into PS and PL Banks. PS Banks are groups of I/Os that are connected directly to the processing system, while the respective PL are those groups of pins connected to the FPGA fabric. The PL Banks are further divided into High Range (HR) and High Performance (HP) Banks. The HR are compatible with a wide variety of I/O standards (up to 3.3Volts), while the HP are used for high-speed interfaces.

The Zynq-7000 family comprises several general purpose devices, with diﬀerent features and characteristics. Table 2 summarizes some of their basic characteristics, based on which we can choose the appropriate device for our project.

Z-7010 Z-7015 Z-7020 Z-7030 Z-7045 Z-7100

Processor Dual core ARM Cortex-A9 with NEON and FPU extensions

Max. processor

clock frequency 866MHz 1GHz

Programmable,Logic Artix-7 Kintex-7

No. of Flip-Flops 35.200 96.400 106.400 157.200 437.200 554.800

No. of 6-input LUTs 17.600 46.200 53.200 78.600 218.600 277.400

No. of 36Kb Block,RAMs 60 95 140 265 545 755

No. of DSP48 slices

(18x25 bit) 80 160 220 400 900 2020

No. of SelectIO,

Input/Output,Blocks HR: 100,HP: 0 HR: 150,HP: 0 HR: 200,HP: 0 HR: 100,HP: 150 HR: 212,HP: 150 HR: 250,HP: 150

No. of PCI Express Blocks - 4 - 4 8 8

No. of serial transceivers - 4 - 4 8 or 16 16

Serial transceivers

maximum rate - 6.25Gbps - 6.6Gbps/,12.5Gbps 6.6Gbps/,12.5Gbps 10.3Gbps

Table 2: Zynq-7000 family members

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As we said in the introductory part, the board should be specialized for optical communication. In order to support optical links, the SoC should be equipped with a number of serial transceivers, which are the de facto interfaces for applications with optical communication. Moreover, since our system needs to deliver a vast amount of data and implement a data acquisition process on it, it should be powerful enough to meet the expectations. According to the table 2, Z-7030, Z- 7045 and Z-7100 provide both serial transceivers for optical links and suﬃcient resources (No. of flip-flops, No. of Input/Output Blocks) for the purpose of our project. Another important factor to take into account is the price of the above devices, with Z-7030 being the least expensive. Therefore, we decided to use a Z-7030 SoC and more specifically an XC7Z030-1FBG484C SoC, which has the following characteristics, in addition to those on table 2:

Package Type BGA

Size (mm) 23 x 23

Pitch (mm) 1.0

Maximum SelectIO Resources 163

Maximum PS I/Os 128

GTX Channel by Package 4

PS I/O 128

PL I/O HR:148

HP:92 Maximum Frequency 667MHz

Table 3: XC7Z030-1FBG484C Specification

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3 Related Work

There is a wide variety of products on the market that are designed for data collection over optical links. However, most of these systems are intended to be extensions of a motherboard (daughterboards), which results in transferring bulky equipment at the place of the experiment. On the other hand, there is a plethora of standalone development boards that can be used as examples for our project, even if they do not provide optical communication. In this section we talk about a number of boards that are available on the market and we used them as guidelines for the design of our system. There are several reasons that made us to follow this procedure. Firstly, we need to identify how major companies, such as Xilinx, address this kind of projects. Secondly, since we have already selected the SoC that can cope with the requirements of our project, we would like to select compatible I/O peripherals (Ethernet transceivers, SD card etc.). Finally, when it comes to software debugging and testing, it is really important to run our test code on an approved board that has as much similarity as possible with the one that we design (similar SoC, peripherals etc.). For all the above, we studied thoroughly the design of ZedBoard, PicoZed and ZC706, all of which are evaluation boards constructed by Xilinx, which helped us both on selecting the appropriate peripheral components and on creating the interconnection with the SoC.

3.1 ZedBoard

ZedBoard is a low-cost evaluation and development board, based on Xilinx Zynq- 7000 All Programmable SoC [11]. It includes all the necessary components in order to design an Android, Linux and Windows based system or a Real-Time Operating System for deterministic applications. ZedBoard has been used for a wide variety of applications such as video processing, software acceleration, motor control, Android/Linux/RTOS development and others [12]. The main reason that led us to study ZedBoards design, although it does not contain the desired SoC (they belong in the same family though), is that most of its peripherals are available on the market and as a result we could buy them for our construction. Furthermore, its price and its availability on the market make ZedBoard the optimal choice, in order to use it as a test board for the software debugging procedure. Conse- quently, we used it mainly as a guideline in selecting the peripheral interfaces for

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our system and the way they are connected with a Zynq-7000 SoC.

Figure 3.1: ZedBoard

3.2 PicoZed

PicoZed is a highly flexible, low cost development board also based on Xilinx Zynq-7000 All Programmable SoC [13]. It is available with a variety of SoCs, from which the designers can choose the one that fits better with their application. More specifically, PicoZed is available with XC7Z010, XC7Z015, XC7Z020 or XC7Z030 Zynq-7000 AP SoC devices. As we previously mentioned, the SoC device that can meet the requirements of our project is the XC7Z030, therefore we need to investigate PicoZeds design along with Zynq-7000s documentation, in order to assure the proper interconnection of the SoC. PicoZed is mainly used for applications in the field of industrial automation, motor control and in the design of Software-defined Radios [13]. We need to emphasize on the fact that, although PicoZed contains the desired SoC device, the majority of its peripherals are not available on the market. As a result, we decided to use most of the peripherals of

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the ZedBoard platform and compare its schematic diagrams with those of PicoZed, so as to identify what kind of changes we should do to properly connect them with the chosen SoC.

Figure 3.2: PicoZed

3.3 Trigger/DAQ Mezzanine

Both PicoZed and ZedBoard are standalone devices, equipped with several interfaces making them extremely powerful and flexible modules. On the other hand, they do not contain optical links which are central components for our project.

Therefore, we need to examine another board that features optical communication.

As we have mentioned several times, there is not a standalone system designed for optical communication, but there are several daughterboards that are intended to extend the circuitry of another board [14]. An example is the Trigger/DAQ Mezzanine board, constructed in Uppsala University, which we used as a guide, mainly to connect the optical links. As can be seen in figure 3.3 , it contains 16 optical links while at the same time SAMTEC-QTH-090-D external connectors are used to connect the device with another board. Finally, we need to highlight that Trigger/DAQ Mezzanine is not designed based on a SoC from the Zynq-7000 family, rather it uses a Xilinx Virtex-5 FPGA.

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Figure 3.3: Mezzanine

4 Tools

Throughout our project we have used Altium designer [15] which is a powerful electronic computer-assisted design (ECAD) software. Altium is a fairly easy tool which depending on the needs of the project can go into great depth on design rules and features that provide great assistance to the designer, everything with detailed documentation and examples. Altium was issued to Uppsala University under a student license which had access to most of its features. It is also

5 System Overview

Before proceeding with the analysis of the individual components, it is important to present a high level overview of the system. As we mentioned in the introduction, the heart of the system is the XC7Z030-1FBG484C SoC, which combines an ARM processor along with Xilinx 7-series FPGA. In order to achieve the desired optical communication, the board features four front-end data converters over optical links, along with the NIM standard, which provides the means of communication with the front end system. The data is transferred from the board to a PC via Gigabit Ethernet or USB. For the Ethernet communication we use a Marvell’s 88E1518 Gigabit Ethernet transceiver, while the USB communication is being implemented using SMSC’s USB3320 transceiver. In case more complex data

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processing or extended data storage space is required, it also supports up to 512 MB of RAM memory and a Micro SD slot. Finally, we decided to include an HDMI transmitter, in order to support a video interface. For that we use the ADV7511 transmitter from Analog Devices, which is used for a broad range of applications.

In the following figure, we can see a high level block diagram of the system:

Figure 5.1: High Level Overview

6 Component Interconnection

In this part of the report we present some of the basic components of the board, besides the Zynq SoC that we have already talked about. For each component we specify some of its basic characteristics along with information regarding their interconnection with the X7C030 SoC. For some devices we need also to discuss the process we followed in order to choose them.

6.1 10/100/1000 Ethernet Transceiver

The primary function of the system we design is to collect data through optical links and, after a data acquisition process, send them to a PC. The data transfer will be performed via USB interface or Gigabit Ethernet. Ethernet communication is going to be implemented using Marvells 88E1518 Gigabit Ethernet transceiver.

Following the discussion of the previous section, the Gigabit Ethernet transmitter is connected directly to the PS module, through the PS MIO Bank 501. 88E1518

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requires an external oscillator, connected on the XTAL IN and XTAL OUT pins, therefore we use a 25MHz clock by FOX Electronics. The transmitter must be supplied with three diﬀerent power supply voltages, i.e. 3.3, 1.8 and 1.0 Volts, which must be filtered out using ferrites and decoupling capacitors, in order to reduce the ripple from the power rails. Finally, the RJ-45 connector is a W¨urth Electronics 7498111120R with integrated magnetics. The following figure depicts the connection of the 88E1518 transceiver with the SoC and the RJ-45 external connectort, while in table 4 we specify the respective pin assignment:

Figure 6.1: Ethernet Transceiver Block Diagram

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Signal Name Description Zynq pin MIO 88E1510 pin

ETH-RXCK Receive Clock G12 22 40

ETH-RXCTL Receive Control A7 27 37

ETH-RXD[3:0] Receive Data

RXD0: B10 RXD1: F11 RXD2: B9 RXD3: G9

RXD0: 23 RXD1: 24 RXD2: 25 RXD3: 26

38 39 41 42

ETH-TXCK Transmit Clock G10 16 47

ETH-TXCTL Transmit

Control A9 21 2

ETH-TXD[3:0] Transmit Data

TXD0: A10 TXD1: H11 TXD2: A11 TXD3: H10

TXD0: 17 TXD1: 18 TXD2: 19 TXD3: 20

44 45 48 1 ETH-MDIO Management

Data C7 53 5

ETH-MDC Management Clock D8 52 4

Table 4: Ethernet Pin Assignment

6.2 USB Transceiver

In order to transfer data to another computer we have implemented a USB device interface. The transceiver we are using is the USB3320 from SMSC that supports high-speed 480Mbs and ULPI (Low Pin) interface and comes in a QFN package 5x5 mm. The level of the output signals of this component are 1.8 Volt and are connected to the MIO bank. Additionally an external clock is required to drive the ULPI clock, a 26MHz oscillator from TXC is used. Finally the USB connector is a type B connector from W¨urth Electronics 629105150521.

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Figure 6.2: USB PHY Block Diagram

Signal Name Description XC7Z030 Pin MIO Bank (501) TUSB1210 Pin

USB D[7:0] Data

E6 B8 E4 A5 H8 E7 B7 D5

32 33 34 35 28 37 38 39

3 4 5 6 7 9 10 13 USB DIR Direction

signal C11 29 31

USB STP Stop

Signal F9 30 29

USB NXT Next

output signal A6 31 2

USB CLK 60MHz

ULPI clock C10 40 26

Table 5: USB Pin Assignment

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6.3 DDR3 Memory

In case complex data processing is required, the board will support up to 512 MB of Random Access Memory (RAM). More specifically, it includes two MT41K128M16JT- 125 memory chips by Micron. This is a 2Gbit DDR3 SDRAM chip with double data rate architecture for high transfer rates [16]. It supports 1066 MT/s (mil- lion transfers per second) and its size is 14x8mm in a 96-Balls FBGA package.

The X7C030 chip contains a dedicated bank for memory communication, which is connected to the PS module via the PS BANK 502. The PS has a dynamic memory controller, which is compatible with DDR3 memory in order to support high eﬃciency memory communication. Table 6 presents the connections between the PS Bank and the memory chips.

Signal Name Description XC7Z030 Pin DDR3 pin

DDR3-A[14:0] Address PS DDR A[14:0] 502 A[13:0], T7 DDR3-BA[2:0] Bank Address PS DDR BA[14:0] 502 BA[2:0]

DDR3-CLK0 P Diﬀerential Clock Input H17 J7

DDR3-CLK0 N Diﬀerential Clock Input G17 K7

DDR3-CKE0 Clock Enable M15 K9

DDR3-S0 Chip Select K16 L2

DDR3-DM[3:0] Input Data Mask PS DDR DM[3:0] 502 LDM/UDM,x2

DDR3-ODT0 On-die Termination N16 K1

DDR3-RAS Row Address Select M17 J3

DDR3-CAS Column Address Select M18 K3

DDR3-WE Write Enable L16 L3

DDR3-RESET Reset E16 T2

DDR3-D[31:0] Data Input/Output PS DDR DQ[31:0] 502 DQ pins DDR3-DQS[3:0] P I/O Diﬀerential Data Strobe PS DDR DQS P[3:0] 502 UDQS/LDQS DDR3-DQS[3:0] N I/O Diﬀerential Data Strobe PS DDR DQS N[3:0] 502 UDQS#/LDQS#

DDR-VRP I/O Used to calibrate

input termination K17 N/A

DDR-VRN I/O Used to calibrate

input termination K18 N/A

DDRVREF I/O Reference voltage PS DDR VREF[1:0] 502 M8, H1

Table 6: DDR3 Memory Pin Assignment

According to documentation, the ZQ input (external reference for output calibration) of each memory chip should be connected to a 240-ohm pull-down resistor [16]. The power inputs VDD and VDDQ are connected to the 1.5 Volt power rail,

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through a ferrite and several decoupling capacitors, and the VSS and VSSQ balls to ground. When it comes to decoupling capacitors, the manufacturer notes that it is not necessary to place one capacitor on each input pair (VDDQ: VSSQ, VDD:

VSS) but recommends to allocate four capacitors around the chip, one at each side. However, in order to ensure the best performance for our memory, we decided to place one capacitor for every power input, excluding only those that aﬀect the routing. Finally, special care should be taken for terminating accurately the address bus to manage reflections and ringing. For that, each address signal along with the control/command signals are parallel terminated using 47 ohm resistors.

6.4 Micro SD Card

In order to make the design more flexible we decided to include a micro SD Card to our board. The micro SD Card is issued by the PS of the FPGA and can be used as external memory or as an alternative booting method. For example the PL program can be stored on the card and deployed to the board without the use of JTAG. The micro SD Card interface is 3.3Volt, thus in order to connect it to the 1.8Volt logic of the MIO bank we used a TI TXS02612 level shifter. The card itself is adressed through the translator using Serial Peripheral Interface (SPI) [17]. The micro SD Card is connected through an 8-pin standard micro SD card connector, J4, WE - 693 071 010 811.

Figure 6.3: Micro SD Card Block Diagram

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Signal Name Description XC7Z030 Pin MIO Bank

(501) SD Card Pin

SD CLK Clock C10 40 5

SD CMD Command C5 41 3

SD D[3:0] Data

D11 D6 B5 E9

45:42

7 D0 8 D1 1 D2 2 D3

SD CD Card Detect C8 46 CD

Table 7: SD Card Pin Assignment

6.5 Optical Links

6.5.1 GTX Transceivers

Considering the purpose of the project, we particularly chosen the XC7Z030 chip to take advantage of its GTX transceivers, which are power-eﬃcient and highly configurable transceivers [18]. The GTX is a sensitive circuitry which requires three power supplies to function. In order to provide a clean of noise power supply we have used linear regulators which downgrade the input voltage to a clean lower voltage output. The regulators need to be as close as possible to the chip to prevent interference from other devices and the power must be filtered using ferrite beads.

Decoupling capacitors are also placed on the pins to filter the high frequency noise created by the internal circuitry. Lastly the chip has a resistor calibration circuit, the resistor used must be the same as the internal diﬀerential impedance and the traces that connect it to the two pins need to have the same geometry and length.

6.5.2 SFP/SFP+ Module Connector

We have equipped the board with four small form-factor pluggable (SFP/SFP+) connectors P1-4 that accept SFP or SFP+ modules. Figure 6.4 shows the SFP/SFP+

module circuitry. The SFP connectors XXXX have 100 Ohm input impedance, we have place a 400 Ohm resistor in parallel with the transmit lines to decrease it to 80 Ohm in order to match the diﬀerential impedance of our board. There are six control signals for each module that provide information and control to the FPGA based on the I²C protocol [20]. The transmit and receive diﬀerential signals from the sfp module, connect to the transceiver quad on the XC7Z030 chip.

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Figure 6.4: SFP Block Diagram

Signal Name Description XC7Z030 Pin Bank 112 SFP Module Pin

MGTXRX[3:0] N Diﬀerential Receive Signal

AA5 Y3 V3 T3

MGTXRXN[3:0]

A12 B12 C12 D12

MGTXRX[3:0] P Diﬀerential Receive Signal

AA6 Y4 V4 T4

MGTXRXP[3:0]

A13 B13 C13 D13

MGTXTX[3:0] N Diﬀerential Transmit Signal

AB3 AA1 W1

U1

MGTXTXN[3:0]

A19 B19 C19 D19

MGTXTX[3:0] P Diﬀerential Transmit Signal

AB4 AA2 W2

U2

MGTXTXP[3:0]

A18 B18 C18 D18

Table 8: GTX Transmit and Receive Diﬀerential Signals

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Signal Name Description XC7Z030

Pin Bank SFP Module Pin 13

SFP[3:0] TX FAULT Transmitter fault indication

AB22 AB18 AB9

V8 12

A2 B2 C2 D2 13

SFP[3:0] TX DISABLE Disable optical output when high

AA22 Y18 AB10

W8 12

A3 B3 C3 D3 13

SFP[3:0] SDA Serial Data

Y22 AB19

W10

Y8 12

A4 B4 C4 D4 13

SFP[3:0] SCL Serial Clock

V22 AA19

V10

Y9 12

A5 B5 C5 D5 13

SFP[3:0] MODE DETECT Grounded by the module to indicate module presence

U22 AB20

Y11

AA9 12

A6 B6 C6 D6 13

SFP[3:0] LOS

When high, indicates received optical power below worst-case

receiver sensitivity

T22 AA21

W11

AB8 12

A8 B8 C8 D8

Table 9: Control Signals of SFP/SFP+ Modules

6.6 NIM- Negative Logic Signals

The data acquisition board will be connected to a front-end data collection and distribution system. We have included on the board the negative signal NIM standard [19] to provide the means of communication with the front-end system. Even though some protocols for communication through optical links are under development, due to the fact that most data collection systems already have coaxial NIM modules installed, we decided to include it in our design. The four coaxial connectors on the board go through a series of transistors and diﬀerential transla- tors in order to be connected to the 3.3 Volt bank of the FPGA. In particular we have used MC10ELT24 from ON and SN65LVDS34D from TI.

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Signal Name XC7Z030 Pin MIO Bank(501)

NIM IN[3:0]

AB14 AB13 AA12 V12

NIM OUT[3:0]

AB15 AA14 AB12 U12

12

Table 10: Nim Modules Pin Assignment

6.7 HDMI Transmitter

With respect to a video interface, the board will feature a High Definition Mul- timedia Interface (HDMI) transmitter and more specifically the most common HDMI transmitter, an Analog Devices ADV7511. Although this is not a crucial component for the proper operation of our system, during the design we realized that there is enough space on the board and several unused I/Os, this is why we decided to add this feature also. Common applications that the ADV7511 transmitter is used include gaming consoles, DVD players and recorders, PCs and many other home entertainment products. The external connection of the HDMI transmitter is being implemented via a Micro HDMI W¨urth Electronics 685119248123 connector. The transmitter is connected to the HP Bank 33 of the XC7Z030 SoC.

It should be noted that on ZedBoard, which uses the same transmitter, it is connected on a 3.3 Volt HR Bank. Nevertheless, since video inputs are compatible with logic levels from 1.8 Volt to 3.3 Volt, according to documentation, we can connect it to a 1.8 Volt HP Bank such as Bank 33 [21]. In table 11 we present the HDMI interface connections with our SoC:

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Signal Name Description XC7Z030 Pin ADV7511 Pin

HPD Transmitter

fault indication

AB22 AB18 AB9

V8

A2 B2 C2 D2

HD-INT Disable optical output when high

AA22 Y18 AB10

W8

A3 B3 C3 D3

HD-SCL Serial Data

Y22 AB19

W10 Y8

A4 B4 C4 D4

HD-SDA Serial Clock

V22 AA19

V10 Y9

A5 B5 C5 D5

HD-CLK Grounded by the module,to indicate module presence

U22 AB20

Y11 AA9

A6 B6 C6 D6

HD-VSYNC

When high, indicates received optical power below worst-case

receiver sensitivity

T22 AA21

W11 AB8

A8 B8 C8 D8

HD-HSYNC Horizontal Sync Input H3 98

HD-DE Data Enable signal input

for Digital Video J4 97

HD-D[15:0] Video Data Input

D0: F7 D1: F6 D2: G5 D3: F5 D4: H5 D5: F4 D6: G4 D7: G3 D8: J3 D9: F2 D10: J1 D11: H2 D12: H1 D13: G2 D14: E1 D15: F1

88 87 86 85 84 83 82 81 80 78 74 73 72 71 70 69

HD-SPDIF Audio Input

(Sony/Philips Digital Interface) J5 10 HD-SPDIFO Audio Output

(Sony/Philips Digital Interface) L2 46

Table 11: HDMI Transmitter Pin Assignment

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The transmitter can receive from as few as 8-bit to as many as 36-bit data, as it can recognize all the video formats of the EIA/CEA-861D specification [22].

In our case, we decided to use 16-bit data, following ZedBoards design, not only for compatibility reasons (ZedBoard will be the test board) but also due to the fact that 16-bits are more than suﬃcient for our purpose. A 26MHz external oscillator must also be used for clocking the device, connected to the CEC CLK input pin. The ADV7511 has six diﬀerent power domains, which are summarized in the following table 12:

Signal Name Description Voltage Rail

AVDD Power Supply for TMDS

Outputs 1.8V

DVDD Power Supply for

Digital and I/O Power Supply 1.8V PVDD Power Supply for PLLs

digital portion 1.8V

PLVDD Power Supply for PLLs

analog portion 1.8V

BGVDD Band Gap Vdd 1.8V

MVDD Power Supply 3.3V

Table 12: HDMI Transmitter Power Domains

As can be seen on the table 12 above, most of the domains are to be supplied from the 1.8 Volt power rail. However, because of the sensitive nature of the HDMI transmitter (it consists of several sensitive parts, such as PLLs), it is highly recommended to separate the power supply voltages using LC filters, in order to provide the chip with noise-free power. As shown in table 12, it is suﬃcient to separate the 1.8 Volt power domains into tree PCB power planes (BGVDD is supplied by PLVDD and PVDD by AVDD) [22]. Finally, the MVDD power domain must also be filtered out from the central 3.3 Volt power plane. Figure 6.5 illustrates the ferrites along with several decoupling capacitors that are used to create clean supply voltages for the ADV7511 chip.

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Figure 6.5: HDMI LC filters

6.8 Power Supply

One of the most critical parts of an electronic device, including PCBs, is the design of its power supplies. Todays FPGAs have become much more powerful and complex in order to provide additional necessary features such as memory interfaces, phased-locked loops (PLL) circuitry, transceiver functionality etc. [23].

All these elements operate at diﬀerent input voltages and as a result FPGAs need to be fed with multiple supply voltages to support the previously mentioned features.

In table 13 we summarize the required voltage levels for the XC7Z030 SoC.

At this point we should note that the external input voltage of a board is always higher than those we supply the SoC. For example, in our project the external input voltage is 12 Volts, from which we need to generate the required operating voltages both for the SoC and the rest of the components. The conversion from high to low voltage levels is performed using special devices called DC-DC converters. This section highlights the required steps in order to select the appropriate DC-DC converter modules for our system.

6.8.1 Voltage Rails

The first step is to identify the desired voltage rails of the board. In other words, we need to identify all the diﬀerent supply voltage levels that occur in our system.

In addition to XC7Z030s voltages, named above, there is also a number of other

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Type Pin Name Nominal Voltage Power Pin Description

VCCPINT 1.0V Internal logic

VCCPAUX 1.8V I/O buﬀer pre-driver

VCCO DDR 1.2V to 1.8V DDR memory interface

VCCO MIO0 1.8V to 3.3V MIO bank 0, pins 0:15 VCCO MIO1 1.8V to 3.3V MIO bank 1, pins 16:53 PS Power

VCCPLL 1.8V Three PLL clocks, analog

VCCPLL 1.0V Internal core logic

VCCAUX 1.8V I/O buﬀer pre-driver

VCCO X 1.8V to 3.3V I/O buﬀers drivers (per bank)

VCC BATT 1.5V PL decryption key memory backup

VCCBRAM 1.0V PL block RAM

PL Power

VCCAUX IO G X 1.8V to 2.0V PL auxiliary I/O circuits

XADC VCCADC

GNDADC N/A Analog power and ground

Ground GND Ground Digital and analog grounds

Table 13: Zynq-7000 Power Supply Voltages

components that must be fed with their own input voltages. These supply voltages will be the desired output voltage levels of our converters, thus they constitute the first criterion when choosing them (they must be able to generate that output voltage). In the following list we summarize all the necessary input voltage levels for each component:

Component Description Input Voltage

MT41K128M16JT-125 DDR3 Memory 1.5V

RPACK 0402-8 Terminating Resistors 0.75V 88E1518-A0-NNB2C000 Ethernet Transceiver 1V, 1.8V, 3.3V

USB3320 USB Transceiver 1.8V, 3.3V S25FL128SAGNFI000 Flash Memory 3.3V

TXS02612RTWR SD card 1.8V, 3.3V

ADV7511KSTZ HDMI Transmitter 1.8V, 3.3V

MC10ELT24 LEMO 5V, -5V

Table 14: Component Supply Voltages

Comparing tables 13 and 14 we obtain the final list of all the necessary power rails that occur on the system. These are: 0.75V, 1V, 1.2V, 1.5V, 1.8V, 3.3V,

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5V and -5V. As we have already mentioned, the supply voltages for the SFPs are generated using linear regulators, which have the advantage of providing low noise power signals at their output. The same applies for the DDR3 terminating resistors fed with 0.75V. As far as the -5V rail is concerned, it will be produced by a separate DC-DC Converter able to invert 5V to -5V. Using the above information we can draw a basic power architecture, illustrated in figure 6.6. As can be seen, the external input voltage is 12 Volts, thus we use several intermediate step-down DC-DC converters in order to generate the appropriate voltage rails. Up to this point we have not yet specified the exact DC-DC converters, but only the general power architecture. Figure 6.11 at the end of the section, illustrates the final power architecture of our board.

Figure 6.6: Block Diagram of Basic Power Architecture

6.8.2 Current Consumption

DC-DC converters should not just convert the input voltage to the desired output one. They also need to provide the right amount of current on the rails. Thus, we need to calculate the total current consumption for each voltage rail, specifying in this way how much current each converter must provide. After that we will have all the necessary information to choose the exact devices. The current consumption calculation is a rather complex process, therefore FPGA vendors provide designers with special EXCEL spreadsheets, such as Xilinx Power Estimator (XPE) [24]. In figure 6.7 we present the output from the XPE, having imported a basic description of our system. From these we can make a rough estimate of the total current consumption for each voltage rail. For example adding VCCINT, VCCBRAM,

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MGTAVCC and VCCPINT we can conclude a 8.093 A current consumption for the 1V rail, which is the most demanding of our system.

Figure 6.7: Current cosumption in Xilinx Power Estimator In the following list we summarize the current consumption for each rail:

Voltage Rail Current Consumption

1.0 V 8.093 A

1.2 V 0.306 A

1.5 V 0.293 A

1.8 V 0.777 A

3.3 V <1 A

Table 15: XC7Z030 Current Consumption per Rail

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6.8.3 Quad DC-DC Module Regulator LTM4644

Taking all the above into consideration, we have chosen the DC-DC converters of our system. For the 5V, 3.3V, 1.8V and 1.5V outputs we have chosen the Quad DC-DC Module Regulator LTM4644 by Linear Technology, which features four outputs [25]. It can provide 4A at each output, which is more than enough according to the above calculation, while its size is 9mm 15mm 5.01mm BGA package [25], including the inductors, power FETs and switching controllers [25].

It oﬀers an input voltage range between 4V and 14V and output range between 0.6V and 5.5V, covering all the requirements that we previously set.

The schematic configuration of the LTM4644 is displayed below. In principle it is has four regulators packed into one chip making it really small and powerful component. The output voltage of each rail is defined by the values of the resistor at the FB pins [25]. The chip provides the means to track the output voltages to ensure that all the voltages become ready at the same time, this is achieved by implementing the feedback circuitry on TRACK pins as described in the datasheet.

The components in our design will reset after the voltages are stabilized so the tracking feature is not used.. The PGOOD pins are pulled low if the output voltage is oﬀ by 10%, these signals are driven to LEDs.

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Figure 6.8: LTM4644 Schematic Diagram

6.8.4 LMZ31710 RVQ 42

For the most demanding 1V power rail we use a really powerful and easy-to-use DC- DC converter, able to provide up to 10 Amps at its output. It is a high eﬃciency converter with integrated inductor in a QFN 10mm 10mm 4.3mm package [26].

Regarding input and output voltage levels, it can receive up to 20V input voltages, generating an output between 0.6V and 5.5V, making it an ideal component for our board.

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Figure 6.9: LMZ31710 RVQ 42 Schematic Diagram

In the above picture we present the schematic diagram of the DC-DC converter.

Besides the decoupling capacitors at input and output pins, we need to highlight the importance of the 1000k and 2.15k resistors connected to the RT/CLK and VADJ pins respectively. As previously mentioned the converter is able to generate a wide range of output voltage levels. The output voltage depends on the values of the resistors on the RT/CLK and VADJ pins. In order to generate 1 Volt output, the manufacturer suggests placing a 1000k resistor on RT/CLK and 2.15k on VADJ. The converter also features a Power Good signal (PWRGD), which indicates whether the output voltage has reached an appropriate level (between 95% and 104%). The purpose of that signal is to prevent the system from starting operating, in case the corresponding output voltage has not reached the desired value. Finally, we need to underline that the converter needs both analog and digital grounds, since it includes both analog and digital circuitry that must be isolated from each other. The way the ground system is being implemented will be discussed in the next section.

6.8.5 MGT Regulators

As we have described previously the MGT require three power rails that must be clean of noise. For this purpose we reproduce the voltages needed in local linear regulators. Our estimation for the SFP modules is that each of them needs at

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most 200mA, that adds up to a total of 800mA. The IC we chose is the MIC47100 which provides output range of 0.8-2V with 2

Figure 6.10: MGT Regulators Schematic Diagram

As with the DC-DC converters the values of the resistors connected to the ADJ pin provide the feedback circuit to the operation amplifier(OpAmp) that determine the output voltage while VBIAS powers the OpAmp circuitry.

6.8.6 Complete Power Architecture

Now that we have talked about the DC-DC converters and the regulators of our board, we can present the final power architecture of our system.

Figure 6.11: Complete Power Architectire Block Diagram

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6.9 Configuration and External Control

There is a number of inputs/outputs used to externally control and configure the Zynq device. These pins include external power-on-reset and reset inputs, PL reconfiguration pins and others. In this section we will try to clarify some of these dedicated pins and we will give a brief overview of the booting process in Zynq-7000 SoC devices.

6.9.1 Power-on-Reset (PS POR B)

When power is applied on the board, the DC-DC converters should as fast as possible generate the appropriate voltage levels to power-up the SoC. All power supply devices do not immediately reach the desired output value, as they present a ramp-up behavior, illustrated in figure 6.12, for a short period of time. During this period the Zynq SoC should not start operating, as these intermediate values on power pins might damage the device. In order to avoid these problems a Power-on-Reset (PS POR B) signal is used to keep the PS in reset mode (resets all internal registers), until all power supplies reach the desired voltage level [27].

As soon as the PS POR B signal deasserts, the PS module starts the booting and configuration process. There are several techniques to drive the PS POR B signal and ensure proper system startup. In our case we use a voltage supervisor (TLV803S), which initializes the SoC (deasserting the PS POR B) as long as the voltage on the 3.3V power rail exceeds a threshold of 2.93V. As indicated in figure 6.12, it is quite robust to test the 3.3V rail, since it ensures that all other power signals have already reached their final values. The PS POR B signal is also used to reset the USB and Ethernet transceivers.

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Figure 6.12: Ramp-up Output Voltage Response

6.9.2 User Buttons

The board provides two user buttons for some basic control of the Zynq-7000 SoC.

S3 button drives the PS SRST B input, through which the user can reset the functional logic and the Cortex A9 processor leaving untouched only the debug environment [27]. The second push button is used to control the PROGRAM B input of the configuration Bank 0, with which the user can trigger a PL reconfiguration process.

6.9.3 Boot and Configuration

Before we talk about the actual devices that are used for booting the SoC, we need to give a brief overview of the booting process in Zynq-7000 devices. There are several user specified boot modes, through which we can select the booting/programming device. In our case we provide the possibility to boot the device from a flash memory, an SD card or through JTAG. The selection of the booting device is being implemented through a number of hardware defined boot strapping pins that the user can set, before powering-up the system. Shortly after the active low PS POR B signal becomes zero, the boot mode strapping pins are sampled and their values are stored to software readable registers [27]. According to these values, the PS module selects the corresponding booting device. The boot mode pins are MIO[6:2] and in the following table16 we present their encoding:

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MIO[6] MIO[5] MIO[4] MIO[3] MIO[2]

JTAG Mode

Cascaded JTAG - - - - 0

Independent JTAG - - - - 1

Boot Device

JTAG 0 0 0 -

Quad-SPI (flash) 1 0 0 -

SD Card 1 1 0 -

PLL Mode

PLL Used 0 - - - -

PLL Bypassed 1 - - - -

Table 16: Boot Mode Pins

As can be seen, MIO[5:3] are used for specifying the booting device, while MIO[2] is used for specifying the JTAG mode. Another option is to bypass the PLLs using MIO[6]. Note that after sampling the boot mode strapping pins, the same MIO pins are used for communication with the flash memory. Finally, we need to highlight that in order to avoid the use of bulky switches or jumpers on our board, we preferred to use just the 20k pull-up or pull-down resistors that in any case are needed. As illustrated in the following picture, each mode signal is connected with two 2k resistors to 3.3V (digital value 1) and ground (digital value 0). Once we decide the mode we prefer, we will hardwire the corresponding resistor.

Figure 6.13: Resistors for Boot Mode Selection

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6.9.4 Flash Memory

The most usual boot mode is the master boot mode, according to which the system is being configured from a flash memory. The board is equipped with a four-bit S25FL128S flash memory that is used both to initialize the PS module and configure the PL module [11]. The flash memory will be connected directly with the PS, through the PS MIO Bank 500. As previously mentioned, MIO[6:2] are used both for selecting the boot mode, before initialization and for communication with the flash memory, during and after initialization.

Signal Name Description XC7Z030 Pin MIO Bank(501) S25FL128S Pin

SPI-CS Chip Select B15 1 1

SPI-IO0/MODE0 Data bit 0 C15 2 5

SPI-IO1/MODE1 Data bit 1 B14 3 2

SPI-IO2/MODE2 Data bit 2 F12 4 3

SPI-IO3/MODE3 Data bit 3 B13 5 7

SPI-SCK/MODE4 Serial Data Clock D15 6 6

Table 17: Flash Memory Pin Assignment

7 Layout

When the components and the connections between them are completed in the schematics, we are ready to move into the PCB layout and create the actual connections. The first step we need to take is to define the dimensions of the board and transfer the footprints of the components to it, in our design we wanted something small so we started with a 100x100 mm board. Altium designer and most CAD software place all the components outside the boards perimeter grouped by the datasheet they are in. The next step is to place the biggest components on the board and get a feeling for where you want the components to be. For example the FPGA, since everything connects to it, has to be in the center of the board and the SFP modules will have to be at the edge of the board. Furthermore we identified the components that are the most demanding in routing space and layers needed for this routing, such as the DDR chips, and started from there. We grouped the rest of the components based on functionality making only the local routing but without connecting them to the FPGA yet, because having connections

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routed creates restrictions, since other routes have to either go around them or through other layers. The designer has to imagine the connections and understand where traces overlap to avoid problems later on, most CAD tools draw lines that indicate connection between pads. When everything in its final place, we route the connections and move on to the final stages of the design. We create the copper polygons for the power and ground planes and make adjustments to them in order to have large continuous areas. As we go through the design again we may make minor changes to achieve better ground plane flow and shorter current return loops.

This is the best case scenario, in reality it is a much more complicated procedure that has many variables to consider. For example, extra features may be added later to the project forcing the designer to make the appropriate changes in the schematics and layout. We gained this experience as we decided to add the SD card and the HDMI chip about half way through the project, so we had to change the position of components even after they had already been routed, which meant that they had to be rerouted from the begging. Doing so of course, frees up space in some places but squeeze routes on other places, leading to more changes. As we perceive it, the board is an alive organism were even the slightest change may trigger a chain reaction of modifications, and this is what makes it an enjoyable and satisfying procedure. While the design grows we will have to return in the schematics and make changes in the connections to favor routing. A good example of this are the NIM and HDMI interfaces, in principle we can connect them to any GPIO pin of the FPGA. Since these are flexible connections we can postpone their connection until the late stages of the design where components with limitations in pin selection are in place and routed.

The rule of thumb in layout, as well as in datasheets, is to thoroughly read the datasheets and take notes. There are suggestions and limitations provided by the manufacturer to guarantee the proper operation of the component. Some datasheets also include a layout suggestion with pictures to assist the designer.

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7.1 Layer Stacks and Impedance

Nowadays it is common for the PCBs to have multiple internal layers. We use these layers to distribute the signals around the board without having conflicts. If two traces need to be routed through a specific track, one of them can go through vias to a diﬀerent layer. This technic allows the creation of advanced and complicated PCBs. The basic idea is to have a copper layer, where we have signals and power planes created by copper, between two dielectric layers, which are layers populated by FR-4, a fiberglass material with a defined dielectric constant (4.2 in our design).

The layers are symmetrical from the center to keep the characteristic impedance the same in all layers. In order to explain characteristic impedance [28] and how it eﬀects signals we need first to define trace impedance. Let us take for example a 10 Ohm resistor with two traces connected to it, the traces has 50 Ohm impedance.

We use a multi-meter to measure the trace impedance and we see a value around 10 Ohm, of course this is what we expect see. If we instead had professional equipment, with fast response, we would see that for the initial stage where we apply the testing voltage, the trace impedance is 50 Ohm. During this initial time we are not driving the load (resistor) but the trace itself, until it is charged up, so trace impedance can be described as a resistance to fast current changes on a trace. If the trace impedance is constant we call it characteristic impedance, when we design the traces to have the same impedance throughout its length, we refer to it as controlled impedance. High frequency signals like clocks or data, have fast rise times, in an impedance discontinuous trace this will cause reflection, some of the energy will bounce back while the rest will continue distorted, these discontinuities are vias, pads or variations in trace width. An example is shown in figure 7.1, which illustrates the reflection of a single pulse on a 50 Ohm impedance trace with 50 Ohm, 100 Ohm, open and short receiver. For this simulation we used Qucs [29].

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(a) Short (b) Open

(c) 50 Ohm - Impedance matched (d) 100 Ohm Figure 7.1: Reflection of a single pulse

7.1.1 Impedance matching

Usually the receiver IC has a high-impedance input for protection, this of course creates reflection back to the source. In order to avoid this reflection we need impedance matching. To put it simply, impedance matching is the process of making an impedance to look like another. As seen in figure XX, with the termination resistor equal to the characteristic impedance we eliminate the reflection.

Throughout our design we have used series and parallel termination for single ended clocks and data buses respectively, the values needed for the terminating resistors can be derived through formulas or by using one of the numerous impedance calculating tools.

Stand-alone Data Acquisition Board for optical links

Examensarbete 30 hp Juli 2015

Stand-alone Data Acquisition Board for optical links

Georgios Ntounas

Panagiotis Stamatakopoulos

Institutionen för informationsteknologi

Abstract

Stand-alone Data Acquisition Board for optical links

Contents

List of Figures

List of Tables

1 Introduction

2 Background

2.1 Electromagnetic Interference and Compatibility

2.2 Zynq-7000 All Programmable System-on-Chip (SoC)

3 Related Work

3.1 ZedBoard

3.2 PicoZed

3.3 Trigger/DAQ Mezzanine

4 Tools

5 System Overview

6 Component Interconnection

6.1 10/100/1000 Ethernet Transceiver

6.2 USB Transceiver

6.3 DDR3 Memory

6.4 Micro SD Card

6.5 Optical Links

6.6 NIM- Negative Logic Signals

6.7 HDMI Transmitter

6.8 Power Supply

6.9 Configuration and External Control

7 Layout

7.1 Layer Stacks and Impedance