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A MADMUNT AR ZAKLOUTA
KT ROYAL IN TITUTE OF TEC NOLOGY
Abstract
This thesis is part of a project at Bombardier’s Object Controller System. This system acts as a communication interface for several sub-systems that control the railway traffic. Therefore, part of the safety and availability of railway transportation is dependent on the performance and reliability of this system especially the digital communication system that handles the board-to-board communication. Thus, Bombardier has implemented new high-speed LVDS channels to use instead of the implemented RS-485 channels to improve the board-to-board communication performance in the Object Controller System but they lack a transceiver. This thesis work explores possible transceiver solutions that achieve Bombardier requirements. Reusability is very important for Bombardier for safety compliance and certification. Therefore, the investigation was carried out by looking into what is currently implemented and then was carried on by looking into transceivers that used in high-speed communication and check their suitability and compliance for the FPGA and the requirements. This exploration results in three experiments for different transceiver architecture. The first experiment exploits the currently implemented transceiver architecture and it is not suitable for high-speed data rate due to a limitation in the buffer. The second experiment overcomes the buffer limitation by using a clock domain crossing buffer and results in a 100-time faster system. The third experiment aimed to achieve a higher data rate by using a clock and data recovery transceiver and results in a promising solution but needs some enhancements. For testing, a verification methodology following the one-way stress test architecture has been developed using VHDL for simulation and for in-chip testing and the results were verified using ChipScope logic analyzer from Xilinx. In addition, a thermal test for the solution from the second experiment has been performed.
Keywords
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Abstrakt
Denna avhandling är en del av ett projekt på Bombardiers Object Controller System. Detta system fungerar som ett kommunikationsgränssnitt för flera delsystem som styr järnvägstrafiken. Därför är en del av säkerheten och tillgängligheten av järnvägstransporten beroende av systemets prestanda och tillförlitlighet, särskilt det
digitala kommunikationssystemet som hanterar kommunikationen ombord.
Acknowledgment
To my wonderful family, especially my beloved mother who has spared no effort providing to make my life better. It is so great to have a person like you. Thank you for your love and for supporting me during the harshest period of my life. Without you, I could never do it.
To Sweden, the country that received me, support me and gave me a chance for a new life after I lost everything.
To kTH Alumni, the organization that believed in me gave me hope and made my studies in kTH possible.
To all the kind souls who helped me, encouraged me, and stood beside me.
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Content
Abstract ... 1 Abstrakt ...2 Acknowledgment ... 3 Content...4 List of tables ... 6 List of figures ... 7 List of equations ... 9 Terminology ... 10 1. Introduction... 11 1.1. Background ... 11 1.2. Problem ... 11 1.3. Purpose ... 11 1.4. Goal ... 12 1.5. Methods ... 12 1.6. Outline ... 12 2. Theoretic Background ... 132.1. Introduction to Railway Signaling System ... 13
2.2. Introduction to Digital Communication System ... 15
2.2.1. Serial Versus Parallel Transfer ... 17
2.2.2. Signaling protocol (Line Coding) ... 18
2.2.3. Clocking Scheme ... 19
2.2.4. High-Speed Self-Synchronous Serial Link System ... 21
2.2.5. Digital Communication System Performance Quality ... 27
2.3. Introduction to Bombardier’s Object Controller LVDS-Link Communication System ... 32
3. LVDS-Link Implementation and Testing ... 34
3.2. Verification Methodology... 36
4. LVDS-Link Channel Stress Test ... 37
4.1. Stress Test with LVDS-Link UART Implementation ... 38
4.1.1. Stress Test with LVDS-Link UART and Generic FIFO Implementation .... 38
4.1.2. Stress Test with LVDS-LINK UART and CDC FIFO Implementation ... 46
4.2. Stress Test with LVDS-Link CDR Implementation ... 55
4.2.1. 5x Blind Oversampling CDR Overview... 55
4.2.2. Test Setup with 5x Blind Oversampling CDR ... 59
Conclusion ... 67
Future Work ... 68
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List of tables
TABLE 1:EXAMPLE OF BERESTIMATION. ... 28
TABLE 2:ITU-T STANDARDIZATION FOR PRBS. ... 30
TABLE 3:UART INTERFACE DESCRIPTION. ... 35
TABLE 4:OUTPUT SIGNAL FOR PATTERN GENERATOR AND ERROR DETECTOR. ... 39
TABLE 5:LVDS-LINK WITH GENERIC FIFOSTRESS TEST PARAMETERS. ... 43
TABLE 6:LVDS-LINK WITH CDCFIFOSTRESS TEST PARAMETERS. ... 51
List of figures
FIGURE 1:RAILWAY SIGNALING SYSTEM HIERARCHY. ... 14
FIGURE 2:BASIC FUNCTIONAL ELEMENTS OF DIGITAL COMMUNICATION SYSTEM [2]. ... 15
FIGURE 3:PARALLEL DATA TRANSFER VSSERIAL DATA TRANSFER [3]... 17
FIGURE 4:NRZ,RZ, AND MANCHESTER LINE CODING [4]. ... 18
FIGURE 5:SYSTEM-SYNCHRONOUS DIAGRAM. ... 19
FIGURE 6:SOURCE-SYNCHRONOUS DIAGRAM. ... 19
FIGURE 7:SELF-SYNCHRONOUS DIAGRAM. ... 20
FIGURE 8:SELF-SYNCHRONOUS SYSTEM ARCHITECTURE. ... 20
FIGURE 9:BASIC ARCHITECTURE OF HIGH-SPEED ELECTRICAL SERIAL LINK. ... 21
FIGURE 10:UART(DOWN) AND SERDES(UP)BLOCK DIAGRAM [3][5]. ... 22
FIGURE 11:DIFFERENTIAL SIGNALING CHANNEL. ... 23
FIGURE 12:SIMPLIFIED FUNCTIONAL DIAGRAM OF CDR[8]. ... 23
FIGURE 13:PLL-BASED CDR WITHOUT A REFERENCE CLOCK,PLL-BASED CDR WITH A REFERENCE CLOCK [8]. ... 24
FIGURE 14:A BLOCK DIAGRAM OF A BLIND OVERSAMPLING CDR,BIT BOUNDARY DETECTION, AND DATA SAMPLE SELECTION [6]. ... 25
FIGURE 15:CLOCK DOMAIN CROSSING AND META-STABILITY [13]. ... 25
FIGURE 16:CDCASYNCHRONOUS FIFO WITH INDEPENDENT CLOCK DOMAINS [15]. ... 26
FIGURE 17:BIT ERROR RATIO TEST. ... 28
FIGURE 18:TESTING CONFIGURATION OF BERT. ... 29
FIGURE 19:PRBS PATTERN GENERATOR USING LFSR. ... 29
FIGURE 20:ERROR DETECTOR USING MANUAL SYNCHRONIZATION. ... 31
FIGURE 21:STACK MODELS FOR LVDS-LINK. ... 32
FIGURE 22:FUNCTIONAL BLOCK DIAGRAM FOR LVDS-LINK COMMUNICATION SYSTEM. ... 33
FIGURE 23:UARTTRANSMISSION/RECEPTION PROTOCOL. ... 34
FIGURE 24:UART TOP MODULE. ... 34
FIGURE 25:ARCHITECTURE OF THE VERIFICATION METHOD. ... 36
FIGURE 26:LVDS-LINK UART WITH GENERIC FIFOSTRESS TEST SETUP. ... 38
FIGURE 27:LVDS-LINK UARTBLOCK DIAGRAM. ... 39
FIGURE 28:START AND STOP FOR INBOUND FIFO AND OUTBOUND FIFO. ... 40
FIGURE 29:TEST FLOWCHART OF THE TRANSMITTER (SECONDARY_BOARD). ... 41
FIGURE 30:TEST FLOWCHART OF THE RECEIVER (MAINBOARD). ... 42
FIGURE 31:RESULT FOR LVDS-LINK UART WITH GENERIC FIFO FROM SERIAL TERMINAL. ... 43
FIGURE 32:SCREENSHOT,EYE DIAGRAM,PERIOD HISTOGRAM, AND LOW-HIGH HISTOGRAM FOR LVDS-LINK CHANNEL NO.(0) AT 100 MHZ ON THE BACKPLANE ... 45
FIGURE 33:LVDS-LINK UART WITH CDCFIFOSTRESS TEST SETUP. ... 47
FIGURE 34:LVDS-LINK UART WITH CDCFIFO. ... 47
FIGURE 35:START AND STOP FOR INBOUND FIFO AND OUTBOUND FIFO. ... 48
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FIGURE 37:TEST FLOWCHART OF THE RECEIVER (DC_BOARD). ... 50
FIGURE 38:SCREENSHOT,EYE DIAGRAM,PERIOD HISTOGRAM, AND LOW-HIGH HISTOGRAM FOR LVDS-LINK CHANNEL NO.(0) AT 50 MHZ ON THE BACKPLANE. ... 52
FIGURE 39:SNAPSHOT FROM CHIPSCOPE OF THE TRANSMITTER AND RECEIVER FOR LVDS-LINK UART WITH CDCFIFOSTRESS TEST AT 50MHZ. ... 53
FIGURE 40:SNAPSHOT FROM CHIPSCOPE OF THE RECEIVER AT THE END OF THE LVDS-LINK UART WITH CDCFIFOSTRESS TEST AT 50MHZ. ... 53
FIGURE 41:RESULT FOR LVDS-LINK UART WITH CDCFIFO FROM SERIAL TERMINAL. ... 54
FIGURE 42:BASIC PLLIOSERDES2ARCHITECTURE. ... 55
FIGURE 43:5X BLIND OVERSAMPLING CDRARCHITECTURE [10]... 56
FIGURE 44:CLOCK GENERATION USING TWO DCM IN THE FPGA[26]. ... 56
FIGURE 45:OPERATION ILLUSTRATION FOR 5X BLIND OVERSAMPLING CDR AND HARDWARE IMPLEMENTATION OF CCNT ALGORITHM [10][30]. ... 57
FIGURE 46:(A)DUPLICATE DATA (B)MISSING DATA [30]. ... 58
FIGURE 47:LVDS-LINK CDRSTRESS TEST SETUP. ... 59
FIGURE 48:TEST FLOWCHART OF THE TRANSMITTER (CPU_BOARD). ... 60
FIGURE 49:TEST FLOWCHART OF THE RECEIVER (DC_BOARD). ... 61
FIGURE 50:SNAPSHOT FROM ISIM OF THE SIMULATION RESULT FOR LVDS-LINK CDRSTRESS TEST. ... 63
FIGURE 51:SNAPSHOT FROM CHIPSCOPE OF THE RECEIVER FOR LVDS-LINK CDR WHEN IT SUCCEEDS. ... 63
FIGURE 52:SCREENSHOT,EYE DIAGRAM,PERIOD HISTOGRAM, AND LOW-HIGH HISTOGRAM FOR LVDS-LINK CHANNEL NO.(0) AT 100MHZ ON THE BACKPLANE. ... 64
List of equations
EQUATION 1:BIT ERROR RATIO. ... 27
EQUATION 2:ESTIMATION OF BER. ... 27
EQUATION 3:BERCONFIDENTIAL LEVEL. ... 27
EQUATION 4:CONFIDENTIAL LEVEL WITH CUMULATIVE BINOMIAL DISTRIBUTION FUNCTION. ... 28
EQUATION 5:ESTIMATION OF BINOMIAL DISTRIBUTION FUNCTION BY POISSON THEOREM. ... 28
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Terminology
Acronym Explanation
TMS Traffic Management System
CBI Computer-Based Interlocking System
CIS Central Interlocking System
OCS Object Controller System
DC_Board Data Concentrator Module
GPMC General Purpose Memory Controller
OC Object Controller Unit
CPU_Board CPU Board
UART Universal Asynchronous Receiver/Transmitter
LVDS Low Voltage Differential Signaling
RS-422 Recommended Standard 422 (ANSI/TIA/EIA-422-B)
RS-485 Recommended Standard 485 (ANSI/TIA/EIA-485-A)
FPGA Field Programmable Gate Array
VHDL Very high speed integrated circuit Hardware Description Language
DUT Design Under Test
USB Universal Serial Bus
CCU Communication Control Unit
BER Bit Error Ratio
BERT Bit Error Ratio Test
CL Confidence Level
PRBS Pseudo-Random Binary Sequence
LFSR Linear Feedback Shift Register
ITU-T International Telecommunication Union - Telecommunication
Standardization Sector
CDR Clock Data Recovery
CDC Clock Domain Crossing
PLL Phase-Locked Loop
UART Universal Asynchronous Receiver/Transmitter
SERDES Serializer/Deserializer
VCO Voltage Control Oscillator
CP Charge Pump LF Linear Filter PD Phase Detector FD Frequency Detector PG Pattern Generator ED Error Detector
FIFO First In First Out
PCB Printed Circuit Board
DCM Digital Clock Manager
1. Introduction
Transportation has been a very important and critical issue to the humankind over the time as their lives depend on the movement of themselves and their goods and commodities. “The development of steam locomotive and the invention of the wrought iron rail technology were the two crucial factors that led to the establishment of the modern railway transportation” [1]. Railway transportation is considered to be the best land transportation option as it provides numerous advantages over other transportation means in terms of efficiency, speed, environment, and energy. In addition, it provides a solution to congestion, pollution, and fuel inefficiency [1]. Railway transportation can be defined as a mean of transporting goods (passengers or commodities) on vehicles that run on tracks over long or short distances. The railway transportation involves complex operations, infrastructure, and systems. One of the critical systems involved in railway transportation is the Object Controller System in the Signaling System as it is in direct connection with the rail. Therefore, fast response, reliability, and availability of the digital communication system inside the Object Controller System are crucial issues. This thesis covers this digital communication system.
1.1. Background
The background knowledge section is divided into three main parts (field, system, and product).
The field background part is concerning the Railway Signaling System where this thesis work falls into and is explained in (section 2.1 on page 13). The system background part is concerning the Digital Communication System that this thesis is classified as and is explained in (section 2.2 on page 15). Finally, the product background part is concerning Bombardier’s Object Controller System that this thesis work applied in and is explained in (section 2.3 on page 32).
1.2. Problem
The current board-to-board communication performance in Bombardier’s Object Controller System (RS485-Link) needs to be upgraded to support new requirements that are demanded for a newer version of Bombardier’s Object Controller System in terms of performance, availability, and reliability. Therefore, a new board-to-board communication system (LVDS-Link) should be implemented and integrated into the current system.
This thesis aims to determine what the maximum performance of the LVDS-Link channels in Bombardier’s Object Controller System and to improve the previous implementation.
1.3. Purpose
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testing a communication system that achieves maximum data rate on LVDS-Link channels in Bombardier’s Object Controller System.
1.4. Goal
The goal of this thesis is to increase the board-to-board communication performance in Bombardier’s Object Controller System in order to achieve shorter headway between the trains, having a fully redundant system, and better maintenance by communicating maintenance massages along with the safety messages.
LVDS-Link channels can be used as an alternative for the board-to-board communication system in Bombardier’s Object Controller System.
1.5. Methods
This thesis used an iterative waterfall process consisting of three major procedures (Functional Design, Simulation, Verification). The simulation was mixed between Top-down testing and Bottom-up testing. The verification was in-chip testing and was carried out using FPGA-PC communication module provided by Bombardier and using ChipScope Pro Analyzer provided by Xilinx.
The project involved two students, I (Ahmad Zaklouta) and my college Elena Migliorin, but this thesis work was completely carried out by me except for some help in the first experiment (See 4.1.1 on page 38). We discussed the project together to agree on the architecture and splitted up the tasks in agreement with supervisors.
1.6. Outline
2. Theoretic Background
This section will be mainly an introduction to the three main parts (field, system, and product) required to be studied for this thesis work.
2.1. Introduction to Railway Signaling System
Railway traffic needs to be controlled to achieve the reliability, maintenance, safety, and availability needed for such a system. The system which performs this control is called a railway signaling system. The system is arranged in a hierarchy as Figure 1 shows. It comprises the following subsystem:
Traffic Management System (TMS)
This system is at the top of the hierarchy. This system is responsible for planning, monitoring, and controlling the railway traffic. This system is usually in the Traffic Control Center.
Computer-Based Interlocking System (CBI)
This system is in the middle of the hierarchy. This system is responsible for supervising and controlling wayside objects. This system comprises the following subsystem:
Central Interlocking System (CIS)
This system is responsible for locking the routes for the train movements, maintaining protected areas to these routes and preventing new train movements that are in conflict with already locked routes. It is the communication node between the Traffic Management System and the Object Controller System.
Transmission Network
The network between Central Interlocking System and Object Controller System. Object Controller System (OCS)
This system is responsible for interfacing, monitoring, and controlling the wayside objects by receiving orders from Central Interlocking System and sending statuses back.
Wayside Objects
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Figure 1: Railway Signaling System Hierarchy.
TMS
2.2. Introduction to Digital Communication System
This section will provide an introduction for a digital communication system and cover some principles such as serial versus parallel transfer, signaling protocol, and clocking scheme. Then it will continue in more details about high-speed Self-Synchronous Serial link system and digital communication system performance quality.
The digital communication system can be defined as exchanging information in form of digital signals between different parties over a communication channel via digital modulation and demodulation. The main advantage of the digital communication system over an analog communication system is that the digital signal is noise immune. Through digital transmission, the noise effect can be eliminated and the digital signal can be regenerated. In contrast, when the analog signal is amplified in analog transmission, the noise is also amplified. Digital communication systems consist of three basic elements, namely, the transmitter, the channel, and the receiver as shown in Figure 2(modified from [2] figure 1.2, page 8).
Source Encoder Channel Encoder Digital Modulator Input Transducer Communication Channel Destination Decoder Channel Decoder Digital Demodulator Output Transducer Information Destination Information Source
Figure 2: Basic Functional Elements of Digital Communication System [2].
A brief description of each element is summarized from [2] and presented below:
Input/Output Transducer: “convert information from source output into an electrical signal that is suitable for transmission and the received electrical signals into a form that is suitable for the destination”.
Transmitter: converts the information electrical signal into a form that is suitable for transmission through the communication channel.
Source Encoder: convert the output of either an analog or a digital source into a sequence of binary digits called “Information Sequence”. Channel Encoder: introduce, in a controlled manner, some redundancy
in the binary information sequence which can be used at the receiver to overcome the effects of noise and interference encountered in the transmission of the signal through the channel to increase the reliability of the received data and improve the fidelity of the received signal.
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Communication Channel: the physical medium that is used to send the signal from the transmitter to the receiver. The transmitted signal is corrupted in a random manner by a variety of possible mechanisms.
Receiver: recover the information electrical signal contained in the received signal.
Digital Demodulator: processes the channel-corrupted transmitted waveform and reduce each waveform to a single number that represents an estimate of the transmitted data symbol (whether the transmitted bit is a 1 or a 0).
Channel Decoder: reconstruct the original information sequence from knowledge of the code used by the channel encoder and the redundancy contained in the received data.
2.2.1. Serial Versus Parallel Transfer
There are two methods to transfer binary data from one point to another; serial data transfer and parallel data transfer. In parallel transfer, all bits of the word are sent from the source to the destination at the same time. This requires an independent data line, and IC pin for each bit, lines impedance matching to prevent reflection1, timing skews
due to different line length, and complicated layout design due to more IC pins. Also because of larger word sizes, parallel data transfer becomes an inefficient, very complex, costly, and difficult to implement. In contrast, during serial data transfer all bits of the word are sent from the source to the destination one at a time sequentially. Therefore, only a single data line and one or two IC pins are required. Thus, serial data transfer is easier, simpler, and cheaper (Summarized from [3]). Figure 3(Modified from [3] figure 2.1, page 6) depicts the difference between serial transfer and parallel transfer.
Source Destination 1 0 0 1 0 1 1 0
Figure 3: Parallel Data Transfer VS Serial Data Transfer [3].
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2.2.2. Signaling protocol (Line Coding)
“Line coding refers to the ways that the serial data signal is shaped to represent the binary 1s and 0s” [3]. There are several line coding schemes such as Non-Return to Zero (NRZ), Return to Zero (RZ), and Manchester. As this work uses only Unipolar NZR, it will be explained. In Unipolar NRZ the binary ‘1’ is represented by high voltage level and the binary ‘0’ by zero voltage level and “the voltage level remains at a constant level for the entire bit time or does not return to zero” [3]. Figure 4 (taken from [4])Depicts NRZ, RZ, and Manchester line coding.
2.2.3. Clocking Scheme
There are several clocking schemes (timing models) for communication between two components (ICs, Boards, etc). This thesis investigated only three schemes: system-synchronous, source-system-synchronous, and self-synchronous.
System-Synchronous System
This is the most commonly used scheme. In this scheme (shown in Figure 5) a common clock is applied to both source and destination and used for data transmission and reception.
OCS
Source DATA Destination
Figure 5: System-Synchronous Diagram.
Source-Synchronous System
This scheme also called “Clock Forwarded” [5]. In this scheme (shown in Figure 6) the source (transmitter) send a copy of the clock used for transmitting the data along with the data and the destination (Receiver) uses the forwarded clock for the reception. Several design considerations must be taken into account:
1- The forwarded clock is generated so that the clock transitions in the middle of the data cell.
2- The trace lengths of the data and clock lines must be matched.
3- The destination must move the received data from the forwarded clock domain to its global clock domain.
OCS Source Destination
DATA
OCS CLOCK
Figure 6: Source-Synchronous Diagram.
Self-Synchronous System
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Source DATA & CLOCK Destination
OCS OCS
Figure 7: Self-Synchronous Diagram.
The LVDS-Link channels are only data channels without a clock channel. Therefore, the self-synchronous scheme is the most suitable scheme to use.
The general architecture of the self-synchronous system comprises Transmitter, clock generation, and Receiver which include Clock Data Recovery (CDR) and Clock Domain Crossing (CDC) as shown in Figure 8.
Source Destination
DATA & CLOCK
OCS OCS TRANSMITTER CLOCK GENERATION RECEIVER CLOCK GENERATION CDR CDC LOGIC
2.2.4. High-Speed Self-Synchronous Serial Link System
Figure 9 depicts the major components of a high-speed self-synchronous serial link system. It comprises Serializer/Deserializer (SERDES), Transmitter/Receiver Driver, Differential Signaling Channel, Phased-Locked Loop (PLL), and CDR.
Figure 9: Basic Architecture of High-Speed Electrical Serial Link.
Serializer/Deserializer (SERDES)
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Figure 10: UART (Down) and SERDES (Up) Block Diagram [3] [5].
Differential Signaling Channel
Differential signaling mode requires a pair of complementary traces (wires) between the transmitter and receiver to transmit a signal. Thus, two equal signals are generated with opposite polarity and referenced to each other. One trace carries the positive signal and the other carries the negative signal. The main advantages of a differential signaling scheme over the single-ended scheme are high noise immunity, large common-mode rejection, and low power. See Figure 11 for an overview.
Low Voltage Differential Signaling (LVDS) Standard
LVDS is a high-performance electrical differential data transmission standard
currently standardized by (ANSI/TIA/EIA-644-A) titled “Electrical
Figure 11: Differential Signaling Channel.
Clock Data Recovery (CDR)
The highest priority in serial communication goes to timing control. Therefore, a CDR circuit is an essential component in many high-speed serial communication applications. The transmitter serializes the parallel data into serial data by time-division multiplexing; thus, distinguishing between bits is achieved by looking into their position in time. As there is no clock accompanying the data in the self-synchronous system, the receiver does not have a timing reference to sample each bit. Therefore, the receiver must use the embedded bit transition in the received data to recover the timing in order to be able to sample and interpret each bit correctly. But often the transmitted data get distorted due to external and internal noise during transmission and this will introduce jitter and skew in the received data. Thus, a robust CDR circuit is very important to extract the transmitted data and recover the clock from the distorted received signal [7] [8]. See Figure 12 (taken from [8] figure 2, page 46).
Figure 12: Simplified Functional Diagram of CDR [8].
There is a various approach to design CDR circuit (summarized in [8]). A brief classification is done in the following section in order to justify the decision of choosing the Blind Oversampling method. “CDR circuits can be classified according to the phase relationship between the received input data and the local clock at the receiver into three major categories” [8]: Phase Tracking Feedback such as PLL-based CDR (also called Hardware Recovery [9]), without Phase Tracking Feedback such as Blind Oversampling-based CDR (also called Software Recovery [9]), and Phase Alinement CDR.
Phased Locked Loop-based CDR (PLL-based CDR)
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and aligned to the transition of the received data. Then the data can be sampled at the middle of the eye using the recovered clock. There are various PLL-based CDR architectures but in general, it comprises Phase Detector (PD), Frequency Detector (FD), Linear Filter (LF), Charge Pump (CP), and Voltage Control Oscillator (VCO). Figure 13 (taken from [8] figure 4&5, page 47&48) depicts two different designs of PLL-based CDR.
Figure 13: PLL-Based CDR without a reference clock, PLL-Based CDR with a reference clock [8].
The frequency tracking loop provides a frequency comparison between the input data D(in) or the reference clock F(ref), and the (VCO) output clock (Recovered Clock) through the (FD) and produces a control voltage through (CP) and (LF) to lock the (VCO) oscillation frequency onto the input data rate. Once the frequency is locked the phase tracking loop takes over and provides a phase comparison between the input data D(in), and the (VCO) output clock (Recovered Clock) through the (PD) and produces a control voltage through (CP) and (LF) to lock the (VCO) oscillation phase onto the input data phase [8].
Blind Oversampling CDR
Figure 14: A block diagram of a blind oversampling CDR, Bit boundary detection, and data sample selection [6].
The multiple phase clock generator block generates multiple mutually phase-shifted clocks that are uniformly distributed over one period of the data signal (also called the Unit Interval – UI) depending on the oversampling rate (M) so
the bit period is divided into M equally spaced sampling domains. Each generated clock triggers one of the parallel samplers (also called Oversampler) once every cycle to sample the data bit in its domain. Once the samples are collected, the Sample Storage unit stores the sample and moves them into the local clock domain. The bit boundary detection detects the data transition and selects the most reliable data samples that is as close to the center of the data eye as possible, assuming that within the decision window spanned by the collected samples, the unit intervals for each bit are equal (the bit boundary will reappear every M samples) and each unit interval contains the same number of samples [7] [8] [10] [11] [12].
Clock Domain Crossing (CDC)
CDC can be defined as transferring signals between asynchronous clock domains in multiple asynchronous clock domains system in a safe way in order to avoid setup or hold timing violations of flip-flops that could lead to meta-stability. A clock domain is a part of a design operating by a clock asynchronous to (or has a variable phase relationship with) another clock in the design. See Figure 15 (taken from [13] figure 2&3, page 2) for illustration.
Domain A Domain B
Figure 15: Clock Domain Crossing and Meta-Stability [13].
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long as the FIFO is not empty. A dual port memory is used for the FIFO storage and control signals such as FIFO is empty, full, almost-full, and almost-empty are used [14]. Figure 16 (taken from [15] figure 3-22, page 121) depicts a CDC asynchronous FIFO from XILINX.
2.2.5. Digital Communication System Performance Quality
In a digital communication system, the sources of the error come from two types of degradations. The first is deterministic impairments that come from the imperfections in the channel. The presence and effects of these impairments are predictable and generally are not cost effective to remove. The second is random impairments that come from external influences and disturb the signal in an unpredictable fashion [16]. Errors in digital communication usually result from a combination of several impairments, all of which act so as to reduce the differences between the signal waveforms to the point where a small additional impairment causes an error [16]. As a result of this degradations “The transmitter may send incorrect data; the signal may be altered along the transmission path, and the receiver may make incorrect bit decision” [17]. Therefore, an overall evaluation of the performance of the communication systems is needed. “The most accurate method of assessing the quality of the information delivered to the receiver is to compare the received information to that transmitted” [16] and any discrepancies between the received and the transmitted bit is flagged as an error. Bit Error Ratio (BER) is a widely used quantitative accuracy parameter to express how well the overall communication system performs [18] [19].
Bit Error Ratio (BER)
“The BER represents the ratio of the number of bits received in error to the total number of bits transmitted ” [18].
=
Equation 1: Bit Error Ratio.
BER also can be viewed as the probability of bit error ( ). The accuracy of BER is depends on the number of transmitted bits. As it is impossible to transmit an infinite number of bits to calculate the real ( ) because it requires infinite time, a sufficient estimation ( ) that prove that the ( ) is less than some upper limit is usually enough.
( ) =
→
⎯⎯⎯ ( )
Equation 2: Estimation of BER.
To ensure that ( ) is an accurate estimation of the true ( ), the number of transmitted bits needs to be enough. The number of bits depends on the desired BER Confidence Level (CL) which is defined as the probability, based on detected errors out of bits transmitted, that the actual ( ) probability is better than a specified level, (such as 10 ). Mathematically, this can be expressed as:
= [ ( ) < | , ]
Equation 3: BER Confidential Level.
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= ( > | ) = 1 − !
! ( − )! ( ) (1 − )
Equation 4: Confidential Level with Cumulative Binomial Distribution Function.
( ) = !
! ( − )! ⎯⎯→
( )
!
Equation 5: Estimation of Binomial Distribution Function by Poisson Theorem.
By combining Equation 4 and Equation 5, and then solving it for n, we can calculate the total number of bits that must be transmitted through the system in order to achieve a desired confidence level that ( ) is less than by using Equation 6.
= −ln (1 − )+
∑ ( )
!
Equation 6: Total number of bits must be transmitted for the desired confidence level.
An example of BER estimation is shown in Table 1.
Table 1: Example of BER Estimation.
CL=99% , p=10-10
Bit Errors N 0 1 2 3 4
Required bits n 4.16*1010 6.64*1010 8.40*1010 1.00*1011 1.16*1011
Note: The section above is a summery from [20] and [19]. For details refer to the
original discussions in the mentioned sources.
Bit Error Ratio Test (BERT)
BERT is composed of a Pattern Generator (PG) that generate and sends a known data stream to a Device Under Test (DUT), and an Error Detector (ED) that conducts a bit-by-bit comparison between the received signal from the DUT and the values generated in same fashion that used in the Pattern Generator and then records the bit errors [19]. An overview of BERT architecture shown in Figure 17 (adapted from [16] figure 7, page 812).
Pattern Generator PG
Device Under Test DUT Digital Communication System Error Detector ED
Figure 17: Bit Error Ratio Test.
Pattern Generator PG Line Driver Transmitter ---Receiver Line Driver Receiver ---Transmitter Error Detector ED
Device Under Test Digital Communication System Backplane Pattern Generator PG Error Detector ED Line Driver Transmitter ---Receiver Backplane
Device Under Test Digital Communication
System
Figure 18: Testing configuration of BERT.
Device Under Test (DUT)
The DUT (communication system) is transparent to the test. It could be passive devices (e.g., connectors, cables, and backplanes) or simple active devices (e.g., line buffers) to the entire transmission systems [17].
Pattern Generator (PG)
In order to test the digital communication system, a predefined known digital test sequence, also called a stress pattern, which stimulates the input of the digital communication system and simulates the traffic is needed. To detect an error, the error detector must know the exact transmitted test pattern and the location of each bit, so it can perform bit-by-bit comparison. Therefore, the test pattern must be completely deterministic, reproducible and predictable for the error detector. This test pattern is usually a Pseudo-Random Binary Sequence (PRBS) or specific user-defined word patterns generated by the pattern generator [21]. A common approach to generate PRBS is to use Linear Feedback Shift Register (LFSR) as shown in Figure 19 adapted from [16] figure 9, page 813. D1 D2 Dn-1 Dn Output Transmitted Sequence Mod 2 Adder
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An appropriate choice of the location of the feedback node and the maximal
length sequence (2 − 1 ; : . ) for the LFSR are chosen as a
compromise between “the desire to obtain as close an approximation to randomness as possible and simulation of real traffic, and the cost of hardware required to implement the pattern generator and synchronize the error detector” [16]. The LFSR is usually defined by a polynomial, + + 1 = 0 that determines where the feedback connections are made.
Recommendations O.151, O.152, and O.153 by ITU-T contain standardized PRBS patterns for testing a digital communication system. Table 2 shows a summary of this recommendation [22].
Table 2: ITU-T standardization for PRBS.
Length of sequence
(bits)
Recommendation Bit Rate/s
2^9 – 1 O.153 up to 14400 bit/s
2^11 – 1 O.152 64 kbit/s and N × 64 kbit/s
2^15 – 1 O.151 1544, 2048, 6312, 8448, 32064 and 44736 kbit/s
2^20 – 1 O.153 up to 72 kbit/s
2^20 – 1 O.151 1544, 6312, 32064 and 44736 kbit/s
2^23 – 1 O.151 34368 and 139264 kbit/s
2^29 – 1 – Specific measurement tasks
2^31 – 1 – Specific measurement tasks
Error Detector (ED)
D1 D2 Dn-1 Dn Synchronaization Mod 2 Adder Received Sequence Error Counter Comparator Detection
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2.3. Introduction to Bombardier’s Object Controller LVDS-Link Communication System
The LVDS-Link communication system connects different functional units of Bombardier’s Object Controller System. Each functional unit contains an FPGA that provides support for the LVDS-Link channel interface. The firmware2 for the FPGA is
implemented using VHDL. The LVDS-Link communication system interface is specified in different layers as the stack in Figure 21depict.
Safety Layer Safety Layer
Presentation Layer CIS-OCS
Session Layer CIS-OCS
Transport Layer UDP
Network Layer IPv4
Data Link Layer Ethernet
Physical Layer LVDS
Figure 21: Stack Models for LVDS-Link.
2 Firmware is a term used for FPGA code even though it is originally defined as software. Refer to
Figure 22 depicts a functional block diagram for the LVDS-Link communication system.
LVDS-Link Transceiver LVDS-Link
Interface LVDS-Link Channel
LVDS-Link Interface LVDS-Link Transceiver Traffic Management Center
Figure 22: Functional Block Diagram For LVDS-Link communication system.
The LVDS-Link transceiver with the LVDS-Link channel is the new physical interface for communication with the wayside objects and the main topic of this thesis work. The LVDS-Link physical channels, PCB traces on the Backplane, are already implemented but they are lacking support from the FPGA to be activated. Activating the LVDS-Link will introduce many benefits to the system in terms of performance.
LVDS-Link is superior to RS485-Link in term of speed. RS485-Link is currently running on 500Kbps baud rate and it needs an external transceiver which has 5Mbps as maximum signaling rate. On the other hand, LVDS-Link uses LVDS standard and can run on higher speed depending on the switching characteristics and clock resources of the used FPGA. In addition, LVDS-Link does not need an external transceiver as it can exploit the Differential SelectIO Buffer Primitives (IBUFDS/OBUFDS) available in Xilinx’s FPGA [23].
The LVDS-Link Interface module is carried out by my college Elena Migliorin and the LVDS-Link Transceiver module is carried out by me.
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3. LVDS-Link Implementation and Testing
This section covers LVDS-Link transceiver implementation and explains the verification methodology used for testing.
3.1. LVDS-Link UART Implementation
A decision of using the already implemented and tested UART as LVDS-Link transceiver has been taken by the supervisors.
The UART module is a simple UART that transmit and receive serial data with one start bit and one stop bit (See Figure 23).
Figure 23: UART Transmission/Reception Protocol.
Figure 24 depicts the UART top module and Table 3 presents a description of its interface. serial_i serial_o data_i data_o write_i empty_o read_i full_o divisor_i overRun_o frameError_o
Table 3: UART interface Description.
Signal Name Value Description
Input
s
Serial_i --- Port to receive incoming serial data from the
transmitter.
Data_i[] --- Port for the word desired to be transmitted by the UART transmitter.
Write_i ‘1’ Control signal indicates that there is data presented on
the input port (data_i).
Read_i ‘1’ Control signal indicates that the data presented on the
output port (data_o) has read.
Divisor_i[] --- Port for choosing the desired baud rate for
transmitting and receiving.
Out
put
s
Serial_o --- Port to transmit serial data to the receiver.
Data_o[] --- Port for the word received by the UART receiver.
Empty_o ‘1’ Control signal indicates that the UART receiver is free. Full_o ‘1’ Control signal indicates that the UART transmitter is
busy.
OverRun_o ‘1’ Control signal indicates the new data has been received without the output port being read.
Page | 36 3.2. Verification Methodology
The used verification method is based on implementing a PC Communication UART and testbench beside the DUT in the FPGA. The PC Communication UART is used to handle the communication between the computer and the testbench. It receives the testbench stimulus (test order) from the PC and sends the testbench feedback (test result) to the PC. The testbench executes the test order received from the computer via the PC Communication UART by applying the test cases on the DUT and produces the test result to be sent back to the PC via the PC Communication UART. See Figure 25 for an overview of the architecture of the verification method.
UART SERIAL MONITOR DUT TEST CASES FEEDBACK TEST ORDER TEST RESULT
Figure 25: Architecture of the Verification Method.
In addition, software simulators (ModelSim3 and ISim4) are used to verify the design
and a Tektronix mso70404c oscilloscope5 with a differential probe is used to capture,
display, and analyze the signal of interest.
4. LVDS-Link Channel Stress Test
In order to determine the LVDS-Link channel capacity, a BERT (see section 0 on page 28) has been conducted to determine the upper limit for the LVDS-Link channel.
Three experiments have been conducted:
1- Stress test with LVDS-Link UART and Generic FIFO. 2- Stress test with LVDS-Link UART and CDC FIFO. 3- Stress test with LVDS-Link Blind Oversampling CDR.
Each experiment is explained in a separate section following this segmentation: 1- Test setup and component explanation.
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4.1. Stress Test with LVDS-Link UART Implementation
Two testing experiments for LVDS-Link UART implementation have been conducted. The first experiment involved using GenericFIFO with the LVDS-Link UART and the second one involved using CDC FIFO with the LVDS-Link UART.
4.1.1. Stress Test with LVDS-Link UART and Generic FIFO Implementation
The test platform is built following the one-way scheme (see section 0 on page 28) by using two DC_Board, designated as Mainboard and Secondary_board, mounted on a mini-backplane6. The FPGA in the Mainboard contains the Receiver LVDS-Link UART
and the Error Detector. The FPGA in the Secondary_board contains the Transmitter LVDS-Link UART and the Pattern Generator. Only one LVDS-Link channel, LVDS-Link
_o[0], is tested. In both boards, there is a PC Communication UART that communicate
with a PC to control and log information about the test. The used serial monitor is Tera
Term [24] with baud rate 115200Kbit on both boards. Figure 26 depicts an overview of
the test setup.
LVDS-Link UART LVDS-Link_o[0] P C U A R T ERROR DETECTOR PATTERN GENERATOR LVDS-Link UART CONTROL PC UART CONTROL Serializer SERIAL MONITOR SERIAL MONITOR
Figure 26: LVDS-Link UART with Generic FIFO Stress Test Setup.
Device Under Test (Communication System)
The DUT in the test covers the transmitter and the receiver LVDS-Link UART module and the physical link in the mini-backplane. The LVDS-Link UART is comprised of UART, generic outbound FIFO, generic inbound FIFO, and Digital Filter as shown in Figure 27.
Serial Filter UART outboundFIFO inboundFIFO Serial_i Serial_o Data_o Data_i RX TX
Figure 27: LVDs-Link UART Block Diagram.
The UART module reads a word from the outbound FIFO and transmits it or receives serial data through the Serial Filter and writes it in the inbound FIFO. The Serial Filter cleans the received signal by oversampling the signal by three and select the output (‘0’ or ‘1’) depending on the majority. The inbound FIFO and the
outbound FIFO are generic dual-port memory buffers. This module was provided by
the company and was not modified.
Pattern Generator and the Error Detector Modules
The Pattern Generator and the Error Detector modules are based on T.Gaertner’s design in [25]. A few modifications have been made so the modules can be integrated into the test. The PRBS used in the Pattern Generator and the Error Detector is a 32767-bit pseudo-random test sequence built by a fifteen-stage LFSR whose 14th and 15th stage outputs are added in a modulo-two addition stage, and the result is fed back to the input of the first stage.
The outputs of the Pattern Generator and the Error Detector are explained in Table 4.
Table 4: Output signal for Pattern Generator and Error Detector.
Module Output signal Description
Pattern Generator
TX_BYTE[0..8] A random 9-bits output from PRBS. This signal is mapped to the data port in the UART outbound FIFO.
UARTWRITE Write enable for the UART outbound FIFO.
SEQ_DONE
An indicator that the LFSR completed a full sequence. High ‘1’ for one clock cycle when LFSR is x“7FFF” otherwise Low ‘0’.
Used to count the number of sent sequence from the Pattern Generator.
Error Detector
SYN_STATE
An indicator that the two LFSR’s are synchronized. Goes to high ‘1’ when 30 (15 for loading and 15 for testing that it is error-free bits) error-free bits are received.
Goes to low ‘0’ if the error rate exceeds 0.2.
SYN_LOS Indicator for loss of synchronization.
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synchronization is lost.
ERROR_CNT Output the number of the detected error bit.
Serializer Module
As the Error detector is designed to receive a serial input, a serializer module has been added between the 9-bit UART and the Error Detector to serialize the 9-bit output of the 9-bit UART inbound FIFO to the Error Detector.
Control Module
This module is responsible for starting the test upon receiving an order from the PC via the PC Communication UART and logging the test result back to the PC. It is also Starts\Stops the Pattern Generator and the Error Detector based on monitoring the
outbound FIFO and inbound FIFO respectively. The Pattern Generator and the Error
Detector are running on the system clock which is much higher than the baud rate. Therefore, they must be controlled (Start\Stop) to avoid reaching the FULL condition of the outbound FIFO in the UART of the Pattern Generator and the EMPTY and OVERRUN conditions of the inbound FIFO in the UART of the Error Detector. The size of the FIFO is 9*4096. The Start/Stop signals are triggered depending on the used space of the FIFO. Figure 28 is depicting the FIFOs behavior.
4 0 96 START WRITING STOP WRITING 16 Almost EMPTY 4000 Almost FULL 4 0 96 STOP READING START READING 16 Almost EMPTY 4000 Almost FULL 9-bits 9-bits
Test Flowchart
Figure 29 depicts the state machine and the test flow chart of the transmitter which reside in the SECONDARY_BOARD.
Start Start Test? From PC Start PG? From ER Start PG Write to outboundFIFO OutboundFIFO almost FULL? OutboundFIFO almost EMPTY? Stop PG No. Sequences = test end? OutboundFIFO FULL or EMPTY YES YES YES YES YES YES NO NO NO NO Stop Test OutboundFIFO EMPTY? NO NO NO
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Figure 30 depicts the state machine and the test flow chart of the receiver which reside on the MAINBOARD.
Start Start Test? From PC Trigger PG to start Start ER Read from inboundFIFO inboundFIFO almost EMPTY? inboundFIFO almost FULL? Stop ER
Free place in the SR_Serializer? YES YES YES YES NO NO NO NO Update SR_Serializer boundFIFO Filled? NO SR serializer filled with 3 elements? NO YES YES PG Finished & inboundFIFO EMPTY inboundFIFO EMPTY or OVERRUN or SYNC_LOSS NO Stop Test Serialize to ER YES YES NO
Test case
The test has been conducted on the parameters presented in Table 5.
Table 5: LVDS-Link with generic FIFO Stress Test Parameters.
Parameter Value Notes
BE
R
Confidential Level 99% See 0
Probability of Error 10-10 See 0
Number of sent bits 1.16*1011 See 0
Bit Errors 4 See 0
Baud rate Clock Number of Errors
50 Mbps 200 MHz No Errors
Test Result
The eye diagram and the period histogram for 100 MHz baud rates has been made to see the signal integrity. There is a reflection as the mini-backplane is only for development purposes and the trace impedances are not balanced and matched. Nevertheless, the eye is open as shown in Figure 32.
The test result obtained by the report from the secondary UART. No errors happened. Figure 31 shows an example of the results.
Figure 31: Result for LVDS-Link UART with Generic FIFO from Serial Terminal.
The first picture shows the various states that the Transmitter goes through and the number of the sequences that have been sent. The second picture shows the various states that the Receiver goes through and the result as follow:
MSG No. of Errors No. of stops for Error Detector No. of starts for Error Detector
number of 9-bits word received
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The MSG field has three options as follow:
MSG Description
ERR The test finished correctly without losing synchronization.
OVR The test has been terminated because an Overrun happened. (inbound FIFO is FULL)
SYL
The test has been terminated because of the loss of synchronization between the two LFSRs inside the Pattern Generator and the Error Detector respectively. (more the 25 errors occurred)
Discussion
Even though the test succeeded without errors, this design is not practical for three reasons:
1- The whole design must be clocked by the high clock (200 MHz) in order to make it work and the synchronization is achieved using a common clock for both write and read domains in the FIFO. Therefore, a FIFO with clock domain crossing feature is needed and this led to the second experiment which is described in the next section.
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4.1.2. Stress Test with LVDS-LINK UART and CDC FIFO Implementation
This experiment’s setup is very similar to the first experiment (section 4.1.1 on page 38) but differs in two things to overcome the drawbacks in the first experiment:
1- The inbound FIFO and the outbound FIFO are replaced by FIFOs generated using Xilinx Core Generator that supports clock domain crossing. The inbound
FIFO and the outbound FIFO are now working as a domain boundary which
allows the LVDS-Link transceiver (running in high-speed) to be separated from the rest of the design (running in the system clock).
2- The regular backplane is used instead of the mini-backplane to get rid of the reflection.
Another two differences are:
1- Using a different pattern generator (PN23 [26]) that produce 8 bits each clock cycle and the comparison is now carried out byte by byte instead of bit by bit. Therefore, the exact number of bit error cannot be determined precisely because of the byte comparison but this has been done for simplicity.
2- Using ChipScope Pro Analyzer7 [27] to debug the system and monitor the status
of the signals.
Figure 33 depicts an overview of the test setup.
LVDS-Link UART LVDS-Link_i[0] ERROR DETECTOR PATTERN GENERATOR LVDS-Link UART CONTROL PC UART CONTROL SERIAL MONITOR SERIAL MONITOR PC UART
ChipScope ILA ChipScope ILA
ChipScope Pro ChipScope Pro Oscilloscope
Figure 33: LVDS-Link UART with CDC FIFO Stress Test Setup.
Device Under Test (Communication System)
The DUT in this experiment covers the transmitter and the receiver LVDS-Link UART modules and the longest physical link (PCB trace) in the backplane. The LVDs-Link UART differs than the previous DUT that used in the first experiment by using CDC FIFO instead of the generic FIFO. See Figure 34.
UART OutboundData_o RX TX Writing Domain Reading Domain OutboundData_i Writing Domain Reading Domain InboundData_o InboundData_i CLK_UART CLK CLK
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Pattern Generator and the Error Detector Modules
The Pattern Generator and the Error Detector modules are based on [26]. A sequence finish indicator has been added to the design (refer to pn23.vhd) so the modules can be integrated into the test. The Pattern Generator and the Error Detector are implemented using Pseudo Noise (PN) built by twenty-three stage LFSR which its [10th and 15th], [11th and 16th], [12th and 17th], [13th and 18th], [14th and
19th], [15th and 20th], [16th and 21st], and [17th and 22nd] stages outputs are added in a
modulo-two addition stage, and the result is fed back to the input [0..7] stages respectively in order to produce 8 bits each clock cycle.
Control Module
This module is responsible for starting the test upon receiving an order from the PC via the PC Communication UART and logging the test result back to the PC. It is also controlling the Start\Stop for the Pattern Generator and the Error Detector based on monitoring the CDC outbound FIFO and inbound FIFO respectively. The Pattern Generator and the Error Detector must be controlled (Start\Stop) to avoid reaching the FULL condition of the outbound FIFO in the LVDS-Link UART of the CPU_Board (Transmitter) and the EMPTY conditions of the inbound FIFO in the LVDS-Link UART of the DC_Board (Receiver). The size of the FIFO is 8*256. The Start/Stop signals are triggered depending on the Read data count (inboundrdcnt_o) for the Error Detector and Write data count (outboundwrcnt_o) for the Pattern Generator.
Note: “Read data count (RD_DATA_COUNT) pessimistically reports the number of
words available for reading. The count is guaranteed to never over-report the number of words available in the FIFO (although it may temporarily under-report the number of words available) to ensure that the user design never underflows the FIFO. Write data count (WR_DATA_COUNT) pessimistically reports the number of words written into the FIFO. The count is guaranteed to never under-report the number of words in the FIFO (although it may temporarily over-report the number of words present) to ensure that you never overflow the FIFO” [15].
Figure 35 is depicting the behavior.
2 5 6 START WRITING STOP WRITING 10 Almost EMPTY 245 Almost FULL 2 5 6 STOP READING START READING 10 Almost EMPTY 200 Almost FULL 8-bits 8-bits
Test Flowchart
Figure 36 depicts the state machine and the test flow chart of the transmitter which reside in the CPU_Board.
Start Start Test? From PC Start PG? From ER Sequence finished? Finish Test? From ER YES YES YES YES NO NO Stop Test OutboundFIFO EMPTY? NO NO NO Start PG Write to outboundFIFO OutboundFIFO almost FULL? OutboundFIFO almost EMPTY? Stop PG YES YES NO NO Increment Sequence Counter Report Sequence Number FIFO Reseted? NO YES YES
Page | 50
Figure 37 depicts the state machine and the test flow chart of the receiver which reside in the DC_Board.
Start Start Test? From PC Start PG in MIO_Board Sequence finished? Error > 25 or nboundFIFO is EMPTY or
seq_cnt = test end YES YES NO NO Stop Test Stop PG in MIO_Board NO Start ED Read from InboundFIFO InboundFIFO almost EMPTY? InboundFIFO almost FULL? Stop ED YES YES NO NO Increment Sequence Counter
Report Error and Sequence Number FIFO Reseted? NO YES YES Received correct? YES NO Increment Error Counter FCF0FF received? Framed, Initialize ED YES NO
Test case
The test has been conducted on the parameters presented in Table 6.
Table 6: LVDS-Link with CDC FIFO Stress Test Parameters.
Parameter Value Note
BE
R
Confidence Level 99% See 0
Probability of Error 10-10 See 0
Number of sent bits 1.16*1011 See 0
Bit Errors 4 See 0
Baud rate Clock Number of Errors
50 MHz 200 MHz No Errors
Test Result
The eye diagram and the period histogram for 50 MHz baud rate has been made to see the signal integrity. There is no reflection and the eye is open as shown in Figure 38 for LVDS-Link[0].
The test was completed successfully without any error recorded as the reported result from Chipscope Pro Analyzer shows in Figure 39 and Figure 40 and from the serial terminal in Figure 41.
Note: the error appears in err_cnt in Chipscope’s and the serial terminal’s
snapshots is produced from the first comparison when the Error Detector is initialized to become synchronized with the Pattern Generator and does not count as bit errors.
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Figure 39: Snapshot from ChipScope of the Transmitter and Receiver for LVDS-Link UART with CDC FIFO Stress Test at 50MHz.
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Figure 41: Result for LVDS-Link UART with CDC FIFO from Serial Terminal.
Discussion
The second experiment is more realistic in terms of the test setup as the new test setup, using Backplane, matches the setup in real life. In terms of functionality, using CDC FIFOs restrict the fast clock only within the transceiver block (LVDS-Link UART), and in terms of verification accuracy, using ChipScope Pro to verify the result add more credibility to the result.
4.2. Stress Test with LVDS-Link CDR Implementation
In order to achieve a higher data rate in the self-synchronous serial link system, a CDR circuit is needed (See section 0 on page 23). Therefore, two CDR approaches have been investigated as an alternative to LVDS-Link UART implementation. The first approach is based on a PLL-Based CDR (See section 0 on page 23). It can be implemented by using the High-Speed IOSERDES2 advanced SelectIO logic resource primitive available in Xilinx’s FPGA with a High-Speed I/O Clock generated by the PLL [23] [29].
Figure 42 (taken from [29] figure 1-16, page 33) depicts this approach.
Figure 42: Basic PLL IOSERDES2 Architecture.
The second investigated approach is based on Blind Oversampling CDR (See section 0 on page 24). It can be implemented by using the DCM or PLL primitives available in the FPGA to generate the multiple mutually phase-shifted clocks required for sampling the data stream.
After an overview study of the two possible solutions, a decision of proceeding with the Blind Oversampling CDR solution was taken based on two reasons:
1- Simplicity: from the overview study, the Blind Oversampling CDR solution seems easier than PLL-Based CDR solution. Simplicity was an important factor because of time limitation.
2- Availability of reference example design.
Thus, this section will continue with an explanation of the chosen Blind Oversampling CDR and then follow the same segmentation used before (See section 4 on page 37).
4.2.1. 5x Blind Oversampling CDR Overview
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Figure 43: 5x Blind Oversampling CDR Architecture [10].
Multiphase Clock Generation
The incoming system clock (single-ended 25MHz) is fed to a two DCMs primitive two clocks with a frequency that is 5/4 of the desired data rate. One DCM provides a CLK clock and the other DCM provides CLK90, a delayed version by 90 degrees, using the fixed phase shift feature available in Xilinx’s devices (See Figure 44 taken from [26] figure 2, page 2).
Figure 44: Clock Generation Using Two DCM in the FPGA [26].
CDR Core
Figure 45 (taken from [10] figures 2&4, page 75&76 [30] figure 2, page 157) shows an illustration 5x blind oversampling CDR the optimum sampling phase selection for (M=5) and the hardware implementation of Ccnt.
Figure 45: Operation Illustration For 5x Blind Oversampling CDR and Hardware Implementation of Ccnt Algorithm [10] [30].
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4.2.2. Test Setup with 5x Blind Oversampling CDR
This experiment’s setup is similar to the second experiment (section 4.1.2 on page 46) but differs in using the 5x blind oversampling CDR and Serializer instead of the LVDS-Link UART modules in DC_Board and CPU_Board respectively.
Note: a reference example provided by the author (Michal KUBÍČEK) of [10] is used
with minor modification.
Figure 47 depicts an overview of the test setup.
BO CDR LVDS-Link_i[0] ERROR DETECTOR PATTERN GENERATOR Serializer CONTROL PC UART CONTROL SERIAL MONITOR SERIAL MONITOR PC UART
ChipScope ILA ChipScope ILA
ChipScope Pro ChipScope Pro
Oscilloscope
Figure 47: LVDS-Link CDR Stress Test Setup.
Device Under Test (Communication System)
The DUT in this experiment covers the serializer, the receiver LVDS-Link CDR modules, and the longest physical link (PCB trace) in the backplane.
Pattern Generator and the Error Detector Modules
The Pattern Generator and the Error Detector in this experiment is the same one used in the previous experiment (Stress Test with LVDS-LINK UART and CDC FIFO Implementation).
Control Module
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Test Flowchart
Figure 48 depicts the state machine and the test flow chart of the transmitter that resides in the CPU_Board.
Start Preamble Finished? NO Report Sequence Number Start Test? From PC NO YES YES Finish Test? From ER YES NO Stop Test
Figure 49 depicts the state machine and the test flow chart of the transmitter that resides in the DC_Board.
Start Start Test? From PC Start PG in MIO_Board Sequence finished? Error > 25 or nboundFIFO is EMPTY or
seq_cnt = test end
YES YES NO NO Stop Test Stop PG in MIO_Board NO Increment Sequence Counter
Report Error and Sequence Number YES Received correct? YES NO Increment Error Counter FCF0FF received? Framed, Initialize ED YES NO
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Test case
The test has been conducted on the parameters presented in Table 7.
Table 7: LVDS-Link CDR Stress Test Parameters
Parameter Value Note
BE
R
Confidence Level 99% See 0
Probability of Error 10-10 See 0
Number of sent bits 1.16*1011 See 0
Bit Errors 4 See 0
Baud rate Clock Number of Errors
100 MHz 125 MHz Failed
200 Mhz 250 MHz Failed
Test Result
At 100 MHz, sometimes it succeeded and sometimes failed (See Figure 50 and Figure 51). It has been noticed from ChipScope that sometimes the data recovered by CDR are shifted by one or two bits either to the right or to the left. At 200 MHz it failed all the time.
Figure 50: Snapshot from Isim of the simulation result for LVDS-Link CDR Stress Test.
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Discussion
Conclusion
Page | 68
Future Work
Several paths could be followed as a continuation of this thesis;
1- Continue to debug the LVDS-Link CDR implementation and integrate it into the design.
2- Investigate other possible blind oversampling solution such as the solution in [32] which use DDR Asynchronous Sampling Delay Line and the solution in [31] which use IDELAY-based oversampler. Both solutions use a single DCM to reduce the clock phase jitter problem. Another solution is to use the SERDES primitive for oversampling, as in [33] and [34]. This has an advantage that the sampling flip-flops are moved from the Configurable Logic Block (CLB) to inside the SERDES which make them close to each other. A newer FPGA version has already implemented oversampling mode for SERDES but similar functionality can be achieved.
3- Investigate other possible Digital PLL-Based CDR solution such as the one proposed in [35] which use the phase shift feature of the DCM.
4- A jitter study could be carried out based on the LVDS-Link UART with CDC FIFO Implementation.
