Department of Electrical Engineering
Examensarbete
Read and Write Circuits for Ferroelectric Memory
Using Printed Transistor Technologies
Examensarbete utfört i Elektroniska kretsar och system vid Tekniska högskolan vid Linköpings universitet
av
Fredrik Blomgren
LiTH-ISY-EX--15/4832--SE
Linköping 2015
Department of Electrical Engineering Linköpings tekniska högskola
Linköpings universitet Linköpings universitet
Examensarbete utfört i Elektroniska kretsar och system
vid Tekniska högskolan vid Linköpings universitet
av
Fredrik Blomgren
LiTH-ISY-EX--15/4832--SE
Handledare: Dr. Niklas U. Andersson
Thin Film Electronics AB
Joakim Alvbrant
isy, Linköpings universitet
Examinator: Dr. J Jacob Wikner
isy, Linköpings universitet
Department of Electrical Engineering SE-581 83 Linköping 2015-05-29 Språk Language Svenska/Swedish Engelska/English Rapporttyp Report category Licentiatavhandling Examensarbete C-uppsats D-uppsats Övrig rapport
URL för elektronisk version
ISBN — ISRN
LiTH-ISY-EX--15/4832--SE Serietitel och serienummer
Title of series, numbering ISSN—
Titel
Title Kretsar för Skrivning och Läsning av Ferroelektriska Minnen med Tryckta Transistorteknolo-gier Read and Write Circuits for Ferroelectric Memory Using Printed Transistor Technologies
Författare
Author Fredrik Blomgren
Sammanfattning Abstract
Printed electronics holds the promise of adding intelligence to disposable objects. Low tem-perature additive manufacturing using low-cost substrates, less complex equipment and fewer processing steps allow drastically reduced cost compared to conventional silicon cir-cuits. Ferroelectric memories is a suitable technology for non-volatile storage in printed circuits. Printed organic thin film transistors can be used for logic. Another approach is to reduce the complexity of silicon manufacturing by substituting as many steps as possible for printed alternatives and substitute silicon wafers for cheaper substrates, one such process is printed dopant polysilicon. This thesis explores the possibility of designing circuits using these two transistor technologies for reading and writing ferroelectric memories. Both gen-eration of the voltage pulses necessary for memory opgen-eration from a lower supply voltage and the interpretation of the memory response as one of two states is investigated. It is con-cluded, with some reservations, that such circuitry can be implemented using the polysilicon process. Using organic thin film transistors only the latter functionality is shown, generation of the necessary voltage pulses is not achieved but also not completely precluded.
Nyckelord
Keywords Printed electronics, Organic thin-film transistors, Printed dopant polysilicon, Ferroelectric memory
Printed electronics holds the promise of adding intelligence to disposable objects. Low temperature additive manufacturing using low-cost substrates, less complex equipment and fewer processing steps allow drastically reduced cost compared to conventional silicon circuits. Ferroelectric memories is a suitable technology for non-volatile storage in printed circuits. Printed organic thin film transistors can be used for logic. Another approach is to reduce the complexity of silicon manufacturing by substituting as many steps as possible for printed alternatives and substitute silicon wafers for cheaper substrates, one such process is printed dopant polysilicon. This thesis explores the possibility of designing circuits us-ing these two transistor technologies for readus-ing and writus-ing ferroelectric memo-ries. Both generation of the voltage pulses necessary for memory operation from a lower supply voltage and the interpretation of the memory response as one of two states is investigated. It is concluded, with some reservations, that such circuitry can be implemented using the polysilicon process. Using organic thin film transistors only the latter functionality is shown, generation of the necessary voltage pulses is not achieved but also not completely precluded.
I would like to thank my colleagues at Thinfilm Electronics, especially my su-pervisor Dr. Niklas Andersson, for guidance and feedback. Thanks also goes to my examiner, Dr. J Jacob Wikner, and supervisor, Joakim Alvbrant, at Linköping University. Certainly not least I would like to thank friends and family for their support and welcome distractions, with a special thanks to my Cecilia.
Linköping, February 2015 Fredrik Blomgren
Notation xi 1 Introduction 1 1.1 Background . . . 1 1.2 Thesis Purpose . . . 2 1.2.1 Goals . . . 2 1.3 Delimitations . . . 3 2 Theory 5 2.1 Ferroelectric Memories . . . 5
2.2 Organic Thin Film Transistors . . . 6
2.3 Printed Dopant Polysilicon Transistors . . . 8
2.4 Memory Read and Write Circuits . . . 8
2.4.1 Memory Readout Circuitry . . . 9
2.4.2 Memory Drive Circuitry . . . 11
3 Method and Tools 15 3.1 Modelling and Simulation . . . 15
3.2 Manufacturing . . . 18
3.3 Measurements . . . 18
3.4 Data Analysis and Visualisation . . . 19
4 System and Components 21 4.1 Available Processes and Components . . . 21
4.1.1 Ferroelectric Memories . . . 21
4.1.2 Transistors . . . 23
4.1.3 Passive Components, Diodes and Batteries . . . 23
4.2 System Overview . . . 25
5 Results 27 5.1 Memory Readout Circuitry Overview . . . 28
5.2 OTFT Memory Readout Circuitry . . . 28
5.2.1 OTFT Integrator Modelling and Simulation . . . 28
5.2.2 OTFT Sawyer-Tower Modelling and Simulation . . . 31
5.2.3 OTFT Sawyer-Tower Assembly and Measurements . . . 36
5.3 PDPS Memory Readout Circuitry . . . 42
5.3.1 PDPS Sawyer-Tower Modelling and Simulation . . . 42
5.4 Memory Drive Circuitry Overview . . . 46
5.4.1 Switched Capacitor Voltage Multiplier . . . 48
5.4.2 Dickson Charge Pump . . . 49
5.5 OTFT Dickson Charge Pump . . . 54
5.5.1 With Zinc Oxide Diodes . . . 54
5.5.2 With Diode Connected OTFTs . . . 61
5.5.3 Pulsed Charge Pump . . . 61
5.6 PDPS Dickson Charge Pump . . . 65
5.6.1 Pulsed Charge Pump . . . 71
5.7 OTFT Complete Memory Circuitry . . . 76
5.8 PDPS Complete Memory Circuitry . . . 79
5.8.1 Pump Output Formed into Pulse . . . 80
5.8.2 Pump Started and Stopped to Form Pulse . . . 85
6 Discussion 89 6.1 Results . . . 89
6.1.1 Memory Readout Circuitry . . . 90
6.1.2 Memory Drive Circuitry . . . 91
6.1.3 Comparison of Pulse Formation Approaches . . . 93
6.2 Method . . . 95
6.2.1 Clock Generator Approximation . . . 95
6.2.2 Circuit Design Considerations . . . 96
6.2.3 Memory Considerations . . . 97
6.2.4 Parameter Selection . . . 98
6.2.5 Circuit Robustness . . . 99
6.2.6 Data Analysis and Visualisation . . . 100
6.3 Review of Reference Material . . . 101
7 Conclusions 103 7.1 OTFT Circuits for FE-Memories . . . 103
7.2 PDPS Circuits for FE-Memories . . . 104
7.3 Goals . . . 104
7.4 Future Work . . . 105
7.4.1 OTFT Circuits for FE-Memories . . . 105
7.4.2 PDPS Circuits for FE-Memories . . . 105
7.4.3 Memory Properties . . . 106
7.4.4 Power Consumption . . . 106
A Amorphous-Si TFT Model ASIA2 (Level 15) 109 A.1 Model Parameters . . . 110
A.2 Equivalent Circuit . . . 111
A.4 Drain Current Equations . . . 111
A.5 Temperature Dependence . . . 113
A.6 Capacitance Equations . . . 113
B Additional Results 115 B.1 Inductive DC-DC Converters . . . 115
B.2 Switched Capacitor Multiplier . . . 117
B.3 Dickson Charge Pump with Ideal Diodes . . . 121
B.4 OTFT Dickson Charge Pump . . . 125
B.5 PDPS Dickson Charge Pump . . . 140
B.6 OTFT Complete Memory Circuitry . . . 150
B.7 PDPS Complete Memory Circuitry . . . 152
Abbreviations
Abbreviation Meaning
awg Arbitrary waveform generator
bl Bitline
cmos Complementary metal-oxide-semiconductor
csv Comma-separated values (file)
dc Direct current
dram Dynamic random-access memory
eeprom Electrically erasable programmable read-only mem-ory
fe Ferroelectric
fefet Ferroelectric field-effect transistor
mosfet Metal–oxide–semiconductor field-effect transistor
nmos N-channel mosfet
otft Organic thin-film transistor pdps Printed dopant polysilicon
pen Polyethylene naphthalate
pfi Programmable function interface
pmos P-channel mosfet
rfid Radio frequency identification
smt Surface-mount technology
spice Simulation program with integrated circuit emphasis
usb Universal serial bus
uv Ultraviolet
wl Wordline
Parameters, signals and components Abbreviation Meaning CFE Ferroelectric capacitor Cf b Feedback capacitor CO Output capacitor CP Pump capacitor
Cref Reference capacitor
Csawyer Sawyer-Tower capacitor
Iof f Off-state current
Ion On-state current
Qr Remanent charge
Qs Saturation charge
Rpull Load resistor Tread Read pulse length
Twrite Write pulse length
VT Threshold voltage
VC Coercive voltage
Vread Read pulse voltage
Vwrite Write pulse voltage
Vin Input voltage
Vout Output voltage
φ1 Clock signal
φ2 Anti-phase clock signal
µ Carrier mobility
µlin Mobility in the linear region µsat Mobility in the saturation region
1
Introduction
This report describes work that has been conducted as a master thesis at Linköping University. The thesis evaluates circuit designs and topologies for reading and writing ferroelectric capacitor memories. The circuits are designed and evaluated for implementation using either printed organic thin film transistors or polysil-icon thin film transistors with printed dopants. The work is performed at Thin Film Electronics AB in Linköping, Sweden.
1.1
Background
Thanks to printed electronics low-cost, flexible circuits on plastic foils, or even paper or cloth, are now possible. These are very important for diverse applica-tions such as smart sensor systems for food or biomedical monitoring and rfid, radio frequency identification, tags. The combination of low temperature addi-tive manufacturing with fewer steps than conventional silicon processing, flexi-ble low-cost substrates and less complex machinery can dramatically reduce costs compared to traditional circuits. This allows electronics in places and applica-tions where it have not been cost effective before [1–3].
The fundamental building blocks of most complex circuits are logic and mem-ory. Organic thin film transistors, otfts, are a suitable technology to implement the logic part due to being compatible with a fully printed manufacturing pro-cess with all the advantages mentioned above [4, 5]. Another approach is to start from a traditional silicon process and reduce complexity by replacing as many complicated steps, e.g., lithography, as possible with printed alternatives.
In combination with the of use cheaper substrates onto which the semiconductor is extruded rather than expensive silicon wafers this can dramatically lower costs although not reaching as low as fully printed otfts. This manufacturing process is called printed dopant polysilicon, pdps [6, 7].
Ferroelectric, fe, memories were once destined as a replacement for nand Flash and eeprom, then facing problems moving to nanoscale devices, in our smart-phones and computers. The technology has now been repurposed for use in fully printed memories on flexible substrates [4, 8].
Ferroelectric memories has already been used together with otft circuits [4]. However, no printed circuits for performing the actual reading and writing of ferroelectric memories has been demonstrated. This work will evaluate the possi-bility of operating on such memories using otft and/or pdps circuits as well as the viability of some different implementation alternatives.
1.2
Thesis Purpose
The purpose of this work is to investigate if and how write and readout circuitry for printed ferroelectric memories can be implemented using printed organic thin film transistors or printed dopant poly-silicon transistors.
In practice this means that the progress of the work depend on the initial evalua-tion of the above. If it is deemed possible a circuit implementing the chosen ap-proach should be designed, simulated, manufactured (if possible, see Section 3.2) and evaluated. If on the other hand implementation is not considered possible the process limitations preventing it should be described.
After the theoretical basis of the work has been presented in Chapter 2 an initial overview of the complete system will be given in Section 4.2.
1.2.1
Goals
To further focus the scope of the work, additional goals are defined. The primary goal is the implementation of a circuit fulfilling the functionality specified in Section 1.2. After that the goal is to implement as much peripheral functionality as possible using printed circuits in order to demonstrate an integrated system for memory operations which is as complete as possible.
Targets for optimisation of the circuits are also given. These are secondary to the implementation of a functioning circuit and are to be pursued to an extent con-sidered reasonable and time efficient. The optimisation goals in order of priority are to:
Minimise complexity in number of devices used, to improve yield and decrease sensitivity to process variations.
Minimise supply voltage needed for circuit operation, to reduce the number of batteries needed for stand-alone operation.
Minimise stand by current to improve battery life and/or reduce the num-ber/size of batteries needed for stand-alone operation.
1.3
Delimitations
The work of this thesis should be focused on circuit design and not process de-velopment. That means the processes for manufacturing fe-memories, otfts and pdps-circuits and their parameters, limitations, etc. are fixed. Hence, when changes and properties of processes are discussed in this thesis it will be on the level of needed or available characteristics and not the development and improve-ment needed to achieve them.
Additionally, the issues of working with multiple memory cells will not be ad-dressed in the project, only a single memory cell will be used.
Further, the devices used and evaluated are limited to those implemented in pro-cesses available and in use at Thin Film Electronics AB in Linköping, Sweden.
2
Theory
This chapter presents a summary of available literature on the devices that are used in this project, focusing on the parts most relevant for the intended func-tionality. Also, circuit designs relevant to the operation of ferroelectric memories are introduced.
2.1
Ferroelectric Memories
The ferroelectric (fe) effect was discovered in Rochelle salt in 1921 by Valasek [9]. When a voltage is applied across an ferroelectric crystal it is polarised in the direction of the field and when the voltage is removed a majority of it remains po-larised, called remanent polarisation [10]. This is contrary to the more common dielectric or paraelectric (linear and non-linear respectively) polarisation which is zero when the applied electric field is zero.
This means that ferroelectric materials can be used as memory devices with the polarisation direction representing either a “0” or a “1”. However, the polarisa-tion cannot be measured directly. But when a ferroelectric material is used in-stead of a dielectric in a capacitor, polarising it will cause a compensating charge on the plates. When a voltage is applied opposite to this polarisation it will shift state and force the compensating charge to move. When a voltage is applied in the same direction as the ferroelectric polarisation however, it won’t switch and only the smaller compensation charge shift due to the non-remanent polarisa-tion will occur [10]. This is illustrated in the hysteresis curve in figure 2.1, which shows the two stable states, “0” and “1”, when the applied voltage, V, is zero. Qr 5
is the remanent charge from the ferroelectric polarisation and Qsis the saturation charge that also includes the maximum charge from the dielectric non-remanent polarisation. Also shown is the coercive voltage, VC, that is needed to switch the polarisation [11].
The electrical properties of a ferroelectric material can be considered analogous to the magnetic properties of ferromagnets. This gave the effect its name, despite the fact that there is no iron in ferroelectric materials [11, 12].
-VC VC Qr -Qr “0” “1” Qs -Qs Vmax V Q
Figure 2.1:The hysteresis curve shows the charge on a ferroelectric capacitor as a function of the applied voltage. Figure adapted from [11].
2.2
Organic Thin Film Transistors
To manufacture the low cost and flexible printed electronics as described in Sec-tion 1.1 tradiSec-tional crystalline silicon semiconductor devices need to be replaced [1]. Organic thin film transistors are a promising candidate that has undergone large developments in research the last decades. Low processing temperatures, typically under 150℃, in addition to mechanical properties of organic electron-ics materials allow use of different plastic substrates. This in conjunction with solution based additive processing, in contrast to vacuum deposition and lithog-raphy methods, holds promise of high volume production in cheap, low complex-ity fabs [3].
However, organic electronics presents some challenges and differences compared to conventional silicon based devices that has to be considered when they are used in circuits. otft technology suffers from limited carrier mobility, µ, in-trinsic gain and cut-off frequency [3]. According to Wu, Zhang and Qiu [1] the mobility of the best otft devices are usually in the 1∼2 cm2/Vs range while the
Figure 2.2: The effect of VT variation on dc current in a transistor. Figure adapted from [3].
Another important factor is the variance of primarily carrier mobility and thresh-old voltage, VT, due to processing variations. The µ variations results in variation
of the cut-off frequency since it affects the current delivered through the transis-tor. However, the effect on circuit gain is negligible since it isn’t directly deter-mined by the current flow. In contrast, VTvariations have a very non-linear effect
on transistor and thereby circuit behaviour, as shown in Figure 2.2. A VTshift
affects DC voltages on nodes in the circuit which through change of bias-level impacts AC behaviour as well [3]. This is illustrated by the first order current-voltage relationship of organic thin film transistors presented in Equation 2.1 for the linear regime and in Equation 2.2 for the saturation regime.
ID = µCdielW L (VGS− VT) VDS− VDS2 2 for |VGS− VT| > |VDS| (linear regime)
(2.1)
ID =
µCdielW
2L (VGS− VT)2 for |VDS| > |VGS− VT| > 0 (saturation regime)
(2.2) Additionally, VTshifts over time due to trapping of charge carriers, so called bias
Until the last few years available n-type organic thin film transistors (n-otft) has had significantly lower carrier mobility than p-type (p-otft) transistors, more than an order of magnitude. They have also been unstable in air and less reliable [1, 13]. This has led to work on using circuit topologies with mainly p-otfts, such as pseudo-pmos and different types of dynamic logic [3, 13].
Lately however, great progress has been made on n-type otfts making organic complementary circuits, cmos, possible [5, 14]. The main benefit of using com-plementary logic is reduced static power consumption since very limited current can flow from the supply voltage to ground in the static states [13].
2.3
Printed Dopant Polysilicon Transistors
As described in the review of reference material in Section 6.3 not much literature has been published on printed dopant polysilicon processing, however some de-tails can be learnt by examining the associated patents [6, 7]. However, although the process of manufacturing is different, the behaviour and parameters of the devices are qualitatively the same as traditional polysilicon devices.
Firstly, several semiconducting (i.e. silicon), dielectric or metal layers of the de-vices can be deposited using printing techniques. This reduces costs due to being additive, which allows more efficient usage of materials compared to the subtrac-tive methods of a conventional lithographic process. It also combines the steps of deposition and patterning into one printing step. The process also allows for a smooth, dome-shaped geometry of features, which compared to the sharp, abrupt edges of lithographically patterned features can reduce leakage current and dis-continuities or gaps in layers. [7]
Secondly, doping can be done by printing dielectric layers containing the dopants on top of the semiconductor and by annealing having them diffuse into the semi-conductor. These relatively simple steps can replace the multiple masking, ion-implant and stripping steps of a conventional process, and thus further reducing cost [6].
2.4
Memory Read and Write Circuits
To describe the circuit alternatives for writing to and reading from a fe memory cell the terminal of the ferroelectric capacitor where stimulus signals are applied is called the wordline, wl. The other terminal, where the response is measured and interpreted, is called the bitline, bl. This denomination reflects the adressing of multi-cell memory arrays.
To write the memory to either a “0” or “1” state a voltage needs to be applied over its terminals as described in Section 2.1. This can be done by connecting the wl to a memory drive voltage that is high enough to switch the cell while bl is kept connected to ground. To write the opposite polarity the wl is instead connected to ground while the bl is connected to the drive voltage [15].
Several approaches are available for reading from fe-memories. Most use a read-ing pulse applied to the wl, strong enough to switch the polarisation of the cell if it is opposite the polarity of the pulse. This results in a significant charge on the bl if the memory was in the state that results in a switch of polarisation and a much lower charge if it was in the other state that doesn’t result in a switch. This means that the readout is destructive since no matter what the polarisation was before the read operation the cell ends up in the same state determined by the read operation. A sense amplifier can be used to sense the bl voltage and thus the charge from the read operation [15].
If a high enough voltage needed for memory read and write drive pulses is not readily available in the system, for example if it is driven by a battery with a limited supply voltage, there are multiple approaches to generate it. There are also several ways to interpret the bitline charge as a digital memory state. These two issues are described separately in Section 2.4.1 and Section 2.4.2.
2.4.1
Memory Readout Circuitry
The bl voltage in the previously described readout scheme results from a capac-itive voltage division between the ferroelectric memory cell and the (parasitic) capacitance of the bitline. The use of capacitive voltage division to characterise the polarisation of a ferroelectric capacitor has been used since 1930 and it is called the Sawyer-Tower circuit [16]. It is shown in Figure 2.3.
Vin
CFE
Cref
Vout
The voltage that is sensed by an amplifier is dependant not only on the state and characteristics of the memory cell but also several parameters of the bl, such as parasitics and length. It also means that to get a large amplitude of the bl voltage signal its capacitance should be low compared to the capacitance of the memory, while to develop a large voltage across the memory cell and thereby switch it completely the bl capacitance should be large. This means that a compromise needs to be made when sizing the capacitance of the memory compared to the bl. An alternative way of sensing the result of a readout is to integrate the charge instead of the voltage. An integrator can be created by connecting the output of an amplifier to its input through a feedback capacitor, the bl is also connected to the input of the amplifier. This will keep the voltage on the input node low and transfer the charge to the feedback capacitor. The output of the amplifier assumes a voltage that balances the charge. This means that the output of the integrator is largely independent of the bl capacitance [17].
Regardless of whether a Sawyer-Tower or integrator approach is used, to read out a digital signal a comparison is needed with a reference signal to determine which state the signal from the memory corresponds to. This reference is ide-ally halfway between the voltage levels corresponding to the two memory states. This is made complicated by the fact that the state values are only known approx-imately in advance. They are dependant on process variations as well as memory degradation with use, so called fatigue. One way of generating a suitable refer-ence signal is to add a referrefer-ence ferroelectric capacitor that is bigger than the memory capacitor but always read in a non-switching way, this means that read-out of this capacitor should result in a value larger than that of a non-switching memory but below that of a switching one. Another approach is to have two refer-ence cells, one that gives a switching readout and one that gives a non-switching, the cells are sized to generate half the signal of the corresponding memory read-out, when they are connected together the resulting signal is the average of the two memory state readouts. These configurations of course make more sense in larger arrays than the one memory cell used in this work where the reference can be shared between multiple memory cells. When used in such larger arrays these reference cells can be arranged in different topologies with different advantages and disadvantages in area, rate of wear distribution and susceptibility to process variation [11].
Another approach is to use two memory cells to store a single value, one always storing the state complementary to the other. This means the readout signals of both memories can simply be compared to each other and the stored value determined by which of them is larger [11].
A way to avoid adding separate reference cells is by utilising the fact that the presented readout schemes are destructive, resulting in that if two readouts are carried out in succession the second is guaranteed to be a non-switch. Thus two sample and hold circuits can be used to store the values of these two readouts which can then be compared. However, in the case of both readouts being non-switches the signals will be approximately identical and comparison impossible
which means a threshold or margin is needed. When a charge integrating sense amplifier is used this can be achieved by having a longer integration period for the second, always non-switching, readout [18]. If instead a voltage sensing am-plifier is used the time between the application of the read pulse to the memory and the sampling of the amplifier output can be made longer for the first, ac-tual memory, readout than for the second, reference, readout. This means that when both readouts are non-switching the voltage level of the first readout will be lower than the reference [19].
An additional way of reading ferroelectric memories is available that is non-des-tructive to the state of the memory. Figure 2.1 shows that the charge response to applied voltage of a memory cell is non-linear in the steady states; “0” and “1”. Then if a small amplitude voltage pulse is applied, not enough to switch the cell, first of positive polarity and then of negative polarity, both of equal length, and the output charge summed together the polarity of the final output signal should indicate which state the memory is in. Even if this readout scheme doesn’t require switching of the memory polarisation every read disturbs the state of the memory slightly and after multiple readouts a refresh of the memory state by rewriting it might be needed [15].
2.4.2
Memory Drive Circuitry
To achieve the voltage needed to operate a ferroelectric memory from a lower voltage from for example a battery a voltage converter is needed. Conventional switched mode power supplies for converting dc to dc use magnetic coils as inductors for converting and stabilising the output voltage. The are multiple types of converters; the step-down, buck, that has a gain lower than one and the step-up, boost that has a gain higher than one. There is also a combination of the two, the step-down-step-up, buck-boost. However, the inductors needed can be bulky [20].
An alternative to the inductive converters are the switched capacitor dc-dc con-verter. The switched capacitor converter consists of an array of switches and capacitors. The switching array charges and discharges the capacitors to achieve the desired output voltage. Since it uses capacitors to store and transfer energy as electric charge it is also called a charge pump. A simple one stage switched ca-pacitor converter is shown in Figure 2.4. The pump caca-pacitor CP is first charged to the input voltage and then switched to charge the output COin series with the input so that the output is charged to twice the input voltage [20].
Probably the most common variant of the switched capacitor dc-dc converter is the Dickson charge pump. A four stage Dickson pump is shown in Figure 2.5. It requires two antiphase clock signals connected to every other capacitor bottom plate. When the clock of a capacitor is low it is charged through its input diode. When the clock then goes high the top plate is pushed up the input voltage plus
Vin CP C0
Figure 2.4:Single stage switched capacitor voltage converter.
Vin Vout
φ1
φ2
Figure 2.5:Four stage Dickson charge pump.φ1andφ2are anti-phase clock
the clock signal amplitude, this voltage can now charge the next capacitor whose clock signal is low. Thus in an ideal pump, if the amplitude of the clock signal is equal to the input voltage of the circuit, Vin, the first capacitor gets charged up to 2Vin the second to 3Vin and so on [20].
The threshold voltage of the switching device, the diodes in Figure 2.5, lowers the possible output voltage from the ideal as it is needed to turn the device on. Schottky diodes are therefor useful in Dickson pumps due to their low forward voltage drop. If no diodes are available diode connected transistors can be used instead, that is more sensitive to the threshold voltage issue however. Several more complex variations of the basic Dickson charge pump exists to address this and other problems of the circuit [20].
3
Method and Tools
The work of this project was divided into several steps. The required function-ality was divided into the circuit parts needed for a complete system described in Section 4.2. The circuit parts most unique to the operation of ferroelectric memory; the drive circuitry and the readout sensing were selected for further in-vestigation. The literature was then consulted to determine what circuit design alternatives that existed for implementation of these parts and their demands on the components used. The circuit alternatives was then matched against the known characteristics of the devices of the available processes, presented in Sec-tion 4.1, to determine viable combinaSec-tions.
A first circuit was selected and put through the modelling and simulation steps described in Section 3.1. The results were then evaluated and if deemed viable it was manufactured as described in Section 3.2, if possible. After evaluation of the simulation and possible measurement results of each circuit a comparison with the expected results and/or literature was done. Then a new circuit approach was selected and the process was repeated.
3.1
Modelling and Simulation
The modelling and simulation was done using the Tanner Tools suite by Tanner edawith T-Spice for simulation. Modelling was done on a schematic level using the S-Edit software. No layout work was done since, as described in Section 3.2, the only manufacturing that was performed was by assembly of discrete otft transistors.
otfttransistors have been modelled using the Amorphous-Si TFT Model ASIA2, level 15, with fixes made by Thin Film Electronics ab [21]. The fixed model in its entirety is presented in Chapter A. pdps transistors have been modelled using the Poly-Si TFT, level 16, model [22]. Finally, diodes have been modelled using the standard Non-Geometric Junction, level 1, diode model.
Simulations were made with multiple variations of the selected circuits and with varying device parameters, such as capacitances, resistances and transistor sizes and relative scaling. The reason for this was twofold. First to find the spread of parameters that allows for correct or acceptable functionality and thereby evalu-ate the robustness of the design and to select parameters for optimal performance going forward. Secondly, since the manufacturing processes are under constant development and in some cases even the type of devices to be used in the future not known, to get an understanding of what device parameters are necessary for a functioning circuit.
When a promising design was found it was further investigating by varying addi-tional parameters and narrowing their values down around the optimum. When a design had been chosen to move forward with to manufacturing it was adapted to a schematic using only devices with the exact same parameters as those that were available for assembly at the time. At this stage some components that pre-viously had been modelled as ideal were switched out for models of the devices that would be used for manufacturing, for example capacitors with large otfts and ideal reset switches with otfts. This adapted circuit was then simulated to confirm functionality.
Robustness to variations of the circuit candidates were supposed to be analysed both by manually varying (or sweeping using the software) device parameters, as described above, and by Monte Carlo simulations. However a bug affecting Monte Carlo simulations was found in the T-Spice software and thus the result of those had to be discarded. This is further discussed in Section 6.2.5.
An initial round of simulations of the memory drive pulse generation circuits were done using ideal equivalents of the components before they were imple-mented using otft or pdps transistors and compatible devices. This was done to get an initial indication of which design that were viable and also get target val-ues of device parameters for future process development. Ideal spice switches modelled transistors with switch on and off resistance modelling their transistor counterparts. A high performance diode using the level 3 Geometric Junction diode model was considered to approximate an ideal diode compared to the ones available in this project. Resistors were used to model the diode’s series and leak-age resistance.
Since capacitors were important for many of the circuits evaluated and their pa-rameters relatively unknown, as further described in Section 4.1.3, a similar ap-proach was used to model them throughout the project. An ideal capacitor was used with resistors to model series and leakage resistance.
The testbenches used to implement the simulations described in the rest of this section, as well as their input signals, are illustrated throughout Chapter 5. The simulations of memory readout circuitry was carried out by applying a signal to the memory wordline terminal while the circuit under evaluation was connected to the bitline. The wl signal consisted of two memory write pulses, each followed by a memory read pulse. The memory write pulses had a length of 5 ms and were of opposite polarity -20 V and 20 V, to ensure complete switching of the memory cell, see the standard operating conditions in Section 4.1.1. The read pulses were of the same polarity at 20 V and same pulse length, the latter was however varied between simulations. This resulted in a switching memory state during the first readout and a non-switching state during the second. A switch or transistor controlled by a Reset signal was used to force the bitline to ground during a write so the memory experienced the full write pulse amplitude. Initially the output of the different readout circuitry designs was compared to evaluate which one provided the most promising functionality. Then a latch was added after the output so the functionality could be evaluated simply as whether it latched correctly or not. This latch was reset to a high state between each read-out, using the same Reset signal that forced the bl to ground, allowing the cir-cuitry under test to switch it to a low state when the memory state was switched during readout.
When simulating the memory drive pulse generation circuitry the target output of 20 V and 1 µA, as described in Section 4.1.1 to ensure complete switching of the fe cells, was used to design the testbenches. The output of the circuitry under test was dissipated through a 20 MΩ resistor. If an output voltage of 20 V was achieved it could then be concluded, through Ohm’s law, that a current of 1 µA had been reached as well. The impact of using transistors to control the output voltage of the high voltage generation part of the pulse circuitry was also eval-uated using an Enable_n signal to decide when to switch on and off the output voltage.
After both the drive pulse generation and readout parts had been evaluated in isolation they were integrated into one memory control circuitry and tested to-gether. No negative pulse voltage was available now, so instead the pulses had to be switched to the either one of the memory terminals separately to be able to write it to both states, this was controlled with the PulseWL and PulseBL signals. Consequently, the ability to force both terminals to ground separately was needed for the memory to experience the full pulse voltage during writes of both states, this was controlled with the ResetWL and ResetBL signals. In this more complex control scheme the reset of the output latch was controlled by the separate signal ResetLatch.
Throughout all simulations a standard fe memory cell size of 200 µm x 200 µm was used. The memory was set to an uninitialised state in the beginning of each simulation, this should have had little impact on the stand-alone simulations of the readout circuitry as complete writes were ensured, the possible effect on sim-ulations of the integrated complete circuitry is discussed in Section 6.2.3.
3.2
Manufacturing
As previously mentioned there were two available processes for circuit manufac-turing evaluated in this project, pdps and otft. In the latter, discrete transistors are assembled into the intended circuit, possibly on a purpose-made backplane. The manufacturing method used, pdps or assembled otft transistors, depended not only on the result of the presented evaluation but also on the manufacturing capabilities and resources available at the time. In the end, resource and time constraints only allowed assembly of an otft Sawyer-Tower with sense amplifier using discrete devices and no pdps production.
Before assembly could begin the components to be used for the circuit had to be selected, this was done with the goal of using the otfts with behaviour most similar to that of the transistor model used in simulations. To achieve this with-out spending significant time on measurements, already available data from gate voltage sweeps at a drain voltage of 9V using a Keithley 4200-SCS parameter anal-yser was used. The measurement data was used to extract the threshold voltage of each transistor. This was then compared to the threshold voltage of a corre-sponding modelled transistor extracted in the same way from a correcorre-sponding simulated “measurement”. The physical transistors with a threshold voltage clos-est to that of their simulated counterparts was chosen for assembly.
The assembly was done on a pen, polyethylene naphthalate, substrate using epoxy cured by around 7 seconds of exposure to ultraviolet, uv, light and in-terconnects made with silver glue cured in oven at 50◦C during 30 minutes.
Mul-tiple iterations of the curing process was needed, both to be able to make cross-ing interconnects and for switchcross-ing out transistors durcross-ing troubleshootcross-ing of the prototype. This means that components was subjected to multiple heating cycles, with the number also varying between devices. Each device should however just have been exposed to one cycle of direct uv light when attached to the substrate, however they might have been further indirectly exposed during attachment of nearby components.
As described in Section 4.1.3 the only capacitive devices compatible with printed processing available was large otfts. To separate the evaluation of their per-formance of that of the rest of the design critical capacitors were attached first as commercial 0805 package, 50 V working voltage, surface mount capacitors. These were then switched out for the final otfts with source and drain used as one capacitor terminal and gate as the other.
3.3
Measurements
Evaluation of the assembled otft Sawyer-Tower with sense amplifier prototype was conducted with a measurement setup consisting of:
• Two National Instruments PXI5412 arbitrary waveform generators, awgs, in a PXIe-1073 chassis
• Thin Film Electronics high voltage amplifier based on the PA119CEA power amplifier
• Thin Film Electronics active high impedance probe • Hameg HMO1024 oscilloscope
The arbitrary waveform generators were configured using Thin Film Electronics software. One awg output the reset signal to the prototype under test while the other was used for the input signal, via the high voltage amplifier due to limited output voltage of the awg. Both the reset and input signals were also recorded on the oscilloscope. The output of the prototype under test was connected to the oscilloscope via the high impedance probe to avoid putting a significant load on the circuit. A digital signal from the programmable function interface, pfi, connector on one of the awgs was used to trigger the oscilloscope at the start of each measurement. The recorded data was downloaded from the oscilloscope to a computer via usb and saved to a csv file.
Measurements were analogous to the simulations of readout circuitry described in Section 3.1 and were done using an input waveform consisting of two memory write pulses, each followed by a memory read pulse. The memory write pulses were of pulse length Twriteand of opposite polarity but same amplitude; Vwrite.
The memory read pulses had pulse length Tread and same polarity amplitude
Vread. The reset signal of the prototype was high during writes, connecting the
bland latch input nodes to ground, ensuring the full write voltage was applied over the memory and resetting the latch state respectively. During reads the reset signal was low allowing a switching memory to switch the state of the latch. Measurements were done with different write and read pulse lengths and am-plitudes as well as different supply voltages of the prototype. Finally, different nodes of the prototype circuit was measured with the high impedance probe and the oscilloscope to give a more complete picture of the circuit behaviour.
3.4
Data Analysis and Visualisation
To visualise the results of the many parameter combinations tested during mea-surements and simulations Shmoo plots will be presented in Chapter 5 in addi-tion to traces of input and output signals of some tests. Shmoo plots visualise the performance of the evaluated circuit with a matrix with the colour of each cell representing whether the circuit operates successfully, given a specified criteria, for the parameter values given on the x and y axes [23]. Red if it fails and green if it passes.
For simulations and measurements of memory readouts with latch, that is both the stand-alone readout circuitry and complete integrated memory circuitry, the colour indicates whether it latches correctly for reads of both memory states. Af-ter the readout of a switching memory cell the latch output voltage should be low and it should be high after a non-switching readout. The threshold voltage used for deciding whether the latch state was correct was half of the supply voltage of the circuit.
For the stand-alone simulations of drive pulse generating circuitry the colour in-dicates whether the circuit reached an output voltage of 20 V. In more detail, the output signal was divided into segments for each high and low clock pulse. Then the lowest output voltage for each of the segments was calculated, the lowest was used to account for charge and discharge behaviour during the clock cycle. In fact, the true minimum was not used, instead the third percentile of the samples was used to discard samples during the switching of the clock. Finally the maxi-mum of these minimaxi-mum voltages for the high clock pulses was used to determine the color of the Shmoo cell. For additional information this maximum voltage was also presented in each cell. Further motivation for the use of this analysis scheme can be found in Section 6.2.6.
4
System and Components
This chapter presents the components available and their performance charac-teristics, the evaluation of different circuit designs will be based upon this data. Overall, there is a rapid development of the manufacturing processes and thus the device characteristics but the information available at the start of the project is presented. An overview of the complete system and a delimitation of the focus of this work to some of its parts is also given.
4.1
Available Processes and Components
Chapter 2 described the processes and devices used in this project according to existing literature; their history, manufacturing, behaviour and high-level perfor-mance characteristics. This section describes in closer detail the processes and devices actually available for use in the project with a focus on the character-istics and performances important for the evaluation of the circuit alternatives presented in Section 2.4.
4.1.1
Ferroelectric Memories
The most important parameters of the fe-memories for the purpose of reading and writing is the coercive voltage (VC) needed to switch the cell from one state
to the other, as well as the amount of charge displaced when it switches and when it does not respectively.
As per the product specification of a 100 µm x 100 µm memory the non-switching charge displacement current, i.e. the saturation charge minus the remnant polar-isation charge (Qs−Qr), should be 0.4–2.4 nC (nano Coulomb). Meanwhile the
switching charge displacement current, i.e. the saturation charge plus the rem-nant polarisation charge (Qs+Qr), should be 3.6–10.0 nC. Additionally the
differ-ence between the two should be at least 2.0 nC.
Figure 4.1: Switching charge depends on both the applied voltage, Vd, and time. Note: Polarisation (charge per area) is used instead of charge in this figure. The character of the correlation is the same with charge notation but the values differs, P∗corresponds to (Qs+Qr) and bP to (Qs−Qr).
The coercive voltage depends on multiple factors; variations in the ferroelectric film, primarily thickness, the operating temperature and the so called imprint ef-fect, which means that the ferroelectric becomes resistant to polarisation reversal with time that a given value is held [10]. The voltage needed to switch the mem-ory cell is also highly dependant on the period it is applied, this is illustrated in Figure 4.1. In the end, for products, a drive voltage of 20 V over a period of 50 µs is normally used for standard memories. In this project different voltage to time trade-offs were examined.
Further, experience has showed that with a drive pulse voltage of 20 V, a current of 1 µA is enough to reliably switch the memory cell. This target specification is useful for evaluating drive pulse generating circuitry without the added com-plexity of an actual memory cell.
4.1.2
Transistors
The characteristics of the otfts were a moving target during the time of the project. Available statistics on the characteristics of both n- and p-type otfts are shown in Table 4.1. Most otfts manufactured to date have a channel width of 1 mm and length of between 30 µm and 80 µm. Clock oscillators implemented in the process have shown frequencies in the 100–500 Hz range.
Parameter N-Type P-Type
Samples 30 24 Ion/Iof f 3920 932 VT [V] -0.27 0.08 µlin [cm2/Vs] 1.26 1.76 µsat [cm2/Vs] 1.00 1.76 Swing [V/dec.] 1.11 1.36
Table 4.1:Statistics for n- and p-type otfts from printed and base process. Mean values with standard deviation in brackets.
Characteristics of pdps transistors are shown in Table 4.2, they are of standard size with a channel width of 8 µm and length of 4 µm. Clock oscillators have been implemented using the process with frequencies of up to 100 MHz.
Parameter N-Type P-Type
VT [V] 0.6 -0.8
Mobility [cm2/Vs] 200 90
Off Current[pA] 75 20
Swing [V/dec.] 0.25 0.25
Table 4.2:Typical parameters for n- and p-type pdps transistors with a gate width of 8 µm and length of 4 µm.
Due to not previously being used for high voltage applications there is little data on how the process behaves under the voltages needed for fe-memory operation. However there is a known maximum source drain voltage of around 9–10 V, but the maximum gate voltage should be safely beyond what is used in this project.
4.1.3
Passive Components, Diodes and Batteries
There were also other devices needed in several of the circuits explored such as diodes, resistors and capacitors. Some of these are available for printing or in the pdps process. However for some a suitable process were not available, instead it was attempted to determine the values of device parameters of these components needed for functioning circuits. Also, external components that the circuits possibly will be used in conjunction with, such as batteries, put restraints on the designs.
In the pdps process there were poly-silicon and metal resistors available. Poly-silicon resistors gives sheet resistances in the kΩ range, with p-doped slightly higher than n-doped, while metal resistors are in the 10–100 mΩ range. However, variance is large, especially for the poly-silicon resistors, making precise high-resistance resistors unfeasible.
Printed resistors have been demonstrated using rectangles of carbon mixed with binder connected to silver contact pads. The sheet resistance can be tuned by the ratio of carbon to binder and the results of different mixtures are shown in Table 4.3.
Carbon:Binder Ratio Mean Sheet Resistance Standard Deviation
kOhm/sq kOhm/sq
100:0 2.57 0.08
70:30 55.4 1.0
Table 4.3: Statistics for printed resistors with different carbon to binder ra-tios.
Capacitors can in the pdps process be constructed between the interconnect and gate layers as well as between the gate and semiconductor layer, both with the gate-dielectric layer as insulator. These approaches gives capacitances in the 10s of pF for 100 µm x 100 µm squares.
Exploration of printed capacitors, or capacitors compatible with printed devices, has been done without finding a suitable candidate. Metal-insulator-semiconductor capacitors made with the otft process has shown capacitances in the nF/cm2 range but further examination and work on them have not been done.
For several designs in this projects capacitors have been important components. Since the search is on for suitable capacitive devices ideal capacitors were used for simulations during the project with non-ideal behaviour modelled with a se-ries resistor and a parallel leakage resistor. For prototype assembly large otfts, with up to 50 mm gate width, has been the only devices with significant capaci-tance available. Their capacicapaci-tance have been measured using a Hameg HM8118 programmable lcr bridge and the results are presented in Section 5.2.3.
Diodes can be implemented by using both pdps and otft transistors in diode connected mode, that is with the gate and drain connected together. Additionally, initial printed Schottky diodes have been shown using zinc oxide, with rectifica-tion ratios up to 105–106[24].
The intended use of the final system is in stand-alone tags powered by batteries. The batteries used must meet size and thickness requirements to be suitable for products. Available batteries provide 3 V, higher voltages can be supplied by connecting them in series but in total a maximum of 6–9 V supply voltage can be expected.
4.2
System Overview
An overview of the intended complete system can be given here according to the theory presented in Chapter 2. In order of priority, in the sense of being implemented as otft or pdps circuits, the functional blocks of the system are: Memory readout circuitry discerning the bl charge or voltage as the response
of a “0” or “1” state memory readout.
Drive pulse generation circuitry delivering sufficient voltage pulses to write the state of the memory and to read it.
Memory readout comparator and possible sample and hold and/or reference signal generation circuits for interpreting the memory readout circuitry out-put as a digital signal.
Clock generation to provide clock signal to other circuitry if needed.
Timing and control state machine or similar, that controls the functionality of other circuitry according to read and write commands.
Power supply circuitry if supplied battery voltage is not sufficient to drive other circuitry (not memory).
The memory readout and pulse generation circuitry are the main parts that are examined in this project, they are the most unique to the application of operat-ing (ferroelectric) memories and thus not thoroughly explored elsewhere. The pulse generation can in many cases further be divided into voltage conversion and pulse formation. The former supplies the high voltage needed to operate the memory and the latter controls this voltage into a pulse of appropriate length for memory operations.
Several approaches for digitally interpreting the output of the memory readout circuitry are described in Section 2.4.1, however a simple approach was used throughout this project. It is described in Section 5.1 and discussed in Section 6.2.2. Many of the drive pulse generation circuits require a clock signal. To be able to focus this work on the primary circuits a simplified model of clock signal genera-tors have been used. An ideal clock signal source with an output resistance was used to simulate a signal generator with limited output current. The achieved clock frequencies presented in Section 4.1.2 were used to select frequencies used for simulations. Output resistance was roughly estimated by connecting an in-verter to a resistive load. By varying the load the voltage division between the inverter and the load resistor could be used to estimate the formers output resis-tance. When the inverter output voltage was half of the output voltage with an approximately infinite load resistor the output resistance is roughly equal to the load resistance. The results of this estimation is presented in Section 5.4. There are of course other non-ideal behaviour that is not modelled by this approach and some issues are discussed in Section 6.2.1.
No effort was made on the implementation of timing and control or power sup-ply circuitry. Ideal signal generators were used to supsup-ply the necessary control signals of the circuits and an ideal voltage source was used for supply voltage generation.
5
Results
The results of the analysis, modelling, simulation, manufacturing and measure-ments described in Chapter 3 are presented in this chapter. They are divided by circuitry block and (target) manufacturing process.
First the results of the effort to design memory readout circuitry are described, that is; ideal signal generators are used as stimuli for the memory cell and focus is on converting the output of the cell to a digital signal. After a general analysis of the different readout approaches an otft integrator is designed and simulated followed by a Sawyer-Tower with sense amplifier. The latter is also assembled as a prototype using discrete otfts and measured. Then a pdps version of the Sawyer-Tower with sense amplifier is also designed and simulated.
After the work on readout circuitry has been presented the design of the drive part of memory control circuitry is described. These are the circuits intended to produce the high voltage pulses used to switch the fe cell state during writes and reads. Once again a general analysis is first presented followed by implemen-tation and simulation of the chosen Dickson charge pump design for use with both otft and pdps circuits. Additional circuitry to form pulses from the charge pump output is also explored.
Finally, the readout and drive parts are integrated, again first for otft and then pdps, and the implementation and simulation results presented.
Additional figures that were not considered as important to the discussions of Chapter 6 and conclusions of Chapter 7 are presented in Chapter B.
5.1
Memory Readout Circuitry Overview
This section presents an overview of the work done on the readout side of the ferroelectric memory control circuitry. Section 5.2 and Section 5.3 then present the results of readout circuits implemented using otft and pdps technology re-spectively.
Three readout circuit alternatives where presented in Section 2.4, of these the non-destructive approach was discarded. THe demands of additional accuracy of the readout circuitry with this approach was a bad match with the project goal of robustness as well as lower transistor performance and process maturity compared to conventional silicon devices. Hence, the circuits analysed in the following sections are the Sawyer-Tower with sense amplifier and the integrator. To keep the circuit complexity low the threshold voltage of the otft and pdps transistors were used as reference to achieve a digital output rather than the sig-nal reference schemes described in Section 2.4. In effect, the threshold of a single pmostransistor was used to interpret the output of sense amplifiers and integra-tors as digital values, as will be shown in testbench illustrations in the following sections. The reasoning behind this is further discussed in Section 6.2.2.
5.2
OTFT Memory Readout Circuitry
An overview of the complete otft readout circuitry with testbench is shown in Figure 5.1. It includes the memory cell, latch as well as signal generators for wordline stimuli, reset signal and supply voltage. The voltage source V1 gener-ates the supply dc-voltage, Vwl the wl stimuli signal and V2 the bl and latch reset signal. The P-type (channel width 500 µm and length 40 µm) and N-type (channel width 2 mm and length 40 µm) transistors sets and resets the latch re-spectively. Also included is resistor R1, with resistance Rwl, on the wordline simulating the output impedance of an otft signal generator. Simulations were done with the resistance Rwl at both 0 Ω and 1 MΩ to compare the behaviour under ideal circumstances with an approximation of the behaviour with memory drive circuitry implemented using otfts, the estimation of 1 MΩ is presented in Section 5.4. The readout circuitry under evaluation is the big square cell, cur-rently named Integrator_1.
5.2.1
OTFT Integrator Modelling and Simulation
The cmos implementation of an integrator based readout circuit is shown in Fig-ure 5.2a. The best results, i.e. with the most clear distinction in output signal between the readout of different memory states are shown in Figure 5.3. The simulation was made under ideal conditions, that is no output impedance of the driver pulse generator, Rwl. Further, the feedback capacitance, Cfb, was 1 nF, the
supply voltage 6 V and the inverter transistor width was 2 mm for both nmos and pmos.
+ + -+ -+ -In Reset Out V D D V S S In Out Vdd Vss In Out Vdd Vss B L WL Vdd Vdd Vdd Vdd Vdd Vss Vss Vss Reset O u t p u t LatchIn LatchOut R 1 V1 V2 Mn1 Mp1 Vwl F E _ c e l l _ 1 Integrator_1 R = R w l 'Vpwr' NF = 1 L = 40u M = 1 TW = 2m* W = 2m NF = 1 L = 40u M = 1 TW = 500u* W = 500u I n i t i a l S t a t e = F E s t a t e A R E A = 2 0 0 * 2 0 0 In tegr ato rVDD
Figure 5.1: Testbench and peripheral circuits used during simulations of otftreadout circuitry. Including memory cell, latch with set and reset tran-sistors, signal generators with output resistor and readout circuit under eval-uation. + In Out Vdd Vss Vss Vss Vss C1 Out In Reset VDD VSS M = 1 C = Cfb
(a) cmosintegrator design.
+ + C1 R 1 Mn1 Out In Reset VDD VSS M = 1 C = Cfb R = R p u l l NF = 1 L = 40u M = 1 TW = wNMOS* W = wNMOS
(b) nmosintegrator design.
Figure 5.2: otftintegrator readout circuitry, with ideal reset switch. With (a) showing cmos implementations and (b) nmos.
In addition to the integrator using a cmos inverter, implementations using pure nmosand pmos inverting amplifiers were evaluated. The nmos version showed similar performance to cmos and is shown in Figure 5.2b. The results of a sim-ulation with 10 MΩ load resistor (Rpull), 464 pF feedback capacitance (Cfb), 6 V
supply voltage and 2 mm nmos transistor width are also shown in Figure 5.3.
−20 0 20 WL (V) 0 2 4 6 Reset (V) 5 10 BL (V) C MOS 0 5 10 BL (V) NMOS 0 5 10 Output (V) C MOS 0 10 20 30 40 50 60 70 80 90 100 110 120 130 0 5 10 Time (ms) Output (V) NMOS
Figure 5.3:Bitline and integrator output voltages for both cmos and nmos integrator circuits. Waveform names correspond to nodes in the testbench in Figure 5.1.
Comparing the Output signal before the end of each read pulse, that is at 40 ms and 101 ms, shows the distinction between the memory states that the circuit made when it had reached a steady state during the application of the readout pulse. This distinction was around 1 V for both the cmos and nmos circuits. However, the absolute signal level was around 0 V for the former while it was just over a volt higher for the latter.
The slope of the Output signal after the readout pulse was released and before the Reset signal was activated, that is 41–60 ms as well as from 73 ms onwards, means that the circuit didn’t reach a steady state during this phase. Additionally, the bitline voltage fluctuates significantly during the readouts. These behaviours are not expected from an integrator readout approach. The bl voltage should be kept approximately constant by the feedback from the amplifier. Also, the output should gradually change as the charge on the input is integrated. Instead, this behaviour is more like the response of a Sawyer-Tower capacitive voltage divider between the memory and the feedback capacitor.
With the insight that the behaviour that provided distinction between memory states was more reminiscent of a Sawyer-Tower, even for an integrator circuit, further work on an integrator solution was abandoned in favour of the former approach.
5.2.2
OTFT Sawyer-Tower Modelling and Simulation
The implementation of a Sawyer-Tower sense amplifier using a cmos inverter is shown in Figure 5.4. Figure 5.5 shows a simulation made without output resis-tance on the drive signal generator, again using the testbench in Figure 5.1. The capacitance between the bl and ground (Csawyer) is 500 pF, the supply voltage 6 V
and both nmos and pmos transistor widths 500 µm. The simulation showed a near complete distinction between the readouts of different memory states, that is a difference in sense amplifier Output voltage approximately equal to the sup-ply voltage. Figure 5.5 also shows the correct latching behaviour of the circuit with the LatchOut signal set in opposite states after the memory readouts.
+
In
Out
Vdd
Vss
C 1 Mn1 Out In Reset VDD VSS M = 1 C = C f b NF = 1 L = 40u M = 1 TW = 2m* W = 2mFigure 5.4: Sawyer-Tower with cmos sense amplifier design with a nmos transistor for reset.
0 2 4 6 8 Output (V) 0 2 4 6 La tchIn (V) 0 2 4 6 La tchOut (V) −20 0 20 WL (V) 0 5 10 BL (V) 0 10 20 30 40 50 60 70 80 90 100 110 120 0 2 4 6 Time (ms) Reset (V)
Figure 5.5: Response of Sawyer-Tower with sense amplifier. No output impedance of the wordline signal generator.
This design was perceived significantly better than the integrator described in Section 5.2.1 and hence the effect of different device and usage parameters was analysed using this architecture. Figure 5.6 shows if the design latches correctly for different sizes of Csawyerand different read pulse lengths using varying sense
amplifier transistor sizing. Except for the variation of said parameters the simu-lation is the same as the one in Figure 5.5. It shows that larger nmos transistors might be beneficial for shorter pulse lengths as well as with large Sawyer capaci-tor. Larger pmos transistor mainly seem to have a detrimental effect with shorter pulse lengths and larger capacitors but might have a somewhat positive effect when using long pulses and a small capacitor.
100p 215.4p 464.2p 1n 2.2n 4.6n Wnmos =500um 100p 215.4p 464.2p1n 2.2n 4.6n Wnmos =1mm 100p 215.4p 464.2p1n 2.2n 4.6n Wnmos =2mm
1u 5u 10u 50u 100u 500u 1m 5m 100p 215.4p 464.2p1n 2.2n 4.6n Wpmos=500um Wnmos =5mm
1u 5u 10u 50u 100u 500u 1m 5m
Wpmos=1mm
1u 5u 10u 50u 100u 500u 1m 5m
Wpmos=2mm
1u 5u 10u 50u 100u 500u 1m 5m
Wpmos=5mm
Memory read pulse length (seconds)
Sa wy er tow er capacitance (F)
Figure 5.6:Latching behaviour of Sawyer-Tower with sense amplifier for dif-ferent transistor sizing, Sawyer capacitance and read pulse lengths. If reads of both memory states results in a correct (opposite) latch output signal the box is green, otherwise it’s red. No output impedance of the wordline signal generator.
To further investigate the expected behaviour in a real circuit the wordline signal output impedance was upped to 1 MΩ and the resulting waveforms are shown in Figure 5.7. The simulation was made using the same parameters as in the pre-vious case except for the change in Rwl. This figure shows a slight delay of the signals compared to Figure 5.5 where Rwl is 0 Ω. However, when the latching behaviour is analysed over additional sense amplifier transistor and Sawyer ca-pacitor sizes as well as read pulse lengths as shown in Figure 5.8 it is clear that functionality for pulses shorter than 500 µs is severely impacted. The impact of sense amplifier transistor sizing is still low, except for some cases with large capacitor or 5 ms read pulses.
0 2 4 6 Output (V) 0 2 4 6 La tchIn (V) 0 2 4 6 La tchOut (V) −20 0 20 WL (V) 0 5 10 BL (V) 0 10 20 30 40 50 60 70 80 90 100 110 120 0 2 4 6 Time (ms) Reset (V)
Figure 5.7: Response of Sawyer-Tower with sense amplifier. 1 MΩ output impedance of the wordline signal generator.
100p 215.4p 464.2p1n 2.2n 4.6n Wnmos =500um 100p 215.4p 464.2p1n 2.2n 4.6n Wnmos =1mm 100p 215.4p 464.2p1n 2.2n 4.6n Wnmos =2mm
1u 5u 10u 50u 100u 500u 1m 5m 100p 215.4p 464.2p 1n 2.2n 4.6n Wpmos=500um Wnmos =5mm
1u 5u 10u 50u 100u 500u 1m 5m
Wpmos=1mm
1u 5u 10u 50u 100u 500u 1m 5m
Wpmos=2mm
1u 5u 10u 50u 100u 500u 1m 5m
Wpmos=5mm
Memory read pulse length (seconds)
Sa wy er tow er capacitance (F)
Figure 5.8:Latching behaviour of Sawyer-Tower with sense amplifier for dif-ferent transistor sizing, Sawyer capacitance and read pulse lengths. If reads of both memory states results in a correct (opposite) latch output signal the box is green, otherwise it’s red. 1 MΩ output impedance of the wordline signal generator.
Other important factors are the behaviour for low supply voltages as well as lower read pulse amplitudes. To analyse this the transistor widths of the sense ampli-fier was fixed to the standard size of 500 µm and Sawyer capacitor to 500 pF. The results in Figure 5.9 show that a decreased supply voltage does not prevent circuit functionality for voltages larger than 3 V. Also there is an optimum for shorter pulse lengths and/or lower pulse amplitudes at a supply voltage below 6 V, shown by the behaviour at 4 V.
1u 5u 10u 50u 100u 500u1m 5m RWL =0 Ω 5 6 7 8 10 12 15 20 1u 5u 10u 50u 100u 500u1m 5m Vdd=2V RWL =1M Ω 5 6 7 8 10 12 15 20 Vdd=3V 5 6 7 8 10 12 15 20 Vdd=4V 5 6 7 8 10 12 15 20 Vdd=6V
Memory read pulse amplitude (V)
Memory
read
pulse
length
(seconds)
Figure 5.9:Latching behaviour of Sawyer-Tower with sense amplifier for dif-ferent read pulse length and amplitude, supply voltage and wordline signal output impedance. If reads of both memory states results in a correct (oppo-site) latch output signal the box is green, otherwise it’s red.
The results of the Sawyer-Tower and sense amplifier presented in this section were considered good enough to proceed with the manufacturing of a prototype using this design.
5.2.3
OTFT Sawyer-Tower Assembly and Measurements
With the previously described simulation results of the Sawyer-Tower with sense amplifier readout circuitry, it was selected and prepared for assembly. The as-sembly and measurement processes has been described in Section 3.2 and Sec-tion 3.3 respectively. The prototype was first assembled and measured with a commercial 0805 package, 50V working voltage, surface mount capacitor as the Sawyer-Tower capacitor. It was then exchanged for large otfts connected in
